From 21f9c90d6893336bbb08619eb090f3f2a0bc4d8c Mon Sep 17 00:00:00 2001
From: Minsu Kim <minsu.kim@amd.com>
Date: Tue, 25 Aug 2026 21:24:58 +0000
Subject: [PATCH] Add MAF/MAB kernels for MC system

---
 ...ik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...AE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml |   0
 ...AE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ..._B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...lk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...lk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml |   0
 ...Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml |   0
 ...jlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml |   0
 ..._Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml |   0
 ...lk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...k_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 .../gfx1250_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml  |   0
 ...gfx1250_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml |   0
 ...gfx1250_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml |   0
 .../gfx1250_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml  |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ..._F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ..._F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...lk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...lk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml |   0
 ...Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml |   0
 ...jlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml |   0
 ...Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml |   0
 ..._Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml |   0
 ...Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml |   0
 ...lk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...k_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml |   0
 ...k_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...ijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml |   0
 ..._Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml |   0
 ..._Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml |   0
 ..._S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml |   0
 .../gfx1250_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml  |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ..._B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...jk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...jk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml |   0
 ...Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml |   0
 ...ljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml |   0
 ..._Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml |   0
 ...lk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...k_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 .../gfx1250_Cijk_Ailk_Bljk_C_B_UserArgs.yaml  |   0
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 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ..._F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
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 ..._F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
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 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...jk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...jk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml |   0
 ...Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml |   0
 ...ljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml |   0
 ...Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml |   0
 ..._Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml |   0
 ...Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml |   0
 ...lk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...k_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml |   0
 ...k_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...ijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml |   0
 ..._Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml |   0
 ..._Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml |   0
 ..._S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml |   0
 .../gfx1250_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml  |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
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 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
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 ...k_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 .../gfx1250_Cijk_Alik_Bjlk_C_B_UserArgs.yaml  |   0
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 ...gfx1250_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml |   0
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 ..._Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml |   0
 ..._S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml |   0
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 ...ljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml |   0
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 ...v0_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml |   0
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 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml |   0
 ...Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml |   0
 ...ljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml |   0
 ..._Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml |   0
 ...ik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...k_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...gfx1250v0_Cijk_Alik_Bljk_C_B_UserArgs.yaml |   0
 ...gfx1250v0_Cijk_Alik_Bljk_D_B_UserArgs.yaml |   0
 ...AE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml |   0
 ...AF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml |   0
 ...AE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml |   0
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 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
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 ...v0_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml |   0
 ...jk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...AE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml |   0
 ...AE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml |   0
 ...BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml |   0
 ...jk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...AE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml |   0
 ..._SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml |   0
 ...Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml |   0
 ...ljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml |   0
 ...Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml |   0
 ..._Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml |   0
 ...Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml |   0
 ...ik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...k_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml |   0
 ...k_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...ijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml |   0
 ..._Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml |   0
 ..._Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml |   0
 ..._S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...gfx1250v0_Cijk_Alik_Bljk_Z_B_UserArgs.yaml |   0
 ...x1250v0_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml |   0
 ...250v0_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml |   0
 ...250v0_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml |   0
 ...x1250v0_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml |   0
 ...x1250v0_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml |   0
 ...x1250v0_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml |   0
 ...ik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml |   0
 ...XBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...XBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml |   0
 ...1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml | 622 +++++++++++++
 ...jk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml | 850 +++++++++++++++++
 ...jk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml | 853 ++++++++++++++++++
 ...250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml | 637 +++++++++++++
 ...jk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml | 805 +++++++++++++++++
 ...1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml | 622 +++++++++++++
 ...jk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml | 850 +++++++++++++++++
 ...jk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml | 853 ++++++++++++++++++
 ...250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml | 637 +++++++++++++
 ...jk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml | 805 +++++++++++++++++
 444 files changed, 15068 insertions(+)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Equality/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_Bljk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/GridBased/gfx1250_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Origami/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Origami/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Origami/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Origami/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/{ => gfx1250}/Origami/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Equality/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_D_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_Bljk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Origami/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Origami/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Origami/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Origami/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 rename projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/{ => gfx1250v0}/Origami/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml (100%)
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
 create mode 100644 projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml

diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Equality/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_D_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_D_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_D_B_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_D_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_C_B_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_D_B_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_D_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_Bljk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/GridBased/gfx1250_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250/Origami/gfx1250_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..bb4cd4e4e526
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
@@ -0,0 +1,622 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 7
+  DataTypeA: 7
+  DataTypeAmaxD: 0
+  DataTypeB: 7
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 7
+  MacDataTypeB: 7
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI18jnnk6ntvRYVX0eaBWRp9Fsz0h5u8eSImBWu8obJHz8=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 128]
+      name: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 4
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 2
+    TemporalHintC: 4
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 48
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT1H9I8DvrtmoQmwWFI3BOEvHnXDdTx7dkqEW0Fg9kS5ms=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 64]
+      name: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 64
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 64
+    LSCB: 64
+    LSPA: 16
+    LSPB: 4
+    LVCA: 64
+    LVCB: 64
+    LVPA: 16
+    LVPB: 4
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52352
+    LdsInitCVgprs: false
+    LdsNumBytes: 52352
+    LdsNumElementsAlignedA: 2176
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2176
+    LdsOffsetB_Blk: 34944
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2176
+    LdsOffsetMXSA_Blk: 34944
+    LdsOffsetMXSB: 2176
+    LdsOffsetMXSB_Blk: 34944
+    LdsOffsetMetadata: 2176
+    LdsOffsetMetadata_Blk: 34944
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 64
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonTemporalD: 4
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    StaggerU: 0
+    StaggerUStride: 128
+    StoreSwapAddr: false
+    StoreSyncOpt: 1
+    StoreVectorWidth: 8
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintC: 5
+    TemporalHintD: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 0
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: -8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 64
+    _DepthUA: 64
+    _DepthUB: 64
+    _DepthUMetadata: 64
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 16384]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..3f46c28073a5
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,850 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgq1wU-xTunSrgVw9l4iMooNjUHaJ6-IjGAZQp3a8uVj4=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: address, semantic: AddressWorkspace}
+      - {type: address, semantic: AddressFlags}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: uint32, semantic: ItersPerTile}
+      - {type: uint32, semantic: MagicNumberItersPerTile}
+      - {type: uint32, semantic: MagicShiftItersPerTile}
+      - {type: uint32, semantic: SKItersPerWG}
+      - {type: uint32, semantic: SKGrid}
+      - {type: uint32, semantic: SKTilesAndSplit}
+      generated: true
+      grid: [StreamKWithBatch, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 0
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: false, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 256
+    LSPB: 64
+    LSPMXSA: 256
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 128
+    LVPB: 32
+    LVPMXSA: 256
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 282624
+    LdsInitCVgprs: false
+    LdsNumBytes: 282624
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 4096
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 141312
+    LdsOffsetB: 74752
+    LdsOffsetB_Blk: 216064
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 207872
+    LdsOffsetMXSB: 70656
+    LdsOffsetMXSB_Blk: 211968
+    LdsOffsetMetadata: 74752
+    LdsOffsetMetadata_Blk: 216064
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 8
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    StreamK: 3
+    StreamKXCCMapping: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintB: 4
+    TemporalHintC: 1
+    TemporalHintD: 6
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 0]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: PartialsBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 4096
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgGunNTgb6yQgzIn9AmKopJL1iPwzkUMBe8qgm5RqIDE4=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 239616
+    LdsInitCVgprs: false
+    LdsNumBytes: 239616
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 79872
+    LdsOffsetB: 13312
+    LdsOffsetB_Blk: 93184
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 88576
+    LdsOffsetMXSB: 9216
+    LdsOffsetMXSB_Blk: 89088
+    LdsOffsetMetadata: 13312
+    LdsOffsetMetadata_Blk: 93184
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
new file mode 100644
index 000000000000..3fa5b99353c6
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
@@ -0,0 +1,853 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 15
+  DataTypeMXSB: 15
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 16
+  MXBlockB: 16
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgndDHhb6IF2auxlWVaLbbsGvf0HeFG8cyrzfP62xQY-c=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 256
+    LSPB: 4
+    LSPMXSA: 256
+    LSPMXSB: 4
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 128
+    LVPB: 2
+    LVPMXSA: 256
+    LVPMXSB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 256
+    LdsBlockSizePerPadMXSB: 256
+    LdsBytesNoAmax: 301056
+    LdsInitCVgprs: false
+    LdsNumBytes: 301056
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 8704
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 150528
+    LdsOffsetB: 83968
+    LdsOffsetB_Blk: 234496
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 217088
+    LdsOffsetMXSB: 75264
+    LdsOffsetMXSB_Blk: 225792
+    LdsOffsetMetadata: 83968
+    LdsOffsetMetadata_Blk: 234496
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 16
+    LdsPadMXSB: 16
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 16
+    StaggerUStride: 512
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 0
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 3
+    TemporalHintC: 3
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 2
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 2
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 1
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 8704
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgLMRyF3A9tMXsItd_g46pWoCDOYH3E0f4-fMK8srTqpc=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 256
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 254976
+    LdsInitCVgprs: false
+    LdsNumBytes: 254976
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 1024
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 84992
+    LdsOffsetB: 18432
+    LdsOffsetB_Blk: 103424
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 93696
+    LdsOffsetMXSB: 9728
+    LdsOffsetMXSB_Blk: 94720
+    LdsOffsetMetadata: 18432
+    LdsOffsetMetadata_Blk: 103424
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 16
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 1024
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..c091e1ef6296
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
@@ -0,0 +1,637 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MIHHAkicRqFE8MfSChETXNJxIsbX9msJ39k6Km2k6lvsk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSPA: 64
+    LSPB: 64
+    LVCA: 256
+    LVCB: 256
+    LVPA: 64
+    LVPB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 3
+    TemporalHintB: 4
+    TemporalHintC: 3
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 24
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgJQUTVrM8gpmsSPydn8gLWtpUVnH4sGZV-OrEtY1wOrk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleA}
+      - {type: address, semantic: AddressScaleB}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 128]
+      name: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 32
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 32
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52480
+    LdsInitCVgprs: false
+    LdsNumBytes: 52480
+    LdsNumElementsAlignedA: 2304
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2304
+    LdsOffsetB_Blk: 35072
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2304
+    LdsOffsetMXSA_Blk: 35072
+    LdsOffsetMXSB: 2304
+    LdsOffsetMXSB_Blk: 35072
+    LdsOffsetMetadata: 2304
+    LdsOffsetMetadata_Blk: 35072
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 1
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 8
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 0
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 0
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StaggerUStride: 128
+    StorePriorityOpt: true
+    StoreSwapAddr: false
+    StoreVectorWidth: 1
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 5
+    TemporalHintC: 2
+    TemporalHintD: 1
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 24
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..fac5f67bf108
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_192cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,805 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgVnvJ6vTJ2S1GnFjpav5NRXpELKApdvuNrVCUIQ269iE=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSCMXSA: 8
+    LSCMXSB: 8
+    LSPA: 64
+    LSPB: 64
+    LSPMXSA: 64
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 8
+    LVCMXSB: 8
+    LVPA: 64
+    LVPB: 64
+    LVPMXSA: 64
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 274432
+    LdsInitCVgprs: false
+    LdsNumBytes: 274432
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 2048
+    LdsNumElementsAlignedMXSB: 2048
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 137216
+    LdsOffsetB: 70656
+    LdsOffsetB_Blk: 207872
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 203776
+    LdsOffsetMXSB: 68608
+    LdsOffsetMXSB_Blk: 205824
+    LdsOffsetMetadata: 70656
+    LdsOffsetMetadata_Blk: 207872
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 1
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 6
+    TemporalHintC: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 1
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 1
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: -4
+    WorkGroupMappingXCC: 8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMXSA: 8
+    _DepthUMXSB: 8
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 2048
+    ldsNumBytesMXSB: 2048
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 1
+    AssertFree1ElementMultiple: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArg3I_K79pFqJah_TTy1aco2e4lmeHGn8O_KDI1sVtnLJo=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernelName: ''
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 1
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 512
+    LVCB: 512
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 32
+    LVPB: 256
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 309248
+    LdsInitCVgprs: false
+    LdsNumBytes: 309248
+    LdsNumElementsAlignedA: 16896
+    LdsNumElementsAlignedB: 133120
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 154624
+    LdsOffsetB: 21504
+    LdsOffsetB_Blk: 176128
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 16896
+    LdsOffsetMXSA_Blk: 171520
+    LdsOffsetMXSB: 17408
+    LdsOffsetMXSB_Blk: 172032
+    LdsOffsetMetadata: 21504
+    LdsOffsetMetadata_Blk: 176128
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 64
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSU1_GSUAMB_GSUC0_GSUWGMRR0_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SU32_SUM0_SUS512_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGM1_WGMXCC1_WGMXCCGn1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 512
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: true
+    StoreSyncOpt: 0
+    StoreVectorWidth: 1
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 0
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 1
+    VectorWidthB: 2
+    VectorWidthMXSA: 1
+    VectorWidthMXSB: 2
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: false
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 16896
+    ldsNumBytesB: 133120
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..7a17cfebaf90
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
@@ -0,0 +1,622 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 7
+  DataTypeA: 7
+  DataTypeAmaxD: 0
+  DataTypeB: 7
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 7
+  MacDataTypeB: 7
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI18jnnk6ntvRYVX0eaBWRp9Fsz0h5u8eSImBWu8obJHz8=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 128]
+      name: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 4
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 2
+    TemporalHintC: 4
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 48
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT1H9I8DvrtmoQmwWFI3BOEvHnXDdTx7dkqEW0Fg9kS5ms=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 64]
+      name: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 64
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 64
+    LSCB: 64
+    LSPA: 16
+    LSPB: 4
+    LVCA: 64
+    LVCB: 64
+    LVPA: 16
+    LVPB: 4
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52352
+    LdsInitCVgprs: false
+    LdsNumBytes: 52352
+    LdsNumElementsAlignedA: 2176
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2176
+    LdsOffsetB_Blk: 34944
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2176
+    LdsOffsetMXSA_Blk: 34944
+    LdsOffsetMXSB: 2176
+    LdsOffsetMXSB_Blk: 34944
+    LdsOffsetMetadata: 2176
+    LdsOffsetMetadata_Blk: 34944
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 64
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonTemporalD: 4
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    StaggerU: 0
+    StaggerUStride: 128
+    StoreSwapAddr: false
+    StoreSyncOpt: 1
+    StoreVectorWidth: 8
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintC: 5
+    TemporalHintD: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 0
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: -8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 64
+    _DepthUA: 64
+    _DepthUB: 64
+    _DepthUMetadata: 64
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 16384]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..69315e0b8249
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,850 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgq1wU-xTunSrgVw9l4iMooNjUHaJ6-IjGAZQp3a8uVj4=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: address, semantic: AddressWorkspace}
+      - {type: address, semantic: AddressFlags}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: uint32, semantic: ItersPerTile}
+      - {type: uint32, semantic: MagicNumberItersPerTile}
+      - {type: uint32, semantic: MagicShiftItersPerTile}
+      - {type: uint32, semantic: SKItersPerWG}
+      - {type: uint32, semantic: SKGrid}
+      - {type: uint32, semantic: SKTilesAndSplit}
+      generated: true
+      grid: [StreamKWithBatch, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 0
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: false, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 256
+    LSPB: 64
+    LSPMXSA: 256
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 128
+    LVPB: 32
+    LVPMXSA: 256
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 282624
+    LdsInitCVgprs: false
+    LdsNumBytes: 282624
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 4096
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 141312
+    LdsOffsetB: 74752
+    LdsOffsetB_Blk: 216064
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 207872
+    LdsOffsetMXSB: 70656
+    LdsOffsetMXSB_Blk: 211968
+    LdsOffsetMetadata: 74752
+    LdsOffsetMetadata_Blk: 216064
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 8
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    StreamK: 3
+    StreamKXCCMapping: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintB: 4
+    TemporalHintC: 1
+    TemporalHintD: 6
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 0]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: PartialsBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 4096
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgGunNTgb6yQgzIn9AmKopJL1iPwzkUMBe8qgm5RqIDE4=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 239616
+    LdsInitCVgprs: false
+    LdsNumBytes: 239616
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 79872
+    LdsOffsetB: 13312
+    LdsOffsetB_Blk: 93184
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 88576
+    LdsOffsetMXSB: 9216
+    LdsOffsetMXSB_Blk: 89088
+    LdsOffsetMetadata: 13312
+    LdsOffsetMetadata_Blk: 93184
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
new file mode 100644
index 000000000000..2268b0ef9280
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
@@ -0,0 +1,853 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 15
+  DataTypeMXSB: 15
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 16
+  MXBlockB: 16
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgndDHhb6IF2auxlWVaLbbsGvf0HeFG8cyrzfP62xQY-c=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 256
+    LSPB: 4
+    LSPMXSA: 256
+    LSPMXSB: 4
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 128
+    LVPB: 2
+    LVPMXSA: 256
+    LVPMXSB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 256
+    LdsBlockSizePerPadMXSB: 256
+    LdsBytesNoAmax: 301056
+    LdsInitCVgprs: false
+    LdsNumBytes: 301056
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 8704
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 150528
+    LdsOffsetB: 83968
+    LdsOffsetB_Blk: 234496
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 217088
+    LdsOffsetMXSB: 75264
+    LdsOffsetMXSB_Blk: 225792
+    LdsOffsetMetadata: 83968
+    LdsOffsetMetadata_Blk: 234496
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 16
+    LdsPadMXSB: 16
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 16
+    StaggerUStride: 512
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 0
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 3
+    TemporalHintC: 3
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 2
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 2
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 1
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 8704
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgLMRyF3A9tMXsItd_g46pWoCDOYH3E0f4-fMK8srTqpc=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 256
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 254976
+    LdsInitCVgprs: false
+    LdsNumBytes: 254976
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 1024
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 84992
+    LdsOffsetB: 18432
+    LdsOffsetB_Blk: 103424
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 93696
+    LdsOffsetMXSB: 9728
+    LdsOffsetMXSB_Blk: 94720
+    LdsOffsetMetadata: 18432
+    LdsOffsetMetadata_Blk: 103424
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 16
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 1024
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..0d6a1e3400d4
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
@@ -0,0 +1,637 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MIHHAkicRqFE8MfSChETXNJxIsbX9msJ39k6Km2k6lvsk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSPA: 64
+    LSPB: 64
+    LVCA: 256
+    LVCB: 256
+    LVPA: 64
+    LVPB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 3
+    TemporalHintB: 4
+    TemporalHintC: 3
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 24
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgJQUTVrM8gpmsSPydn8gLWtpUVnH4sGZV-OrEtY1wOrk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleA}
+      - {type: address, semantic: AddressScaleB}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 128]
+      name: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 32
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 32
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52480
+    LdsInitCVgprs: false
+    LdsNumBytes: 52480
+    LdsNumElementsAlignedA: 2304
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2304
+    LdsOffsetB_Blk: 35072
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2304
+    LdsOffsetMXSA_Blk: 35072
+    LdsOffsetMXSB: 2304
+    LdsOffsetMXSB_Blk: 35072
+    LdsOffsetMetadata: 2304
+    LdsOffsetMetadata_Blk: 35072
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 1
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 8
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 0
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 0
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StaggerUStride: 128
+    StorePriorityOpt: true
+    StoreSwapAddr: false
+    StoreVectorWidth: 1
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 5
+    TemporalHintC: 2
+    TemporalHintD: 1
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 24
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..e64c0ea38f56
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250/gfx1250_96cu/Equality/gfx1250_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,805 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgVnvJ6vTJ2S1GnFjpav5NRXpELKApdvuNrVCUIQ269iE=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSCMXSA: 8
+    LSCMXSB: 8
+    LSPA: 64
+    LSPB: 64
+    LSPMXSA: 64
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 8
+    LVCMXSB: 8
+    LVPA: 64
+    LVPB: 64
+    LVPMXSA: 64
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 274432
+    LdsInitCVgprs: false
+    LdsNumBytes: 274432
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 2048
+    LdsNumElementsAlignedMXSB: 2048
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 137216
+    LdsOffsetB: 70656
+    LdsOffsetB_Blk: 207872
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 203776
+    LdsOffsetMXSB: 68608
+    LdsOffsetMXSB_Blk: 205824
+    LdsOffsetMetadata: 70656
+    LdsOffsetMetadata_Blk: 207872
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 1
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 6
+    TemporalHintC: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 1
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 1
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: -4
+    WorkGroupMappingXCC: 8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMXSA: 8
+    _DepthUMXSB: 8
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 2048
+    ldsNumBytesMXSB: 2048
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 1
+    AssertFree1ElementMultiple: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArg3I_K79pFqJah_TTy1aco2e4lmeHGn8O_KDI1sVtnLJo=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernelName: ''
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 1
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 512
+    LVCB: 512
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 32
+    LVPB: 256
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 309248
+    LdsInitCVgprs: false
+    LdsNumBytes: 309248
+    LdsNumElementsAlignedA: 16896
+    LdsNumElementsAlignedB: 133120
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 154624
+    LdsOffsetB: 21504
+    LdsOffsetB_Blk: 176128
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 16896
+    LdsOffsetMXSA_Blk: 171520
+    LdsOffsetMXSB: 17408
+    LdsOffsetMXSB_Blk: 172032
+    LdsOffsetMetadata: 21504
+    LdsOffsetMetadata_Blk: 176128
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 64
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSU1_GSUAMB_GSUC0_GSUWGMRR0_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SU32_SUM0_SUS512_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGM1_WGMXCC1_WGMXCCGn1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 512
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: true
+    StoreSyncOpt: 0
+    StoreVectorWidth: 1
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 0
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 1
+    VectorWidthB: 2
+    VectorWidthMXSA: 1
+    VectorWidthMXSB: 2
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: false
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 16896
+    ldsNumBytesB: 133120
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Equality/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_C_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bjlk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_D_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_D_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Ailk_Bljk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_C_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_D_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_D_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bjlk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8F8_SS_BH_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_D_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_GradB_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_BSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_B_BS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_D_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_D_B_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_D_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_D_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAF8B16_MXBF8B16_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8B8_SS_BH_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8F8S_BH_Bias_SHB_HA_S_SAB_SCD_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8HS_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_F8_SS_BH_Bias_SHB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_A_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_D_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HHS_BH_GradH_HA_S_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_GG_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_HSS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_AuxH_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_H_HS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_I8_II_BH_HA_I_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_B_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_S_MX_B_Bias_SB_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_Z_B_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_Bljk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_C_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bjlk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml
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rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_C_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml
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rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/GridBased/gfx1250v0_Cijk_Alik_C_Bljk_Z_B_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F4SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
similarity index 100%
rename from projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
rename to projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0/Origami/gfx1250v0_Cijk_Alik_Bljk_F8SS_MXAE8B32_MXBE8B32_BH_Bias_HA_S_SAB_SAV_UserArgs.yaml
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..1eada7546fa2
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
@@ -0,0 +1,622 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 7
+  DataTypeA: 7
+  DataTypeAmaxD: 0
+  DataTypeB: 7
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 7
+  MacDataTypeB: 7
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI18jnnk6ntvRYVX0eaBWRp9Fsz0h5u8eSImBWu8obJHz8=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 128]
+      name: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 4
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 2
+    TemporalHintC: 4
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 48
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT1H9I8DvrtmoQmwWFI3BOEvHnXDdTx7dkqEW0Fg9kS5ms=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 64]
+      name: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 64
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 64
+    LSCB: 64
+    LSPA: 16
+    LSPB: 4
+    LVCA: 64
+    LVCB: 64
+    LVPA: 16
+    LVPB: 4
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52352
+    LdsInitCVgprs: false
+    LdsNumBytes: 52352
+    LdsNumElementsAlignedA: 2176
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2176
+    LdsOffsetB_Blk: 34944
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2176
+    LdsOffsetMXSA_Blk: 34944
+    LdsOffsetMXSB: 2176
+    LdsOffsetMXSB_Blk: 34944
+    LdsOffsetMetadata: 2176
+    LdsOffsetMetadata_Blk: 34944
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 64
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonTemporalD: 4
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    StaggerU: 0
+    StaggerUStride: 128
+    StoreSwapAddr: false
+    StoreSyncOpt: 1
+    StoreVectorWidth: 8
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintC: 5
+    TemporalHintD: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 0
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: -8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 64
+    _DepthUA: 64
+    _DepthUB: 64
+    _DepthUMetadata: 64
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 16384]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..5c1876930986
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,850 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgq1wU-xTunSrgVw9l4iMooNjUHaJ6-IjGAZQp3a8uVj4=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: address, semantic: AddressWorkspace}
+      - {type: address, semantic: AddressFlags}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: uint32, semantic: ItersPerTile}
+      - {type: uint32, semantic: MagicNumberItersPerTile}
+      - {type: uint32, semantic: MagicShiftItersPerTile}
+      - {type: uint32, semantic: SKItersPerWG}
+      - {type: uint32, semantic: SKGrid}
+      - {type: uint32, semantic: SKTilesAndSplit}
+      generated: true
+      grid: [StreamKWithBatch, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 0
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: false, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 256
+    LSPB: 64
+    LSPMXSA: 256
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 128
+    LVPB: 32
+    LVPMXSA: 256
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 282624
+    LdsInitCVgprs: false
+    LdsNumBytes: 282624
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 4096
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 141312
+    LdsOffsetB: 74752
+    LdsOffsetB_Blk: 216064
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 207872
+    LdsOffsetMXSB: 70656
+    LdsOffsetMXSB_Blk: 211968
+    LdsOffsetMetadata: 74752
+    LdsOffsetMetadata_Blk: 216064
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 8
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    StreamK: 3
+    StreamKXCCMapping: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintB: 4
+    TemporalHintC: 1
+    TemporalHintD: 6
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 0]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: PartialsBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 4096
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgGunNTgb6yQgzIn9AmKopJL1iPwzkUMBe8qgm5RqIDE4=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 239616
+    LdsInitCVgprs: false
+    LdsNumBytes: 239616
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 79872
+    LdsOffsetB: 13312
+    LdsOffsetB_Blk: 93184
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 88576
+    LdsOffsetMXSB: 9216
+    LdsOffsetMXSB_Blk: 89088
+    LdsOffsetMetadata: 13312
+    LdsOffsetMetadata_Blk: 93184
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
new file mode 100644
index 000000000000..90f175c7da75
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
@@ -0,0 +1,853 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 15
+  DataTypeMXSB: 15
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 16
+  MXBlockB: 16
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgndDHhb6IF2auxlWVaLbbsGvf0HeFG8cyrzfP62xQY-c=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 256
+    LSPB: 4
+    LSPMXSA: 256
+    LSPMXSB: 4
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 128
+    LVPB: 2
+    LVPMXSA: 256
+    LVPMXSB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 256
+    LdsBlockSizePerPadMXSB: 256
+    LdsBytesNoAmax: 301056
+    LdsInitCVgprs: false
+    LdsNumBytes: 301056
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 8704
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 150528
+    LdsOffsetB: 83968
+    LdsOffsetB_Blk: 234496
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 217088
+    LdsOffsetMXSB: 75264
+    LdsOffsetMXSB_Blk: 225792
+    LdsOffsetMetadata: 83968
+    LdsOffsetMetadata_Blk: 234496
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 16
+    LdsPadMXSB: 16
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 16
+    StaggerUStride: 512
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 0
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 3
+    TemporalHintC: 3
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 2
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 2
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 1
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 8704
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgLMRyF3A9tMXsItd_g46pWoCDOYH3E0f4-fMK8srTqpc=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 256
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 254976
+    LdsInitCVgprs: false
+    LdsNumBytes: 254976
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 1024
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 84992
+    LdsOffsetB: 18432
+    LdsOffsetB_Blk: 103424
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 93696
+    LdsOffsetMXSB: 9728
+    LdsOffsetMXSB_Blk: 94720
+    LdsOffsetMetadata: 18432
+    LdsOffsetMetadata_Blk: 103424
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 16
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 1024
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..d5f9afd12085
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
@@ -0,0 +1,637 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MIHHAkicRqFE8MfSChETXNJxIsbX9msJ39k6Km2k6lvsk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSPA: 64
+    LSPB: 64
+    LVCA: 256
+    LVCB: 256
+    LVPA: 64
+    LVPB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 3
+    TemporalHintB: 4
+    TemporalHintC: 3
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 24
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgJQUTVrM8gpmsSPydn8gLWtpUVnH4sGZV-OrEtY1wOrk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleA}
+      - {type: address, semantic: AddressScaleB}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 128]
+      name: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 32
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 32
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52480
+    LdsInitCVgprs: false
+    LdsNumBytes: 52480
+    LdsNumElementsAlignedA: 2304
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2304
+    LdsOffsetB_Blk: 35072
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2304
+    LdsOffsetMXSA_Blk: 35072
+    LdsOffsetMXSB: 2304
+    LdsOffsetMXSB_Blk: 35072
+    LdsOffsetMetadata: 2304
+    LdsOffsetMetadata_Blk: 35072
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 1
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 8
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 0
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 0
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StaggerUStride: 128
+    StorePriorityOpt: true
+    StoreSwapAddr: false
+    StoreVectorWidth: 1
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 5
+    TemporalHintC: 2
+    TemporalHintD: 1
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 24
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..adada19115ce
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_192cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,805 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 192}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgVnvJ6vTJ2S1GnFjpav5NRXpELKApdvuNrVCUIQ269iE=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSCMXSA: 8
+    LSCMXSB: 8
+    LSPA: 64
+    LSPB: 64
+    LSPMXSA: 64
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 8
+    LVCMXSB: 8
+    LVPA: 64
+    LVPB: 64
+    LVPMXSA: 64
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 274432
+    LdsInitCVgprs: false
+    LdsNumBytes: 274432
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 2048
+    LdsNumElementsAlignedMXSB: 2048
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 137216
+    LdsOffsetB: 70656
+    LdsOffsetB_Blk: 207872
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 203776
+    LdsOffsetMXSB: 68608
+    LdsOffsetMXSB_Blk: 205824
+    LdsOffsetMetadata: 70656
+    LdsOffsetMetadata_Blk: 207872
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 1
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 6
+    TemporalHintC: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 1
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 1
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: -4
+    WorkGroupMappingXCC: 8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMXSA: 8
+    _DepthUMXSB: 8
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 2048
+    ldsNumBytesMXSB: 2048
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 1
+    AssertFree1ElementMultiple: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArg3I_K79pFqJah_TTy1aco2e4lmeHGn8O_KDI1sVtnLJo=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernelName: ''
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 1
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 512
+    LVCB: 512
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 32
+    LVPB: 256
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 309248
+    LdsInitCVgprs: false
+    LdsNumBytes: 309248
+    LdsNumElementsAlignedA: 16896
+    LdsNumElementsAlignedB: 133120
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 154624
+    LdsOffsetB: 21504
+    LdsOffsetB_Blk: 176128
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 16896
+    LdsOffsetMXSA_Blk: 171520
+    LdsOffsetMXSB: 17408
+    LdsOffsetMXSB_Blk: 172032
+    LdsOffsetMetadata: 21504
+    LdsOffsetMetadata_Blk: 176128
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 64
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSU1_GSUAMB_GSUC0_GSUWGMRR0_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SU32_SUM0_SUS512_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGM1_WGMXCC1_WGMXCCGn1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 512
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: true
+    StoreSyncOpt: 0
+    StoreVectorWidth: 1
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 0
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 1
+    VectorWidthB: 2
+    VectorWidthMXSA: 1
+    VectorWidthMXSB: 2
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: false
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 16896
+    ldsNumBytesB: 133120
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..b897dfe1f852
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_BBS_BH_UserArgs.yaml
@@ -0,0 +1,622 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 7
+  DataTypeA: 7
+  DataTypeAmaxD: 0
+  DataTypeB: 7
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 7
+  MacDataTypeB: 7
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI18jnnk6ntvRYVX0eaBWRp9Fsz0h5u8eSImBWu8obJHz8=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 128]
+      name: Cijk_Alik_Bljk_BBS_BH_UserArgs_MT256x256x128_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB2_THC4_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA2_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 4
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 2
+    TemporalHintC: 4
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 48
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+    AdaptiveGemm: 1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT1H9I8DvrtmoQmwWFI3BOEvHnXDdTx7dkqEW0Fg9kS5ms=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 64]
+      name: Cijk_Alik_Bljk_BBS_BH_Bias_HA_S_SAV_UserArgs_MT16x128x64_MI16x16x1_SN_LDSB0_AFC1_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA8_LPB8_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD4_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS0_SPO0_SRVW0_SSO1_SVW8_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB0_THC5_THD4_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB2_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 64
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 64
+    LSCB: 64
+    LSPA: 16
+    LSPB: 4
+    LVCA: 64
+    LVCB: 64
+    LVPA: 16
+    LVPB: 4
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52352
+    LdsInitCVgprs: false
+    LdsNumBytes: 52352
+    LdsNumElementsAlignedA: 2176
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2176
+    LdsOffsetB_Blk: 34944
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2176
+    LdsOffsetMXSA_Blk: 34944
+    LdsOffsetMXSB: 2176
+    LdsOffsetMXSB_Blk: 34944
+    LdsOffsetMetadata: 2176
+    LdsOffsetMetadata_Blk: 34944
+    LdsPadA: 8
+    LdsPadB: 8
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 8
+    LocalReadVectorWidthB: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 64
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 32, 1, 1, 1]
+    MIInputPerThread: 16
+    MIInputPerThreadA: 16
+    MIInputPerThreadB: 16
+    MIInputPerThreadMetadata: 16
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 32
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 32, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonTemporalD: 4
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    StaggerU: 0
+    StaggerUStride: 128
+    StoreSwapAddr: false
+    StoreSyncOpt: 1
+    StoreVectorWidth: 8
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintC: 5
+    TemporalHintD: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 0
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadB: 2
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: -8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 64
+    _DepthUA: 64
+    _DepthUB: 64
+    _DepthUMetadata: 64
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 16384]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..62f237ad824e
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,850 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgq1wU-xTunSrgVw9l4iMooNjUHaJ6-IjGAZQp3a8uVj4=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: address, semantic: AddressWorkspace}
+      - {type: address, semantic: AddressFlags}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: uint32, semantic: ItersPerTile}
+      - {type: uint32, semantic: MagicNumberItersPerTile}
+      - {type: uint32, semantic: MagicShiftItersPerTile}
+      - {type: uint32, semantic: SKItersPerWG}
+      - {type: uint32, semantic: SKGrid}
+      - {type: uint32, semantic: SKTilesAndSplit}
+      generated: true
+      grid: [StreamKWithBatch, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA2_GRVWB2_GSU0_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW4_SK3_SKFTR0_SKFDPO0_SKWS0_SKXCCM4_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB4_THC1_THD6_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 0
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: false, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 256
+    LSPB: 64
+    LSPMXSA: 256
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 128
+    LVPB: 32
+    LVPMXSA: 256
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 282624
+    LdsInitCVgprs: false
+    LdsNumBytes: 282624
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 4096
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 141312
+    LdsOffsetB: 74752
+    LdsOffsetB_Blk: 216064
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 207872
+    LdsOffsetMXSB: 70656
+    LdsOffsetMXSB_Blk: 211968
+    LdsOffsetMetadata: 74752
+    LdsOffsetMetadata_Blk: 216064
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 8
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    StreamK: 3
+    StreamKXCCMapping: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintB: 4
+    TemporalHintC: 1
+    TemporalHintD: 6
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMappingXCC: 32
+    WorkspaceCheck: [4, 0, 0]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: PartialsBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 4096
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgGunNTgb6yQgzIn9AmKopJL1iPwzkUMBe8qgm5RqIDE4=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 239616
+    LdsInitCVgprs: false
+    LdsNumBytes: 239616
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 79872
+    LdsOffsetB: 13312
+    LdsOffsetB_Blk: 93184
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 88576
+    LdsOffsetMXSB: 9216
+    LdsOffsetMXSB_Blk: 89088
+    LdsOffsetMetadata: 13312
+    LdsOffsetMetadata_Blk: 93184
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
new file mode 100644
index 000000000000..811b0756616f
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs.yaml
@@ -0,0 +1,853 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 21
+  DataTypeA: 21
+  DataTypeAmaxD: 0
+  DataTypeB: 21
+  DataTypeE: 7
+  DataTypeMXSA: 15
+  DataTypeMXSB: 15
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 16
+  MXBlockB: 16
+  MacDataTypeA: 21
+  MacDataTypeB: 21
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgndDHhb6IF2auxlWVaLbbsGvf0HeFG8cyrzfP62xQY-c=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT256x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA256_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA16_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS4_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP0_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA5_THB3_THC3_THD7_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA0_WSGRB2_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 512
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 256
+    LSPB: 4
+    LSPMXSA: 256
+    LSPMXSB: 4
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 128
+    LVPB: 2
+    LVPMXSA: 256
+    LVPMXSB: 4
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 256
+    LdsBlockSizePerPadMXSB: 256
+    LdsBytesNoAmax: 301056
+    LdsInitCVgprs: false
+    LdsNumBytes: 301056
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 8704
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 150528
+    LdsOffsetB: 83968
+    LdsOffsetB_Blk: 234496
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 217088
+    LdsOffsetMXSB: 75264
+    LdsOffsetMXSB_Blk: 225792
+    LdsOffsetMetadata: 83968
+    LdsOffsetMetadata_Blk: 234496
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 16
+    LdsPadMXSB: 16
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 4
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 16
+    StaggerUStride: 512
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 0
+    TDMInst: 3
+    TemporalHintA: 5
+    TemporalHintB: 3
+    TemporalHintC: 3
+    TemporalHintD: 7
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadB: 2
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 2
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 2
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 1
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 8704
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 2
+    AssertFree1ElementMultiple: 2
+    AssertSummationElementMultiple: 16
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgLMRyF3A9tMXsItd_g46pWoCDOYH3E0f4-fMK8srTqpc=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [32, 256, 512]
+      name: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 2
+    GlobalReadVectorWidthB: 2
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 2
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 0
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 32
+    LSCMXSB: 32
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 32
+    LVCMXSB: 32
+    LVPA: 16
+    LVPB: 128
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 256
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 254976
+    LdsInitCVgprs: false
+    LdsNumBytes: 254976
+    LdsNumElementsAlignedA: 8704
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 1024
+    LdsNumElementsAlignedMXSB: 8704
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 84992
+    LdsOffsetB: 18432
+    LdsOffsetB_Blk: 103424
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 8704
+    LdsOffsetMXSA_Blk: 93696
+    LdsOffsetMXSB: 9728
+    LdsOffsetMXSB_Blk: 94720
+    LdsOffsetMetadata: 18432
+    LdsOffsetMetadata_Blk: 103424
+    LdsPadA: 32
+    LdsPadB: 32
+    LdsPadMXSA: 0
+    LdsPadMXSB: 16
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 32
+    LocalReadVectorWidthB: 32
+    LocalReadVectorWidthMXS: 8
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 8
+    MIInputPerThreadMXSB: 8
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 32
+    NumLdsBlk: 3
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F4BS_MXAF8B16_MXBF8B16_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM2_AFEM2_ASEM16_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA2_GRVWB2_GSUAMB_GLS0_HPLR0_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB256_LBSPPM0_LPA32_LPB32_LPMXSA0_LPMXSB16_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW2_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB1_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA2_VWB4_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 256
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: false
+    StoreSyncOpt: 0
+    StoreVectorWidth: 2
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: false
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 1
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 2
+    VectorWidthB: 4
+    VectorWidthMXSA: 2
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 32
+    _DepthUMXSB: 32
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 8448
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 1024
+    ldsNumBytesMXSB: 8704
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 65536]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
new file mode 100644
index 000000000000..cbcc0c65a3c4
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_BH_UserArgs.yaml
@@ -0,0 +1,637 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 0
+  MXBlockB: 0
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MIHHAkicRqFE8MfSChETXNJxIsbX9msJ39k6Km2k6lvsk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA3_THB4_THC3_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSPA: 64
+    LSPB: 64
+    LVCA: 256
+    LVCB: 256
+    LVPA: 64
+    LVPB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 266240
+    LdsInitCVgprs: false
+    LdsNumBytes: 266240
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 133120
+    LdsOffsetB: 66560
+    LdsOffsetB_Blk: 199680
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 199680
+    LdsOffsetMXSB: 66560
+    LdsOffsetMXSB_Blk: 199680
+    LdsOffsetMetadata: 66560
+    LdsOffsetMetadata_Blk: 199680
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 3
+    TemporalHintB: 4
+    TemporalHintC: 3
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    TransposeLDS: 1
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: 24
+    WorkGroupMappingXCC: 4
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+  - SolutionIndex: 1
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgJQUTVrM8gpmsSPydn8gLWtpUVnH4sGZV-OrEtY1wOrk=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      - {type: address, semantic: AddressScaleA}
+      - {type: address, semantic: AddressScaleB}
+      - {type: address, semantic: AddressScaleAlphaVec}
+      - {type: address, semantic: AddressBias}
+      - {type: uint32, semantic: BiasType}
+      - {type: uint32, semantic: StrideBias}
+      - {type: float32, semantic: ActivationArg}
+      - {type: float32, semantic: ActivationArg, index: 1}
+      - {type: uint32, semantic: ActivationTypeArg}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [16, 128, 128]
+      name: Cijk_Alik_Bljk_F8BS_BH_Bias_HA_S_SAB_SAV_UserArgs_MT16x128x128_MI16x16x1_SN_LDSB0_AFC1_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM1_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR0_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA256_LBSPPB256_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT1_2_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA4_NTB4_NTC4_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NV1_NVA1_NVB1_NVC1_NVD1_NVE1_NVMXSA1_NVMXSB1_NVM1_NVWS1_NEPBS8_NLCA1_NLCB1_ONLL0_PAP0_PGL0_PGR2_PLR0_PKA1_SGROB0_SIA4_SS1_SPO1_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL0_SIPn1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB5_THC2_THD1_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGROn1_USI0_VSn1_VWA1_VWB2_WSGRA2_WSGRB1_WS32_WG16_8_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 128
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalWriteVectorWidth: 1
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLRA: false
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 128
+    LSCB: 128
+    LSPA: 4
+    LSPB: 32
+    LVCA: 128
+    LVCB: 128
+    LVPA: 4
+    LVPB: 32
+    LdsBlockSizePerPadA: 256
+    LdsBlockSizePerPadB: 256
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 52480
+    LdsInitCVgprs: false
+    LdsNumBytes: 52480
+    LdsNumElementsAlignedA: 2304
+    LdsNumElementsAlignedB: 17408
+    LdsNumElementsAlignedMXSA: 0
+    LdsNumElementsAlignedMXSB: 0
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 32768
+    LdsOffsetB: 2304
+    LdsOffsetB_Blk: 35072
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 2304
+    LdsOffsetMXSA_Blk: 35072
+    LdsOffsetMXSB: 2304
+    LdsOffsetMXSB_Blk: 35072
+    LdsOffsetMetadata: 2304
+    LdsOffsetMetadata_Blk: 35072
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 1
+    LoopUnroll: 128
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [1, 2]
+    MIWaveTileA: 1
+    MIWaveTileB: 2
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 16
+    MacroTile1: 128
+    MacroTileA: 16
+    MacroTileB: 128
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporalA: 4
+    NonTemporalB: 4
+    NonTemporalC: 4
+    NonVolatile: 1
+    NonVolatileA: 1
+    NonVolatileB: 1
+    NonVolatileC: 1
+    NonVolatileD: 1
+    NonVolatileE: 1
+    NonVolatileMXSA: 1
+    NonVolatileMXSB: 1
+    NonVolatileMetadata: 1
+    NonVolatileWS: 1
+    NumElementsPerBatchStore: 8
+    NumElementsPerThread: 16
+    NumGlobalWriteVectorsPerThread: 16
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 0
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 0
+    ScheduleGROverBarrier: 0
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StaggerUStride: 128
+    StorePriorityOpt: true
+    StoreSwapAddr: false
+    StoreVectorWidth: 1
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SwInstructionPrefetch: -1
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 5
+    TemporalHintC: 2
+    TemporalHintD: 1
+    ThreadTile: [1, 1]
+    ThreadTile0: 8
+    ThreadTile1: 2
+    ThreadTileA: 8
+    ThreadTileB: 2
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    Valid: true
+    VectorWidthA: 1
+    VectorWidthB: 2
+    WaveSeparateGlobalReadA: 2
+    WaveSeparateGlobalReadB: 1
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 24
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 128
+    _DepthUA: 128
+    _DepthUB: 128
+    _DepthUMetadata: 128
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 2176
+    ldsNumBytesB: 17408
+    ldsNumBytesMXSA: 0
+    ldsNumBytesMXSB: 0
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 65536, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality
diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
new file mode 100644
index 000000000000..8a138c0a9433
--- /dev/null
+++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/gfx1250v0/gfx1250v0_96cu/Equality/gfx1250v0_Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs.yaml
@@ -0,0 +1,805 @@
+- {MinimumRequiredVersion: 5.0.0}
+- gfx1250v0
+- {Architecture: gfx1250, CUCount: 96}
+- [Device 75c7]
+- Activation: false
+  ActivationComputeDataType: 0
+  ActivationNoGuard: false
+  ActivationType: none
+  AllowNoFreeDims: false
+  AssignedDerivedParameters: true
+  Batched: true
+  BetaOnlyUseBias: false
+  BiasDataTypeList: [0, 7]
+  BiasSrc: D
+  ComplexConjugateA: false
+  ComplexConjugateB: false
+  ComputeDataType: 0
+  DataType: 15
+  DataTypeA: 15
+  DataTypeAmaxD: 0
+  DataTypeB: 15
+  DataTypeE: 7
+  DataTypeMXSA: 22
+  DataTypeMXSB: 22
+  DestDataType: 7
+  F32XdlMathOp: 0
+  GateResidualDataTypeList: []
+  Gradient: false
+  GroupedGemm: false
+  HighPrecisionAccumulate: true
+  Index0: 0
+  Index01A: 0
+  Index01B: 1
+  Index01MXSA: 0
+  Index01MXSB: 1
+  Index1: 1
+  IndexAssignmentsA: [3, 0, 2]
+  IndexAssignmentsB: [3, 1, 2]
+  IndexAssignmentsLD: [4, 5, 6, 7]
+  IndexAssignmentsMXSA: [3, 0, 2]
+  IndexAssignmentsMXSB: [3, 1, 2]
+  IndexAssignmentsMetadata: [3, 0, 2]
+  IndexUnroll: 3
+  IndexUnrollA: 0
+  IndexUnrollB: 0
+  IndexUnrollM: 0
+  IndexUnrollMXSA: 0
+  IndexUnrollMXSB: 0
+  IndicesBatch: [2]
+  IndicesFree: [0, 1]
+  IndicesSummation: [3]
+  MXBlockA: 32
+  MXBlockB: 32
+  MacDataTypeA: 15
+  MacDataTypeB: 15
+  MetadataLayout: 0
+  MirrorDimsA: []
+  MirrorDimsB: []
+  MirrorDimsMXSA: []
+  MirrorDimsMXSB: []
+  MirrorDimsMetadata: []
+  NumIndicesBatch: 1
+  NumIndicesC: 3
+  NumIndicesFree: 2
+  NumIndicesLD: 4
+  NumIndicesSummation: 1
+  OperationType: GEMM
+  OutputAmaxD: false
+  SetConstStrideA: []
+  SetConstStrideB: []
+  SetConstStrideBias: []
+  SetConstStrideGate: []
+  SilentHighPrecisionAccumulate: false
+  Sparse: 0
+  StochasticRounding: false
+  StridedBatched: true
+  SupportUserArgs: true
+  SwizzleTensorA: false
+  SwizzleTensorB: false
+  TLUA: false
+  TLUB: false
+  TLUMXSA: false
+  TLUMXSB: false
+  Tensor0: 0
+  Tensor1: 1
+  TileA: 0
+  TileAwareSelection: false
+  TileB: 1
+  TotalIndices: 4
+  TransposeA: true
+  TransposeB: false
+  UseBeta: true
+  UseBias: 0
+  UseE: false
+  UseGateResidual: false
+  UseInitialStridesAB: false
+  UseInitialStridesCD: false
+  UseScaleAB: ''
+  UseScaleAlphaVec: 0
+  UseScaleCD: false
+  isMixMode: false
+- - SolutionIndex: 0
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+    ActivationFuncCall: false
+    AdaptiveGemm: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgVnvJ6vTJ2S1GnFjpav5NRXpELKApdvuNrVCUIQ269iE=
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CustomKernel:
+      args:
+      - {type: uint32, semantic: GemmInfo}
+      - {type: uint32, semantic: InternalArgs}
+      - {type: uint32, semantic: InternalArgs1}
+      - {type: uint32, semantic: NumWorkGroups}
+      - {type: uint32, semantic: SizeFree0}
+      - {type: uint32, semantic: SizeFree1}
+      - {type: uint32, semantic: SizeFree2}
+      - {type: uint32, semantic: SizeSum}
+      - {type: address, semantic: AddressD}
+      - {type: address, semantic: AddressC}
+      - {type: address, semantic: AddressA}
+      - {type: address, semantic: AddressMXScaleA}
+      - {type: address, semantic: AddressB}
+      - {type: address, semantic: AddressMXScaleB}
+      - {type: uint32, semantic: StrideD0}
+      - {type: uint32, semantic: StrideD1}
+      - {type: uint32, semantic: StrideC0}
+      - {type: uint32, semantic: StrideC1}
+      - {type: uint32, semantic: StrideA0}
+      - {type: uint32, semantic: StrideA1}
+      - {type: uint32, semantic: StrideScaleA0}
+      - {type: uint32, semantic: StrideScaleA1}
+      - {type: uint32, semantic: StrideB0}
+      - {type: uint32, semantic: StrideB1}
+      - {type: uint32, semantic: StrideScaleB0}
+      - {type: uint32, semantic: StrideScaleB1}
+      - {type: uint32, semantic: Alpha}
+      - {type: uint32, semantic: Beta}
+      generated: true
+      grid: [TilesXYBatchGSU, One, One]
+      macrotile: [256, 256, 256]
+      name: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT256x256x256_MI16x16x1_SN_LDSB0_AFC0_AG1_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLL0_FDSI0_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR1_ISA1250_ICIW0_IU1_K1_LDSTI1_LBSPPA1024_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT8_8_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS2_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB1_SIA4_SS1_SPO1_SRVW0_SSO0_SVW4_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA2_THB6_THC4_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS2_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO1_USI0_VSn1_VWA4_VWB4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGMXCC1
+      threads: [128, 1, 1]
+      workspaceSizePerElemBias: 0
+      workspaceSizePerElemC: 0
+      workspaceType: None
+    DepthU: 256
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraMiLatencyLeft: 0
+    ForceUnrollSubIter: false
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalWriteVectorWidth: 4
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 1
+    HalfPLRA: true
+    HalfPLRB: false
+    ISA: [12, 5, 0]
+    InitCIterWmma: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    LDSSegInterleaveOffsets: null
+    LDSTrInst: true
+    LSCA: 256
+    LSCB: 256
+    LSCMXSA: 8
+    LSCMXSB: 8
+    LSPA: 64
+    LSPB: 64
+    LSPMXSA: 64
+    LSPMXSB: 64
+    LVCA: 256
+    LVCB: 256
+    LVCMXSA: 8
+    LVCMXSB: 8
+    LVPA: 64
+    LVPB: 64
+    LVPMXSA: 64
+    LVPMXSB: 64
+    LdsBlockSizePerPadA: 1024
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBytesNoAmax: 274432
+    LdsInitCVgprs: false
+    LdsNumBytes: 274432
+    LdsNumElementsAlignedA: 66560
+    LdsNumElementsAlignedB: 66560
+    LdsNumElementsAlignedMXSA: 2048
+    LdsNumElementsAlignedMXSB: 2048
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 137216
+    LdsOffsetB: 70656
+    LdsOffsetB_Blk: 207872
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 66560
+    LdsOffsetMXSA_Blk: 203776
+    LdsOffsetMXSB: 68608
+    LdsOffsetMXSB_Blk: 205824
+    LdsOffsetMetadata: 70656
+    LdsOffsetMetadata_Blk: 207872
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 2
+    LoopUnroll: 256
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [2, 2]
+    MIWaveTile: [8, 8]
+    MIWaveTileA: 8
+    MIWaveTileB: 8
+    MIWaveTileMXSA: 8
+    MIWaveTileMXSB: 8
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 256
+    MacroTile1: 256
+    MacroTileA: 256
+    MacroTileB: 256
+    MacroTileMXSA: 256
+    MacroTileMXSB: 256
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NumElementsPerBatchStore: 2
+    NumElementsPerThread: 512
+    NumGlobalWriteVectorsPerThread: 128
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchGlobalRead: 2
+    ScheduleGROverBarrier: 1
+    ScheduleIterAlg: 4
+    SourceSwap: true
+    StaggerU: 0
+    StorePriorityOpt: true
+    StoreSwapAddr: true
+    StoreVectorWidth: 4
+    SubGroup0: 4
+    SubGroup1: 32
+    SubGroupA: 4
+    SubGroupB: 32
+    SubGroupMXSA: 4
+    SubGroupMXSB: 32
+    SuppressNoLoadLoop: true
+    TDMInst: 3
+    TemporalHintA: 2
+    TemporalHintB: 6
+    TemporalHintC: 4
+    ThreadTile: [1, 1]
+    ThreadTile0: 64
+    ThreadTile1: 8
+    ThreadTileA: 64
+    ThreadTileB: 8
+    ThreadTileMXSA: 64
+    ThreadTileMXSB: 8
+    TransposeLDS: 2
+    ULSGRODoubleG2L: 0
+    UnrollMajorLDSA: 1
+    UnrollMajorLDSB: 1
+    UnrollMajorLDSMXSA: 1
+    UnrollMajorLDSMXSB: 1
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseMFMAF32XEmulation: false
+    UseSgprForGRO: 1
+    Valid: true
+    VectorWidthA: 4
+    VectorWidthB: 4
+    VectorWidthMXSA: 4
+    VectorWidthMXSB: 4
+    WaveSeparateGlobalReadA: 1
+    WaveSeparateGlobalReadB: 1
+    WaveSeparateGlobalReadMXSA: 1
+    WaveSeparateGlobalReadMXSB: 1
+    WavefrontSize: 32
+    WorkGroup: [32, 4, 1]
+    WorkGroupMapping: -4
+    WorkGroupMappingXCC: 8
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 256
+    _DepthUA: 256
+    _DepthUB: 256
+    _DepthUMXSA: 8
+    _DepthUMXSB: 8
+    _DepthUMetadata: 256
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 1
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: true
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 66560
+    ldsNumBytesB: 66560
+    ldsNumBytesMXSA: 2048
+    ldsNumBytesMXSB: 2048
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+  - 1LDSBuffer: 0
+    ActivationAlt: false
+    ActivationFuncCall: false
+    ActivationFused: true
+    AdaptiveGemm: 0
+    AdaptiveGemmGSUA: 0
+    AdaptiveGemmNTAB: 0
+    AssertAIGreaterThanEqual: -1
+    AssertAILessThanEqual: -1
+    AssertFree0ElementMultiple: 1
+    AssertFree1ElementMultiple: 1
+    AssertSummationElementMultiple: 32
+    AssignedDerivedParameters: true
+    AssignedProblemIndependentDerivedParameters: true
+    BaseName: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArg3I_K79pFqJah_TTy1aco2e4lmeHGn8O_KDI1sVtnLJo=
+    BufferLoad: true
+    BufferStore: true
+    CUCount: null
+    CUOccupancy: -1
+    ClusterBarrier: false
+    ClusterDim: [1, 1]
+    ClusterLocalRead: 0
+    CodeObjectVersion: '4'
+    CompactLoopStore: false
+    ConvertAfterDS: false
+    CustomKernelName: ''
+    DebugPersistentKernelLoopForever: false
+    DebugStreamK: 0
+    DepthU: 512
+    DirectToLds: 0
+    DirectToLdsA: false
+    DirectToLdsB: false
+    DirectToLdsMXSA: false
+    DirectToLdsMXSB: false
+    DirectToLdsMetadata: 0
+    DirectToVgprA: false
+    DirectToVgprB: false
+    DirectToVgprMXSA: false
+    DirectToVgprMXSB: false
+    DirectToVgprSparseMetadata: false
+    DtlPlusLdsBuf: 0
+    ESMRuntimeGate: false
+    EdgeType: None
+    EnableESM2TrackValuVsrc: false
+    EnableF32XdlMathOp: false
+    EnableMatrixInstruction: true
+    EnableStinkyTofuESM2: true
+    ExpandPointerSwap: false
+    ExpertSchedulingMode: 0
+    ExtraLatencyForLR: 0
+    ExtraMiLatencyLeft: -1
+    ForceDisableShadowInit: true
+    ForceUnrollSubIter: false
+    GlobalReadPerMfma: 1.0
+    GlobalReadVectorWidthA: 1
+    GlobalReadVectorWidthB: 1
+    GlobalReadVectorWidthMXSA: 1
+    GlobalReadVectorWidthMXSB: 1
+    GlobalSplitU: 1
+    GlobalSplitUAlgorithm: MultipleBuffer
+    GlobalSplitUCoalesced: false
+    GlobalSplitUWorkGroupMappingRoundRobin: false
+    GlobalWriteVectorWidth: 1
+    GroupLoadStore: false
+    GuaranteeNoPartialA: true
+    GuaranteeNoPartialB: true
+    GuaranteeNoPartialMetadata: true
+    HalfPLR: 2
+    HalfPLRA: false
+    HalfPLRB: true
+    ISA: [12, 5, 0]
+    InitCIterWmma: 1
+    InnerUnroll: 1
+    InterleaveAlpha: 0
+    InternalSupportParams: {KernArgsVersion: 2, SupportCustomStaggerU: true, SupportCustomWGM: true, SupportUserGSU: true, UseSFC: false, UseUniversalArgs: true}
+    Kernel: true
+    KernelLanguage: Assembly
+    KernelNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSUAMB_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGMXCC1
+    LDSSegInterleaveOffsets: null
+    LDSSegmentInterleave: 0
+    LDSTrInst: true
+    LSCA: 512
+    LSCB: 512
+    LSCMXSA: 16
+    LSCMXSB: 16
+    LSPA: 32
+    LSPB: 256
+    LSPMXSA: 32
+    LSPMXSB: 256
+    LVCA: 512
+    LVCB: 512
+    LVCMXSA: 16
+    LVCMXSB: 16
+    LVPA: 32
+    LVPB: 256
+    LVPMXSA: 32
+    LVPMXSB: 256
+    LdsBlockSizePerPadA: 512
+    LdsBlockSizePerPadB: 1024
+    LdsBlockSizePerPadMXSA: 0
+    LdsBlockSizePerPadMXSB: 0
+    LdsBlockSizePerPadMetadata: 0
+    LdsBytesNoAmax: 309248
+    LdsInitCVgprs: false
+    LdsNumBytes: 309248
+    LdsNumElementsAlignedA: 16896
+    LdsNumElementsAlignedB: 133120
+    LdsNumElementsAlignedMXSA: 512
+    LdsNumElementsAlignedMXSB: 4096
+    LdsNumElementsAlignedMetadata: 0
+    LdsOffsetA: 0
+    LdsOffsetA_Blk: 154624
+    LdsOffsetB: 21504
+    LdsOffsetB_Blk: 176128
+    LdsOffsetBias: 0
+    LdsOffsetBiasGSU: 0
+    LdsOffsetBiasNonGSU: 0
+    LdsOffsetMXSA: 16896
+    LdsOffsetMXSA_Blk: 171520
+    LdsOffsetMXSB: 17408
+    LdsOffsetMXSB_Blk: 172032
+    LdsOffsetMetadata: 21504
+    LdsOffsetMetadata_Blk: 176128
+    LdsPadA: 16
+    LdsPadB: 16
+    LdsPadMXSA: 0
+    LdsPadMXSB: 0
+    LdsPadMetadata: 0
+    LocalReadVectorWidth: -1
+    LocalReadVectorWidthA: 16
+    LocalReadVectorWidthB: 16
+    LocalReadVectorWidthMXS: 4
+    LocalSplitU: 1
+    LocalSplitUReuseLDS: 1
+    LocalWritePerMfma: -1
+    LocalWriteUseSgprA: false
+    LocalWriteUseSgprB: false
+    LocalWriteUseSgprMXSA: false
+    LocalWriteUseSgprMXSB: false
+    LocalWriteUseSgprMetadata: false
+    LoopIters: 4
+    LoopUnroll: 512
+    MFMA_BF16_1K: 0
+    MIArchVgpr: true
+    MIBlock: [16, 16, 128, 1, 1, 1]
+    MIInputPerThread: 64
+    MIInputPerThreadA: 64
+    MIInputPerThreadB: 64
+    MIInputPerThreadMXSA: 4
+    MIInputPerThreadMXSB: 4
+    MIInputPerThreadMetadata: 64
+    MIOutputVectorWidth: 8
+    MIRegPerOut: 1
+    MIWaveGroup: [1, 4]
+    MIWaveTile: [2, 4]
+    MIWaveTileA: 2
+    MIWaveTileB: 4
+    MIWaveTileMXSA: 2
+    MIWaveTileMXSB: 4
+    MIWaveTileMetadata: 0
+    MXLoadInst: TDM
+    MXScaleFormat: InMemorySwizzle
+    MacroTile0: 32
+    MacroTile1: 256
+    MacroTileA: 32
+    MacroTileB: 256
+    MacroTileMXSA: 32
+    MacroTileMXSB: 256
+    MagicDivAlg: 2
+    MathClocksUnrolledLoop: 0
+    MatrixInstB: 1
+    MatrixInstBM: 1
+    MatrixInstBN: 1
+    MatrixInstK: 128
+    MatrixInstM: 16
+    MatrixInstN: 16
+    MatrixInstruction: [16, 16, 128, 1]
+    MaxLDS: 327680
+    MaxOccupancy: 40
+    MbskPrefetchMethod: 0
+    MfmaInitCVgprs: false
+    MinGRIncPerMfma: 1
+    Multicast: false
+    NoLdsWriteCode: true
+    NoReject: false
+    NoTailLoop: false
+    NonDTLTailLoopA: false
+    NonDTLTailLoopB: false
+    NonDTLTailLoopMXSA: false
+    NonDTLTailLoopMXSB: false
+    NonDTLTailLoopMetadata: false
+    NonTemporal: -1
+    NonTemporalA: 0
+    NonTemporalB: 0
+    NonTemporalC: 0
+    NonTemporalD: 0
+    NonTemporalE: 0
+    NonTemporalGate: 0
+    NonTemporalMXSA: 0
+    NonTemporalMXSB: 0
+    NonTemporalMetadata: 0
+    NonTemporalWS: 0
+    NonVolatile: -1
+    NonVolatileA: 0
+    NonVolatileB: 0
+    NonVolatileC: 0
+    NonVolatileD: 0
+    NonVolatileE: 0
+    NonVolatileMXSA: 0
+    NonVolatileMXSB: 0
+    NonVolatileMetadata: 0
+    NonVolatileWS: 0
+    NumElementsPerBatchStore: 0
+    NumElementsPerThread: 64
+    NumGlobalWriteVectorsPerThread: 64
+    NumLdsBlk: 2
+    NumLoadsA: 1
+    NumLoadsB: 1
+    NumLoadsCoalescedA: 1
+    NumLoadsCoalescedB: 1
+    NumLoadsCoalescedMXSA: 1
+    NumLoadsCoalescedMXSB: 1
+    NumLoadsMXSA: 1
+    NumLoadsMXSB: 1
+    NumLoadsPerpendicularA: 1
+    NumLoadsPerpendicularB: 1
+    NumLoadsPerpendicularMXSA: 1
+    NumLoadsPerpendicularMXSB: 1
+    NumThreads: 128
+    NumTotalPackedLoadsA: -1
+    NumTotalPackedLoadsB: -1
+    NumTotalPackedLoadsMXSA: -1
+    NumTotalPackedLoadsMXSB: -1
+    NumWaveSplitK: 1
+    NumWaves: 4
+    OptNoLoadLoop: 1
+    PackedC0IdxChars: [I]
+    PackedC0IndicesX: [0]
+    PackedC1IdxChars: [J]
+    PackedC1IndicesX: [1]
+    PrefetchAcrossPersistent: 0
+    PrefetchGL2: 0
+    PrefetchGlobalRead: 2
+    PrefetchLocalRead: 1
+    PreloadKernArgs: true
+    SFCWGM:
+    - [1, 1]
+    - [1, 1]
+    ScheduleGROverBarrier: 0
+    ScheduleGlobalRead: 1
+    ScheduleIterAlg: 4
+    ScheduleLocalWrite: 1
+    SolutionIndex: 1
+    SolutionNameMin: Cijk_Alik_Bljk_F8BS_MXAE8B32_MXBE8B32_BH_UserArgs_MT32x256x512_MI16x16x1_SN_LDSB0_AFC0_AG0_AGGSUA0_AGNTAB0_AFEM1_AFEM1_ASEM32_BL1_BS1_CD1_1_CLR0_CLS0_CADS0_DTLA0_DTLB0_DTLM0_DTVA0_DTVB0_DTVMXSA0_DTVMXSB0_DTVSM0_DPLB0_EPS0_ELFLR0_EMLLn1_FDSI1_GRPM1_GRVWA1_GRVWB1_GSU1_GSUAMB_GSUC0_GSUWGMRR0_GLS0_HPLR2_ISA1250_ICIW1_IU1_K1_LDSTI1_LBSPPA512_LBSPPB1024_LBSPPMXSA0_LBSPPMXSB0_LBSPPM0_LPA16_LPB16_LPMXSA0_LPMXSB0_LPM0_LRVWn1_LWPMn1_MIAV1_MIWT2_4_MXLITDM_MXSFIMS_MO40_MGRIPM1_NTn1_NTA0_NTB0_NTC0_NTD0_NTE0_NTMXSA0_NTMXSB0_NTM0_NTWS0_NVn1_NVA0_NVB0_NVC0_NVD0_NVE0_NVMXSA0_NVMXSB0_NVM0_NVWS0_NEPBS0_NLCA1_NLCB1_ONLL1_PAP0_PGL0_PGR2_PLR1_PKA1_SGROB0_SIA4_SS1_SU32_SUM0_SUS512_SPO0_SRVW0_SSO0_SVW1_SK0_SKFTR0_SKFDPO0_SKWS0_SKXCCM0_SNLL1_SIP1_SGRO0_TDMI3_TDMIM0_TDMLWS0_TDMPLB0_TDMS0_TIN0_THn1_THA0_THB0_THC0_THD0_THE0_THMXSA0_THMXSB0_THM0_THWS0_TLDS1_TLDSMn1_ULSGRO0_USL1_USLMX0_UDFMAC0_UIOFGRO0_UPLRP0_USFGRO0_USI0_VSn1_VWA1_VWB2_WSGRA0_WSGRB0_WS32_WG16_8_1_WGM1_WGMXCC1_WGMXCCGn1
+    SourceSwap: true
+    SpaceFillingAlgo: []
+    StaggerU: 32
+    StaggerUMapping: 0
+    StaggerUStride: 512
+    StorePriorityOpt: false
+    StoreRemapVectorWidth: 0
+    StoreSwapAddr: true
+    StoreSyncOpt: 0
+    StoreVectorWidth: 1
+    StreamK: 0
+    StreamKAtomic: 0
+    StreamKFixupTreeReduction: 0
+    StreamKForceDPOnly: 0
+    StreamKWorkStealing: 0
+    StreamKXCCMapping: 0
+    SubGroup0: 2
+    SubGroup1: 64
+    SubGroupA: 2
+    SubGroupB: 64
+    SubGroupMXSA: 2
+    SubGroupMXSB: 64
+    SuppressNoLoadLoop: true
+    SwInstructionPrefetch: 1
+    SwapGlobalReadOrder: 0
+    TDMInst: 3
+    TDMIterateMode: 0
+    TDMLoadWaveSync: false
+    TDMPlusLdsBuf: 0
+    TDMSplit: false
+    TailloopInNll: false
+    TemporalHint: -1
+    TemporalHintA: 0
+    TemporalHintB: 0
+    TemporalHintC: 0
+    TemporalHintD: 0
+    TemporalHintE: 0
+    TemporalHintMXSA: 0
+    TemporalHintMXSB: 0
+    TemporalHintMetadata: 0
+    TemporalHintWS: 0
+    ThreadTile: [1, 1]
+    ThreadTile0: 16
+    ThreadTile1: 4
+    ThreadTileA: 16
+    ThreadTileB: 4
+    ThreadTileMXSA: 16
+    ThreadTileMXSB: 4
+    TransposeLDS: 1
+    TransposeLDSMetadata: -1
+    ULSGRODoubleG2L: 0
+    UnrollLoopSwapGlobalReadOrder: 0
+    UnrollMajorLDSA: true
+    UnrollMajorLDSB: true
+    UnrollMajorLDSMXSA: true
+    UnrollMajorLDSMXSB: true
+    Use64bShadowLimit: true
+    Use64bShadowLimitMX: false
+    UseCustomMainLoopSchedule: 0
+    UseDirect32XEmulation: false
+    UseDot2F32XEmulation: false
+    UseDotInstruction: false
+    UseDualFMAC: false
+    UseF32XEmulation: false
+    UseGeneralizedNLCOneA: false
+    UseGeneralizedNLCOneB: false
+    UseGeneralizedNLCOneMXSA: false
+    UseGeneralizedNLCOneMXSB: false
+    UseGeneralizedNLCOneMetadata: false
+    UseInstOffsetForGRO: 0
+    UseMFMAF32XEmulation: false
+    UsePLRPack: 0
+    UseSgprForGRO: 0
+    UseSubtileImpl: false
+    Valid: true
+    VectorStore: -1
+    VectorWidthA: 1
+    VectorWidthB: 2
+    VectorWidthMXSA: 1
+    VectorWidthMXSB: 2
+    WaveSeparateGlobalReadA: 0
+    WaveSeparateGlobalReadB: 0
+    WaveSeparateGlobalReadMXSA: 0
+    WaveSeparateGlobalReadMXSB: 0
+    WaveSeparateGlobalReadMetadata: 0
+    WaveSplitK: false
+    WavefrontSize: 32
+    WorkGroup: [16, 8, 1]
+    WorkGroupMapping: 1
+    WorkGroupMappingXCC: 1
+    WorkGroupMappingXCCGroup: -1
+    WorkGroupReduction: false
+    WorkspaceCheck: [4, 0, 1]
+    _DepthU: 512
+    _DepthUA: 512
+    _DepthUB: 512
+    _DepthUMXSA: 16
+    _DepthUMXSB: 16
+    _DepthUMetadata: 512
+    _GlobalAccumulation: MultipleBuffer
+    _ScheduleIterAlg: 0
+    _StinkyTofuOptLevel: 3
+    _UseSgprForGRO: 0
+    _VectorStore: 1
+    _WorkspaceSizePerElemBias: 0
+    _WorkspaceSizePerElemC: 4
+    _inputVWA_was_auto: false
+    _inputVWB_was_auto: true
+    _staggerStrideShift: 0
+    enableGLTrA: false
+    enableGLTrB: false
+    enableLDSTrA: false
+    enableLDSTrB: false
+    enableLDSTrMXSA: false
+    enableLDSTrMXSB: false
+    enableLDSTrMetadata: 0
+    enableTDMA: true
+    enableTDMB: true
+    enableTDMMetadata: false
+    ldsNumBytesA: 16896
+    ldsNumBytesB: 133120
+    ldsNumBytesMXSA: 512
+    ldsNumBytesMXSB: 4096
+    ldsNumBytesMetadata: 0
+    numSubTiles: 1
+    reorderGRInstForDTVA: false
+    reorderGRInstForDTVB: false
+    tailLoopOptA: false
+    tailLoopOptB: false
+    tailLoopOptMXSA: false
+    tailLoopOptMXSB: false
+- [2, 3, 0, 1]
+- - - [4096, 3072, 1, 65536]
+    - [0, 0.0]
+  - - [16, 49152, 1, 32768]
+    - [1, 0.0]
+- null
+- null
+- DeviceEfficiency
+- Equality