From 539e3d6c69fd61b9a72127b114e6fd645fd25689 Mon Sep 17 00:00:00 2001 From: Christudasan Devadasan Date: Thu, 26 Sep 2024 10:50:00 +0530 Subject: [PATCH] [AMDGPU] Merge the conditions used for deciding CS spills for amdgpu_cs_chain[_preserve] (#109911) Multiple conditions exist to decide whether callee save spills/restores are required for amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions. This patch consolidates them all and moves to a single place. Change-Id: Iceb4609d0b9505ea3ec09023887d4e9261d8d033 --- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 14 ++++---------- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 6 ++++-- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index bdd52e63aa5d14..9a155f60c7109e 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -1601,16 +1601,10 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized( SIMachineFunctionInfo *FuncInfo = MF.getInfo(); // Allocate spill slots for WWM reserved VGPRs. - // For chain functions, we only need to do this if we have calls to - // llvm.amdgcn.cs.chain. - bool IsChainWithoutCalls = - FuncInfo->isChainFunction() && !MF.getFrameInfo().hasTailCall(); - if (!FuncInfo->isEntryFunction() && !IsChainWithoutCalls) { - for (Register Reg : FuncInfo->getWWMReservedRegs()) { - const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); - FuncInfo->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC), - TRI->getSpillAlign(*RC)); - } + for (Register Reg : FuncInfo->getWWMReservedRegs()) { + const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); + FuncInfo->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC), + TRI->getSpillAlign(*RC)); } const bool SpillVGPRToAGPR = ST.hasMAIInsts() && FuncInfo->hasSpilledVGPRs() diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 3a5c1858fd8ebf..dd34427b6f5870 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -280,8 +280,10 @@ void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR, // amdgpu_cs_chain_preserve calling convention and this is a scratch register. // We never need to allocate a spill for these because we don't even need to // restore the inactive lanes for them (they're scratchier than the usual - // scratch registers). - if (isChainFunction() && SIRegisterInfo::isChainScratchRegister(VGPR)) + // scratch registers). We only need to do this if we have calls to + // llvm.amdgcn.cs.chain. + if (isChainFunction() && (SIRegisterInfo::isChainScratchRegister(VGPR) || + !MF.getFrameInfo().hasTailCall())) return; WWMSpills.insert(std::make_pair(