diff --git a/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aldebaran/110CU/Equality/aldebaran_Cijk_Ailk_Bljk_HHS_BH.yaml b/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aldebaran/110CU/Equality/aldebaran_Cijk_Ailk_Bljk_HHS_BH.yaml new file mode 100644 index 0000000000..edfcc13603 --- /dev/null +++ b/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aldebaran/110CU/Equality/aldebaran_Cijk_Ailk_Bljk_HHS_BH.yaml @@ -0,0 +1,3727 @@ +- {MinimumRequiredVersion: 4.33.0} +- aldebaran +- gfx90a +- [Device 0050, Device 0051, Device 0052, Device 0054, Device 0062, Device 7400, Device + 740c] +- Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false +- - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 32 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 32 + LSPA: 16 + LSPB: 16 + LVCA: 16 + LVCB: 4 + LVPA: 2 + LVPB: 2 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25088 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 32 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [2, 2] + MIWaveTileA: 2 + MIWaveTileB: 2 + MacroTile0: 128 + MacroTile1: 128 + MacroTileA: 128 + MacroTileB: 128 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 64 + NumGlobalWriteVectorsPerThread: 64 + NumLoadsA: 2 + NumLoadsB: 2 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 0 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x128x32_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS0_NLCA1_PLR5_SS0_SU4_SUS128_SVW4_VW1_WG64_4_1_WGM1 + SourceSwap: 0 + StaggerU: 4 + StaggerUMapping: 0 + StaggerUStride: 128 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 32 + ThreadTile1: 2 + ThreadTileA: 32 + ThreadTileB: 2 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 1 + _DepthULds: 32 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 1 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 32 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 32 + LSPA: 16 + LSPB: 16 + LVCA: 16 + LVCB: 4 + LVPA: 2 + LVPB: 2 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25088 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 32 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [2, 2] + MIWaveTileA: 2 + MIWaveTileB: 2 + MacroTile0: 128 + MacroTile1: 128 + MacroTileA: 128 + MacroTileB: 128 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 64 + NumGlobalWriteVectorsPerThread: 64 + NumLoadsA: 2 + NumLoadsB: 2 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 1 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x128x32_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS0_NLCA1_PLR5_SS0_SU4_SUS256_SVW4_VW1_WG64_4_1_WGM1 + SourceSwap: 0 + StaggerU: 4 + StaggerUMapping: 0 + StaggerUStride: 256 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 32 + ThreadTile1: 2 + ThreadTileA: 32 + ThreadTileB: 2 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 1 + _DepthULds: 32 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 2 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 64 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 + LVPA: 2 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] + MIWaveTileA: 2 + MIWaveTileB: 1 + MacroTile0: 128 + MacroTile1: 16 + MacroTileA: 128 + MacroTileB: 16 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 8 + NumLoadsA: 8 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 2 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU1_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS0_SU32_SUS128_SVW4_VW1_WG64_4_1_WGM8 + SourceSwap: 0 + StaggerU: 32 + StaggerUMapping: 0 + StaggerUStride: 128 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 8 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: false + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 32 + LSCB: 64 + LSPA: 64 + LSPB: 8 + LVCA: 4 + LVCB: 8 + LVPA: 8 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 12800 + LdsNumElementsAlignedA: 2048 + LdsNumElementsAlignedB: 2560 + LdsOffsetA: 0 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 2048 + LdsOffsetB_Blk: 10240 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [1, 1] + MIWaveTileA: 1 + MIWaveTileB: 1 + MacroTile0: 32 + MacroTile1: 32 + MacroTileA: 32 + MacroTileB: 32 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 4 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 1 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 3 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_GRVW8_GSU1_LPB16_LRVW8_MIWT1_1_NEPBS2_NLCA1_PLR5_SS0_SU0_SUS0_SVW4_VW1_WG32_8_1_WGM2 + SourceSwap: 0 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 4 + ThreadTile1: 1 + ThreadTileA: 4 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [32, 8, 1] + WorkGroupMapping: 2 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 7 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: false + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 32 + LSCB: 64 + LSPA: 64 + LSPB: 8 + LVCA: 4 + LVCB: 8 + LVPA: 8 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 12800 + LdsNumElementsAlignedA: 2048 + LdsNumElementsAlignedB: 2560 + LdsOffsetA: 0 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 2048 + LdsOffsetB_Blk: 10240 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [1, 1] + MIWaveTileA: 1 + MIWaveTileB: 1 + MacroTile0: 32 + MacroTile1: 32 + MacroTileA: 32 + MacroTileB: 32 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 4 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 1 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 4 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_GRVW8_GSU7_LPB16_LRVW8_MIWT1_1_NEPBS2_NLCA1_PLR5_SS0_SU0_SUS0_SVW4_VW1_WG32_8_1_WGM4 + SourceSwap: 0 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 4 + ThreadTile1: 1 + ThreadTileA: 4 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [32, 8, 1] + WorkGroupMapping: 4 + _DepthULds: 64 + _GlobalAccumulation: MultipleBuffer + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 28 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: false + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 32 + LSCB: 64 + LSPA: 64 + LSPB: 8 + LVCA: 4 + LVCB: 8 + LVPA: 8 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 12800 + LdsNumElementsAlignedA: 2048 + LdsNumElementsAlignedB: 2560 + LdsOffsetA: 0 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 2048 + LdsOffsetB_Blk: 10240 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [1, 1] + MIWaveTileA: 1 + MIWaveTileB: 1 + MacroTile0: 32 + MacroTile1: 32 + MacroTileA: 32 + MacroTileB: 32 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 4 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 1 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 5 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_GRVW8_GSU1_LPB16_LRVW8_MIWT1_1_NEPBS2_NLCA1_PLR5_SS0_SU0_SUS0_SVW4_VW1_WG32_8_1_WGM8 + SourceSwap: 0 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 4 + ThreadTile1: 1 + ThreadTileA: 4 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [32, 8, 1] + WorkGroupMapping: 8 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 64 + LSCB: 64 + LSPA: 32 + LSPB: 8 + LVCA: 8 + LVCB: 8 + LVPA: 4 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25088 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 8 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [1, 1] + MIWaveTileA: 1 + MIWaveTileB: 1 + MacroTile0: 64 + MacroTile1: 64 + MacroTileA: 64 + MacroTileB: 64 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 16 + NumGlobalWriteVectorsPerThread: 16 + NumLoadsA: 2 + NumLoadsB: 2 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 9 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 6 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT64x64x64_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT1_1_NEPBS0_NLCA1_PLR9_SS0_SU0_SUS0_SVW4_VW1_WG64_4_1_WGM8 + SourceSwap: 0 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 16 + ThreadTile1: 1 + ThreadTileA: 16 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 8 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 64 + LSPA: 16 + LSPB: 8 + LVCA: 16 + LVCB: 8 + LVPA: 2 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 31488 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 6912 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 8 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [1, 3] + MIWaveTileA: 1 + MIWaveTileB: 3 + MacroTile0: 128 + MacroTile1: 96 + MacroTileA: 128 + MacroTileB: 96 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 48 + NumGlobalWriteVectorsPerThread: 48 + NumLoadsA: 4 + NumLoadsB: 3 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 4 + NumLoadsPerpendicularB: 3 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 9 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 7 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x96x64_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT1_3_NEPBS0_NLCA1_PLR9_SS0_SU4_SUS128_SVW4_VW1_WG128_2_1_WGM8 + SourceSwap: 0 + StaggerU: 4 + StaggerUMapping: 0 + StaggerUStride: 128 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 16 + ThreadTile1: 3 + ThreadTileA: 16 + ThreadTileB: 3 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [128, 2, 1] + WorkGroupMapping: 8 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 64 + LSPA: 16 + LSPB: 8 + LVCA: 16 + LVCB: 8 + LVPA: 2 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 31488 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 6912 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 8 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [1, 3] + MIWaveTileA: 1 + MIWaveTileB: 3 + MacroTile0: 128 + MacroTile1: 96 + MacroTileA: 128 + MacroTileB: 96 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 48 + NumGlobalWriteVectorsPerThread: 48 + NumLoadsA: 4 + NumLoadsB: 3 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 4 + NumLoadsPerpendicularB: 3 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 9 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 8 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x96x64_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT1_3_NEPBS0_NLCA1_PLR9_SS0_SU32_SUS128_SVW4_VW1_WG128_2_1_WGM8 + SourceSwap: 0 + StaggerU: 32 + StaggerUMapping: 0 + StaggerUStride: 128 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 16 + ThreadTile1: 3 + ThreadTileA: 16 + ThreadTileB: 3 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [128, 2, 1] + WorkGroupMapping: 8 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 1 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 32 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: false + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 32 + LSPA: 8 + LSPB: 8 + LVCA: 32 + LVCB: 8 + LVPA: 2 + LVPB: 2 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 7552 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 3456 + LdsOffsetA: 0 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 12288 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 32 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [1, 3] + MIWaveTileA: 1 + MIWaveTileB: 3 + MacroTile0: 128 + MacroTile1: 96 + MacroTileA: 128 + MacroTileB: 96 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 48 + NumGlobalWriteVectorsPerThread: 48 + NumLoadsA: 4 + NumLoadsB: 3 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 4 + NumLoadsPerpendicularB: 3 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 9 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x96x32_MI32x32x8x1_SN_1LDSB1_GRVW4_GSU1_LPB8_LRVW8_MIWT1_3_NEPBS2_NLCA1_PLR5_SS1_SU0_SUS0_SVW1_VW1_WG128_2_1_WGM8 + SourceSwap: 1 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 1 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 16 + ThreadTile1: 3 + ThreadTileA: 16 + ThreadTileB: 3 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [128, 2, 1] + WorkGroupMapping: 8 + _DepthULds: 32 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 1 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 32 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: false + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 32 + LSPA: 8 + LSPB: 8 + LVCA: 32 + LVCB: 8 + LVPA: 2 + LVPB: 2 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 7552 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 3456 + LdsOffsetA: 0 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 12288 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 32 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [1, 3] + MIWaveTileA: 1 + MIWaveTileB: 3 + MacroTile0: 128 + MacroTile1: 96 + MacroTileA: 128 + MacroTileB: 96 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 48 + NumGlobalWriteVectorsPerThread: 48 + NumLoadsA: 4 + NumLoadsB: 3 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 4 + NumLoadsPerpendicularB: 3 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 10 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x96x32_MI32x32x8x1_SN_1LDSB1_GRVW4_GSU1_LPB8_LRVW8_MIWT1_3_NEPBS2_NLCA1_PLR5_SS1_SU32_SUS256_SVW1_VW1_WG128_2_1_WGM8 + SourceSwap: 1 + StaggerU: 32 + StaggerUMapping: 0 + StaggerUStride: 256 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 1 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 16 + ThreadTile1: 3 + ThreadTileA: 16 + ThreadTileB: 3 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [128, 2, 1] + WorkGroupMapping: 8 + _DepthULds: 32 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 2 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 1 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 32 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 2 + GroupLoadStore: false + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 32 + LSPA: 16 + LSPB: 16 + LVCA: 16 + LVCB: 4 + LVPA: 2 + LVPB: 2 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 8704 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 32 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [2, 2] + MIWaveTileA: 2 + MIWaveTileB: 2 + MacroTile0: 128 + MacroTile1: 128 + MacroTileA: 128 + MacroTileB: 128 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 64 + NumGlobalWriteVectorsPerThread: 32 + NumLoadsA: 2 + NumLoadsB: 2 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 11 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_NLCA1_PLR5_SS1_SU32_SUS128_SVW2_VW2_WG64_4_1_WGM4 + SourceSwap: 1 + StaggerU: 32 + StaggerUMapping: 0 + StaggerUStride: 128 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 2 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 32 + ThreadTile1: 2 + ThreadTileA: 32 + ThreadTileB: 2 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 2 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 4 + _DepthULds: 32 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 1 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 1 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 32 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 8 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 2 + GroupLoadStore: false + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 32 + LSPA: 16 + LSPB: 16 + LVCA: 16 + LVCB: 4 + LVPA: 2 + LVPB: 2 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 8704 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 32 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [2, 2] + MIWaveTileA: 2 + MIWaveTileB: 2 + MacroTile0: 128 + MacroTile1: 128 + MacroTileA: 128 + MacroTileB: 128 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 64 + NumGlobalWriteVectorsPerThread: 32 + NumLoadsA: 2 + NumLoadsB: 2 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 12 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_NLCA1_PLR5_SS1_SU32_SUS128_SVW2_VW2_WG64_4_1_WGM8 + SourceSwap: 1 + StaggerU: 32 + StaggerUMapping: 0 + StaggerUStride: 128 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 2 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 32 + ThreadTile1: 2 + ThreadTileA: 32 + ThreadTileB: 2 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 2 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 8 + _DepthULds: 32 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 1 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 7 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 64 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 + LVPA: 2 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] + MIWaveTileA: 2 + MIWaveTileB: 1 + MacroTile0: 128 + MacroTile1: 16 + MacroTileA: 128 + MacroTileB: 16 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 8 + NumLoadsA: 8 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 13 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU7_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU4_SUS256_SVW1_VW1_WG64_4_1_WGM1 + SourceSwap: 1 + StaggerU: 4 + StaggerUMapping: 0 + StaggerUStride: 256 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 1 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 1 + _DepthULds: 64 + _GlobalAccumulation: MultipleBuffer + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 28 + _staggerStrideShift: 1 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 8 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 2 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 64 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 + LVPA: 2 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] + MIWaveTileA: 2 + MIWaveTileB: 1 + MacroTile0: 128 + MacroTile1: 16 + MacroTileA: 128 + MacroTileB: 16 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 8 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 14 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU8_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU0_SUS0_SVW2_VW2_WG64_4_1_WGM2 + SourceSwap: 1 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 2 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 2 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 2 + _DepthULds: 64 + _GlobalAccumulation: MultipleBuffer + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 32 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 1 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 64 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 + LVPA: 2 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] + MIWaveTileA: 2 + MIWaveTileB: 1 + MacroTile0: 128 + MacroTile1: 16 + MacroTileA: 128 + MacroTileB: 16 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 8 + NumLoadsA: 8 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 15 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU1_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU0_SUS0_SVW1_VW1_WG64_4_1_WGM4 + SourceSwap: 1 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 1 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 1 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 4 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 2 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 + LSCB: 64 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 + LVPA: 2 + LVPB: 1 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 + LdsPadA: 0 + LdsPadB: 16 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 64 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [16, 16, 16, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] + MIWaveTileA: 2 + MIWaveTileB: 1 + MacroTile0: 128 + MacroTile1: 16 + MacroTileA: 128 + MacroTileB: 16 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 8 + NumLoadsB: 1 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: false + ActivationComputeDataType: 4 + ActivationHPA: false + ActivationType: none + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: false + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 16 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU1_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU0_SUS0_SVW2_VW2_WG64_4_1_WGM4 + SourceSwap: 1 + StaggerU: 0 + StaggerUMapping: 0 + StaggerUStride: 0 + StorePriorityOpt: 0 + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 2 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 2 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 4 + _DepthULds: 64 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 0 + allowLRVWforTLUandMI: false +- [2, 3, 0, 1] +- - - [1104, 1, 1, 4608, 1104, 1104, 1104, 4608] + - [3, 230.567] + - - [1104, 16, 1, 4608, 1104, 1104, 1104, 4608] + - [5, 3641.53] + - - [1104, 1335, 1, 4608, 1104, 1104, 1104, 4608] + - [0, 103730.0] + - - [1104, 1408, 1, 4608, 1104, 1104, 1104, 4608] + - [1, 108409.0] + - - [4608, 1, 1, 320, 4608, 4608, 4608, 320] + - [2, 151.206] + - - [4608, 16, 1, 320, 4608, 4608, 4608, 320] + - [15, 2457.6] + - - [4608, 1335, 1, 320, 4608, 4608, 4608, 320] + - [9, 72266.2] + - - [4608, 1408, 1, 320, 4608, 4608, 4608, 320] + - [12, 79485.9] + - - [16, 1, 1, 4608, 16, 16, 16, 4608] + - [4, 3.74633] + - - [16, 16, 1, 4608, 16, 16, 16, 4608] + - [4, 56.7574] + - - [16, 1335, 1, 4608, 16, 16, 16, 4608] + - [3, 4400.33] + - - [16, 1408, 1, 4608, 16, 16, 16, 4608] + - [5, 4596.56] + - - [768, 1, 1, 4608, 768, 768, 768, 4608] + - [14, 162.396] + - - [768, 16, 1, 4608, 768, 768, 768, 4608] + - [13, 2446.55] + - - [768, 1335, 1, 4608, 768, 768, 768, 4608] + - [7, 91602.1] + - - [768, 1408, 1, 4608, 768, 768, 768, 4608] + - [8, 96238.0] + - - [4608, 1, 1, 768, 4608, 4608, 4608, 768] + - [6, 292.57] + - - [4608, 16, 1, 768, 4608, 4608, 4608, 768] + - [16, 4687.32] + - - [4608, 1335, 1, 768, 4608, 4608, 4608, 768] + - [10, 97371.8] + - - [4608, 1408, 1, 768, 4608, 4608, 4608, 768] + - [11, 103361.0] +- null +- null +- DeviceEfficiency +- null +- Equality \ No newline at end of file diff --git a/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aldebaran/110CU/Equality/aldebaran_Cijk_Ailk_Bljk_HHS_BH_Bias_AH.yaml b/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aldebaran/110CU/Equality/aldebaran_Cijk_Ailk_Bljk_HHS_BH_Bias_AH.yaml index cde2ff5e00..12e1ad3957 100644 --- a/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aldebaran/110CU/Equality/aldebaran_Cijk_Ailk_Bljk_HHS_BH_Bias_AH.yaml +++ b/library/src/amd_detail/rocblaslt/src/Tensile/Logic/asm_full/aldebaran/110CU/Equality/aldebaran_Cijk_Ailk_Bljk_HHS_BH_Bias_AH.yaml @@ -11,7 +11,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -59,7 +59,7 @@ UseInitialStridesAB: false UseInitialStridesCD: false - - 1LDSBuffer: 0 - ActivationFuncCall: true + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -86,7 +86,7 @@ GlobalReadVectorWidth: 8 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 2 + GlobalWriteVectorWidth: 1 GroupLoadStore: 0 GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -97,11 +97,11 @@ LSCA: 128 LSCB: 32 LSPA: 16 - LSPB: 64 + LSPB: 16 LVCA: 16 LVCB: 4 LVPA: 2 - LVPB: 8 + LVPB: 2 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 @@ -156,7 +156,7 @@ NonTemporalD: 0 NumElementsPerBatchStore: 0 NumElementsPerThread: 64 - NumGlobalWriteVectorsPerThread: 32 + NumGlobalWriteVectorsPerThread: 64 NumLoadsA: 2 NumLoadsB: 2 NumLoadsCoalescedA: 1 @@ -180,7 +180,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -231,15 +231,15 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 0 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB0_AFC1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS0_PLR5_SU4_SUS128_SPO0_SVW2_VW2_WG64_4_1_WGM4 - SourceSwap: 1 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS0_NLCA1_PLR5_SS0_SU4_SUS128_SVW4_VW1_WG64_4_1_WGM1 + SourceSwap: 0 StaggerU: 4 StaggerUMapping: 0 StaggerUStride: 128 StorePriorityOpt: 0 StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 2 + StoreVectorWidth: 4 SubGroup0: 4 SubGroup1: 64 SubGroupA: 4 @@ -258,12 +258,12 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 2 + VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 WorkGroup: [64, 4, 1] - WorkGroupMapping: 4 + WorkGroupMapping: 1 _DepthULds: 32 _GlobalAccumulation: null _UseSgprForGRO: 1 @@ -272,7 +272,7 @@ _staggerStrideShift: 1 allowLRVWforTLUandMI: false - 1LDSBuffer: 0 - ActivationFuncCall: true + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -283,7 +283,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 32 + DepthU: 64 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -293,13 +293,13 @@ EdgeType: ShiftPtr EnableMatrixInstruction: true ExpandPointerSwap: 0 - GlobalLoadVectorWidthA: 8 - GlobalLoadVectorWidthB: 8 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 GlobalReadPerMfma: 1 - GlobalReadVectorWidth: 8 + GlobalReadVectorWidth: 4 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 2 + GlobalWriteVectorWidth: 1 GroupLoadStore: 0 GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -308,55 +308,55 @@ InterleaveAlpha: 0 KernelLanguage: Assembly LSCA: 128 - LSCB: 32 - LSPA: 16 - LSPB: 64 - LVCA: 16 - LVCB: 4 + LSCB: 64 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 LVPA: 2 - LVPB: 8 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 25088 - LdsNumElementsAlignedA: 4096 - LdsNumElementsAlignedB: 4608 + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 LdsOffsetA: 0 LdsOffsetA_Blk: 16384 - LdsOffsetB: 4096 - LdsOffsetB_Blk: 20480 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 LdsPadA: 0 - LdsPadB: 8 + LdsPadB: 16 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false LoopIters: 4 - LoopUnroll: 32 + LoopUnroll: 64 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [32, 32, 8, 1, 1, 1] + MIBlock: [16, 16, 16, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 - MIWaveGroup: [2, 2] - MIWaveTile: [2, 2] + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] MIWaveTileA: 2 - MIWaveTileB: 2 + MIWaveTileB: 1 MacroTile0: 128 - MacroTile1: 128 + MacroTile1: 16 MacroTileA: 128 - MacroTileB: 128 + MacroTileB: 16 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 8 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 8, 1] + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -368,14 +368,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 0 - NumElementsPerThread: 64 - NumGlobalWriteVectorsPerThread: 32 - NumLoadsA: 2 - NumLoadsB: 2 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 8 + NumLoadsA: 8 + NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 2 - NumLoadsPerpendicularB: 2 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -393,7 +393,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -444,25 +444,25 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 1 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB0_AFC1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS0_PLR5_SU4_SUS256_SPO0_SVW2_VW2_WG64_4_1_WGM4 - SourceSwap: 1 - StaggerU: 4 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU1_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS0_SU0_SUS0_SVW4_VW1_WG64_4_1_WGM4 + SourceSwap: 0 + StaggerU: 0 StaggerUMapping: 0 - StaggerUStride: 256 + StaggerUStride: 0 StorePriorityOpt: 0 StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 2 - SubGroup0: 4 - SubGroup1: 64 - SubGroupA: 4 - SubGroupB: 64 + StoreVectorWidth: 4 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 32 - ThreadTile1: 2 - ThreadTileA: 32 - ThreadTileB: 2 + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -471,21 +471,21 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 2 + VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 WorkGroup: [64, 4, 1] WorkGroupMapping: 4 - _DepthULds: 32 + _DepthULds: 64 _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 2 + _staggerStrideShift: 0 allowLRVWforTLUandMI: false - - 1LDSBuffer: 1 - ActivationFuncCall: true + - 1LDSBuffer: 0 + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -496,7 +496,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 32 + DepthU: 64 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -512,7 +512,7 @@ GlobalReadVectorWidth: 8 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 2 + GlobalWriteVectorWidth: 1 GroupLoadStore: false GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -520,56 +520,56 @@ InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 128 - LSCB: 32 - LSPA: 16 - LSPB: 64 - LVCA: 16 - LVCB: 4 - LVPA: 2 - LVPB: 8 + LSCA: 32 + LSCB: 64 + LSPA: 64 + LSPB: 8 + LVCA: 4 + LVCB: 8 + LVPA: 8 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 8704 - LdsNumElementsAlignedA: 4096 - LdsNumElementsAlignedB: 4608 + LdsNumElements: 12800 + LdsNumElementsAlignedA: 2048 + LdsNumElementsAlignedB: 2560 LdsOffsetA: 0 - LdsOffsetA_Blk: 16384 - LdsOffsetB: 4096 - LdsOffsetB_Blk: 20480 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 2048 + LdsOffsetB_Blk: 10240 LdsPadA: 0 - LdsPadB: 8 + LdsPadB: 16 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false LoopIters: 4 - LoopUnroll: 32 + LoopUnroll: 64 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [32, 32, 8, 1, 1, 1] + MIBlock: [16, 16, 16, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [2, 2] - MIWaveTile: [2, 2] - MIWaveTileA: 2 - MIWaveTileB: 2 - MacroTile0: 128 - MacroTile1: 128 - MacroTileA: 128 - MacroTileB: 128 + MIWaveTile: [1, 1] + MIWaveTileA: 1 + MIWaveTileB: 1 + MacroTile0: 32 + MacroTile1: 32 + MacroTileA: 32 + MacroTileB: 32 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 8 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 8, 1] + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -581,14 +581,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 2 - NumElementsPerThread: 64 - NumGlobalWriteVectorsPerThread: 32 - NumLoadsA: 2 - NumLoadsB: 2 + NumElementsPerThread: 4 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 1 + NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 2 - NumLoadsPerpendicularB: 2 + NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -606,7 +606,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -657,25 +657,25 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 2 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_AFC1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_PLR5_SU0_SUS0_SPO1_SVW2_VW2_WG64_4_1_WGM4 - SourceSwap: 1 - StaggerU: 0 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_GRVW8_GSU1_LPB16_LRVW8_MIWT1_1_NEPBS2_NLCA1_PLR5_SS0_SU4_SUS128_SVW4_VW1_WG32_8_1_WGM1 + SourceSwap: 0 + StaggerU: 4 StaggerUMapping: 0 - StaggerUStride: 0 - StorePriorityOpt: 1 + StaggerUStride: 128 + StorePriorityOpt: false StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 2 - SubGroup0: 4 - SubGroup1: 64 - SubGroupA: 4 - SubGroupB: 64 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 32 - ThreadTile1: 2 - ThreadTileA: 32 - ThreadTileB: 2 + ThreadTile0: 4 + ThreadTile1: 1 + ThreadTileA: 4 + ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -684,21 +684,21 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 2 + VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [64, 4, 1] - WorkGroupMapping: 4 - _DepthULds: 32 + WorkGroup: [32, 8, 1] + WorkGroupMapping: 1 + _DepthULds: 64 _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 _WorkspaceSizePerElemC: 0 _staggerStrideShift: 0 allowLRVWforTLUandMI: false - - 1LDSBuffer: 1 - ActivationFuncCall: true + - 1LDSBuffer: 0 + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -709,7 +709,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 32 + DepthU: 64 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -725,7 +725,7 @@ GlobalReadVectorWidth: 8 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 2 + GlobalWriteVectorWidth: 1 GroupLoadStore: false GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -733,59 +733,59 @@ InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 128 - LSCB: 32 - LSPA: 16 - LSPB: 64 - LVCA: 16 - LVCB: 4 - LVPA: 2 - LVPB: 8 + LSCA: 32 + LSCB: 64 + LSPA: 64 + LSPB: 8 + LVCA: 4 + LVCB: 8 + LVPA: 8 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 8704 - LdsNumElementsAlignedA: 4096 - LdsNumElementsAlignedB: 4608 + LdsNumElements: 12800 + LdsNumElementsAlignedA: 2048 + LdsNumElementsAlignedB: 2560 LdsOffsetA: 0 - LdsOffsetA_Blk: 16384 - LdsOffsetB: 4096 - LdsOffsetB_Blk: 20480 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 2048 + LdsOffsetB_Blk: 10240 LdsPadA: 0 - LdsPadB: 8 + LdsPadB: 16 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false LoopIters: 4 - LoopUnroll: 32 + LoopUnroll: 64 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [32, 32, 8, 1, 1, 1] + MIBlock: [16, 16, 16, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [2, 2] - MIWaveTile: [2, 2] - MIWaveTileA: 2 - MIWaveTileB: 2 - MacroTile0: 128 - MacroTile1: 128 - MacroTileA: 128 - MacroTileB: 128 + MIWaveTile: [1, 1] + MIWaveTileA: 1 + MIWaveTileB: 1 + MacroTile0: 32 + MacroTile1: 32 + MacroTileA: 32 + MacroTileB: 32 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 8 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 8, 1] - MaxOccupancy: 40 - MaxVgprNumber: 256 - MinVgprNumber: 0 + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 NoLdsWriteCode: false NoReject: false NoTailLoop: false @@ -794,14 +794,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 2 - NumElementsPerThread: 64 - NumGlobalWriteVectorsPerThread: 32 - NumLoadsA: 2 - NumLoadsB: 2 + NumElementsPerThread: 4 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 1 + NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 2 - NumLoadsPerpendicularB: 2 + NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -819,7 +819,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -870,25 +870,25 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 3 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_AFC1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_PLR5_SU4_SUS128_SPO1_SVW2_VW2_WG64_4_1_WGM8 - SourceSwap: 1 - StaggerU: 4 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_GRVW8_GSU1_LPB16_LRVW8_MIWT1_1_NEPBS2_NLCA1_PLR5_SS0_SU32_SUS128_SVW4_VW1_WG32_8_1_WGM1 + SourceSwap: 0 + StaggerU: 32 StaggerUMapping: 0 StaggerUStride: 128 - StorePriorityOpt: 1 + StorePriorityOpt: false StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 2 - SubGroup0: 4 - SubGroup1: 64 - SubGroupA: 4 - SubGroupB: 64 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 32 - ThreadTile1: 2 - ThreadTileA: 32 - ThreadTileB: 2 + ThreadTile0: 4 + ThreadTile1: 1 + ThreadTileA: 4 + ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -897,21 +897,21 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 2 + VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [64, 4, 1] - WorkGroupMapping: 8 - _DepthULds: 32 + WorkGroup: [32, 8, 1] + WorkGroupMapping: 1 + _DepthULds: 64 _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 1 + _staggerStrideShift: 0 allowLRVWforTLUandMI: false - - 1LDSBuffer: 1 - ActivationFuncCall: true + - 1LDSBuffer: 0 + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -922,7 +922,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 32 + DepthU: 64 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -936,9 +936,9 @@ GlobalLoadVectorWidthB: 8 GlobalReadPerMfma: 1 GlobalReadVectorWidth: 8 - GlobalSplitU: 1 + GlobalSplitU: 7 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 2 + GlobalWriteVectorWidth: 1 GroupLoadStore: false GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -946,56 +946,56 @@ InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 128 - LSCB: 32 - LSPA: 16 - LSPB: 64 - LVCA: 16 - LVCB: 4 - LVPA: 2 - LVPB: 8 + LSCA: 32 + LSCB: 64 + LSPA: 64 + LSPB: 8 + LVCA: 4 + LVCB: 8 + LVPA: 8 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 8704 - LdsNumElementsAlignedA: 4096 - LdsNumElementsAlignedB: 4608 + LdsNumElements: 12800 + LdsNumElementsAlignedA: 2048 + LdsNumElementsAlignedB: 2560 LdsOffsetA: 0 - LdsOffsetA_Blk: 16384 - LdsOffsetB: 4096 - LdsOffsetB_Blk: 20480 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 2048 + LdsOffsetB_Blk: 10240 LdsPadA: 0 - LdsPadB: 8 + LdsPadB: 16 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false LoopIters: 4 - LoopUnroll: 32 + LoopUnroll: 64 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [32, 32, 8, 1, 1, 1] + MIBlock: [16, 16, 16, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [2, 2] - MIWaveTile: [2, 2] - MIWaveTileA: 2 - MIWaveTileB: 2 - MacroTile0: 128 - MacroTile1: 128 - MacroTileA: 128 - MacroTileB: 128 + MIWaveTile: [1, 1] + MIWaveTileA: 1 + MIWaveTileB: 1 + MacroTile0: 32 + MacroTile1: 32 + MacroTileA: 32 + MacroTileB: 32 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 8 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 8, 1] + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -1007,14 +1007,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 2 - NumElementsPerThread: 64 - NumGlobalWriteVectorsPerThread: 32 - NumLoadsA: 2 - NumLoadsB: 2 + NumElementsPerThread: 4 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 1 + NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 2 - NumLoadsPerpendicularB: 2 + NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -1032,7 +1032,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -1083,25 +1083,25 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 4 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_AFC1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_PLR5_SU4_SUS256_SPO1_SVW2_VW2_WG64_4_1_WGM8 - SourceSwap: 1 - StaggerU: 4 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_GRVW8_GSU7_LPB16_LRVW8_MIWT1_1_NEPBS2_NLCA1_PLR5_SS0_SU0_SUS0_SVW4_VW1_WG32_8_1_WGM1 + SourceSwap: 0 + StaggerU: 0 StaggerUMapping: 0 - StaggerUStride: 256 - StorePriorityOpt: 1 + StaggerUStride: 0 + StorePriorityOpt: false StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 2 - SubGroup0: 4 - SubGroup1: 64 - SubGroupA: 4 - SubGroupB: 64 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 32 - ThreadTile1: 2 - ThreadTileA: 32 - ThreadTileB: 2 + ThreadTile0: 4 + ThreadTile1: 1 + ThreadTileA: 4 + ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -1110,21 +1110,21 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 2 + VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [64, 4, 1] - WorkGroupMapping: 8 - _DepthULds: 32 - _GlobalAccumulation: null + WorkGroup: [32, 8, 1] + WorkGroupMapping: 1 + _DepthULds: 64 + _GlobalAccumulation: MultipleBuffer _UseSgprForGRO: 1 _VectorStore: 1 - _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 2 + _WorkspaceSizePerElemC: 28 + _staggerStrideShift: 0 allowLRVWforTLUandMI: false - 1LDSBuffer: 0 - ActivationFuncCall: false + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -1145,11 +1145,11 @@ EdgeType: ShiftPtr EnableMatrixInstruction: true ExpandPointerSwap: 0 - GlobalLoadVectorWidthA: 4 - GlobalLoadVectorWidthB: 4 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 GlobalReadPerMfma: 1 - GlobalReadVectorWidth: 4 - GlobalSplitU: 5 + GlobalReadVectorWidth: 8 + GlobalSplitU: 7 GlobalSplitUAlgorithm: MultipleBuffer GlobalWriteVectorWidth: 1 GroupLoadStore: false @@ -1159,25 +1159,25 @@ InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 64 + LSCA: 32 LSCB: 64 - LSPA: 16 - LSPB: 16 - LVCA: 16 - LVCB: 16 - LVPA: 4 - LVPB: 4 + LSPA: 64 + LSPB: 8 + LVCA: 4 + LVCB: 8 + LVPA: 8 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 13568 - LdsNumElementsAlignedA: 4096 - LdsNumElementsAlignedB: 1280 + LdsNumElements: 12800 + LdsNumElementsAlignedA: 2048 + LdsNumElementsAlignedB: 2560 LdsOffsetA: 0 LdsOffsetA_Blk: 8192 - LdsOffsetB: 4096 - LdsOffsetB_Blk: 12288 + LdsOffsetB: 2048 + LdsOffsetB_Blk: 10240 LdsPadA: 0 LdsPadB: 16 LocalReadVectorWidth: 8 @@ -1193,14 +1193,14 @@ MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 - MIWaveGroup: [4, 1] + MIWaveGroup: [2, 2] MIWaveTile: [1, 1] MIWaveTileA: 1 MIWaveTileB: 1 - MacroTile0: 64 - MacroTile1: 16 - MacroTileA: 64 - MacroTileB: 16 + MacroTile0: 32 + MacroTile1: 32 + MacroTileA: 32 + MacroTileB: 32 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 @@ -1222,11 +1222,11 @@ NumElementsPerBatchStore: 2 NumElementsPerThread: 4 NumGlobalWriteVectorsPerThread: 4 - NumLoadsA: 4 + NumLoadsA: 1 NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 4 + NumLoadsPerpendicularA: 1 NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 @@ -1245,7 +1245,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -1296,19 +1296,19 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 5 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT64x16x64_MI16x16x16x1_SN_1LDSB0_AFC0_GRVW4_GSU5_LPB16_LRVW8_MIWT1_1_NEPBS2_PLR5_SU4_SUS256_SPO1_SVW1_VW1_WG64_4_1_WGM4 - SourceSwap: 1 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_GRVW8_GSU7_LPB16_LRVW8_MIWT1_1_NEPBS2_NLCA1_PLR5_SS0_SU4_SUS128_SVW4_VW1_WG32_8_1_WGM2 + SourceSwap: 0 StaggerU: 4 StaggerUMapping: 0 - StaggerUStride: 256 - StorePriorityOpt: 1 + StaggerUStride: 128 + StorePriorityOpt: false StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 1 - SubGroup0: 16 - SubGroup1: 16 - SubGroupA: 16 - SubGroupB: 16 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 SuppressNoLoadLoop: false ThreadTile: [1, 1] ThreadTile0: 4 @@ -1325,19 +1325,19 @@ VectorStore: -1 VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [64, 4, 1] - WorkGroupMapping: 4 + WorkGroup: [32, 8, 1] + WorkGroupMapping: 2 _DepthULds: 64 _GlobalAccumulation: MultipleBuffer _UseSgprForGRO: 1 _VectorStore: 1 - _WorkspaceSizePerElemC: 20 - _staggerStrideShift: 1 + _WorkspaceSizePerElemC: 28 + _staggerStrideShift: 0 allowLRVWforTLUandMI: false - 1LDSBuffer: 0 - ActivationFuncCall: true + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -1358,70 +1358,70 @@ EdgeType: ShiftPtr EnableMatrixInstruction: true ExpandPointerSwap: 0 - GlobalLoadVectorWidthA: 4 - GlobalLoadVectorWidthB: 4 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 GlobalReadPerMfma: 1 - GlobalReadVectorWidth: 4 + GlobalReadVectorWidth: 8 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer GlobalWriteVectorWidth: 1 - GroupLoadStore: false + GroupLoadStore: 0 GuaranteeNoPartialA: true GuaranteeNoPartialB: true ISA: [9, 0, 10] InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 64 + LSCA: 128 LSCB: 64 LSPA: 16 - LSPB: 16 + LSPB: 8 LVCA: 16 - LVCB: 16 - LVPA: 4 - LVPB: 4 + LVCB: 8 + LVPA: 2 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 13568 - LdsNumElementsAlignedA: 4096 - LdsNumElementsAlignedB: 1280 + LdsNumElements: 31488 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 6912 LdsOffsetA: 0 - LdsOffsetA_Blk: 8192 - LdsOffsetB: 4096 - LdsOffsetB_Blk: 12288 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 LdsPadA: 0 - LdsPadB: 16 + LdsPadB: 8 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false - LoopIters: 4 + LoopIters: 8 LoopUnroll: 64 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [16, 16, 16, 1, 1, 1] + MIBlock: [32, 32, 8, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [4, 1] - MIWaveTile: [1, 1] + MIWaveTile: [1, 3] MIWaveTileA: 1 - MIWaveTileB: 1 - MacroTile0: 64 - MacroTile1: 16 - MacroTileA: 64 - MacroTileB: 16 + MIWaveTileB: 3 + MacroTile0: 128 + MacroTile1: 96 + MacroTileA: 128 + MacroTileB: 96 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 16 - MatrixInstM: 16 - MatrixInstN: 16 - MatrixInstruction: [16, 16, 16, 1] + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -1432,15 +1432,15 @@ NonTemporalB: 0 NonTemporalC: 0 NonTemporalD: 0 - NumElementsPerBatchStore: 2 - NumElementsPerThread: 4 - NumGlobalWriteVectorsPerThread: 4 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 48 + NumGlobalWriteVectorsPerThread: 48 NumLoadsA: 4 - NumLoadsB: 1 + NumLoadsB: 3 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 NumLoadsPerpendicularA: 4 - NumLoadsPerpendicularB: 1 + NumLoadsPerpendicularB: 3 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -1448,7 +1448,7 @@ PackedC1IdxChars: [J] PackedC1IndicesX: [1] PrefetchGlobalRead: 2 - PrefetchLocalRead: 5 + PrefetchLocalRead: 9 ProblemType: Activation: true ActivationComputeDataType: 0 @@ -1458,7 +1458,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -1509,25 +1509,25 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 6 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT64x16x64_MI16x16x16x1_SN_1LDSB0_AFC1_GRVW4_GSU1_LPB16_LRVW8_MIWT1_1_NEPBS2_PLR5_SU0_SUS0_SPO1_SVW1_VW1_WG64_4_1_WGM8 - SourceSwap: 1 - StaggerU: 0 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x96x64_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT1_3_NEPBS0_NLCA1_PLR9_SS0_SU4_SUS128_SVW4_VW1_WG128_2_1_WGM8 + SourceSwap: 0 + StaggerU: 4 StaggerUMapping: 0 - StaggerUStride: 0 - StorePriorityOpt: 1 + StaggerUStride: 128 + StorePriorityOpt: 0 StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 1 - SubGroup0: 16 - SubGroup1: 16 - SubGroupA: 16 - SubGroupB: 16 + StoreVectorWidth: 4 + SubGroup0: 8 + SubGroup1: 32 + SubGroupA: 8 + SubGroupB: 32 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 4 - ThreadTile1: 1 - ThreadTileA: 4 - ThreadTileB: 1 + ThreadTile0: 16 + ThreadTile1: 3 + ThreadTileA: 16 + ThreadTileB: 3 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -1538,9 +1538,9 @@ VectorStore: -1 VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [64, 4, 1] + WorkGroup: [128, 2, 1] WorkGroupMapping: 8 _DepthULds: 64 _GlobalAccumulation: null @@ -1550,7 +1550,7 @@ _staggerStrideShift: 0 allowLRVWforTLUandMI: false - 1LDSBuffer: 0 - ActivationFuncCall: true + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -1561,7 +1561,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 64 + DepthU: 32 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -1571,14 +1571,14 @@ EdgeType: ShiftPtr EnableMatrixInstruction: true ExpandPointerSwap: 0 - GlobalLoadVectorWidthA: 4 - GlobalLoadVectorWidthB: 4 + GlobalLoadVectorWidthA: 8 + GlobalLoadVectorWidthB: 8 GlobalReadPerMfma: 1 - GlobalReadVectorWidth: 4 + GlobalReadVectorWidth: 8 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer GlobalWriteVectorWidth: 2 - GroupLoadStore: 0 + GroupLoadStore: false GuaranteeNoPartialA: true GuaranteeNoPartialB: true ISA: [9, 0, 10] @@ -1586,55 +1586,55 @@ InterleaveAlpha: 0 KernelLanguage: Assembly LSCA: 128 - LSCB: 64 - LSPA: 8 + LSCB: 32 + LSPA: 16 LSPB: 16 - LVCA: 32 - LVCB: 16 + LVCA: 16 + LVCB: 4 LVPA: 2 - LVPB: 4 + LVPB: 2 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 25856 - LdsNumElementsAlignedA: 8192 - LdsNumElementsAlignedB: 1280 + LdsNumElements: 14592 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 2304 LdsOffsetA: 0 - LdsOffsetA_Blk: 16384 - LdsOffsetB: 8192 - LdsOffsetB_Blk: 24576 + LdsOffsetA_Blk: 8192 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 12288 LdsPadA: 0 - LdsPadB: 16 + LdsPadB: 8 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false LoopIters: 4 - LoopUnroll: 64 + LoopUnroll: 32 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [16, 16, 16, 1, 1, 1] + MIBlock: [32, 32, 8, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 - MIWaveGroup: [4, 1] + MIWaveGroup: [2, 2] MIWaveTile: [2, 1] MIWaveTileA: 2 MIWaveTileB: 1 MacroTile0: 128 - MacroTile1: 16 + MacroTile1: 64 MacroTileA: 128 - MacroTileB: 16 + MacroTileB: 64 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 16 - MatrixInstM: 16 - MatrixInstN: 16 - MatrixInstruction: [16, 16, 16, 1] + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -1645,14 +1645,14 @@ NonTemporalB: 0 NonTemporalC: 0 NonTemporalD: 0 - NumElementsPerBatchStore: 0 - NumElementsPerThread: 8 - NumGlobalWriteVectorsPerThread: 4 - NumLoadsA: 8 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 32 + NumGlobalWriteVectorsPerThread: 16 + NumLoadsA: 2 NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularA: 2 NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 @@ -1671,7 +1671,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -1722,24 +1722,24 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 7 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_AFC1_GRVW4_GSU1_LPB16_LRVW8_MIWT2_1_NEPBS0_PLR5_SU0_SUS0_SPO0_SVW2_VW2_WG64_4_1_WGM2 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x64x32_MI32x32x8x1_SN_1LDSB0_GRVW8_GSU1_LPB8_LRVW8_MIWT2_1_NEPBS2_NLCA1_PLR5_SS1_SU0_SUS0_SVW2_VW2_WG64_4_1_WGM8 SourceSwap: 1 StaggerU: 0 StaggerUMapping: 0 StaggerUStride: 0 - StorePriorityOpt: 0 + StorePriorityOpt: false StoreRemapVectorWidth: 0 StoreSyncOpt: 0 StoreVectorWidth: 2 - SubGroup0: 16 - SubGroup1: 16 - SubGroupA: 16 - SubGroupB: 16 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 8 + ThreadTile0: 32 ThreadTile1: 1 - ThreadTileA: 8 + ThreadTileA: 32 ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false @@ -1751,19 +1751,19 @@ VectorStore: -1 VectorWidth: 2 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 WorkGroup: [64, 4, 1] - WorkGroupMapping: 2 - _DepthULds: 64 + WorkGroupMapping: 8 + _DepthULds: 32 _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 _WorkspaceSizePerElemC: 0 _staggerStrideShift: 0 allowLRVWforTLUandMI: false - - 1LDSBuffer: 0 - ActivationFuncCall: true + - 1LDSBuffer: 1 + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -1774,7 +1774,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 64 + DepthU: 32 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -1790,7 +1790,7 @@ GlobalReadVectorWidth: 8 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 1 + GlobalWriteVectorWidth: 2 GroupLoadStore: false GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -1798,56 +1798,56 @@ InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 32 - LSCB: 64 - LSPA: 64 - LSPB: 32 - LVCA: 4 - LVCB: 8 - LVPA: 8 - LVPB: 4 + LSCA: 128 + LSCB: 32 + LSPA: 16 + LSPB: 16 + LVCA: 16 + LVCB: 4 + LVPA: 2 + LVPB: 2 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 12800 - LdsNumElementsAlignedA: 2048 - LdsNumElementsAlignedB: 2560 + LdsNumElements: 8704 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 LdsOffsetA: 0 - LdsOffsetA_Blk: 8192 - LdsOffsetB: 2048 - LdsOffsetB_Blk: 10240 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 LdsPadA: 0 - LdsPadB: 16 + LdsPadB: 8 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false LoopIters: 4 - LoopUnroll: 64 + LoopUnroll: 32 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [16, 16, 16, 1, 1, 1] + MIBlock: [32, 32, 8, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [2, 2] - MIWaveTile: [1, 1] - MIWaveTileA: 1 - MIWaveTileB: 1 - MacroTile0: 32 - MacroTile1: 32 - MacroTileA: 32 - MacroTileB: 32 + MIWaveTile: [2, 2] + MIWaveTileA: 2 + MIWaveTileB: 2 + MacroTile0: 128 + MacroTile1: 128 + MacroTileA: 128 + MacroTileB: 128 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 16 - MatrixInstM: 16 - MatrixInstN: 16 - MatrixInstruction: [16, 16, 16, 1] + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -1859,14 +1859,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 2 - NumElementsPerThread: 4 - NumGlobalWriteVectorsPerThread: 4 - NumLoadsA: 1 - NumLoadsB: 1 + NumElementsPerThread: 64 + NumGlobalWriteVectorsPerThread: 32 + NumLoadsA: 2 + NumLoadsB: 2 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 1 - NumLoadsPerpendicularB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -1884,7 +1884,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -1935,25 +1935,25 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 8 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_AFC1_GRVW8_GSU1_LPB16_LRVW8_MIWT1_1_NEPBS2_PLR5_SU0_SUS0_SPO1_SVW1_VW1_WG32_8_1_WGM2 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_NLCA1_PLR5_SS1_SU0_SUS0_SVW2_VW2_WG64_4_1_WGM1 SourceSwap: 1 StaggerU: 0 StaggerUMapping: 0 StaggerUStride: 0 - StorePriorityOpt: 1 + StorePriorityOpt: false StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 1 - SubGroup0: 8 - SubGroup1: 32 - SubGroupA: 8 - SubGroupB: 32 + StoreVectorWidth: 2 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 4 - ThreadTile1: 1 - ThreadTileA: 4 - ThreadTileB: 1 + ThreadTile0: 32 + ThreadTile1: 2 + ThreadTileA: 32 + ThreadTileB: 2 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -1962,21 +1962,21 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 1 + VectorWidth: 2 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [32, 8, 1] - WorkGroupMapping: 2 - _DepthULds: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 1 + _DepthULds: 32 _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 _WorkspaceSizePerElemC: 0 _staggerStrideShift: 0 allowLRVWforTLUandMI: false - - 1LDSBuffer: 0 - ActivationFuncCall: true + - 1LDSBuffer: 1 + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -1987,7 +1987,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 64 + DepthU: 32 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -2003,7 +2003,7 @@ GlobalReadVectorWidth: 8 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 1 + GlobalWriteVectorWidth: 2 GroupLoadStore: false GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -2011,56 +2011,56 @@ InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 32 - LSCB: 64 - LSPA: 64 - LSPB: 32 - LVCA: 4 - LVCB: 8 - LVPA: 8 - LVPB: 4 + LSCA: 128 + LSCB: 32 + LSPA: 16 + LSPB: 16 + LVCA: 16 + LVCB: 4 + LVPA: 2 + LVPB: 2 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 12800 - LdsNumElementsAlignedA: 2048 - LdsNumElementsAlignedB: 2560 + LdsNumElements: 8704 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 LdsOffsetA: 0 - LdsOffsetA_Blk: 8192 - LdsOffsetB: 2048 - LdsOffsetB_Blk: 10240 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 LdsPadA: 0 - LdsPadB: 16 + LdsPadB: 8 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false LoopIters: 4 - LoopUnroll: 64 + LoopUnroll: 32 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [16, 16, 16, 1, 1, 1] + MIBlock: [32, 32, 8, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [2, 2] - MIWaveTile: [1, 1] - MIWaveTileA: 1 - MIWaveTileB: 1 - MacroTile0: 32 - MacroTile1: 32 - MacroTileA: 32 - MacroTileB: 32 + MIWaveTile: [2, 2] + MIWaveTileA: 2 + MIWaveTileB: 2 + MacroTile0: 128 + MacroTile1: 128 + MacroTileA: 128 + MacroTileB: 128 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 16 - MatrixInstM: 16 - MatrixInstN: 16 - MatrixInstruction: [16, 16, 16, 1] + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -2072,14 +2072,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 2 - NumElementsPerThread: 4 - NumGlobalWriteVectorsPerThread: 4 - NumLoadsA: 1 - NumLoadsB: 1 + NumElementsPerThread: 64 + NumGlobalWriteVectorsPerThread: 32 + NumLoadsA: 2 + NumLoadsB: 2 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 1 - NumLoadsPerpendicularB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -2097,7 +2097,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -2148,25 +2148,25 @@ ScheduleIterAlg: 3 ScheduleLocalWrite: 1 SolutionIndex: 9 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_AFC1_GRVW8_GSU1_LPB16_LRVW8_MIWT1_1_NEPBS2_PLR5_SU0_SUS0_SPO1_SVW1_VW1_WG32_8_1_WGM4 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_NLCA1_PLR5_SS1_SU4_SUS256_SVW2_VW2_WG64_4_1_WGM4 SourceSwap: 1 - StaggerU: 0 + StaggerU: 4 StaggerUMapping: 0 - StaggerUStride: 0 - StorePriorityOpt: 1 + StaggerUStride: 256 + StorePriorityOpt: false StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 1 - SubGroup0: 8 - SubGroup1: 32 - SubGroupA: 8 - SubGroupB: 32 + StoreVectorWidth: 2 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 4 - ThreadTile1: 1 - ThreadTileA: 4 - ThreadTileB: 1 + ThreadTile0: 32 + ThreadTile1: 2 + ThreadTileA: 32 + ThreadTileB: 2 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -2175,21 +2175,21 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 1 + VectorWidth: 2 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [32, 8, 1] + WorkGroup: [64, 4, 1] WorkGroupMapping: 4 - _DepthULds: 64 + _DepthULds: 32 _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 0 + _staggerStrideShift: 2 allowLRVWforTLUandMI: false - - 1LDSBuffer: 0 - ActivationFuncCall: false + - 1LDSBuffer: 1 + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -2200,7 +2200,7 @@ BufferStore: true CodeObjectVersion: V3 CustomKernelName: '' - DepthU: 64 + DepthU: 32 DepthULdsDivisor: 1 DirectToLds: false DirectToLdsA: false @@ -2214,9 +2214,9 @@ GlobalLoadVectorWidthB: 8 GlobalReadPerMfma: 1 GlobalReadVectorWidth: 8 - GlobalSplitU: 8 + GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 1 + GlobalWriteVectorWidth: 2 GroupLoadStore: false GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -2224,25 +2224,238 @@ InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 32 + LSCA: 128 + LSCB: 32 + LSPA: 16 + LSPB: 16 + LVCA: 16 + LVCB: 4 + LVPA: 2 + LVPB: 2 + LdsBlockSizePerPad: 128 + LdsBlockSizePerPadA: 0 + LdsBlockSizePerPadB: 128 + LdsInitCVgprs: false + LdsNumElements: 8704 + LdsNumElementsAlignedA: 4096 + LdsNumElementsAlignedB: 4608 + LdsOffsetA: 0 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 4096 + LdsOffsetB_Blk: 20480 + LdsPadA: 0 + LdsPadB: 8 + LocalReadVectorWidth: 8 + LocalSplitU: 1 + LocalWritePerMfma: -1 + LocalWriteUseSgprA: false + LocalWriteUseSgprB: false + LoopIters: 4 + LoopUnroll: 32 + MFMA_BF16_1K: false + MIArchVgpr: false + MIBlock: [32, 32, 8, 1, 1, 1] + MIInputPerThread: 4 + MIOutputVectorWidth: 4 + MIRegPerOut: 1 + MIWaveGroup: [2, 2] + MIWaveTile: [2, 2] + MIWaveTileA: 2 + MIWaveTileB: 2 + MacroTile0: 128 + MacroTile1: 128 + MacroTileA: 128 + MacroTileB: 128 + MagicDivAlg: 2 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MatrixInstK: 8 + MatrixInstM: 32 + MatrixInstN: 32 + MatrixInstruction: [32, 32, 8, 1] + MaxOccupancy: 40 + MaxVgprNumber: 256 + MinVgprNumber: 0 + NoLdsWriteCode: false + NoReject: false + NoTailLoop: false + NonTemporalA: 0 + NonTemporalB: 0 + NonTemporalC: 0 + NonTemporalD: 0 + NumElementsPerBatchStore: 2 + NumElementsPerThread: 64 + NumGlobalWriteVectorsPerThread: 32 + NumLoadsA: 2 + NumLoadsB: 2 + NumLoadsCoalescedA: 1 + NumLoadsCoalescedB: 1 + NumLoadsPerpendicularA: 2 + NumLoadsPerpendicularB: 2 + NumThreads: 256 + OptNoLoadLoop: 1 + PackedC0IdxChars: [I] + PackedC0IndicesX: [0] + PackedC1IdxChars: [J] + PackedC1IndicesX: [1] + PrefetchGlobalRead: 2 + PrefetchLocalRead: 5 + ProblemType: + Activation: true + ActivationComputeDataType: 0 + ActivationHPA: true + ActivationType: all + AllowNoFreeDims: false + AssignedDerivedParameters: true + Batched: true + BetaOnlyUseBias: false + BiasDataTypeList: [0, 4] + ComplexConjugateA: false + ComplexConjugateB: false + ComputeDataType: 0 + DataType: 4 + DestDataType: 4 + Fp16AltImpl: false + HighPrecisionAccumulate: true + Index0: 0 + Index01A: 0 + Index01B: 1 + Index1: 1 + IndexAssignmentsA: [0, 3, 2] + IndexAssignmentsB: [3, 1, 2] + IndexAssignmentsLD: [4, 5, 6, 7] + IndexUnroll: 3 + IndexUnrollA: 1 + IndexUnrollB: 0 + IndicesBatch: [2] + IndicesFree: [0, 1] + IndicesSummation: [3] + MirrorDimsA: [] + MirrorDimsB: [] + NumIndicesBatch: 1 + NumIndicesC: 3 + NumIndicesFree: 2 + NumIndicesLD: 4 + NumIndicesSummation: 1 + OperationType: GEMM + SetConstStrideA: [] + SetConstStrideB: [] + SilentHighPrecisionAccumulate: false + StridedBatched: true + TLUA: true + TLUB: false + Tensor0: 0 + Tensor1: 1 + TileA: 0 + TileAwareSelection: false + TileB: 1 + TotalIndices: 4 + TransposeA: 0 + TransposeB: 0 + UseBeta: true + UseBias: true + UseInitialStridesAB: false + UseInitialStridesCD: false + ScheduleGlobalRead: 1 + ScheduleIterAlg: 3 + ScheduleLocalWrite: 1 + SolutionIndex: 10 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x128x32_MI32x32x8x1_SN_1LDSB1_GRVW8_GSU1_LPB8_LRVW8_MIWT2_2_NEPBS2_NLCA1_PLR5_SS1_SU32_SUS128_SVW2_VW2_WG64_4_1_WGM8 + SourceSwap: 1 + StaggerU: 32 + StaggerUMapping: 0 + StaggerUStride: 128 + StorePriorityOpt: false + StoreRemapVectorWidth: 0 + StoreSyncOpt: 0 + StoreVectorWidth: 2 + SubGroup0: 4 + SubGroup1: 64 + SubGroupA: 4 + SubGroupB: 64 + SuppressNoLoadLoop: false + ThreadTile: [1, 1] + ThreadTile0: 32 + ThreadTile1: 2 + ThreadTileA: 32 + ThreadTileB: 2 + TransposeLDS: 1 + UnrollMajorLDSA: false + UnrollMajorLDSB: true + Use64bShadowLimit: 1 + UseInstOffsetForGRO: 0 + UseSgprForGRO: -1 + Valid: true + VectorStore: -1 + VectorWidth: 2 + WaveSeparateGlobalReadA: 0 + WaveSeparateGlobalReadB: 1 + WavefrontSize: 64 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 8 + _DepthULds: 32 + _GlobalAccumulation: null + _UseSgprForGRO: 1 + _VectorStore: 1 + _WorkspaceSizePerElemC: 0 + _staggerStrideShift: 1 + allowLRVWforTLUandMI: false + - 1LDSBuffer: 0 + ActivationFuncCall: 0 + ActivationFused: true + AssertFree0ElementMultiple: 8 + AssertFree1ElementMultiple: 1 + AssertSummationElementMultiple: 1 + AssignedDerivedParameters: true + AssignedProblemIndependentDerivedParameters: true + BufferLoad: true + BufferStore: true + CodeObjectVersion: V3 + CustomKernelName: '' + DepthU: 64 + DepthULdsDivisor: 1 + DirectToLds: false + DirectToLdsA: false + DirectToLdsB: false + DirectToVgprA: false + DirectToVgprB: false + EdgeType: ShiftPtr + EnableMatrixInstruction: true + ExpandPointerSwap: 0 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 + GlobalReadPerMfma: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 1 + GlobalSplitUAlgorithm: MultipleBuffer + GlobalWriteVectorWidth: 2 + GroupLoadStore: 0 + GuaranteeNoPartialA: true + GuaranteeNoPartialB: true + ISA: [9, 0, 10] + InnerUnroll: 1 + InterleaveAlpha: 0 + KernelLanguage: Assembly + LSCA: 128 LSCB: 64 - LSPA: 64 - LSPB: 32 - LVCA: 4 - LVCB: 8 - LVPA: 8 - LVPB: 4 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 + LVPA: 2 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 12800 - LdsNumElementsAlignedA: 2048 - LdsNumElementsAlignedB: 2560 + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 LdsOffsetA: 0 - LdsOffsetA_Blk: 8192 - LdsOffsetB: 2048 - LdsOffsetB_Blk: 10240 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 LdsPadA: 0 LdsPadB: 16 LocalReadVectorWidth: 8 @@ -2258,14 +2471,14 @@ MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 - MIWaveGroup: [2, 2] - MIWaveTile: [1, 1] - MIWaveTileA: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] + MIWaveTileA: 2 MIWaveTileB: 1 - MacroTile0: 32 - MacroTile1: 32 - MacroTileA: 32 - MacroTileB: 32 + MacroTile0: 128 + MacroTile1: 16 + MacroTileA: 128 + MacroTileB: 16 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 @@ -2284,14 +2497,14 @@ NonTemporalB: 0 NonTemporalC: 0 NonTemporalD: 0 - NumElementsPerBatchStore: 2 - NumElementsPerThread: 4 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 8 NumGlobalWriteVectorsPerThread: 4 - NumLoadsA: 1 + NumLoadsA: 8 NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularA: 8 NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 @@ -2310,7 +2523,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -2360,25 +2573,25 @@ ScheduleGlobalRead: 1 ScheduleIterAlg: 3 ScheduleLocalWrite: 1 - SolutionIndex: 10 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_AFC0_GRVW8_GSU8_LPB16_LRVW8_MIWT1_1_NEPBS2_PLR5_SU4_SUS128_SPO1_SVW1_VW1_WG32_8_1_WGM4 + SolutionIndex: 11 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU1_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU0_SUS0_SVW2_VW2_WG64_4_1_WGM1 SourceSwap: 1 - StaggerU: 4 + StaggerU: 0 StaggerUMapping: 0 - StaggerUStride: 128 - StorePriorityOpt: 1 + StaggerUStride: 0 + StorePriorityOpt: 0 StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 1 - SubGroup0: 8 - SubGroup1: 32 - SubGroupA: 8 - SubGroupB: 32 + StoreVectorWidth: 2 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 4 + ThreadTile0: 8 ThreadTile1: 1 - ThreadTileA: 4 + ThreadTileA: 8 ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false @@ -2388,21 +2601,21 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 1 + VectorWidth: 2 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [32, 8, 1] - WorkGroupMapping: 4 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 1 _DepthULds: 64 - _GlobalAccumulation: MultipleBuffer + _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 - _WorkspaceSizePerElemC: 32 + _WorkspaceSizePerElemC: 0 _staggerStrideShift: 0 allowLRVWforTLUandMI: false - 1LDSBuffer: 0 - ActivationFuncCall: false + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -2423,39 +2636,39 @@ EdgeType: ShiftPtr EnableMatrixInstruction: true ExpandPointerSwap: 0 - GlobalLoadVectorWidthA: 8 - GlobalLoadVectorWidthB: 8 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 GlobalReadPerMfma: 1 - GlobalReadVectorWidth: 8 - GlobalSplitU: 5 + GlobalReadVectorWidth: 4 + GlobalSplitU: 7 GlobalSplitUAlgorithm: MultipleBuffer GlobalWriteVectorWidth: 1 - GroupLoadStore: false + GroupLoadStore: 0 GuaranteeNoPartialA: true GuaranteeNoPartialB: true ISA: [9, 0, 10] InnerUnroll: 1 InterleaveAlpha: 0 KernelLanguage: Assembly - LSCA: 32 + LSCA: 128 LSCB: 64 - LSPA: 64 - LSPB: 32 - LVCA: 4 - LVCB: 8 - LVPA: 8 - LVPB: 4 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 + LVPA: 2 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 12800 - LdsNumElementsAlignedA: 2048 - LdsNumElementsAlignedB: 2560 + LdsNumElements: 25856 + LdsNumElementsAlignedA: 8192 + LdsNumElementsAlignedB: 1280 LdsOffsetA: 0 - LdsOffsetA_Blk: 8192 - LdsOffsetB: 2048 - LdsOffsetB_Blk: 10240 + LdsOffsetA_Blk: 16384 + LdsOffsetB: 8192 + LdsOffsetB_Blk: 24576 LdsPadA: 0 LdsPadB: 16 LocalReadVectorWidth: 8 @@ -2471,14 +2684,14 @@ MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 - MIWaveGroup: [2, 2] - MIWaveTile: [1, 1] - MIWaveTileA: 1 + MIWaveGroup: [4, 1] + MIWaveTile: [2, 1] + MIWaveTileA: 2 MIWaveTileB: 1 - MacroTile0: 32 - MacroTile1: 32 - MacroTileA: 32 - MacroTileB: 32 + MacroTile0: 128 + MacroTile1: 16 + MacroTileA: 128 + MacroTileB: 16 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 @@ -2497,14 +2710,14 @@ NonTemporalB: 0 NonTemporalC: 0 NonTemporalD: 0 - NumElementsPerBatchStore: 2 - NumElementsPerThread: 4 - NumGlobalWriteVectorsPerThread: 4 - NumLoadsA: 1 + NumElementsPerBatchStore: 0 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 8 + NumLoadsA: 8 NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 1 + NumLoadsPerpendicularA: 8 NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 @@ -2523,7 +2736,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -2573,25 +2786,25 @@ ScheduleGlobalRead: 1 ScheduleIterAlg: 3 ScheduleLocalWrite: 1 - SolutionIndex: 11 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT32x32x64_MI16x16x16x1_SN_1LDSB0_AFC0_GRVW8_GSU5_LPB16_LRVW8_MIWT1_1_NEPBS2_PLR5_SU0_SUS0_SPO1_SVW1_VW1_WG32_8_1_WGM8 + SolutionIndex: 12 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU7_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU4_SUS128_SVW1_VW1_WG64_4_1_WGM1 SourceSwap: 1 - StaggerU: 0 + StaggerU: 4 StaggerUMapping: 0 - StaggerUStride: 0 - StorePriorityOpt: 1 + StaggerUStride: 128 + StorePriorityOpt: 0 StoreRemapVectorWidth: 0 StoreSyncOpt: 0 StoreVectorWidth: 1 - SubGroup0: 8 - SubGroup1: 32 - SubGroupA: 8 - SubGroupB: 32 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 4 + ThreadTile0: 8 ThreadTile1: 1 - ThreadTileA: 4 + ThreadTileA: 8 ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false @@ -2603,19 +2816,19 @@ VectorStore: -1 VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [32, 8, 1] - WorkGroupMapping: 8 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 1 _DepthULds: 64 _GlobalAccumulation: MultipleBuffer _UseSgprForGRO: 1 _VectorStore: 1 - _WorkspaceSizePerElemC: 20 + _WorkspaceSizePerElemC: 28 _staggerStrideShift: 0 allowLRVWforTLUandMI: false - 1LDSBuffer: 0 - ActivationFuncCall: true + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -2636,10 +2849,10 @@ EdgeType: ShiftPtr EnableMatrixInstruction: true ExpandPointerSwap: 0 - GlobalLoadVectorWidthA: 8 - GlobalLoadVectorWidthB: 8 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 GlobalReadPerMfma: 1 - GlobalReadVectorWidth: 8 + GlobalReadVectorWidth: 4 GlobalSplitU: 1 GlobalSplitUAlgorithm: MultipleBuffer GlobalWriteVectorWidth: 1 @@ -2652,54 +2865,54 @@ KernelLanguage: Assembly LSCA: 128 LSCB: 64 - LSPA: 16 - LSPB: 32 - LVCA: 16 - LVCB: 8 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 LVPA: 2 - LVPB: 4 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 31488 + LdsNumElements: 25856 LdsNumElementsAlignedA: 8192 - LdsNumElementsAlignedB: 6912 + LdsNumElementsAlignedB: 1280 LdsOffsetA: 0 LdsOffsetA_Blk: 16384 LdsOffsetB: 8192 LdsOffsetB_Blk: 24576 LdsPadA: 0 - LdsPadB: 8 + LdsPadB: 16 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false - LoopIters: 8 + LoopIters: 4 LoopUnroll: 64 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [32, 32, 8, 1, 1, 1] + MIBlock: [16, 16, 16, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [4, 1] - MIWaveTile: [1, 3] - MIWaveTileA: 1 - MIWaveTileB: 3 + MIWaveTile: [2, 1] + MIWaveTileA: 2 + MIWaveTileB: 1 MacroTile0: 128 - MacroTile1: 96 + MacroTile1: 16 MacroTileA: 128 - MacroTileB: 96 + MacroTileB: 16 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 8 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 8, 1] + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -2711,14 +2924,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 0 - NumElementsPerThread: 48 - NumGlobalWriteVectorsPerThread: 48 - NumLoadsA: 4 - NumLoadsB: 3 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 8 + NumLoadsA: 8 + NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 4 - NumLoadsPerpendicularB: 3 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -2726,7 +2939,7 @@ PackedC1IdxChars: [J] PackedC1IndicesX: [1] PrefetchGlobalRead: 2 - PrefetchLocalRead: 9 + PrefetchLocalRead: 5 ProblemType: Activation: true ActivationComputeDataType: 0 @@ -2736,7 +2949,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -2786,26 +2999,26 @@ ScheduleGlobalRead: 1 ScheduleIterAlg: 3 ScheduleLocalWrite: 1 - SolutionIndex: 12 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x96x64_MI32x32x8x1_SN_1LDSB0_AFC1_GRVW8_GSU1_LPB8_LRVW8_MIWT1_3_NEPBS0_PLR9_SU4_SUS256_SPO0_SVW1_VW1_WG128_2_1_WGM4 + SolutionIndex: 13 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU1_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU0_SUS0_SVW1_VW1_WG64_4_1_WGM2 SourceSwap: 1 - StaggerU: 4 + StaggerU: 0 StaggerUMapping: 0 - StaggerUStride: 256 + StaggerUStride: 0 StorePriorityOpt: 0 StoreRemapVectorWidth: 0 StoreSyncOpt: 0 StoreVectorWidth: 1 - SubGroup0: 8 - SubGroup1: 32 - SubGroupA: 8 - SubGroupB: 32 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 16 - ThreadTile1: 3 - ThreadTileA: 16 - ThreadTileB: 3 + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -2816,19 +3029,19 @@ VectorStore: -1 VectorWidth: 1 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [128, 2, 1] - WorkGroupMapping: 4 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 2 _DepthULds: 64 _GlobalAccumulation: null _UseSgprForGRO: 1 _VectorStore: 1 _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 1 + _staggerStrideShift: 0 allowLRVWforTLUandMI: false - 1LDSBuffer: 0 - ActivationFuncCall: true + ActivationFuncCall: 0 ActivationFused: true AssertFree0ElementMultiple: 8 AssertFree1ElementMultiple: 1 @@ -2849,13 +3062,13 @@ EdgeType: ShiftPtr EnableMatrixInstruction: true ExpandPointerSwap: 0 - GlobalLoadVectorWidthA: 8 - GlobalLoadVectorWidthB: 8 + GlobalLoadVectorWidthA: 4 + GlobalLoadVectorWidthB: 4 GlobalReadPerMfma: 1 - GlobalReadVectorWidth: 8 - GlobalSplitU: 1 + GlobalReadVectorWidth: 4 + GlobalSplitU: 8 GlobalSplitUAlgorithm: MultipleBuffer - GlobalWriteVectorWidth: 1 + GlobalWriteVectorWidth: 2 GroupLoadStore: 0 GuaranteeNoPartialA: true GuaranteeNoPartialB: true @@ -2865,54 +3078,54 @@ KernelLanguage: Assembly LSCA: 128 LSCB: 64 - LSPA: 16 - LSPB: 32 - LVCA: 16 - LVCB: 8 + LSPA: 8 + LSPB: 4 + LVCA: 32 + LVCB: 16 LVPA: 2 - LVPB: 4 + LVPB: 1 LdsBlockSizePerPad: 128 LdsBlockSizePerPadA: 0 LdsBlockSizePerPadB: 128 LdsInitCVgprs: false - LdsNumElements: 31488 + LdsNumElements: 25856 LdsNumElementsAlignedA: 8192 - LdsNumElementsAlignedB: 6912 + LdsNumElementsAlignedB: 1280 LdsOffsetA: 0 LdsOffsetA_Blk: 16384 LdsOffsetB: 8192 LdsOffsetB_Blk: 24576 LdsPadA: 0 - LdsPadB: 8 + LdsPadB: 16 LocalReadVectorWidth: 8 LocalSplitU: 1 LocalWritePerMfma: -1 LocalWriteUseSgprA: false LocalWriteUseSgprB: false - LoopIters: 8 + LoopIters: 4 LoopUnroll: 64 MFMA_BF16_1K: false MIArchVgpr: false - MIBlock: [32, 32, 8, 1, 1, 1] + MIBlock: [16, 16, 16, 1, 1, 1] MIInputPerThread: 4 MIOutputVectorWidth: 4 MIRegPerOut: 1 MIWaveGroup: [4, 1] - MIWaveTile: [1, 3] - MIWaveTileA: 1 - MIWaveTileB: 3 + MIWaveTile: [2, 1] + MIWaveTileA: 2 + MIWaveTileB: 1 MacroTile0: 128 - MacroTile1: 96 + MacroTile1: 16 MacroTileA: 128 - MacroTileB: 96 + MacroTileB: 16 MagicDivAlg: 2 MatrixInstB: 1 MatrixInstBM: 1 MatrixInstBN: 1 - MatrixInstK: 8 - MatrixInstM: 32 - MatrixInstN: 32 - MatrixInstruction: [32, 32, 8, 1] + MatrixInstK: 16 + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstruction: [16, 16, 16, 1] MaxOccupancy: 40 MaxVgprNumber: 256 MinVgprNumber: 0 @@ -2924,14 +3137,14 @@ NonTemporalC: 0 NonTemporalD: 0 NumElementsPerBatchStore: 0 - NumElementsPerThread: 48 - NumGlobalWriteVectorsPerThread: 48 - NumLoadsA: 4 - NumLoadsB: 3 + NumElementsPerThread: 8 + NumGlobalWriteVectorsPerThread: 4 + NumLoadsA: 8 + NumLoadsB: 1 NumLoadsCoalescedA: 1 NumLoadsCoalescedB: 1 - NumLoadsPerpendicularA: 4 - NumLoadsPerpendicularB: 3 + NumLoadsPerpendicularA: 8 + NumLoadsPerpendicularB: 1 NumThreads: 256 OptNoLoadLoop: 1 PackedC0IdxChars: [I] @@ -2939,7 +3152,7 @@ PackedC1IdxChars: [J] PackedC1IndicesX: [1] PrefetchGlobalRead: 2 - PrefetchLocalRead: 9 + PrefetchLocalRead: 5 ProblemType: Activation: true ActivationComputeDataType: 0 @@ -2949,7 +3162,7 @@ AssignedDerivedParameters: true Batched: true BetaOnlyUseBias: false - BiasDataType: 0 + BiasDataTypeList: [0, 4] ComplexConjugateA: false ComplexConjugateB: false ComputeDataType: 0 @@ -2999,26 +3212,26 @@ ScheduleGlobalRead: 1 ScheduleIterAlg: 3 ScheduleLocalWrite: 1 - SolutionIndex: 13 - SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_BiasS_AH_MT128x96x64_MI32x32x8x1_SN_1LDSB0_AFC1_GRVW8_GSU1_LPB8_LRVW8_MIWT1_3_NEPBS0_PLR9_SU4_SUS256_SPO0_SVW1_VW1_WG128_2_1_WGM8 + SolutionIndex: 14 + SolutionNameMin: Cijk_Ailk_Bljk_HHS_BH_Bias_AH_MT128x16x64_MI16x16x16x1_SN_1LDSB0_GRVW4_GSU8_LPB16_LRVW8_MIWT2_1_NEPBS0_NLCA1_PLR5_SS1_SU0_SUS0_SVW2_VW2_WG64_4_1_WGM2 SourceSwap: 1 - StaggerU: 4 + StaggerU: 0 StaggerUMapping: 0 - StaggerUStride: 256 + StaggerUStride: 0 StorePriorityOpt: 0 StoreRemapVectorWidth: 0 StoreSyncOpt: 0 - StoreVectorWidth: 1 - SubGroup0: 8 - SubGroup1: 32 - SubGroupA: 8 - SubGroupB: 32 + StoreVectorWidth: 2 + SubGroup0: 16 + SubGroup1: 16 + SubGroupA: 16 + SubGroupB: 16 SuppressNoLoadLoop: false ThreadTile: [1, 1] - ThreadTile0: 16 - ThreadTile1: 3 - ThreadTileA: 16 - ThreadTileB: 3 + ThreadTile0: 8 + ThreadTile1: 1 + ThreadTileA: 8 + ThreadTileB: 1 TransposeLDS: 1 UnrollMajorLDSA: false UnrollMajorLDSB: true @@ -3027,62 +3240,62 @@ UseSgprForGRO: -1 Valid: true VectorStore: -1 - VectorWidth: 1 + VectorWidth: 2 WaveSeparateGlobalReadA: 0 - WaveSeparateGlobalReadB: 0 + WaveSeparateGlobalReadB: 1 WavefrontSize: 64 - WorkGroup: [128, 2, 1] - WorkGroupMapping: 8 + WorkGroup: [64, 4, 1] + WorkGroupMapping: 2 _DepthULds: 64 - _GlobalAccumulation: null + _GlobalAccumulation: MultipleBuffer _UseSgprForGRO: 1 _VectorStore: 1 - _WorkspaceSizePerElemC: 0 - _staggerStrideShift: 1 + _WorkspaceSizePerElemC: 32 + _staggerStrideShift: 0 allowLRVWforTLUandMI: false - [2, 3, 0, 1] - - - [1104, 1, 1, 4608, 1104, 1104, 1104, 4608] - - [9, 218.148] + - [2, 225.657] - - [1104, 16, 1, 4608, 1104, 1104, 1104, 4608] - - [8, 3459.52] + - [2, 3590.13] - - [1104, 1335, 1, 4608, 1104, 1104, 1104, 4608] - - [0, 98666.9] + - [0, 102975.0] - - [1104, 1408, 1, 4608, 1104, 1104, 1104, 4608] - - [1, 104426.0] + - [0, 107796.0] - - [4608, 1, 1, 320, 4608, 4608, 4608, 320] - - [7, 136.837] + - [1, 146.518] - - [4608, 16, 1, 320, 4608, 4608, 4608, 320] - - [7, 2214.05] + - [11, 2391.82] - - [4608, 1335, 1, 320, 4608, 4608, 4608, 320] - - [2, 61686.3] + - [7, 65705.4] - - [4608, 1408, 1, 320, 4608, 4608, 4608, 320] - - [4, 65206.6] + - [10, 75750.8] - - [16, 1, 1, 4608, 16, 16, 16, 4608] - - [10, 3.52832] + - [4, 3.67757] - - [16, 16, 1, 4608, 16, 16, 16, 4608] - - [11, 54.0922] + - [5, 55.8544] - - [16, 1335, 1, 4608, 16, 16, 16, 4608] - - [8, 4101.1] + - [3, 4338.28] - - [16, 1408, 1, 4608, 16, 16, 16, 4608] - - [8, 4342.74] + - [2, 4511.86] - - [768, 1, 1, 4608, 768, 768, 768, 4608] - - [5, 148.945] + - [14, 161.154] - - [768, 16, 1, 4608, 768, 768, 768, 4608] - - [8, 2238.42] + - [12, 2382.32] - - [768, 1335, 1, 4608, 768, 768, 768, 4608] - - [12, 84619.7] + - [6, 90493.4] - - [768, 1408, 1, 4608, 768, 768, 768, 4608] - - [13, 86543.4] + - [6, 95735.1] - - [4608, 1, 1, 768, 4608, 4608, 4608, 768] - - [6, 266.807] + - [1, 281.046] - - [4608, 16, 1, 768, 4608, 4608, 4608, 768] - - [7, 4276.67] + - [13, 4587.1] - - [4608, 1335, 1, 768, 4608, 4608, 4608, 768] - - [3, 90148.0] + - [9, 93398.6] - - [4608, 1408, 1, 768, 4608, 4608, 4608, 768] - - [3, 94357.4] + - [8, 102208.0] - null - null - DeviceEfficiency - null -- Equality +- Equality \ No newline at end of file