diff --git a/qiskit/circuit/bit.py b/qiskit/circuit/bit.py
index 2edd6d906cb6..056ebe8f0046 100644
--- a/qiskit/circuit/bit.py
+++ b/qiskit/circuit/bit.py
@@ -19,7 +19,7 @@
 class Bit:
     """Implement a generic bit."""
 
-    __slots__ = {'_register', '_index', '_hash'}
+    __slots__ = {'_register', '_index', '_hash', '_repr'}
 
     def __init__(self, register, index):
         """Create a new generic bit.
@@ -43,6 +43,8 @@ def __init__(self, register, index):
 
     def _update_hash(self):
         self._hash = hash((self._register, self._index))
+        self._repr = "%s(%s, %s)" % (self.__class__.__name__,
+                                     self._register, self._index)
 
     @property
     def register(self):
@@ -68,12 +70,10 @@ def index(self, value):
 
     def __repr__(self):
         """Return the official string representing the bit."""
-        return "%s(%s, %s)" % (self.__class__.__name__, self._register, self._index)
+        return self._repr
 
     def __hash__(self):
         return self._hash
 
     def __eq__(self, other):
-        if isinstance(other, Bit):
-            return other._index == self._index and other._register == self._register
-        return False
+        return self._repr == other._repr
diff --git a/qiskit/circuit/register.py b/qiskit/circuit/register.py
index 80b2d6829eec..ffd859629f51 100644
--- a/qiskit/circuit/register.py
+++ b/qiskit/circuit/register.py
@@ -25,7 +25,7 @@
 class Register:
     """Implement a generic register."""
 
-    __slots__ = ['_name', '_size', '_bits', '_hash']
+    __slots__ = ['_name', '_size', '_bits', '_hash', '_repr']
     name_format = re.compile('[a-z][a-zA-Z0-9_]*')
 
     # Counter for the number of instances in this class.
@@ -69,6 +69,7 @@ def __init__(self, size, name=None):
         self._size = size
 
         self._hash = hash((type(self), self._name, self._size))
+        self._repr = "%s(%d, '%s')" % (self.__class__.__qualname__, self.size, self.name)
         self._bits = [self.bit_type(self, idx) for idx in range(size)]
 
     def _update_bits_hash(self):
@@ -85,6 +86,7 @@ def name(self, value):
         """Set the register name."""
         self._name = value
         self._hash = hash((type(self), self._name, self._size))
+        self._repr = "%s(%d, '%s')" % (self.__class__.__qualname__, self.size, self.name)
         self._update_bits_hash()
 
     @property
@@ -97,11 +99,12 @@ def size(self, value):
         """Set the register size."""
         self._size = value
         self._hash = hash((type(self), self._name, self._size))
+        self._repr = "%s(%d, '%s')" % (self.__class__.__qualname__, self.size, self.name)
         self._update_bits_hash()
 
     def __repr__(self):
         """Return the official string representing the register."""
-        return "%s(%d, '%s')" % (self.__class__.__qualname__, self.size, self.name)
+        return self._repr
 
     def __len__(self):
         """Return register size."""
@@ -147,12 +150,7 @@ def __eq__(self, other):
         Returns:
             bool: `self` and `other` are equal.
         """
-        res = False
-        if type(self) is type(other) and \
-                self._name == other._name and \
-                self._size == other._size:
-            res = True
-        return res
+        return self._repr == other._repr
 
     def __hash__(self):
         """Make object hashable, based on the name and size to hash."""
diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index b1d89d23cf6c..f1d6336cfd4b 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -696,7 +696,7 @@ def wire_names(self, with_initial_state=False):
         previous_creg = None
         for bit in self.cregs:
             if self.cregbundle:
-                if previous_creg == bit.register:
+                if previous_creg and previous_creg == bit.register:
                     continue
                 previous_creg = bit.register
                 label = '{name}: {initial_value}{size}/'
@@ -1120,7 +1120,7 @@ def __init__(self, qregs, cregs, cregbundle=False):
             self.cregs = []
             previous_creg = None
             for bit in cregs:
-                if previous_creg == bit.register:
+                if previous_creg and previous_creg == bit.register:
                     continue
                 previous_creg = bit.register
                 self.cregs.append(bit.register)