mkDE10FanControl.v

//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Thu Feb 20 16:33:31 GMT 2020
//
//
// Ports:
// Name                         I/O  size props
// leds                           O     4 reg
// get_temp                       O     8 reg
// target_speed                   O     8 reg
// RST_N_inner_rst                O     1 reset
// CLK                            I     1 clock
// RST_N                          I     1 reset
// FAN_I2C_SDA                   IO     1 inout
// FAN_I2C_SCL                   IO     1 inout
// TEMP_I2C_SDA                  IO     1 inout
// TEMP_I2C_SCL                  IO     1 inout
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDE10FanControl(CLK,
			RST_N,

			.FAN_I2C_SDA(inner_fan_fan_tSDA$IO),
			.FAN_I2C_SCL(inner_fan_fan_tSCL$IO),
			.TEMP_I2C_SDA(inner_temp_temp_tSDA$IO),
			.TEMP_I2C_SCL(inner_temp_temp_tSCL$IO),

			leds,

			get_temp,

			target_speed,

			RST_N_inner_rst);
  input  CLK;
  input  RST_N;

  inout  inner_fan_fan_tSDA$IO;
  inout  inner_fan_fan_tSCL$IO;
  inout  inner_temp_temp_tSDA$IO;
  inout  inner_temp_temp_tSCL$IO;

  // value method leds
  output [3 : 0] leds;

  // value method get_temp
  output [7 : 0] get_temp;

  // value method target_speed
  output [7 : 0] target_speed;

  // output resets
  output RST_N_inner_rst;

  // signals for module outputs
  wire [7 : 0] get_temp, target_speed;
  wire [3 : 0] leds;
  wire RST_N_inner_rst;

  // inlined wires
  wire inner_main_start_wire$whas, inner_main_state_set_pw$whas;

  // register inner_cnt
  reg [31 : 0] inner_cnt;
  wire [31 : 0] inner_cnt$D_IN;
  wire inner_cnt$EN;

  // register inner_cur_temp
  reg [7 : 0] inner_cur_temp;
  wire [7 : 0] inner_cur_temp$D_IN;
  wire inner_cur_temp$EN;

  // register inner_fan_fan_rAddress
  reg [7 : 0] inner_fan_fan_rAddress;
  wire [7 : 0] inner_fan_fan_rAddress$D_IN;
  wire inner_fan_fan_rAddress$EN;

  // register inner_fan_fan_rOutEn
  reg inner_fan_fan_rOutEn;
  wire inner_fan_fan_rOutEn$D_IN, inner_fan_fan_rOutEn$EN;

  // register inner_fan_fan_rSCL
  reg inner_fan_fan_rSCL;
  wire inner_fan_fan_rSCL$D_IN, inner_fan_fan_rSCL$EN;

  // register inner_fan_fan_rSDA
  reg inner_fan_fan_rSDA;
  wire inner_fan_fan_rSDA$D_IN, inner_fan_fan_rSDA$EN;

  // register inner_fan_fan_rSlaveAddr
  reg [6 : 0] inner_fan_fan_rSlaveAddr;
  wire [6 : 0] inner_fan_fan_rSlaveAddr$D_IN;
  wire inner_fan_fan_rSlaveAddr$EN;

  // register inner_fan_fan_rState
  reg inner_fan_fan_rState;
  wire inner_fan_fan_rState$D_IN, inner_fan_fan_rState$EN;

  // register inner_fan_fan_rWrite
  reg inner_fan_fan_rWrite;
  wire inner_fan_fan_rWrite$D_IN, inner_fan_fan_rWrite$EN;

  // register inner_fan_fan_rWriteData
  reg [7 : 0] inner_fan_fan_rWriteData;
  wire [7 : 0] inner_fan_fan_rWriteData$D_IN;
  wire inner_fan_fan_rWriteData$EN;

  // register inner_fan_fan_vrReadData_0
  reg inner_fan_fan_vrReadData_0;
  wire inner_fan_fan_vrReadData_0$D_IN, inner_fan_fan_vrReadData_0$EN;

  // register inner_fan_fan_vrReadData_1
  reg inner_fan_fan_vrReadData_1;
  wire inner_fan_fan_vrReadData_1$D_IN, inner_fan_fan_vrReadData_1$EN;

  // register inner_fan_fan_vrReadData_2
  reg inner_fan_fan_vrReadData_2;
  wire inner_fan_fan_vrReadData_2$D_IN, inner_fan_fan_vrReadData_2$EN;

  // register inner_fan_fan_vrReadData_3
  reg inner_fan_fan_vrReadData_3;
  wire inner_fan_fan_vrReadData_3$D_IN, inner_fan_fan_vrReadData_3$EN;

  // register inner_fan_fan_vrReadData_4
  reg inner_fan_fan_vrReadData_4;
  wire inner_fan_fan_vrReadData_4$D_IN, inner_fan_fan_vrReadData_4$EN;

  // register inner_fan_fan_vrReadData_5
  reg inner_fan_fan_vrReadData_5;
  wire inner_fan_fan_vrReadData_5$D_IN, inner_fan_fan_vrReadData_5$EN;

  // register inner_fan_fan_vrReadData_6
  reg inner_fan_fan_vrReadData_6;
  wire inner_fan_fan_vrReadData_6$D_IN, inner_fan_fan_vrReadData_6$EN;

  // register inner_fan_fan_vrReadData_7
  reg inner_fan_fan_vrReadData_7;
  wire inner_fan_fan_vrReadData_7$D_IN, inner_fan_fan_vrReadData_7$EN;

  // register inner_last_temp
  reg [7 : 0] inner_last_temp;
  wire [7 : 0] inner_last_temp$D_IN;
  wire inner_last_temp$EN;

  // register inner_led
  reg [3 : 0] inner_led;
  reg [3 : 0] inner_led$D_IN;
  wire inner_led$EN;

  // register inner_main_start_reg
  reg inner_main_start_reg;
  wire inner_main_start_reg$D_IN, inner_main_start_reg$EN;

  // register inner_main_start_reg_1
  reg inner_main_start_reg_1;
  wire inner_main_start_reg_1$D_IN, inner_main_start_reg_1$EN;

  // register inner_main_state_can_overlap
  reg inner_main_state_can_overlap;
  wire inner_main_state_can_overlap$D_IN, inner_main_state_can_overlap$EN;

  // register inner_main_state_fired
  reg inner_main_state_fired;
  wire inner_main_state_fired$D_IN, inner_main_state_fired$EN;

  // register inner_main_state_mkFSMstate
  reg [4 : 0] inner_main_state_mkFSMstate;
  reg [4 : 0] inner_main_state_mkFSMstate$D_IN;
  wire inner_main_state_mkFSMstate$EN;

  // register inner_tSpeed
  reg [7 : 0] inner_tSpeed;
  wire [7 : 0] inner_tSpeed$D_IN;
  wire inner_tSpeed$EN;

  // register inner_temp_temp_rAddress
  reg [7 : 0] inner_temp_temp_rAddress;
  wire [7 : 0] inner_temp_temp_rAddress$D_IN;
  wire inner_temp_temp_rAddress$EN;

  // register inner_temp_temp_rOutEn
  reg inner_temp_temp_rOutEn;
  wire inner_temp_temp_rOutEn$D_IN, inner_temp_temp_rOutEn$EN;

  // register inner_temp_temp_rSCL
  reg inner_temp_temp_rSCL;
  wire inner_temp_temp_rSCL$D_IN, inner_temp_temp_rSCL$EN;

  // register inner_temp_temp_rSDA
  reg inner_temp_temp_rSDA;
  wire inner_temp_temp_rSDA$D_IN, inner_temp_temp_rSDA$EN;

  // register inner_temp_temp_rSlaveAddr
  reg [6 : 0] inner_temp_temp_rSlaveAddr;
  wire [6 : 0] inner_temp_temp_rSlaveAddr$D_IN;
  wire inner_temp_temp_rSlaveAddr$EN;

  // register inner_temp_temp_rState
  reg inner_temp_temp_rState;
  wire inner_temp_temp_rState$D_IN, inner_temp_temp_rState$EN;

  // register inner_temp_temp_rWrite
  reg inner_temp_temp_rWrite;
  wire inner_temp_temp_rWrite$D_IN, inner_temp_temp_rWrite$EN;

  // register inner_temp_temp_rWriteData
  reg [7 : 0] inner_temp_temp_rWriteData;
  wire [7 : 0] inner_temp_temp_rWriteData$D_IN;
  wire inner_temp_temp_rWriteData$EN;

  // register inner_temp_temp_vrReadData_0
  reg inner_temp_temp_vrReadData_0;
  wire inner_temp_temp_vrReadData_0$D_IN, inner_temp_temp_vrReadData_0$EN;

  // register inner_temp_temp_vrReadData_1
  reg inner_temp_temp_vrReadData_1;
  wire inner_temp_temp_vrReadData_1$D_IN, inner_temp_temp_vrReadData_1$EN;

  // register inner_temp_temp_vrReadData_2
  reg inner_temp_temp_vrReadData_2;
  wire inner_temp_temp_vrReadData_2$D_IN, inner_temp_temp_vrReadData_2$EN;

  // register inner_temp_temp_vrReadData_3
  reg inner_temp_temp_vrReadData_3;
  wire inner_temp_temp_vrReadData_3$D_IN, inner_temp_temp_vrReadData_3$EN;

  // register inner_temp_temp_vrReadData_4
  reg inner_temp_temp_vrReadData_4;
  wire inner_temp_temp_vrReadData_4$D_IN, inner_temp_temp_vrReadData_4$EN;

  // register inner_temp_temp_vrReadData_5
  reg inner_temp_temp_vrReadData_5;
  wire inner_temp_temp_vrReadData_5$D_IN, inner_temp_temp_vrReadData_5$EN;

  // register inner_temp_temp_vrReadData_6
  reg inner_temp_temp_vrReadData_6;
  wire inner_temp_temp_vrReadData_6$D_IN, inner_temp_temp_vrReadData_6$EN;

  // register inner_temp_temp_vrReadData_7
  reg inner_temp_temp_vrReadData_7;
  wire inner_temp_temp_vrReadData_7$D_IN, inner_temp_temp_vrReadData_7$EN;

  // ports of submodule inner_fan_fan_fRequest
  reg [23 : 0] inner_fan_fan_fRequest$D_IN;
  wire [23 : 0] inner_fan_fan_fRequest$D_OUT;
  wire inner_fan_fan_fRequest$CLR,
       inner_fan_fan_fRequest$DEQ,
       inner_fan_fan_fRequest$EMPTY_N,
       inner_fan_fan_fRequest$ENQ,
       inner_fan_fan_fRequest$FULL_N;

  // ports of submodule inner_fan_fan_fResponse
  wire [7 : 0] inner_fan_fan_fResponse$D_IN;
  wire inner_fan_fan_fResponse$CLR,
       inner_fan_fan_fResponse$DEQ,
       inner_fan_fan_fResponse$ENQ,
       inner_fan_fan_fResponse$FULL_N;

  // ports of submodule inner_fan_fan_rPlayIndex
  wire [9 : 0] inner_fan_fan_rPlayIndex$DATA_A,
	       inner_fan_fan_rPlayIndex$DATA_B,
	       inner_fan_fan_rPlayIndex$DATA_C,
	       inner_fan_fan_rPlayIndex$DATA_F,
	       inner_fan_fan_rPlayIndex$Q_OUT;
  wire inner_fan_fan_rPlayIndex$ADDA,
       inner_fan_fan_rPlayIndex$ADDB,
       inner_fan_fan_rPlayIndex$SETC,
       inner_fan_fan_rPlayIndex$SETF;

  // ports of submodule inner_fan_fan_rPrescaler
  wire [31 : 0] inner_fan_fan_rPrescaler$DATA_A,
		inner_fan_fan_rPrescaler$DATA_B,
		inner_fan_fan_rPrescaler$DATA_C,
		inner_fan_fan_rPrescaler$DATA_F,
		inner_fan_fan_rPrescaler$Q_OUT;
  wire inner_fan_fan_rPrescaler$ADDA,
       inner_fan_fan_rPrescaler$ADDB,
       inner_fan_fan_rPrescaler$SETC,
       inner_fan_fan_rPrescaler$SETF;

  // ports of submodule inner_fan_fan_tSCL
  wire inner_fan_fan_tSCL$IO;

  // ports of submodule inner_fan_fan_tSDA
  wire inner_fan_fan_tSDA$IO, inner_fan_fan_tSDA$O;

  // ports of submodule inner_temp_temp_fRequest
  wire [23 : 0] inner_temp_temp_fRequest$D_IN, inner_temp_temp_fRequest$D_OUT;
  wire inner_temp_temp_fRequest$CLR,
       inner_temp_temp_fRequest$DEQ,
       inner_temp_temp_fRequest$EMPTY_N,
       inner_temp_temp_fRequest$ENQ,
       inner_temp_temp_fRequest$FULL_N;

  // ports of submodule inner_temp_temp_fResponse
  wire [7 : 0] inner_temp_temp_fResponse$D_IN,
	       inner_temp_temp_fResponse$D_OUT;
  wire inner_temp_temp_fResponse$CLR,
       inner_temp_temp_fResponse$DEQ,
       inner_temp_temp_fResponse$EMPTY_N,
       inner_temp_temp_fResponse$ENQ,
       inner_temp_temp_fResponse$FULL_N;

  // ports of submodule inner_temp_temp_rPlayIndex
  wire [9 : 0] inner_temp_temp_rPlayIndex$DATA_A,
	       inner_temp_temp_rPlayIndex$DATA_B,
	       inner_temp_temp_rPlayIndex$DATA_C,
	       inner_temp_temp_rPlayIndex$DATA_F,
	       inner_temp_temp_rPlayIndex$Q_OUT;
  wire inner_temp_temp_rPlayIndex$ADDA,
       inner_temp_temp_rPlayIndex$ADDB,
       inner_temp_temp_rPlayIndex$SETC,
       inner_temp_temp_rPlayIndex$SETF;

  // ports of submodule inner_temp_temp_rPrescaler
  wire [31 : 0] inner_temp_temp_rPrescaler$DATA_A,
		inner_temp_temp_rPrescaler$DATA_B,
		inner_temp_temp_rPrescaler$DATA_C,
		inner_temp_temp_rPrescaler$DATA_F,
		inner_temp_temp_rPrescaler$Q_OUT;
  wire inner_temp_temp_rPrescaler$ADDA,
       inner_temp_temp_rPrescaler$ADDB,
       inner_temp_temp_rPrescaler$SETC,
       inner_temp_temp_rPrescaler$SETF;

  // ports of submodule inner_temp_temp_tSCL
  wire inner_temp_temp_tSCL$IO;

  // ports of submodule inner_temp_temp_tSDA
  wire inner_temp_temp_tSDA$IO, inner_temp_temp_tSDA$O;

  // ports of submodule r
  wire r$ASSERT_IN, r$OUT_RST;

  // rule scheduling signals
  wire WILL_FIRE_RL_inner_fan_fan_done_read,
       WILL_FIRE_RL_inner_fan_fan_done_write,
       WILL_FIRE_RL_inner_fan_fan_running_read,
       WILL_FIRE_RL_inner_fan_fan_running_write,
       WILL_FIRE_RL_inner_main_action_l102c28,
       WILL_FIRE_RL_inner_main_action_l103c24,
       WILL_FIRE_RL_inner_main_action_l108c28,
       WILL_FIRE_RL_inner_main_action_l109c24,
       WILL_FIRE_RL_inner_main_action_l114c18,
       WILL_FIRE_RL_inner_main_action_l19c27,
       WILL_FIRE_RL_inner_main_action_l24c26,
       WILL_FIRE_RL_inner_main_action_l25c13,
       WILL_FIRE_RL_inner_main_action_l39c27,
       WILL_FIRE_RL_inner_main_action_l40c27,
       WILL_FIRE_RL_inner_main_action_l41c27,
       WILL_FIRE_RL_inner_main_action_l42c27,
       WILL_FIRE_RL_inner_main_action_l43c27,
       WILL_FIRE_RL_inner_main_action_l89c13,
       WILL_FIRE_RL_inner_main_action_l90c14,
       WILL_FIRE_RL_inner_main_action_l94c12,
       WILL_FIRE_RL_inner_main_action_l97c17,
       WILL_FIRE_RL_inner_main_fsm_start,
       WILL_FIRE_RL_inner_temp_temp_done_read,
       WILL_FIRE_RL_inner_temp_temp_done_write,
       WILL_FIRE_RL_inner_temp_temp_running_read,
       WILL_FIRE_RL_inner_temp_temp_running_write;

  // inputs to muxes for submodule ports
  wire [31 : 0] MUX_inner_cnt$write_1__VAL_1;
  wire [23 : 0] MUX_inner_fan_fan_fRequest$enq_1__VAL_1;
  wire [7 : 0] MUX_inner_tSpeed$write_1__VAL_1,
	       MUX_inner_tSpeed$write_1__VAL_2;
  wire MUX_inner_fan_fan_fRequest$enq_1__SEL_1,
       MUX_inner_fan_fan_rOutEn$write_1__SEL_1,
       MUX_inner_fan_fan_rOutEn$write_1__VAL_1,
       MUX_inner_fan_fan_rOutEn$write_1__VAL_2,
       MUX_inner_fan_fan_rSCL$write_1__VAL_1,
       MUX_inner_fan_fan_rSCL$write_1__VAL_2,
       MUX_inner_fan_fan_rSDA$write_1__VAL_1,
       MUX_inner_fan_fan_rSDA$write_1__VAL_2,
       MUX_inner_fan_fan_rState$write_1__SEL_1,
       MUX_inner_fan_fan_rState$write_1__SEL_2,
       MUX_inner_temp_temp_rOutEn$write_1__SEL_1,
       MUX_inner_temp_temp_rOutEn$write_1__VAL_1,
       MUX_inner_temp_temp_rOutEn$write_1__VAL_2,
       MUX_inner_temp_temp_rSCL$write_1__VAL_1,
       MUX_inner_temp_temp_rSCL$write_1__VAL_2,
       MUX_inner_temp_temp_rSDA$write_1__VAL_1,
       MUX_inner_temp_temp_rSDA$write_1__VAL_2,
       MUX_inner_temp_temp_rState$write_1__SEL_1,
       MUX_inner_temp_temp_rState$write_1__SEL_2;

  // remaining internal signals
  wire [119 : 0] _1044393425259576759155060135206397075__q5,
		 _1329227987119335533342540869413109767__q3,
		 _306783360__q1,
		 wRdData__h1559,
		 wRdData__h16184;
  wire [86 : 0] _121583396715528419856163987__q4,
		_154742503901866210315206599__q2,
		wWrData__h1563,
		wWrData__h16188;
  wire [11 : 0] x__h76513, y__h76530;
  wire [7 : 0] x__h78896;
  wire [2 : 0] a0__h1548,
	       a0__h16173,
	       a1__h1547,
	       a1__h16172,
	       a2__h1546,
	       a2__h16171,
	       a3__h1545,
	       a3__h16170,
	       a4__h1544,
	       a4__h16169,
	       a5__h1543,
	       a5__h16168,
	       a6__h1542,
	       a6__h16167,
	       a7__h1541,
	       a7__h16166,
	       d0__h1557,
	       d0__h16182,
	       d1__h1556,
	       d1__h16181,
	       d2__h1555,
	       d2__h16180,
	       d3__h1554,
	       d3__h16179,
	       d4__h1553,
	       d4__h16178,
	       d5__h1552,
	       d5__h16177,
	       d6__h1551,
	       d6__h16176,
	       d7__h1550,
	       d7__h16175,
	       s0__h1539,
	       s0__h16164,
	       s1__h1538,
	       s1__h16163,
	       s2__h1537,
	       s2__h16162,
	       s3__h1536,
	       s3__h16161,
	       s4__h1535,
	       s4__h16160,
	       s5__h1534,
	       s5__h16159,
	       s6__h1533,
	       s6__h16158;
  wire NOT_inner_cur_temp_33_ULT_40_42_66_OR_NOT_inne_ETC___d369,
       NOT_inner_cur_temp_33_ULT_40_42_66_OR_NOT_inne_ETC___d386,
       _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108,
       _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233,
       inner_cur_temp_33_ULE_40___d357,
       inner_cur_temp_33_ULE_inner_last_temp_43___d344,
       inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d370,
       inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d387,
       inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393,
       inner_cur_temp_33_ULT_40___d342,
       inner_cur_temp_33_ULT_inner_last_temp_43___d359,
       inner_main_abort_whas__60_AND_inner_main_abort_ETC___d402,
       inner_tSpeed_19_ULE_35___d346,
       inner_tSpeed_19_ULT_100___d362;

  // output resets
  assign RST_N_inner_rst = r$OUT_RST ;

  // value method leds
  assign leds = inner_led ;

  // value method get_temp
  assign get_temp = inner_cur_temp ;

  // value method target_speed
  assign target_speed = inner_tSpeed ;

  // submodule inner_fan_fan_fRequest
  SizedFIFO #(.p1width(32'd24),
	      .p2depth(32'd16),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) inner_fan_fan_fRequest(.RST(r$OUT_RST),
						      .CLK(CLK),
						      .D_IN(inner_fan_fan_fRequest$D_IN),
						      .ENQ(inner_fan_fan_fRequest$ENQ),
						      .DEQ(inner_fan_fan_fRequest$DEQ),
						      .CLR(inner_fan_fan_fRequest$CLR),
						      .D_OUT(inner_fan_fan_fRequest$D_OUT),
						      .FULL_N(inner_fan_fan_fRequest$FULL_N),
						      .EMPTY_N(inner_fan_fan_fRequest$EMPTY_N));

  // submodule inner_fan_fan_fResponse
  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd16),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) inner_fan_fan_fResponse(.RST(r$OUT_RST),
						       .CLK(CLK),
						       .D_IN(inner_fan_fan_fResponse$D_IN),
						       .ENQ(inner_fan_fan_fResponse$ENQ),
						       .DEQ(inner_fan_fan_fResponse$DEQ),
						       .CLR(inner_fan_fan_fResponse$CLR),
						       .D_OUT(),
						       .FULL_N(inner_fan_fan_fResponse$FULL_N),
						       .EMPTY_N());

  // submodule inner_fan_fan_rPlayIndex
  Counter #(.width(32'd10), .init(10'd0)) inner_fan_fan_rPlayIndex(.CLK(CLK),
								   .RST(r$OUT_RST),
								   .DATA_A(inner_fan_fan_rPlayIndex$DATA_A),
								   .DATA_B(inner_fan_fan_rPlayIndex$DATA_B),
								   .DATA_C(inner_fan_fan_rPlayIndex$DATA_C),
								   .DATA_F(inner_fan_fan_rPlayIndex$DATA_F),
								   .ADDA(inner_fan_fan_rPlayIndex$ADDA),
								   .ADDB(inner_fan_fan_rPlayIndex$ADDB),
								   .SETC(inner_fan_fan_rPlayIndex$SETC),
								   .SETF(inner_fan_fan_rPlayIndex$SETF),
								   .Q_OUT(inner_fan_fan_rPlayIndex$Q_OUT));

  // submodule inner_fan_fan_rPrescaler
  Counter #(.width(32'd32),
	    .init(32'd125)) inner_fan_fan_rPrescaler(.CLK(CLK),
						     .RST(r$OUT_RST),
						     .DATA_A(inner_fan_fan_rPrescaler$DATA_A),
						     .DATA_B(inner_fan_fan_rPrescaler$DATA_B),
						     .DATA_C(inner_fan_fan_rPrescaler$DATA_C),
						     .DATA_F(inner_fan_fan_rPrescaler$DATA_F),
						     .ADDA(inner_fan_fan_rPrescaler$ADDA),
						     .ADDB(inner_fan_fan_rPrescaler$ADDB),
						     .SETC(inner_fan_fan_rPrescaler$SETC),
						     .SETF(inner_fan_fan_rPrescaler$SETF),
						     .Q_OUT(inner_fan_fan_rPrescaler$Q_OUT));

  // submodule inner_fan_fan_tSCL
  TriState #(.width(32'd1)) inner_fan_fan_tSCL(.I(inner_fan_fan_rSCL),
					       .OE(1'd1),
					       .O(),
					       .IO(inner_fan_fan_tSCL$IO));

  // submodule inner_fan_fan_tSDA
  TriState #(.width(32'd1)) inner_fan_fan_tSDA(.I(inner_fan_fan_rSDA),
					       .OE(inner_fan_fan_rOutEn),
					       .O(inner_fan_fan_tSDA$O),
					       .IO(inner_fan_fan_tSDA$IO));

  // submodule inner_temp_temp_fRequest
  SizedFIFO #(.p1width(32'd24),
	      .p2depth(32'd16),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) inner_temp_temp_fRequest(.RST(r$OUT_RST),
							.CLK(CLK),
							.D_IN(inner_temp_temp_fRequest$D_IN),
							.ENQ(inner_temp_temp_fRequest$ENQ),
							.DEQ(inner_temp_temp_fRequest$DEQ),
							.CLR(inner_temp_temp_fRequest$CLR),
							.D_OUT(inner_temp_temp_fRequest$D_OUT),
							.FULL_N(inner_temp_temp_fRequest$FULL_N),
							.EMPTY_N(inner_temp_temp_fRequest$EMPTY_N));

  // submodule inner_temp_temp_fResponse
  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd16),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) inner_temp_temp_fResponse(.RST(r$OUT_RST),
							 .CLK(CLK),
							 .D_IN(inner_temp_temp_fResponse$D_IN),
							 .ENQ(inner_temp_temp_fResponse$ENQ),
							 .DEQ(inner_temp_temp_fResponse$DEQ),
							 .CLR(inner_temp_temp_fResponse$CLR),
							 .D_OUT(inner_temp_temp_fResponse$D_OUT),
							 .FULL_N(inner_temp_temp_fResponse$FULL_N),
							 .EMPTY_N(inner_temp_temp_fResponse$EMPTY_N));

  // submodule inner_temp_temp_rPlayIndex
  Counter #(.width(32'd10),
	    .init(10'd0)) inner_temp_temp_rPlayIndex(.CLK(CLK),
						     .RST(r$OUT_RST),
						     .DATA_A(inner_temp_temp_rPlayIndex$DATA_A),
						     .DATA_B(inner_temp_temp_rPlayIndex$DATA_B),
						     .DATA_C(inner_temp_temp_rPlayIndex$DATA_C),
						     .DATA_F(inner_temp_temp_rPlayIndex$DATA_F),
						     .ADDA(inner_temp_temp_rPlayIndex$ADDA),
						     .ADDB(inner_temp_temp_rPlayIndex$ADDB),
						     .SETC(inner_temp_temp_rPlayIndex$SETC),
						     .SETF(inner_temp_temp_rPlayIndex$SETF),
						     .Q_OUT(inner_temp_temp_rPlayIndex$Q_OUT));

  // submodule inner_temp_temp_rPrescaler
  Counter #(.width(32'd32),
	    .init(32'd125)) inner_temp_temp_rPrescaler(.CLK(CLK),
						       .RST(r$OUT_RST),
						       .DATA_A(inner_temp_temp_rPrescaler$DATA_A),
						       .DATA_B(inner_temp_temp_rPrescaler$DATA_B),
						       .DATA_C(inner_temp_temp_rPrescaler$DATA_C),
						       .DATA_F(inner_temp_temp_rPrescaler$DATA_F),
						       .ADDA(inner_temp_temp_rPrescaler$ADDA),
						       .ADDB(inner_temp_temp_rPrescaler$ADDB),
						       .SETC(inner_temp_temp_rPrescaler$SETC),
						       .SETF(inner_temp_temp_rPrescaler$SETF),
						       .Q_OUT(inner_temp_temp_rPrescaler$Q_OUT));

  // submodule inner_temp_temp_tSCL
  TriState #(.width(32'd1)) inner_temp_temp_tSCL(.I(inner_temp_temp_rSCL),
						 .OE(1'd1),
						 .O(),
						 .IO(inner_temp_temp_tSCL$IO));

  // submodule inner_temp_temp_tSDA
  TriState #(.width(32'd1)) inner_temp_temp_tSDA(.I(inner_temp_temp_rSDA),
						 .OE(inner_temp_temp_rOutEn),
						 .O(inner_temp_temp_tSDA$O),
						 .IO(inner_temp_temp_tSDA$IO));

  // submodule r
  MakeResetA #(.RSTDELAY(32'd1), .init(1'd0)) r(.CLK(CLK),
						.RST(RST_N),
						.DST_CLK(CLK),
						.ASSERT_IN(r$ASSERT_IN),
						.ASSERT_OUT(),
						.OUT_RST(r$OUT_RST));

  // rule RL_inner_fan_fan_running_write
  assign WILL_FIRE_RL_inner_fan_fan_running_write =
	     inner_fan_fan_rState && inner_fan_fan_rWrite &&
	     inner_fan_fan_rPrescaler$Q_OUT == 32'd0 &&
	     inner_fan_fan_rPlayIndex$Q_OUT != 10'd0 ;

  // rule RL_inner_fan_fan_running_read
  assign WILL_FIRE_RL_inner_fan_fan_running_read =
	     inner_fan_fan_rState && !inner_fan_fan_rWrite &&
	     inner_fan_fan_rPrescaler$Q_OUT == 32'd0 &&
	     inner_fan_fan_rPlayIndex$Q_OUT != 10'd0 ;

  // rule RL_inner_fan_fan_done_write
  assign WILL_FIRE_RL_inner_fan_fan_done_write =
	     inner_fan_fan_rState && inner_fan_fan_rWrite &&
	     inner_fan_fan_rPrescaler$Q_OUT == 32'd0 &&
	     inner_fan_fan_rPlayIndex$Q_OUT == 10'd0 ;

  // rule RL_inner_fan_fan_done_read
  assign WILL_FIRE_RL_inner_fan_fan_done_read =
	     inner_fan_fan_fResponse$FULL_N && inner_fan_fan_rState &&
	     !inner_fan_fan_rWrite &&
	     inner_fan_fan_rPrescaler$Q_OUT == 32'd0 &&
	     inner_fan_fan_rPlayIndex$Q_OUT == 10'd0 ;

  // rule RL_inner_temp_temp_running_write
  assign WILL_FIRE_RL_inner_temp_temp_running_write =
	     inner_temp_temp_rState && inner_temp_temp_rWrite &&
	     inner_temp_temp_rPrescaler$Q_OUT == 32'd0 &&
	     inner_temp_temp_rPlayIndex$Q_OUT != 10'd0 ;

  // rule RL_inner_temp_temp_running_read
  assign WILL_FIRE_RL_inner_temp_temp_running_read =
	     inner_temp_temp_rState && !inner_temp_temp_rWrite &&
	     inner_temp_temp_rPrescaler$Q_OUT == 32'd0 &&
	     inner_temp_temp_rPlayIndex$Q_OUT != 10'd0 ;

  // rule RL_inner_temp_temp_done_write
  assign WILL_FIRE_RL_inner_temp_temp_done_write =
	     inner_temp_temp_rState && inner_temp_temp_rWrite &&
	     inner_temp_temp_rPrescaler$Q_OUT == 32'd0 &&
	     inner_temp_temp_rPlayIndex$Q_OUT == 10'd0 ;

  // rule RL_inner_temp_temp_done_read
  assign WILL_FIRE_RL_inner_temp_temp_done_read =
	     inner_temp_temp_fResponse$FULL_N && inner_temp_temp_rState &&
	     !inner_temp_temp_rWrite &&
	     inner_temp_temp_rPrescaler$Q_OUT == 32'd0 &&
	     inner_temp_temp_rPlayIndex$Q_OUT == 10'd0 ;

  // rule RL_inner_main_action_l90c14
  assign WILL_FIRE_RL_inner_main_action_l90c14 =
	     inner_cnt == 32'd0 && inner_main_state_mkFSMstate == 5'd1 ;

  // rule RL_inner_main_action_l39c27
  assign WILL_FIRE_RL_inner_main_action_l39c27 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd3 ;

  // rule RL_inner_main_action_l40c27
  assign WILL_FIRE_RL_inner_main_action_l40c27 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd4 ;

  // rule RL_inner_main_action_l41c27
  assign WILL_FIRE_RL_inner_main_action_l41c27 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd5 ;

  // rule RL_inner_main_action_l42c27
  assign WILL_FIRE_RL_inner_main_action_l42c27 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd6 ;

  // rule RL_inner_main_action_l43c27
  assign WILL_FIRE_RL_inner_main_action_l43c27 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd7 ;

  // rule RL_inner_main_action_l19c27
  assign WILL_FIRE_RL_inner_main_action_l19c27 =
	     inner_temp_temp_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd8 ;

  // rule RL_inner_main_action_l94c12
  assign WILL_FIRE_RL_inner_main_action_l94c12 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd9 ;

  // rule RL_inner_main_action_l97c17
  assign WILL_FIRE_RL_inner_main_action_l97c17 =
	     inner_main_state_mkFSMstate == 5'd11 ||
	     inner_main_state_mkFSMstate == 5'd22 ;

  // rule RL_inner_main_action_l24c26
  assign WILL_FIRE_RL_inner_main_action_l24c26 =
	     inner_temp_temp_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd13 ;

  // rule RL_inner_main_action_l25c13
  assign WILL_FIRE_RL_inner_main_action_l25c13 =
	     inner_temp_temp_fResponse$EMPTY_N &&
	     inner_main_state_mkFSMstate == 5'd14 ;

  // rule RL_inner_main_action_l102c28
  assign WILL_FIRE_RL_inner_main_action_l102c28 =
	     inner_cur_temp_33_ULT_40___d342 &&
	     inner_cur_temp_33_ULE_inner_last_temp_43___d344 &&
	     !inner_tSpeed_19_ULE_35___d346 &&
	     inner_main_state_mkFSMstate == 5'd15 ;

  // rule RL_inner_main_action_l103c24
  assign WILL_FIRE_RL_inner_main_action_l103c24 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd16 ;

  // rule RL_inner_main_action_l109c24
  assign WILL_FIRE_RL_inner_main_action_l109c24 =
	     inner_fan_fan_fRequest$FULL_N &&
	     inner_main_state_mkFSMstate == 5'd18 ;

  // rule RL_inner_main_action_l114c18
  assign WILL_FIRE_RL_inner_main_action_l114c18 =
	     inner_cnt == 32'd0 && inner_main_state_mkFSMstate == 5'd21 ;

  // rule RL_inner_main_fsm_start
  assign WILL_FIRE_RL_inner_main_fsm_start =
	     inner_main_abort_whas__60_AND_inner_main_abort_ETC___d402 &&
	     inner_main_start_reg ;

  // rule RL_inner_main_action_l89c13
  assign WILL_FIRE_RL_inner_main_action_l89c13 =
	     inner_main_start_wire$whas &&
	     inner_main_state_mkFSMstate == 5'd0 ;

  // rule RL_inner_main_action_l108c28
  assign WILL_FIRE_RL_inner_main_action_l108c28 =
	     inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d370 &&
	     inner_main_state_mkFSMstate == 5'd15 ||
	     !inner_cur_temp_33_ULE_40___d357 &&
	     !inner_cur_temp_33_ULT_inner_last_temp_43___d359 &&
	     inner_tSpeed_19_ULT_100___d362 &&
	     inner_main_state_mkFSMstate == 5'd17 ;

  // inputs to muxes for submodule ports
  assign MUX_inner_fan_fan_fRequest$enq_1__SEL_1 =
	     WILL_FIRE_RL_inner_main_action_l109c24 ||
	     WILL_FIRE_RL_inner_main_action_l103c24 ||
	     WILL_FIRE_RL_inner_main_action_l94c12 ;
  assign MUX_inner_fan_fan_rOutEn$write_1__SEL_1 =
	     WILL_FIRE_RL_inner_fan_fan_done_write ||
	     WILL_FIRE_RL_inner_fan_fan_running_write ;
  assign MUX_inner_fan_fan_rState$write_1__SEL_1 =
	     WILL_FIRE_RL_inner_fan_fan_done_read ||
	     WILL_FIRE_RL_inner_fan_fan_done_write ;
  assign MUX_inner_fan_fan_rState$write_1__SEL_2 =
	     inner_fan_fan_fRequest$EMPTY_N && !inner_fan_fan_rState ;
  assign MUX_inner_temp_temp_rOutEn$write_1__SEL_1 =
	     WILL_FIRE_RL_inner_temp_temp_done_write ||
	     WILL_FIRE_RL_inner_temp_temp_running_write ;
  assign MUX_inner_temp_temp_rState$write_1__SEL_1 =
	     WILL_FIRE_RL_inner_temp_temp_done_read ||
	     WILL_FIRE_RL_inner_temp_temp_done_write ;
  assign MUX_inner_temp_temp_rState$write_1__SEL_2 =
	     inner_temp_temp_fRequest$EMPTY_N && !inner_temp_temp_rState ;
  assign MUX_inner_cnt$write_1__VAL_1 = inner_cnt - 32'd1 ;
  assign MUX_inner_fan_fan_fRequest$enq_1__VAL_1 = { 16'd51200, x__h78896 } ;
  assign MUX_inner_fan_fan_rOutEn$write_1__VAL_1 =
	     _154742503901866210315206599__q2[inner_fan_fan_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_fan_fan_rOutEn$write_1__VAL_2 =
	     _1329227987119335533342540869413109767__q3[inner_fan_fan_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_fan_fan_rSCL$write_1__VAL_1 =
	     _121583396715528419856163987__q4[inner_fan_fan_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_fan_fan_rSCL$write_1__VAL_2 =
	     _1044393425259576759155060135206397075__q5[inner_fan_fan_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_fan_fan_rSDA$write_1__VAL_1 =
	     wWrData__h1563[inner_fan_fan_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_fan_fan_rSDA$write_1__VAL_2 =
	     wRdData__h1559[inner_fan_fan_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_tSpeed$write_1__VAL_1 = inner_tSpeed - 8'd5 ;
  assign MUX_inner_tSpeed$write_1__VAL_2 = inner_tSpeed + 8'd5 ;
  assign MUX_inner_temp_temp_rOutEn$write_1__VAL_1 =
	     _154742503901866210315206599__q2[inner_temp_temp_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_temp_temp_rOutEn$write_1__VAL_2 =
	     _1329227987119335533342540869413109767__q3[inner_temp_temp_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_temp_temp_rSCL$write_1__VAL_1 =
	     _121583396715528419856163987__q4[inner_temp_temp_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_temp_temp_rSCL$write_1__VAL_2 =
	     _1044393425259576759155060135206397075__q5[inner_temp_temp_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_temp_temp_rSDA$write_1__VAL_1 =
	     wWrData__h16188[inner_temp_temp_rPlayIndex$Q_OUT[6:0]] ;
  assign MUX_inner_temp_temp_rSDA$write_1__VAL_2 =
	     wRdData__h16184[inner_temp_temp_rPlayIndex$Q_OUT[6:0]] ;

  // inlined wires
  assign inner_main_start_wire$whas =
	     WILL_FIRE_RL_inner_main_fsm_start ||
	     inner_main_start_reg_1 && !inner_main_state_fired ;
  assign inner_main_state_set_pw$whas =
	     WILL_FIRE_RL_inner_main_action_l114c18 ||
	     inner_main_state_mkFSMstate == 5'd20 ||
	     inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	     WILL_FIRE_RL_inner_main_action_l109c24 ||
	     WILL_FIRE_RL_inner_main_action_l108c28 ||
	     WILL_FIRE_RL_inner_main_action_l103c24 ||
	     WILL_FIRE_RL_inner_main_action_l102c28 ||
	     WILL_FIRE_RL_inner_main_action_l25c13 ||
	     WILL_FIRE_RL_inner_main_action_l24c26 ||
	     inner_main_state_mkFSMstate == 5'd12 ||
	     WILL_FIRE_RL_inner_main_action_l97c17 ||
	     inner_main_state_mkFSMstate == 5'd10 ||
	     WILL_FIRE_RL_inner_main_action_l94c12 ||
	     WILL_FIRE_RL_inner_main_action_l19c27 ||
	     WILL_FIRE_RL_inner_main_action_l43c27 ||
	     WILL_FIRE_RL_inner_main_action_l42c27 ||
	     WILL_FIRE_RL_inner_main_action_l41c27 ||
	     WILL_FIRE_RL_inner_main_action_l40c27 ||
	     WILL_FIRE_RL_inner_main_action_l39c27 ||
	     inner_main_state_mkFSMstate == 5'd2 ||
	     WILL_FIRE_RL_inner_main_action_l90c14 ||
	     WILL_FIRE_RL_inner_main_action_l89c13 ;

  // register inner_cnt
  assign inner_cnt$D_IN =
	     (inner_cnt != 32'd0) ?
	       MUX_inner_cnt$write_1__VAL_1 :
	       32'd250000000 ;
  assign inner_cnt$EN =
	     inner_cnt != 32'd0 ||
	     inner_cnt == 32'd0 &&
	     inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ;

  // register inner_cur_temp
  assign inner_cur_temp$D_IN = inner_temp_temp_fResponse$D_OUT ;
  assign inner_cur_temp$EN = WILL_FIRE_RL_inner_main_action_l25c13 ;

  // register inner_fan_fan_rAddress
  assign inner_fan_fan_rAddress$D_IN = inner_fan_fan_fRequest$D_OUT[15:8] ;
  assign inner_fan_fan_rAddress$EN = MUX_inner_fan_fan_rState$write_1__SEL_2 ;

  // register inner_fan_fan_rOutEn
  assign inner_fan_fan_rOutEn$D_IN =
	     MUX_inner_fan_fan_rOutEn$write_1__SEL_1 ?
	       MUX_inner_fan_fan_rOutEn$write_1__VAL_1 :
	       MUX_inner_fan_fan_rOutEn$write_1__VAL_2 ;
  assign inner_fan_fan_rOutEn$EN =
	     WILL_FIRE_RL_inner_fan_fan_done_write ||
	     WILL_FIRE_RL_inner_fan_fan_running_write ||
	     WILL_FIRE_RL_inner_fan_fan_done_read ||
	     WILL_FIRE_RL_inner_fan_fan_running_read ;

  // register inner_fan_fan_rSCL
  assign inner_fan_fan_rSCL$D_IN =
	     MUX_inner_fan_fan_rOutEn$write_1__SEL_1 ?
	       MUX_inner_fan_fan_rSCL$write_1__VAL_1 :
	       MUX_inner_fan_fan_rSCL$write_1__VAL_2 ;
  assign inner_fan_fan_rSCL$EN =
	     WILL_FIRE_RL_inner_fan_fan_done_write ||
	     WILL_FIRE_RL_inner_fan_fan_running_write ||
	     WILL_FIRE_RL_inner_fan_fan_done_read ||
	     WILL_FIRE_RL_inner_fan_fan_running_read ;

  // register inner_fan_fan_rSDA
  assign inner_fan_fan_rSDA$D_IN =
	     MUX_inner_fan_fan_rOutEn$write_1__SEL_1 ?
	       MUX_inner_fan_fan_rSDA$write_1__VAL_1 :
	       MUX_inner_fan_fan_rSDA$write_1__VAL_2 ;
  assign inner_fan_fan_rSDA$EN =
	     WILL_FIRE_RL_inner_fan_fan_done_write ||
	     WILL_FIRE_RL_inner_fan_fan_running_write ||
	     WILL_FIRE_RL_inner_fan_fan_done_read ||
	     WILL_FIRE_RL_inner_fan_fan_running_read ;

  // register inner_fan_fan_rSlaveAddr
  assign inner_fan_fan_rSlaveAddr$D_IN = inner_fan_fan_fRequest$D_OUT[22:16] ;
  assign inner_fan_fan_rSlaveAddr$EN =
	     MUX_inner_fan_fan_rState$write_1__SEL_2 ;

  // register inner_fan_fan_rState
  assign inner_fan_fan_rState$D_IN =
	     !MUX_inner_fan_fan_rState$write_1__SEL_1 ;
  assign inner_fan_fan_rState$EN =
	     WILL_FIRE_RL_inner_fan_fan_done_read ||
	     WILL_FIRE_RL_inner_fan_fan_done_write ||
	     inner_fan_fan_fRequest$EMPTY_N && !inner_fan_fan_rState ;

  // register inner_fan_fan_rWrite
  assign inner_fan_fan_rWrite$D_IN = inner_fan_fan_fRequest$D_OUT[23] ;
  assign inner_fan_fan_rWrite$EN = MUX_inner_fan_fan_rState$write_1__SEL_2 ;

  // register inner_fan_fan_rWriteData
  assign inner_fan_fan_rWriteData$D_IN = inner_fan_fan_fRequest$D_OUT[7:0] ;
  assign inner_fan_fan_rWriteData$EN =
	     MUX_inner_fan_fan_rState$write_1__SEL_2 ;

  // register inner_fan_fan_vrReadData_0
  assign inner_fan_fan_vrReadData_0$D_IN = inner_fan_fan_tSDA$O ;
  assign inner_fan_fan_vrReadData_0$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_fan_fan_vrReadData_1
  assign inner_fan_fan_vrReadData_1$D_IN = inner_fan_fan_vrReadData_0 ;
  assign inner_fan_fan_vrReadData_1$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_fan_fan_vrReadData_2
  assign inner_fan_fan_vrReadData_2$D_IN = inner_fan_fan_vrReadData_1 ;
  assign inner_fan_fan_vrReadData_2$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_fan_fan_vrReadData_3
  assign inner_fan_fan_vrReadData_3$D_IN = inner_fan_fan_vrReadData_2 ;
  assign inner_fan_fan_vrReadData_3$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_fan_fan_vrReadData_4
  assign inner_fan_fan_vrReadData_4$D_IN = inner_fan_fan_vrReadData_3 ;
  assign inner_fan_fan_vrReadData_4$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_fan_fan_vrReadData_5
  assign inner_fan_fan_vrReadData_5$D_IN = inner_fan_fan_vrReadData_4 ;
  assign inner_fan_fan_vrReadData_5$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_fan_fan_vrReadData_6
  assign inner_fan_fan_vrReadData_6$D_IN = inner_fan_fan_vrReadData_5 ;
  assign inner_fan_fan_vrReadData_6$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_fan_fan_vrReadData_7
  assign inner_fan_fan_vrReadData_7$D_IN = inner_fan_fan_vrReadData_6 ;
  assign inner_fan_fan_vrReadData_7$EN =
	     WILL_FIRE_RL_inner_fan_fan_running_read &&
	     _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 ;

  // register inner_last_temp
  assign inner_last_temp$D_IN = inner_cur_temp ;
  assign inner_last_temp$EN = inner_main_state_mkFSMstate == 5'd12 ;

  // register inner_led
  always@(WILL_FIRE_RL_inner_main_action_l89c13 or
	  inner_main_state_mkFSMstate or
	  WILL_FIRE_RL_inner_main_action_l97c17)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_inner_main_action_l89c13: inner_led$D_IN = 4'd0;
      inner_main_state_mkFSMstate == 5'd2: inner_led$D_IN = 4'd1;
      inner_main_state_mkFSMstate == 5'd10: inner_led$D_IN = 4'd2;
      WILL_FIRE_RL_inner_main_action_l97c17: inner_led$D_IN = 4'd4;
      inner_main_state_mkFSMstate == 5'd20: inner_led$D_IN = 4'd8;
      default: inner_led$D_IN = 4'b1010 /* unspecified value */ ;
    endcase
  end
  assign inner_led$EN =
	     WILL_FIRE_RL_inner_main_action_l89c13 ||
	     inner_main_state_mkFSMstate == 5'd2 ||
	     inner_main_state_mkFSMstate == 5'd10 ||
	     WILL_FIRE_RL_inner_main_action_l97c17 ||
	     inner_main_state_mkFSMstate == 5'd20 ;

  // register inner_main_start_reg
  assign inner_main_start_reg$D_IN = !WILL_FIRE_RL_inner_main_fsm_start ;
  assign inner_main_start_reg$EN =
	     WILL_FIRE_RL_inner_main_fsm_start ||
	     inner_main_abort_whas__60_AND_inner_main_abort_ETC___d402 &&
	     !inner_main_start_reg ;

  // register inner_main_start_reg_1
  assign inner_main_start_reg_1$D_IN = inner_main_start_wire$whas ;
  assign inner_main_start_reg_1$EN = 1'd1 ;

  // register inner_main_state_can_overlap
  assign inner_main_state_can_overlap$D_IN =
	     inner_main_state_set_pw$whas || inner_main_state_can_overlap ;
  assign inner_main_state_can_overlap$EN = 1'd1 ;

  // register inner_main_state_fired
  assign inner_main_state_fired$D_IN = inner_main_state_set_pw$whas ;
  assign inner_main_state_fired$EN = 1'd1 ;

  // register inner_main_state_mkFSMstate
  always@(WILL_FIRE_RL_inner_main_action_l89c13 or
	  WILL_FIRE_RL_inner_main_action_l90c14 or
	  inner_main_state_mkFSMstate or
	  WILL_FIRE_RL_inner_main_action_l39c27 or
	  WILL_FIRE_RL_inner_main_action_l40c27 or
	  WILL_FIRE_RL_inner_main_action_l41c27 or
	  WILL_FIRE_RL_inner_main_action_l42c27 or
	  WILL_FIRE_RL_inner_main_action_l43c27 or
	  WILL_FIRE_RL_inner_main_action_l19c27 or
	  WILL_FIRE_RL_inner_main_action_l94c12 or
	  WILL_FIRE_RL_inner_main_action_l97c17 or
	  WILL_FIRE_RL_inner_main_action_l24c26 or
	  WILL_FIRE_RL_inner_main_action_l25c13 or
	  WILL_FIRE_RL_inner_main_action_l102c28 or
	  WILL_FIRE_RL_inner_main_action_l103c24 or
	  WILL_FIRE_RL_inner_main_action_l108c28 or
	  WILL_FIRE_RL_inner_main_action_l109c24 or
	  inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 or
	  WILL_FIRE_RL_inner_main_action_l114c18)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_inner_main_action_l89c13:
	  inner_main_state_mkFSMstate$D_IN = 5'd1;
      WILL_FIRE_RL_inner_main_action_l90c14:
	  inner_main_state_mkFSMstate$D_IN = 5'd2;
      inner_main_state_mkFSMstate == 5'd2:
	  inner_main_state_mkFSMstate$D_IN = 5'd3;
      WILL_FIRE_RL_inner_main_action_l39c27:
	  inner_main_state_mkFSMstate$D_IN = 5'd4;
      WILL_FIRE_RL_inner_main_action_l40c27:
	  inner_main_state_mkFSMstate$D_IN = 5'd5;
      WILL_FIRE_RL_inner_main_action_l41c27:
	  inner_main_state_mkFSMstate$D_IN = 5'd6;
      WILL_FIRE_RL_inner_main_action_l42c27:
	  inner_main_state_mkFSMstate$D_IN = 5'd7;
      WILL_FIRE_RL_inner_main_action_l43c27:
	  inner_main_state_mkFSMstate$D_IN = 5'd8;
      WILL_FIRE_RL_inner_main_action_l19c27:
	  inner_main_state_mkFSMstate$D_IN = 5'd9;
      WILL_FIRE_RL_inner_main_action_l94c12:
	  inner_main_state_mkFSMstate$D_IN = 5'd10;
      inner_main_state_mkFSMstate == 5'd10:
	  inner_main_state_mkFSMstate$D_IN = 5'd11;
      WILL_FIRE_RL_inner_main_action_l97c17:
	  inner_main_state_mkFSMstate$D_IN = 5'd12;
      inner_main_state_mkFSMstate == 5'd12:
	  inner_main_state_mkFSMstate$D_IN = 5'd13;
      WILL_FIRE_RL_inner_main_action_l24c26:
	  inner_main_state_mkFSMstate$D_IN = 5'd14;
      WILL_FIRE_RL_inner_main_action_l25c13:
	  inner_main_state_mkFSMstate$D_IN = 5'd15;
      WILL_FIRE_RL_inner_main_action_l102c28:
	  inner_main_state_mkFSMstate$D_IN = 5'd16;
      WILL_FIRE_RL_inner_main_action_l103c24:
	  inner_main_state_mkFSMstate$D_IN = 5'd17;
      WILL_FIRE_RL_inner_main_action_l108c28:
	  inner_main_state_mkFSMstate$D_IN = 5'd18;
      WILL_FIRE_RL_inner_main_action_l109c24:
	  inner_main_state_mkFSMstate$D_IN = 5'd19;
      inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393:
	  inner_main_state_mkFSMstate$D_IN = 5'd20;
      inner_main_state_mkFSMstate == 5'd20:
	  inner_main_state_mkFSMstate$D_IN = 5'd21;
      WILL_FIRE_RL_inner_main_action_l114c18:
	  inner_main_state_mkFSMstate$D_IN = 5'd22;
      default: inner_main_state_mkFSMstate$D_IN =
		   5'b01010 /* unspecified value */ ;
    endcase
  end
  assign inner_main_state_mkFSMstate$EN =
	     WILL_FIRE_RL_inner_main_action_l89c13 ||
	     WILL_FIRE_RL_inner_main_action_l90c14 ||
	     inner_main_state_mkFSMstate == 5'd2 ||
	     WILL_FIRE_RL_inner_main_action_l39c27 ||
	     WILL_FIRE_RL_inner_main_action_l40c27 ||
	     WILL_FIRE_RL_inner_main_action_l41c27 ||
	     WILL_FIRE_RL_inner_main_action_l42c27 ||
	     WILL_FIRE_RL_inner_main_action_l43c27 ||
	     WILL_FIRE_RL_inner_main_action_l19c27 ||
	     WILL_FIRE_RL_inner_main_action_l94c12 ||
	     inner_main_state_mkFSMstate == 5'd10 ||
	     WILL_FIRE_RL_inner_main_action_l97c17 ||
	     inner_main_state_mkFSMstate == 5'd12 ||
	     WILL_FIRE_RL_inner_main_action_l24c26 ||
	     WILL_FIRE_RL_inner_main_action_l25c13 ||
	     WILL_FIRE_RL_inner_main_action_l102c28 ||
	     WILL_FIRE_RL_inner_main_action_l103c24 ||
	     WILL_FIRE_RL_inner_main_action_l108c28 ||
	     WILL_FIRE_RL_inner_main_action_l109c24 ||
	     inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	     inner_main_state_mkFSMstate == 5'd20 ||
	     WILL_FIRE_RL_inner_main_action_l114c18 ;

  // register inner_tSpeed
  assign inner_tSpeed$D_IN =
	     WILL_FIRE_RL_inner_main_action_l102c28 ?
	       MUX_inner_tSpeed$write_1__VAL_1 :
	       MUX_inner_tSpeed$write_1__VAL_2 ;
  assign inner_tSpeed$EN =
	     WILL_FIRE_RL_inner_main_action_l102c28 ||
	     WILL_FIRE_RL_inner_main_action_l108c28 ;

  // register inner_temp_temp_rAddress
  assign inner_temp_temp_rAddress$D_IN =
	     inner_temp_temp_fRequest$D_OUT[15:8] ;
  assign inner_temp_temp_rAddress$EN =
	     MUX_inner_temp_temp_rState$write_1__SEL_2 ;

  // register inner_temp_temp_rOutEn
  assign inner_temp_temp_rOutEn$D_IN =
	     MUX_inner_temp_temp_rOutEn$write_1__SEL_1 ?
	       MUX_inner_temp_temp_rOutEn$write_1__VAL_1 :
	       MUX_inner_temp_temp_rOutEn$write_1__VAL_2 ;
  assign inner_temp_temp_rOutEn$EN =
	     WILL_FIRE_RL_inner_temp_temp_done_write ||
	     WILL_FIRE_RL_inner_temp_temp_running_write ||
	     WILL_FIRE_RL_inner_temp_temp_done_read ||
	     WILL_FIRE_RL_inner_temp_temp_running_read ;

  // register inner_temp_temp_rSCL
  assign inner_temp_temp_rSCL$D_IN =
	     MUX_inner_temp_temp_rOutEn$write_1__SEL_1 ?
	       MUX_inner_temp_temp_rSCL$write_1__VAL_1 :
	       MUX_inner_temp_temp_rSCL$write_1__VAL_2 ;
  assign inner_temp_temp_rSCL$EN =
	     WILL_FIRE_RL_inner_temp_temp_done_write ||
	     WILL_FIRE_RL_inner_temp_temp_running_write ||
	     WILL_FIRE_RL_inner_temp_temp_done_read ||
	     WILL_FIRE_RL_inner_temp_temp_running_read ;

  // register inner_temp_temp_rSDA
  assign inner_temp_temp_rSDA$D_IN =
	     MUX_inner_temp_temp_rOutEn$write_1__SEL_1 ?
	       MUX_inner_temp_temp_rSDA$write_1__VAL_1 :
	       MUX_inner_temp_temp_rSDA$write_1__VAL_2 ;
  assign inner_temp_temp_rSDA$EN =
	     WILL_FIRE_RL_inner_temp_temp_done_write ||
	     WILL_FIRE_RL_inner_temp_temp_running_write ||
	     WILL_FIRE_RL_inner_temp_temp_done_read ||
	     WILL_FIRE_RL_inner_temp_temp_running_read ;

  // register inner_temp_temp_rSlaveAddr
  assign inner_temp_temp_rSlaveAddr$D_IN =
	     inner_temp_temp_fRequest$D_OUT[22:16] ;
  assign inner_temp_temp_rSlaveAddr$EN =
	     MUX_inner_temp_temp_rState$write_1__SEL_2 ;

  // register inner_temp_temp_rState
  assign inner_temp_temp_rState$D_IN =
	     !MUX_inner_temp_temp_rState$write_1__SEL_1 ;
  assign inner_temp_temp_rState$EN =
	     WILL_FIRE_RL_inner_temp_temp_done_read ||
	     WILL_FIRE_RL_inner_temp_temp_done_write ||
	     inner_temp_temp_fRequest$EMPTY_N && !inner_temp_temp_rState ;

  // register inner_temp_temp_rWrite
  assign inner_temp_temp_rWrite$D_IN = inner_temp_temp_fRequest$D_OUT[23] ;
  assign inner_temp_temp_rWrite$EN =
	     MUX_inner_temp_temp_rState$write_1__SEL_2 ;

  // register inner_temp_temp_rWriteData
  assign inner_temp_temp_rWriteData$D_IN =
	     inner_temp_temp_fRequest$D_OUT[7:0] ;
  assign inner_temp_temp_rWriteData$EN =
	     MUX_inner_temp_temp_rState$write_1__SEL_2 ;

  // register inner_temp_temp_vrReadData_0
  assign inner_temp_temp_vrReadData_0$D_IN = inner_temp_temp_tSDA$O ;
  assign inner_temp_temp_vrReadData_0$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // register inner_temp_temp_vrReadData_1
  assign inner_temp_temp_vrReadData_1$D_IN = inner_temp_temp_vrReadData_0 ;
  assign inner_temp_temp_vrReadData_1$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // register inner_temp_temp_vrReadData_2
  assign inner_temp_temp_vrReadData_2$D_IN = inner_temp_temp_vrReadData_1 ;
  assign inner_temp_temp_vrReadData_2$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // register inner_temp_temp_vrReadData_3
  assign inner_temp_temp_vrReadData_3$D_IN = inner_temp_temp_vrReadData_2 ;
  assign inner_temp_temp_vrReadData_3$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // register inner_temp_temp_vrReadData_4
  assign inner_temp_temp_vrReadData_4$D_IN = inner_temp_temp_vrReadData_3 ;
  assign inner_temp_temp_vrReadData_4$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // register inner_temp_temp_vrReadData_5
  assign inner_temp_temp_vrReadData_5$D_IN = inner_temp_temp_vrReadData_4 ;
  assign inner_temp_temp_vrReadData_5$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // register inner_temp_temp_vrReadData_6
  assign inner_temp_temp_vrReadData_6$D_IN = inner_temp_temp_vrReadData_5 ;
  assign inner_temp_temp_vrReadData_6$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // register inner_temp_temp_vrReadData_7
  assign inner_temp_temp_vrReadData_7$D_IN = inner_temp_temp_vrReadData_6 ;
  assign inner_temp_temp_vrReadData_7$EN =
	     WILL_FIRE_RL_inner_temp_temp_running_read &&
	     _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 ;

  // submodule inner_fan_fan_fRequest
  always@(MUX_inner_fan_fan_fRequest$enq_1__SEL_1 or
	  MUX_inner_fan_fan_fRequest$enq_1__VAL_1 or
	  WILL_FIRE_RL_inner_main_action_l39c27 or
	  WILL_FIRE_RL_inner_main_action_l40c27 or
	  WILL_FIRE_RL_inner_main_action_l41c27 or
	  WILL_FIRE_RL_inner_main_action_l42c27 or
	  WILL_FIRE_RL_inner_main_action_l43c27)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_inner_fan_fan_fRequest$enq_1__SEL_1:
	  inner_fan_fan_fRequest$D_IN =
	      MUX_inner_fan_fan_fRequest$enq_1__VAL_1;
      WILL_FIRE_RL_inner_main_action_l39c27:
	  inner_fan_fan_fRequest$D_IN = 24'd13107328;
      WILL_FIRE_RL_inner_main_action_l40c27:
	  inner_fan_fan_fRequest$D_IN = 24'd13107754;
      WILL_FIRE_RL_inner_main_action_l41c27:
	  inner_fan_fan_fRequest$D_IN = 24'd13108469;
      WILL_FIRE_RL_inner_main_action_l42c27:
	  inner_fan_fan_fRequest$D_IN = 24'd13109263;
      WILL_FIRE_RL_inner_main_action_l43c27:
	  inner_fan_fan_fRequest$D_IN = 24'd13112834;
      default: inner_fan_fan_fRequest$D_IN =
		   24'b101010101010101010101010 /* unspecified value */ ;
    endcase
  end
  assign inner_fan_fan_fRequest$ENQ =
	     WILL_FIRE_RL_inner_main_action_l109c24 ||
	     WILL_FIRE_RL_inner_main_action_l103c24 ||
	     WILL_FIRE_RL_inner_main_action_l94c12 ||
	     WILL_FIRE_RL_inner_main_action_l39c27 ||
	     WILL_FIRE_RL_inner_main_action_l40c27 ||
	     WILL_FIRE_RL_inner_main_action_l41c27 ||
	     WILL_FIRE_RL_inner_main_action_l42c27 ||
	     WILL_FIRE_RL_inner_main_action_l43c27 ;
  assign inner_fan_fan_fRequest$DEQ =
	     MUX_inner_fan_fan_rState$write_1__SEL_2 ;
  assign inner_fan_fan_fRequest$CLR = 1'b0 ;

  // submodule inner_fan_fan_fResponse
  assign inner_fan_fan_fResponse$D_IN =
	     { inner_fan_fan_vrReadData_7,
	       inner_fan_fan_vrReadData_6,
	       inner_fan_fan_vrReadData_5,
	       inner_fan_fan_vrReadData_4,
	       inner_fan_fan_vrReadData_3,
	       inner_fan_fan_vrReadData_2,
	       inner_fan_fan_vrReadData_1,
	       inner_fan_fan_vrReadData_0 } ;
  assign inner_fan_fan_fResponse$ENQ = WILL_FIRE_RL_inner_fan_fan_done_read ;
  assign inner_fan_fan_fResponse$DEQ = 1'b0 ;
  assign inner_fan_fan_fResponse$CLR = 1'b0 ;

  // submodule inner_fan_fan_rPlayIndex
  assign inner_fan_fan_rPlayIndex$DATA_A = 10'h0 ;
  assign inner_fan_fan_rPlayIndex$DATA_B = 10'd1023 ;
  assign inner_fan_fan_rPlayIndex$DATA_C = 10'h0 ;
  assign inner_fan_fan_rPlayIndex$DATA_F =
	     inner_fan_fan_fRequest$D_OUT[23] ? 10'd86 : 10'd119 ;
  assign inner_fan_fan_rPlayIndex$ADDA = 1'b0 ;
  assign inner_fan_fan_rPlayIndex$ADDB =
	     WILL_FIRE_RL_inner_fan_fan_done_write ||
	     WILL_FIRE_RL_inner_fan_fan_running_read ||
	     WILL_FIRE_RL_inner_fan_fan_running_write ;
  assign inner_fan_fan_rPlayIndex$SETC = 1'b0 ;
  assign inner_fan_fan_rPlayIndex$SETF =
	     MUX_inner_fan_fan_rState$write_1__SEL_2 ;

  // submodule inner_fan_fan_rPrescaler
  assign inner_fan_fan_rPrescaler$DATA_A = 32'h0 ;
  assign inner_fan_fan_rPrescaler$DATA_B = 32'hFFFFFFFF ;
  assign inner_fan_fan_rPrescaler$DATA_C = 32'h0 ;
  assign inner_fan_fan_rPrescaler$DATA_F = 32'd125 ;
  assign inner_fan_fan_rPrescaler$ADDA = 1'b0 ;
  assign inner_fan_fan_rPrescaler$ADDB =
	     inner_fan_fan_rPrescaler$Q_OUT != 32'd0 ;
  assign inner_fan_fan_rPrescaler$SETC = 1'b0 ;
  assign inner_fan_fan_rPrescaler$SETF =
	     inner_fan_fan_rPrescaler$Q_OUT == 32'd0 ;

  // submodule inner_temp_temp_fRequest
  assign inner_temp_temp_fRequest$D_IN =
	     WILL_FIRE_RL_inner_main_action_l24c26 ?
	       24'd1835264 :
	       24'd10226196 ;
  assign inner_temp_temp_fRequest$ENQ =
	     WILL_FIRE_RL_inner_main_action_l24c26 ||
	     WILL_FIRE_RL_inner_main_action_l19c27 ;
  assign inner_temp_temp_fRequest$DEQ =
	     MUX_inner_temp_temp_rState$write_1__SEL_2 ;
  assign inner_temp_temp_fRequest$CLR = 1'b0 ;

  // submodule inner_temp_temp_fResponse
  assign inner_temp_temp_fResponse$D_IN =
	     { inner_temp_temp_vrReadData_7,
	       inner_temp_temp_vrReadData_6,
	       inner_temp_temp_vrReadData_5,
	       inner_temp_temp_vrReadData_4,
	       inner_temp_temp_vrReadData_3,
	       inner_temp_temp_vrReadData_2,
	       inner_temp_temp_vrReadData_1,
	       inner_temp_temp_vrReadData_0 } ;
  assign inner_temp_temp_fResponse$ENQ =
	     WILL_FIRE_RL_inner_temp_temp_done_read ;
  assign inner_temp_temp_fResponse$DEQ =
	     WILL_FIRE_RL_inner_main_action_l25c13 ;
  assign inner_temp_temp_fResponse$CLR = 1'b0 ;

  // submodule inner_temp_temp_rPlayIndex
  assign inner_temp_temp_rPlayIndex$DATA_A = 10'h0 ;
  assign inner_temp_temp_rPlayIndex$DATA_B = 10'd1023 ;
  assign inner_temp_temp_rPlayIndex$DATA_C = 10'h0 ;
  assign inner_temp_temp_rPlayIndex$DATA_F =
	     inner_temp_temp_fRequest$D_OUT[23] ? 10'd86 : 10'd119 ;
  assign inner_temp_temp_rPlayIndex$ADDA = 1'b0 ;
  assign inner_temp_temp_rPlayIndex$ADDB =
	     WILL_FIRE_RL_inner_temp_temp_done_write ||
	     WILL_FIRE_RL_inner_temp_temp_running_read ||
	     WILL_FIRE_RL_inner_temp_temp_running_write ;
  assign inner_temp_temp_rPlayIndex$SETC = 1'b0 ;
  assign inner_temp_temp_rPlayIndex$SETF =
	     MUX_inner_temp_temp_rState$write_1__SEL_2 ;

  // submodule inner_temp_temp_rPrescaler
  assign inner_temp_temp_rPrescaler$DATA_A = 32'h0 ;
  assign inner_temp_temp_rPrescaler$DATA_B = 32'hFFFFFFFF ;
  assign inner_temp_temp_rPrescaler$DATA_C = 32'h0 ;
  assign inner_temp_temp_rPrescaler$DATA_F = 32'd125 ;
  assign inner_temp_temp_rPrescaler$ADDA = 1'b0 ;
  assign inner_temp_temp_rPrescaler$ADDB =
	     inner_temp_temp_rPrescaler$Q_OUT != 32'd0 ;
  assign inner_temp_temp_rPrescaler$SETC = 1'b0 ;
  assign inner_temp_temp_rPrescaler$SETF =
	     inner_temp_temp_rPrescaler$Q_OUT == 32'd0 ;

  // submodule r
  assign r$ASSERT_IN = 1'b0 ;

  // remaining internal signals
  assign NOT_inner_cur_temp_33_ULT_40_42_66_OR_NOT_inne_ETC___d369 =
	     (!inner_cur_temp_33_ULT_40___d342 ||
	      !inner_cur_temp_33_ULE_inner_last_temp_43___d344) &&
	     !inner_cur_temp_33_ULE_40___d357 &&
	     !inner_cur_temp_33_ULT_inner_last_temp_43___d359 &&
	     inner_tSpeed_19_ULT_100___d362 ;
  assign NOT_inner_cur_temp_33_ULT_40_42_66_OR_NOT_inne_ETC___d386 =
	     (!inner_cur_temp_33_ULT_40___d342 ||
	      !inner_cur_temp_33_ULE_inner_last_temp_43___d344) &&
	     (!inner_tSpeed_19_ULT_100___d362 ||
	      inner_cur_temp_33_ULE_40___d357 ||
	      inner_cur_temp_33_ULT_inner_last_temp_43___d359) ;
  assign _1044393425259576759155060135206397075__q5 =
	     120'hC92492492492493E92492492492493 ;
  assign _121583396715528419856163987__q4 = 87'h6492492492492492492493 ;
  assign _1329227987119335533342540869413109767__q3 =
	     120'hFFFFFFE3FFFFFC7FFFFFFE00000007 ;
  assign _154742503901866210315206599__q2 = 87'h7FFFFFF1FFFFFE3FFFFFC7 ;
  assign _306783360_BIT_inner_fan_fan_rPlayIndex_value___ETC___d108 =
	     _306783360__q1[inner_fan_fan_rPlayIndex$Q_OUT[6:0]] ;
  assign _306783360_BIT_inner_temp_temp_rPlayIndex_value_ETC___d233 =
	     _306783360__q1[inner_temp_temp_rPlayIndex$Q_OUT[6:0]] ;
  assign _306783360__q1 = 120'd306783360 ;
  assign a0__h1548 = {3{inner_fan_fan_rAddress[0]}} ;
  assign a0__h16173 = {3{inner_temp_temp_rAddress[0]}} ;
  assign a1__h1547 = {3{inner_fan_fan_rAddress[1]}} ;
  assign a1__h16172 = {3{inner_temp_temp_rAddress[1]}} ;
  assign a2__h1546 = {3{inner_fan_fan_rAddress[2]}} ;
  assign a2__h16171 = {3{inner_temp_temp_rAddress[2]}} ;
  assign a3__h1545 = {3{inner_fan_fan_rAddress[3]}} ;
  assign a3__h16170 = {3{inner_temp_temp_rAddress[3]}} ;
  assign a4__h1544 = {3{inner_fan_fan_rAddress[4]}} ;
  assign a4__h16169 = {3{inner_temp_temp_rAddress[4]}} ;
  assign a5__h1543 = {3{inner_fan_fan_rAddress[5]}} ;
  assign a5__h16168 = {3{inner_temp_temp_rAddress[5]}} ;
  assign a6__h1542 = {3{inner_fan_fan_rAddress[6]}} ;
  assign a6__h16167 = {3{inner_temp_temp_rAddress[6]}} ;
  assign a7__h1541 = {3{inner_fan_fan_rAddress[7]}} ;
  assign a7__h16166 = {3{inner_temp_temp_rAddress[7]}} ;
  assign d0__h1557 = {3{inner_fan_fan_rWriteData[0]}} ;
  assign d0__h16182 = {3{inner_temp_temp_rWriteData[0]}} ;
  assign d1__h1556 = {3{inner_fan_fan_rWriteData[1]}} ;
  assign d1__h16181 = {3{inner_temp_temp_rWriteData[1]}} ;
  assign d2__h1555 = {3{inner_fan_fan_rWriteData[2]}} ;
  assign d2__h16180 = {3{inner_temp_temp_rWriteData[2]}} ;
  assign d3__h1554 = {3{inner_fan_fan_rWriteData[3]}} ;
  assign d3__h16179 = {3{inner_temp_temp_rWriteData[3]}} ;
  assign d4__h1553 = {3{inner_fan_fan_rWriteData[4]}} ;
  assign d4__h16178 = {3{inner_temp_temp_rWriteData[4]}} ;
  assign d5__h1552 = {3{inner_fan_fan_rWriteData[5]}} ;
  assign d5__h16177 = {3{inner_temp_temp_rWriteData[5]}} ;
  assign d6__h1551 = {3{inner_fan_fan_rWriteData[6]}} ;
  assign d6__h16176 = {3{inner_temp_temp_rWriteData[6]}} ;
  assign d7__h1550 = {3{inner_fan_fan_rWriteData[7]}} ;
  assign d7__h16175 = {3{inner_temp_temp_rWriteData[7]}} ;
  assign inner_cur_temp_33_ULE_40___d357 = inner_cur_temp <= 8'd40 ;
  assign inner_cur_temp_33_ULE_inner_last_temp_43___d344 =
	     inner_cur_temp <= inner_last_temp ;
  assign inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d370 =
	     inner_cur_temp_33_ULT_40___d342 &&
	     inner_cur_temp_33_ULE_inner_last_temp_43___d344 &&
	     inner_tSpeed_19_ULE_35___d346 &&
	     !inner_cur_temp_33_ULE_40___d357 &&
	     !inner_cur_temp_33_ULT_inner_last_temp_43___d359 &&
	     inner_tSpeed_19_ULT_100___d362 ||
	     NOT_inner_cur_temp_33_ULT_40_42_66_OR_NOT_inne_ETC___d369 ;
  assign inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d387 =
	     inner_cur_temp_33_ULT_40___d342 &&
	     inner_cur_temp_33_ULE_inner_last_temp_43___d344 &&
	     inner_tSpeed_19_ULE_35___d346 &&
	     (!inner_tSpeed_19_ULT_100___d362 ||
	      inner_cur_temp_33_ULE_40___d357 ||
	      inner_cur_temp_33_ULT_inner_last_temp_43___d359) ||
	     NOT_inner_cur_temp_33_ULT_40_42_66_OR_NOT_inne_ETC___d386 ;
  assign inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 =
	     inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d387 &&
	     inner_main_state_mkFSMstate == 5'd15 ||
	     (!inner_tSpeed_19_ULT_100___d362 ||
	      inner_cur_temp_33_ULE_40___d357 ||
	      inner_cur_temp_33_ULT_inner_last_temp_43___d359) &&
	     inner_main_state_mkFSMstate == 5'd17 ||
	     inner_main_state_mkFSMstate == 5'd19 ;
  assign inner_cur_temp_33_ULT_40___d342 = inner_cur_temp < 8'd40 ;
  assign inner_cur_temp_33_ULT_inner_last_temp_43___d359 =
	     inner_cur_temp < inner_last_temp ;
  assign inner_main_abort_whas__60_AND_inner_main_abort_ETC___d402 =
	     inner_main_state_mkFSMstate == 5'd0 &&
	     (!inner_main_start_reg_1 || inner_main_state_fired) ;
  assign inner_tSpeed_19_ULE_35___d346 = inner_tSpeed <= 8'd35 ;
  assign inner_tSpeed_19_ULT_100___d362 = inner_tSpeed < 8'd100 ;
  assign s0__h1539 = {3{inner_fan_fan_rSlaveAddr[0]}} ;
  assign s0__h16164 = {3{inner_temp_temp_rSlaveAddr[0]}} ;
  assign s1__h1538 = {3{inner_fan_fan_rSlaveAddr[1]}} ;
  assign s1__h16163 = {3{inner_temp_temp_rSlaveAddr[1]}} ;
  assign s2__h1537 = {3{inner_fan_fan_rSlaveAddr[2]}} ;
  assign s2__h16162 = {3{inner_temp_temp_rSlaveAddr[2]}} ;
  assign s3__h1536 = {3{inner_fan_fan_rSlaveAddr[3]}} ;
  assign s3__h16161 = {3{inner_temp_temp_rSlaveAddr[3]}} ;
  assign s4__h1535 = {3{inner_fan_fan_rSlaveAddr[4]}} ;
  assign s4__h16160 = {3{inner_temp_temp_rSlaveAddr[4]}} ;
  assign s5__h1534 = {3{inner_fan_fan_rSlaveAddr[5]}} ;
  assign s5__h16159 = {3{inner_temp_temp_rSlaveAddr[5]}} ;
  assign s6__h1533 = {3{inner_fan_fan_rSlaveAddr[6]}} ;
  assign s6__h16158 = {3{inner_temp_temp_rSlaveAddr[6]}} ;
  assign wRdData__h1559 =
	     { 3'b100,
	       s6__h1533,
	       s5__h1534,
	       s4__h1535,
	       s3__h1536,
	       s2__h1537,
	       s1__h1538,
	       s0__h1539,
	       6'd0,
	       a7__h1541,
	       a6__h1542,
	       a5__h1543,
	       a4__h1544,
	       a3__h1545,
	       a2__h1546,
	       a1__h1547,
	       a0__h1548,
	       9'd14,
	       s6__h1533,
	       s5__h1534,
	       s4__h1535,
	       s3__h1536,
	       s2__h1537,
	       s1__h1538,
	       s0__h1539,
	       36'hE00000001 } ;
  assign wRdData__h16184 =
	     { 3'b100,
	       s6__h16158,
	       s5__h16159,
	       s4__h16160,
	       s3__h16161,
	       s2__h16162,
	       s1__h16163,
	       s0__h16164,
	       6'd0,
	       a7__h16166,
	       a6__h16167,
	       a5__h16168,
	       a4__h16169,
	       a3__h16170,
	       a2__h16171,
	       a1__h16172,
	       a0__h16173,
	       9'd14,
	       s6__h16158,
	       s5__h16159,
	       s4__h16160,
	       s3__h16161,
	       s2__h16162,
	       s1__h16163,
	       s0__h16164,
	       36'hE00000001 } ;
  assign wWrData__h1563 =
	     { 3'b100,
	       s6__h1533,
	       s5__h1534,
	       s4__h1535,
	       s3__h1536,
	       s2__h1537,
	       s1__h1538,
	       s0__h1539,
	       6'd0,
	       a7__h1541,
	       a6__h1542,
	       a5__h1543,
	       a4__h1544,
	       a3__h1545,
	       a2__h1546,
	       a1__h1547,
	       a0__h1548,
	       3'b0,
	       d7__h1550,
	       d6__h1551,
	       d5__h1552,
	       d4__h1553,
	       d3__h1554,
	       d2__h1555,
	       d1__h1556,
	       d0__h1557,
	       6'd1 } ;
  assign wWrData__h16188 =
	     { 3'b100,
	       s6__h16158,
	       s5__h16159,
	       s4__h16160,
	       s3__h16161,
	       s2__h16162,
	       s1__h16163,
	       s0__h16164,
	       6'd0,
	       a7__h16166,
	       a6__h16167,
	       a5__h16168,
	       a4__h16169,
	       a3__h16170,
	       a2__h16171,
	       a1__h16172,
	       a0__h16173,
	       3'b0,
	       d7__h16175,
	       d6__h16176,
	       d5__h16177,
	       d4__h16178,
	       d3__h16179,
	       d2__h16180,
	       d1__h16181,
	       d0__h16182,
	       6'd1 } ;
  assign x__h76513 = 12'd3968 / y__h76530 ;
  assign x__h78896 = x__h76513[7:0] - 8'd1 ;
  assign y__h76530 = { 4'd0, inner_tSpeed } ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (r$OUT_RST == `BSV_RESET_VALUE)
      begin
        inner_cnt <= `BSV_ASSIGNMENT_DELAY 32'd100000000;
	inner_cur_temp <= `BSV_ASSIGNMENT_DELAY 8'd0;
	inner_fan_fan_rOutEn <= `BSV_ASSIGNMENT_DELAY 1'd1;
	inner_fan_fan_rSCL <= `BSV_ASSIGNMENT_DELAY 1'd1;
	inner_fan_fan_rSDA <= `BSV_ASSIGNMENT_DELAY 1'd1;
	inner_fan_fan_rState <= `BSV_ASSIGNMENT_DELAY 1'd0;
	inner_last_temp <= `BSV_ASSIGNMENT_DELAY 8'd0;
	inner_led <= `BSV_ASSIGNMENT_DELAY 4'hF;
	inner_main_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	inner_main_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	inner_main_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
	inner_main_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
	inner_main_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
	inner_tSpeed <= `BSV_ASSIGNMENT_DELAY 8'd35;
	inner_temp_temp_rOutEn <= `BSV_ASSIGNMENT_DELAY 1'd1;
	inner_temp_temp_rSCL <= `BSV_ASSIGNMENT_DELAY 1'd1;
	inner_temp_temp_rSDA <= `BSV_ASSIGNMENT_DELAY 1'd1;
	inner_temp_temp_rState <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (inner_cnt$EN) inner_cnt <= `BSV_ASSIGNMENT_DELAY inner_cnt$D_IN;
	if (inner_cur_temp$EN)
	  inner_cur_temp <= `BSV_ASSIGNMENT_DELAY inner_cur_temp$D_IN;
	if (inner_fan_fan_rOutEn$EN)
	  inner_fan_fan_rOutEn <= `BSV_ASSIGNMENT_DELAY
	      inner_fan_fan_rOutEn$D_IN;
	if (inner_fan_fan_rSCL$EN)
	  inner_fan_fan_rSCL <= `BSV_ASSIGNMENT_DELAY inner_fan_fan_rSCL$D_IN;
	if (inner_fan_fan_rSDA$EN)
	  inner_fan_fan_rSDA <= `BSV_ASSIGNMENT_DELAY inner_fan_fan_rSDA$D_IN;
	if (inner_fan_fan_rState$EN)
	  inner_fan_fan_rState <= `BSV_ASSIGNMENT_DELAY
	      inner_fan_fan_rState$D_IN;
	if (inner_last_temp$EN)
	  inner_last_temp <= `BSV_ASSIGNMENT_DELAY inner_last_temp$D_IN;
	if (inner_led$EN) inner_led <= `BSV_ASSIGNMENT_DELAY inner_led$D_IN;
	if (inner_main_start_reg$EN)
	  inner_main_start_reg <= `BSV_ASSIGNMENT_DELAY
	      inner_main_start_reg$D_IN;
	if (inner_main_start_reg_1$EN)
	  inner_main_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
	      inner_main_start_reg_1$D_IN;
	if (inner_main_state_can_overlap$EN)
	  inner_main_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
	      inner_main_state_can_overlap$D_IN;
	if (inner_main_state_fired$EN)
	  inner_main_state_fired <= `BSV_ASSIGNMENT_DELAY
	      inner_main_state_fired$D_IN;
	if (inner_main_state_mkFSMstate$EN)
	  inner_main_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
	      inner_main_state_mkFSMstate$D_IN;
	if (inner_tSpeed$EN)
	  inner_tSpeed <= `BSV_ASSIGNMENT_DELAY inner_tSpeed$D_IN;
	if (inner_temp_temp_rOutEn$EN)
	  inner_temp_temp_rOutEn <= `BSV_ASSIGNMENT_DELAY
	      inner_temp_temp_rOutEn$D_IN;
	if (inner_temp_temp_rSCL$EN)
	  inner_temp_temp_rSCL <= `BSV_ASSIGNMENT_DELAY
	      inner_temp_temp_rSCL$D_IN;
	if (inner_temp_temp_rSDA$EN)
	  inner_temp_temp_rSDA <= `BSV_ASSIGNMENT_DELAY
	      inner_temp_temp_rSDA$D_IN;
	if (inner_temp_temp_rState$EN)
	  inner_temp_temp_rState <= `BSV_ASSIGNMENT_DELAY
	      inner_temp_temp_rState$D_IN;
      end
    if (inner_fan_fan_rAddress$EN)
      inner_fan_fan_rAddress <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_rAddress$D_IN;
    if (inner_fan_fan_rSlaveAddr$EN)
      inner_fan_fan_rSlaveAddr <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_rSlaveAddr$D_IN;
    if (inner_fan_fan_rWrite$EN)
      inner_fan_fan_rWrite <= `BSV_ASSIGNMENT_DELAY inner_fan_fan_rWrite$D_IN;
    if (inner_fan_fan_rWriteData$EN)
      inner_fan_fan_rWriteData <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_rWriteData$D_IN;
    if (inner_fan_fan_vrReadData_0$EN)
      inner_fan_fan_vrReadData_0 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_0$D_IN;
    if (inner_fan_fan_vrReadData_1$EN)
      inner_fan_fan_vrReadData_1 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_1$D_IN;
    if (inner_fan_fan_vrReadData_2$EN)
      inner_fan_fan_vrReadData_2 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_2$D_IN;
    if (inner_fan_fan_vrReadData_3$EN)
      inner_fan_fan_vrReadData_3 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_3$D_IN;
    if (inner_fan_fan_vrReadData_4$EN)
      inner_fan_fan_vrReadData_4 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_4$D_IN;
    if (inner_fan_fan_vrReadData_5$EN)
      inner_fan_fan_vrReadData_5 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_5$D_IN;
    if (inner_fan_fan_vrReadData_6$EN)
      inner_fan_fan_vrReadData_6 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_6$D_IN;
    if (inner_fan_fan_vrReadData_7$EN)
      inner_fan_fan_vrReadData_7 <= `BSV_ASSIGNMENT_DELAY
	  inner_fan_fan_vrReadData_7$D_IN;
    if (inner_temp_temp_rAddress$EN)
      inner_temp_temp_rAddress <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_rAddress$D_IN;
    if (inner_temp_temp_rSlaveAddr$EN)
      inner_temp_temp_rSlaveAddr <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_rSlaveAddr$D_IN;
    if (inner_temp_temp_rWrite$EN)
      inner_temp_temp_rWrite <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_rWrite$D_IN;
    if (inner_temp_temp_rWriteData$EN)
      inner_temp_temp_rWriteData <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_rWriteData$D_IN;
    if (inner_temp_temp_vrReadData_0$EN)
      inner_temp_temp_vrReadData_0 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_0$D_IN;
    if (inner_temp_temp_vrReadData_1$EN)
      inner_temp_temp_vrReadData_1 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_1$D_IN;
    if (inner_temp_temp_vrReadData_2$EN)
      inner_temp_temp_vrReadData_2 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_2$D_IN;
    if (inner_temp_temp_vrReadData_3$EN)
      inner_temp_temp_vrReadData_3 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_3$D_IN;
    if (inner_temp_temp_vrReadData_4$EN)
      inner_temp_temp_vrReadData_4 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_4$D_IN;
    if (inner_temp_temp_vrReadData_5$EN)
      inner_temp_temp_vrReadData_5 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_5$D_IN;
    if (inner_temp_temp_vrReadData_6$EN)
      inner_temp_temp_vrReadData_6 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_6$D_IN;
    if (inner_temp_temp_vrReadData_7$EN)
      inner_temp_temp_vrReadData_7 <= `BSV_ASSIGNMENT_DELAY
	  inner_temp_temp_vrReadData_7$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    inner_cnt = 32'hAAAAAAAA;
    inner_cur_temp = 8'hAA;
    inner_fan_fan_rAddress = 8'hAA;
    inner_fan_fan_rOutEn = 1'h0;
    inner_fan_fan_rSCL = 1'h0;
    inner_fan_fan_rSDA = 1'h0;
    inner_fan_fan_rSlaveAddr = 7'h2A;
    inner_fan_fan_rState = 1'h0;
    inner_fan_fan_rWrite = 1'h0;
    inner_fan_fan_rWriteData = 8'hAA;
    inner_fan_fan_vrReadData_0 = 1'h0;
    inner_fan_fan_vrReadData_1 = 1'h0;
    inner_fan_fan_vrReadData_2 = 1'h0;
    inner_fan_fan_vrReadData_3 = 1'h0;
    inner_fan_fan_vrReadData_4 = 1'h0;
    inner_fan_fan_vrReadData_5 = 1'h0;
    inner_fan_fan_vrReadData_6 = 1'h0;
    inner_fan_fan_vrReadData_7 = 1'h0;
    inner_last_temp = 8'hAA;
    inner_led = 4'hA;
    inner_main_start_reg = 1'h0;
    inner_main_start_reg_1 = 1'h0;
    inner_main_state_can_overlap = 1'h0;
    inner_main_state_fired = 1'h0;
    inner_main_state_mkFSMstate = 5'h0A;
    inner_tSpeed = 8'hAA;
    inner_temp_temp_rAddress = 8'hAA;
    inner_temp_temp_rOutEn = 1'h0;
    inner_temp_temp_rSCL = 1'h0;
    inner_temp_temp_rSDA = 1'h0;
    inner_temp_temp_rSlaveAddr = 7'h2A;
    inner_temp_temp_rState = 1'h0;
    inner_temp_temp_rWrite = 1'h0;
    inner_temp_temp_rWriteData = 8'hAA;
    inner_temp_temp_vrReadData_0 = 1'h0;
    inner_temp_temp_vrReadData_1 = 1'h0;
    inner_temp_temp_vrReadData_2 = 1'h0;
    inner_temp_temp_vrReadData_3 = 1'h0;
    inner_temp_temp_vrReadData_4 = 1'h0;
    inner_temp_temp_vrReadData_5 = 1'h0;
    inner_temp_temp_vrReadData_6 = 1'h0;
    inner_temp_temp_vrReadData_7 = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (inner_main_state_mkFSMstate == 5'd20 &&
	  WILL_FIRE_RL_inner_main_action_l114c18)
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l113c17]\n  and [RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l89c13 &&
	  (WILL_FIRE_RL_inner_main_action_l90c14 ||
	   inner_main_state_mkFSMstate == 5'd2 ||
	   WILL_FIRE_RL_inner_main_action_l39c27 ||
	   WILL_FIRE_RL_inner_main_action_l40c27 ||
	   WILL_FIRE_RL_inner_main_action_l41c27 ||
	   WILL_FIRE_RL_inner_main_action_l42c27 ||
	   WILL_FIRE_RL_inner_main_action_l43c27 ||
	   WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l89c13] and\n  [RL_inner_main_action_l90c14, RL_inner_main_action_l91c13,\n  RL_inner_main_action_l39c27, RL_inner_main_action_l40c27,\n  RL_inner_main_action_l41c27, RL_inner_main_action_l42c27,\n  RL_inner_main_action_l43c27, RL_inner_main_action_l19c27,\n  RL_inner_main_action_l94c12, RL_inner_main_action_l95c13,\n  RL_inner_main_action_l97c17, RL_inner_main_action_l98c23,\n  RL_inner_main_action_l24c26, RL_inner_main_action_l25c13,\n  RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l90c14 &&
	  (inner_main_state_mkFSMstate == 5'd2 ||
	   WILL_FIRE_RL_inner_main_action_l39c27 ||
	   WILL_FIRE_RL_inner_main_action_l40c27 ||
	   WILL_FIRE_RL_inner_main_action_l41c27 ||
	   WILL_FIRE_RL_inner_main_action_l42c27 ||
	   WILL_FIRE_RL_inner_main_action_l43c27 ||
	   WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l90c14] and\n  [RL_inner_main_action_l91c13, RL_inner_main_action_l39c27,\n  RL_inner_main_action_l40c27, RL_inner_main_action_l41c27,\n  RL_inner_main_action_l42c27, RL_inner_main_action_l43c27,\n  RL_inner_main_action_l19c27, RL_inner_main_action_l94c12,\n  RL_inner_main_action_l95c13, RL_inner_main_action_l97c17,\n  RL_inner_main_action_l98c23, RL_inner_main_action_l24c26,\n  RL_inner_main_action_l25c13, RL_inner_main_action_l102c28,\n  RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (inner_main_state_mkFSMstate == 5'd2 &&
	  (WILL_FIRE_RL_inner_main_action_l39c27 ||
	   WILL_FIRE_RL_inner_main_action_l40c27 ||
	   WILL_FIRE_RL_inner_main_action_l41c27 ||
	   WILL_FIRE_RL_inner_main_action_l42c27 ||
	   WILL_FIRE_RL_inner_main_action_l43c27 ||
	   WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l91c13] and\n  [RL_inner_main_action_l39c27, RL_inner_main_action_l40c27,\n  RL_inner_main_action_l41c27, RL_inner_main_action_l42c27,\n  RL_inner_main_action_l43c27, RL_inner_main_action_l19c27,\n  RL_inner_main_action_l94c12, RL_inner_main_action_l95c13,\n  RL_inner_main_action_l97c17, RL_inner_main_action_l98c23,\n  RL_inner_main_action_l24c26, RL_inner_main_action_l25c13,\n  RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l39c27 &&
	  (WILL_FIRE_RL_inner_main_action_l40c27 ||
	   WILL_FIRE_RL_inner_main_action_l41c27 ||
	   WILL_FIRE_RL_inner_main_action_l42c27 ||
	   WILL_FIRE_RL_inner_main_action_l43c27 ||
	   WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l39c27] and\n  [RL_inner_main_action_l40c27, RL_inner_main_action_l41c27,\n  RL_inner_main_action_l42c27, RL_inner_main_action_l43c27,\n  RL_inner_main_action_l19c27, RL_inner_main_action_l94c12,\n  RL_inner_main_action_l95c13, RL_inner_main_action_l97c17,\n  RL_inner_main_action_l98c23, RL_inner_main_action_l24c26,\n  RL_inner_main_action_l25c13, RL_inner_main_action_l102c28,\n  RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l40c27 &&
	  (WILL_FIRE_RL_inner_main_action_l41c27 ||
	   WILL_FIRE_RL_inner_main_action_l42c27 ||
	   WILL_FIRE_RL_inner_main_action_l43c27 ||
	   WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l40c27] and\n  [RL_inner_main_action_l41c27, RL_inner_main_action_l42c27,\n  RL_inner_main_action_l43c27, RL_inner_main_action_l19c27,\n  RL_inner_main_action_l94c12, RL_inner_main_action_l95c13,\n  RL_inner_main_action_l97c17, RL_inner_main_action_l98c23,\n  RL_inner_main_action_l24c26, RL_inner_main_action_l25c13,\n  RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l41c27 &&
	  (WILL_FIRE_RL_inner_main_action_l42c27 ||
	   WILL_FIRE_RL_inner_main_action_l43c27 ||
	   WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l41c27] and\n  [RL_inner_main_action_l42c27, RL_inner_main_action_l43c27,\n  RL_inner_main_action_l19c27, RL_inner_main_action_l94c12,\n  RL_inner_main_action_l95c13, RL_inner_main_action_l97c17,\n  RL_inner_main_action_l98c23, RL_inner_main_action_l24c26,\n  RL_inner_main_action_l25c13, RL_inner_main_action_l102c28,\n  RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l42c27 &&
	  (WILL_FIRE_RL_inner_main_action_l43c27 ||
	   WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l42c27] and\n  [RL_inner_main_action_l43c27, RL_inner_main_action_l19c27,\n  RL_inner_main_action_l94c12, RL_inner_main_action_l95c13,\n  RL_inner_main_action_l97c17, RL_inner_main_action_l98c23,\n  RL_inner_main_action_l24c26, RL_inner_main_action_l25c13,\n  RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l43c27 &&
	  (WILL_FIRE_RL_inner_main_action_l19c27 ||
	   WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l43c27] and\n  [RL_inner_main_action_l19c27, RL_inner_main_action_l94c12,\n  RL_inner_main_action_l95c13, RL_inner_main_action_l97c17,\n  RL_inner_main_action_l98c23, RL_inner_main_action_l24c26,\n  RL_inner_main_action_l25c13, RL_inner_main_action_l102c28,\n  RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l19c27 &&
	  (WILL_FIRE_RL_inner_main_action_l94c12 ||
	   inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l19c27] and\n  [RL_inner_main_action_l94c12, RL_inner_main_action_l95c13,\n  RL_inner_main_action_l97c17, RL_inner_main_action_l98c23,\n  RL_inner_main_action_l24c26, RL_inner_main_action_l25c13,\n  RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l94c12 &&
	  (inner_main_state_mkFSMstate == 5'd10 ||
	   WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l94c12] and\n  [RL_inner_main_action_l95c13, RL_inner_main_action_l97c17,\n  RL_inner_main_action_l98c23, RL_inner_main_action_l24c26,\n  RL_inner_main_action_l25c13, RL_inner_main_action_l102c28,\n  RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (inner_main_state_mkFSMstate == 5'd10 &&
	  (WILL_FIRE_RL_inner_main_action_l97c17 ||
	   inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l95c13] and\n  [RL_inner_main_action_l97c17, RL_inner_main_action_l98c23,\n  RL_inner_main_action_l24c26, RL_inner_main_action_l25c13,\n  RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l97c17 &&
	  (inner_main_state_mkFSMstate == 5'd12 ||
	   WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l97c17] and\n  [RL_inner_main_action_l98c23, RL_inner_main_action_l24c26,\n  RL_inner_main_action_l25c13, RL_inner_main_action_l102c28,\n  RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (inner_main_state_mkFSMstate == 5'd12 &&
	  (WILL_FIRE_RL_inner_main_action_l24c26 ||
	   WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l98c23] and\n  [RL_inner_main_action_l24c26, RL_inner_main_action_l25c13,\n  RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l24c26 &&
	  (WILL_FIRE_RL_inner_main_action_l25c13 ||
	   WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l24c26] and\n  [RL_inner_main_action_l25c13, RL_inner_main_action_l102c28,\n  RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l25c13 &&
	  (WILL_FIRE_RL_inner_main_action_l102c28 ||
	   WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l25c13] and\n  [RL_inner_main_action_l102c28, RL_inner_main_action_l103c24,\n  RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l102c28 &&
	  (WILL_FIRE_RL_inner_main_action_l103c24 ||
	   WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l102c28]\n  and [RL_inner_main_action_l103c24, RL_inner_main_action_l108c28,\n  RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l103c24 &&
	  (WILL_FIRE_RL_inner_main_action_l108c28 ||
	   WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l103c24]\n  and [RL_inner_main_action_l108c28, RL_inner_main_action_l109c24,\n  RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l108c28 &&
	  (WILL_FIRE_RL_inner_main_action_l109c24 ||
	   inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l108c28]\n  and [RL_inner_main_action_l109c24, RL_inner_main_action_l112c15,\n  RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in the\n  same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_inner_main_action_l109c24 &&
	  (inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 ||
	   inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l109c24]\n  and [RL_inner_main_action_l112c15, RL_inner_main_action_l113c17,\n  RL_inner_main_action_l114c18] ) fired in the same clock cycle.\n");
    if (r$OUT_RST != `BSV_RESET_VALUE)
      if (inner_cur_temp_33_ULT_40_42_AND_inner_cur_temp_ETC___d393 &&
	  (inner_main_state_mkFSMstate == 5'd20 ||
	   WILL_FIRE_RL_inner_main_action_l114c18))
	$display("Error: \"DE10FanControl.bsv\", line 88, column 5: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_inner_main_action_l112c15]\n  and [RL_inner_main_action_l113c17, RL_inner_main_action_l114c18] ) fired in\n  the same clock cycle.\n");
  end
  // synopsys translate_on
endmodule  // mkDE10FanControl