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JimLewisJimLewis
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Add InterruptGenerator
1 parent 0906346 commit 0eb9cc5

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lines changed

‎Common.pro

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# limitations under the License.
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#
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library OSVVM_Common
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ChangeWorkingDirectory ./src
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analyze ModelParametersPkg.vhd
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analyze FifoFillPkg_slv.vhd
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analyze StreamTransactionPkg.vhd
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analyze StreamTransactionArrayPkg.vhd
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analyze AddressBusTransactionPkg.vhd
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analyze AddressBusTransactionArrayPkg.vhd
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analyze AddressBusResponderTransactionPkg.vhd
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analyze AddressBusResponderTransactionArrayPkg.vhd
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analyze AddressBusVersionCompatibilityPkg.vhd
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analyze InterruptGlobalSignalPkg.vhd
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analyze InterruptHandler.vhd
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analyze InterruptHandlerComponentPkg.vhd
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analyze OsvvmCommonContext.vhd
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include src/Common.pro

‎src/.gitignore

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This file was deleted.

‎src/Common.pro

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# File Name: common.pro
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# Revision: OSVVM MODELS STANDARD VERSION
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#
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# Maintainer: Jim Lewis email: [email protected]
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# Contributor(s):
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# Jim Lewis [email protected]
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#
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#
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# Description:
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# Top level script to compile the OSVVM common packages
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#
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# Developed for:
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# SynthWorks Design Inc.
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# VHDL Training Classes
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# 11898 SW 128th Ave. Tigard, Or 97223
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# http://www.SynthWorks.com
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#
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# Revision History:
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# Date Version Description
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# 11/2022 2022.11 Added AddressBusTransactionArrayPkg and AddressBusResponderTransactionArrayPkg
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# 1/2020 2020.01 Updated Licenses to Apache
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# 1/2019 2019.01 Compile Script for OSVVM Common library
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#
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#
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# This file is part of OSVVM.
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#
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# Copyright (c) 2019 - 2020 by SynthWorks Design Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# https://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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library OSVVM_Common
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analyze ModelParametersPkg.vhd
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analyze FifoFillPkg_slv.vhd
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# MIT
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analyze StreamTransactionPkg.vhd
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analyze StreamTransactionArrayPkg.vhd
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analyze AddressBusTransactionPkg.vhd
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analyze AddressBusTransactionArrayPkg.vhd
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analyze AddressBusResponderTransactionPkg.vhd
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analyze AddressBusResponderTransactionArrayPkg.vhd
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analyze AddressBusVersionCompatibilityPkg.vhd
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# Interrupt
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analyze InterruptGlobalSignalPkg.vhd
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analyze InterruptHandler.vhd
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analyze InterruptHandlerComponentPkg.vhd
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analyze InterruptGeneratorBit.vhd
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analyze InterruptGeneratorBitVti.vhd
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# analyze InterruptGenerator.vhd
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# analyze InterruptGeneratorVti.vhd
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analyze InterruptGeneratorComponentPkg.vhd
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analyze OsvvmCommonContext.vhd

‎src/InterruptGeneratorBit.vhd

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--
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-- File Name: InterruptGeneratorBit.vhd
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-- Design Unit Name: InterruptGeneratorBit
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-- Revision: OSVVM MODELS STANDARD VERSION
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--
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-- Maintainer: Jim Lewis email: [email protected]
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-- Contributor(s):
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-- Jim Lewis [email protected]
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--
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--
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-- Description:
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-- InterruptGeneratorBit
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--
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--
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-- Developed by:
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-- SynthWorks Design Inc.
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-- VHDL Training Classes
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-- http://www.SynthWorks.com
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--
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-- Revision History:
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-- Date Version Description
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-- 01/2023 2023.01 Initial revision
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--
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--
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-- This file is part of OSVVM.
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--
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-- Copyright (c) 2023 by SynthWorks Design Inc.
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- https://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.numeric_std_unsigned.all ;
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use ieee.math_real.all ;
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library osvvm ;
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context osvvm.OsvvmContext ;
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use osvvm.ScoreboardPkg_slv.all ;
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use work.StreamTransactionPkg.all;
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use work.InterruptGlobalSignalPkg.all ;
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entity InterruptGeneratorBit is
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generic (
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MODEL_ID_NAME : string := "" ;
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POLARITY : std_logic := '1'
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) ;
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port (
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-- Interrupt Input
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IntReq : out std_logic ;
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-- Transaction port
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TransRec : inout InterruptGeneratorBitRecType
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) ;
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end entity InterruptGeneratorBit ;
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architecture Behavioral of InterruptGeneratorBit is
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constant MODEL_INSTANCE_NAME : string :=
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-- use MODEL_ID_NAME Generic if set, otherwise use instance label (preferred if set as entityname_1)
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IfElse(MODEL_ID_NAME /= "", MODEL_ID_NAME, to_lower(PathTail(InterruptGeneratorBit'PATH_NAME))) ;
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signal ModelID : AlertLogIDType ;
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begin
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------------------------------------------------------------
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-- Initialize alerts
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------------------------------------------------------------
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Initialize : process
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variable ID : AlertLogIDType ;
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begin
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-- Alerts
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ID := NewID(MODEL_INSTANCE_NAME) ;
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ModelID <= ID ;
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wait ;
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end process Initialize ;
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------------------------------------------------------------
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-- Transaction Handler
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-- Decodes Transactions and Handlers DUT Interface
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------------------------------------------------------------
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TransactionHandler : process
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alias Operation : StreamOperationType is TransRec.Operation ;
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begin
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-- Initialize Outputs
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IntReq <= not POLARITY ;
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TransRec.DataFromModel <= (others => '0') ;
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wait for 0 ns ;
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TransactionDispatcherLoop : loop
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WaitForTransaction(
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Rdy => TransRec.Rdy,
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Ack => TransRec.Ack
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) ;
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case Operation is
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when SEND | SEND_ASYNC =>
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IntReq <= TransRec.DataToModel(0) ;
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when GET | TRY_GET =>
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TransRec.DataFromModel(0) <= IntReq ;
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when WAIT_FOR_TRANSACTION =>
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wait for 0 ns ;
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when WAIT_FOR_CLOCK =>
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Alert(ModelID, "No clocks in this VC. Not waiting.") ;
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when GET_ALERTLOG_ID =>
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TransRec.IntFromModel <= ModelID ;
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when GET_TRANSACTION_COUNT =>
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TransRec.IntFromModel <= TransRec.Rdy ;
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when MULTIPLE_DRIVER_DETECT =>
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Alert(ModelID, "Multiple Drivers on Transaction Record." &
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" Transaction # " & to_string(TransRec.Rdy), FAILURE) ;
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when others =>
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Alert(ModelID, "Unimplemented Transaction: " & to_string(Operation), FAILURE) ;
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end case ;
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end loop TransactionDispatcherLoop ;
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end process TransactionHandler ;
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end architecture Behavioral ;

‎src/InterruptGeneratorBitVti.vhd

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--
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-- File Name: InterruptGeneratorBit.vhd
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-- Design Unit Name: InterruptGeneratorBit
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-- Revision: OSVVM MODELS STANDARD VERSION
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--
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-- Maintainer: Jim Lewis email: [email protected]
7+
-- Contributor(s):
8+
-- Jim Lewis [email protected]
9+
--
10+
--
11+
-- Description:
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-- InterruptGeneratorBit
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--
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--
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-- Developed by:
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-- SynthWorks Design Inc.
17+
-- VHDL Training Classes
18+
-- http://www.SynthWorks.com
19+
--
20+
-- Revision History:
21+
-- Date Version Description
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-- 01/2023 2023.01 Initial revision
23+
--
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--
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-- This file is part of OSVVM.
26+
--
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-- Copyright (c) 2023 by SynthWorks Design Inc.
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
31+
-- You may obtain a copy of the License at
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--
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-- https://www.apache.org/licenses/LICENSE-2.0
34+
--
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-- Unless required by applicable law or agreed to in writing, software
36+
-- distributed under the License is distributed on an "AS IS" BASIS,
37+
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
38+
-- See the License for the specific language governing permissions and
39+
-- limitations under the License.
40+
--
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.numeric_std_unsigned.all ;
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use ieee.math_real.all ;
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library osvvm ;
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context osvvm.OsvvmContext ;
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use osvvm.ScoreboardPkg_slv.all ;
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use work.StreamTransactionPkg.all;
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use work.InterruptGlobalSignalPkg.all ;
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entity InterruptGeneratorBit is
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generic (
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MODEL_ID_NAME : string := "" ;
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POLARITY : std_logic := '1'
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) ;
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port (
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-- Interrupt Input
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IntReq : out std_logic
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) ;
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-- Connects to sequencer (TestCtrl)
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signal TransRec : StreamRecType(DataToModel(0 downto 0), DataFromModel(0 downto 0), ParamToModel(1 to 0), ParamFromModel(1 to 0)) ;
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end entity InterruptGeneratorBit ;
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architecture Behavioral of InterruptGeneratorBit is
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constant MODEL_INSTANCE_NAME : string :=
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-- use MODEL_ID_NAME Generic if set, otherwise use instance label (preferred if set as entityname_1)
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IfElse(MODEL_ID_NAME /= "", MODEL_ID_NAME, to_lower(PathTail(InterruptGeneratorBit'PATH_NAME))) ;
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signal ModelID : AlertLogIDType ;
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begin
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------------------------------------------------------------
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-- Initialize alerts
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------------------------------------------------------------
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Initialize : process
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variable ID : AlertLogIDType ;
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begin
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-- Alerts
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ID := NewID(MODEL_INSTANCE_NAME) ;
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ModelID <= ID ;
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wait ;
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end process Initialize ;
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------------------------------------------------------------
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-- Transaction Handler
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-- Decodes Transactions and Handlers DUT Interface
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------------------------------------------------------------
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TransactionHandler : process
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alias Operation : StreamOperationType is TransRec.Operation ;
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variable Data : std_logic_vector(gIntReq'range) ;
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begin
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-- Initialize Outputs
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IntReq <= not POLARITY ;
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TransRec.DataFromModel <= (others => '0') ;
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wait for 0 ns ;
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TransactionDispatcherLoop : loop
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WaitForTransaction(
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Rdy => TransRec.Rdy,
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Ack => TransRec.Ack
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) ;
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case Operation is
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when SEND | SEND_ASYNC =>
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IntReq <= TransRec.DataToModel(0) ;
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when GET | TRY_GET =>
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TransRec.DataFromModel(0) <= IntReq ;
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when WAIT_FOR_TRANSACTION =>
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wait for 0 ns ;
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when WAIT_FOR_CLOCK =>
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Alert(ModelID, "No clocks in this VC. Not waiting.") ;
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when GET_ALERTLOG_ID =>
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TransRec.IntFromModel <= ModelID ;
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when GET_TRANSACTION_COUNT =>
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TransRec.IntFromModel <= TransRec.Rdy ;
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when MULTIPLE_DRIVER_DETECT =>
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Alert(ModelID, "Multiple Drivers on Transaction Record." &
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" Transaction # " & to_string(TransRec.Rdy), FAILURE) ;
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when others =>
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Alert(ModelID, "Unimplemented Transaction: " & to_string(Operation), FAILURE) ;
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end case ;
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end loop TransactionDispatcherLoop ;
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end process TransactionHandler ;
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end architecture Behavioral ;

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