You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
With FPGA code rev 0.11.x, the timestamp increment from metadata block to metadata block is 508 in single channel mode and 254 in dual channel mode. With FPGA rev 0.12.0 ff, the timestamp increment is 508 in single channel mode and 255 in dual channel mode.
With FPGA 0.12.0 ff, the transfer stalls after about 1794 x 1024-sample buffers (or 897 x 2048 samples, etc) and we get:
[ERROR @ host/libraries/libbladeRF/src/backend/usb/libusb.c:1089] Transfer timed out for buffer 0x55831cdd80
Stream error: Operation timed out
Single channel mode seems to be OK.
Modified version of the async test that demonstrates the problem: test_async.zip
Run with: "test_async rx 1024 8 10000000"
The text was updated successfully, but these errors were encountered:
shclift
changed the title
Dual-channel receive with metadata broken for FPGA code 0.12.0 through 0.15.0 (xA9)?
Dual-channel async receive with metadata broken for FPGA code 0.12.0 through 0.15.0 (xA9)?
Sep 26, 2023
Configuration
Problem
Modified version of the async test that demonstrates the problem: test_async.zip
Run with: "test_async rx 1024 8 10000000"
The text was updated successfully, but these errors were encountered: