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modustollensjynik
modustollens
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jynik
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hdl: Added ATSC TX FPGA implementation
This revision introduces an FPGA-based ATSC transmitter to offload the pilot insertion, filtering, and shift to baseband. This design expects that 4-bit ATSC symbols are written to the device in little-endian 32-bit words, as shown below. |<------- 32 Bit Word ------->| Bit |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| Symbol [ X| 7 ][X| 6 ][X| 5 ][X| 4 ][X| 3 ][X| 2 ][X| 1 ][X| 0 ] The FPGA transmits Symbol 0 first, and Symbol 7 last. The three least-significant bits in each symbol's nibble contain values 0 to 7, mapping to values of -7 to 7, with the most-significant bit left unused. This FPGA image may be built by specifying the "atsc_tx" image to the build_bladerf.sh script. The resulting output files will be atsc_txx40.rbf and atsc_txx115.rbf for the x40 and the x115, respectively. Transmitting a pre-made stream on channel 14-1 can be achieved with the following commands in the bladeRF-cli: set frequency 473000000 set samplerate 32286713 2867 10000 set txvga1 -4 set txvga2 20 tx config file=<path to file> repeat=0 delay=0 tx start
1 parent dfa9f51 commit 35e5a6e

14 files changed

+2535
-47
lines changed

‎hdl/fpga/ip/nuand/nuand.do

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proc compile_nuand { root } {
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vlib nuand
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vcom -work nuand -2008 [file join $root ../altera/tx_fifo/tx_fifo.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/constellation_mapper.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/sync_fifo.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/uart.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/handshake.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/tb/handshake_tb.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/signal_processing_p.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/bit_stripper.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/fir_filter.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/atsc_tx.vhd]
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vcom -work nuand -2008 [file join $root ./simulation/util.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/tb/fir_filter_tb.vhd]
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vcom -work nuand -2008 [file join $root ./synthesis/tb/atsc_tx_tb.vhd]
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vcom -work nuand -2008 [file join $root ./simulation/fx3_model.vhd]
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vcom -work nuand -2008 [file join $root ./simulation/lms6002d_model.vhd]
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}

‎hdl/fpga/ip/nuand/simulation/util.vhd

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Original file line numberDiff line numberDiff line change
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library ieee ;
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use ieee.std_logic_1164.all ;
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library std;
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use std.textio.all;
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-- Utility package
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package util is
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end package body ;
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all;
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library std;
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use std.textio.all;
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entity data_saver is
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generic(
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FILENAME : string := "file.dat";
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DATA_WIDTH : natural := 16
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);
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port(
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reset : in std_logic;
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clock : in std_logic;
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data : std_logic_vector(DATA_WIDTH-1 downto 0);
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data_valid : std_logic
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);
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end entity;
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architecture arch of data_saver is
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begin
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handler : process
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FILE fp : text;
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variable line_data : line;
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begin
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--
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wait until falling_edge(reset);
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file_open(fp, FILENAME, WRITE_MODE);
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while (reset = '0') loop
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wait until rising_edge(data_valid);
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write(line_data, data);
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writeline(fp,line_data);
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end loop;
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file_close(fp);
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end process;
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end architecture;
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all;
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library std;
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use std.textio.all;
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entity signed_saver is
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generic(
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FILENAME : string := "file.dat";
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DATA_WIDTH : natural := 16
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);
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port(
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reset : in std_logic;
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clock : in std_logic;
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data : signed(DATA_WIDTH-1 downto 0);
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data_valid : std_logic
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);
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end entity;
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architecture arch of signed_saver is
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begin
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handler : process
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FILE fp : text;
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variable line_data : line;
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begin
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--
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wait until falling_edge(reset);
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file_open(fp, FILENAME, WRITE_MODE);
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while (reset = '0') loop
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wait until rising_edge(clock);
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if data_valid = '1' then
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write(line_data, (to_integer(data)));
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writeline(fp,line_data);
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end if;
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end loop;
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file_close(fp);
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end process;
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end architecture;
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all;
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library std;
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use std.textio.all;
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entity data_reader is
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generic(
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FILENAME : string := "file.dat";
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DATA_WIDTH : natural := 16
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);
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port(
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reset : in std_logic;
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clock : in std_logic;
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data_request : in std_logic;
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data : out std_logic_vector(DATA_WIDTH-1 downto 0);
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data_valid : out std_logic
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);
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end entity;
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architecture arch of data_reader is
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type character_array_t is array (natural range <>) of character;
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begin
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handler : process
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variable line_data : line;
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variable tmp : integer;
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variable c : character;--_array_t(0 to 3);
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type bin_t is file of character ;
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file fp : bin_t ;
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variable fs : file_open_status ;
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begin
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--
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data <= (others => '0');
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data_valid <= '0';
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wait until falling_edge(reset);
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file_open(fs, fp, FILENAME, READ_MODE);
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if( fs /= OPEN_OK ) then
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report "File open issues" severity failure ;
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end if ;
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--readline(fp,line_data);
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while (reset = '0') loop
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wait until rising_edge(clock);
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data_valid <= '0';
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if data_request = '1' then
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read(fp, c);
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tmp := integer(natural(character'pos(c)));
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data(7 downto 0) <= std_logic_vector(to_unsigned(tmp,8));
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read(fp, c);
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tmp := integer(natural(character'pos(c)));
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data(15 downto 8) <= std_logic_vector(to_unsigned(tmp,8));
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read(fp, c);
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tmp := integer(natural(character'pos(c)));
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data(23 downto 16) <= std_logic_vector(to_unsigned(tmp,8));
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read(fp, c);
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tmp := integer(natural(character'pos(c)));
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data(31 downto 24) <= std_logic_vector(to_unsigned(tmp,8));
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data_valid <= '1';
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wait until rising_edge(clock);
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data_valid <= '0';
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end if;
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end loop;
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file_close(fp);
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end process;
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end architecture;

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