diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index cf2adb1cf170..5a43ccf646ce 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1378,8 +1378,8 @@ static-analysis-files: &static_analysis_files | tests/unittest/_torch/sampler/test_beam_search_util.py | )$ -# Global exclude pattern for vendored third-party code -exclude: '(^triton_kernels/|trtllmGenKernels/fmha/cubin/kernelMetaInfo\.h$|cubin\.cpp$|cubin\.h$)' +# Global exclude: vendored code + trtllm-gen FMHA artifacts (cubin pointers, export headers, cuda_ptx) +exclude: '(^triton_kernels/|trtllmGenKernels/fmha/cubin/kernelMetaInfo\.h$|cubin\.cpp$|cubin\.h$|trtllmGenKernels/fmha/trtllmGen_fmha_export/|trtllmGenKernels/fmha/cuda_ptx/)' default_install_hook_types: [pre-commit, commit-msg] repos: diff --git a/cpp/tensorrt_llm/kernels/fmhaDispatcher.cpp b/cpp/tensorrt_llm/kernels/fmhaDispatcher.cpp index 68e3e4d60040..d8c32a020be7 100644 --- a/cpp/tensorrt_llm/kernels/fmhaDispatcher.cpp +++ b/cpp/tensorrt_llm/kernels/fmhaDispatcher.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2024, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -111,11 +111,22 @@ bool FmhaDispatcher::isSupported() tllmRunnerParams.mKernelType = FmhaKernelType::Context; tllmRunnerParams.mTileScheduler = TileScheduler::Persistent; tllmRunnerParams.mMultiCtasKvMode = false; + tllmRunnerParams.mNumHeadsQ = mFixedParams.numQHeads; + tllmRunnerParams.mNumHeadsKv = mFixedParams.numKvHeads; + tllmRunnerParams.mHeadDimQkNope = mFixedParams.headSizeQkNope; + tllmRunnerParams.mBatchSize = 1; + tllmRunnerParams.mMaxSeqLenQ = 1; + tllmRunnerParams.mMaxSeqLenKv = 1; + tllmRunnerParams.mMaxSeqLenCacheKv = 1; + tllmRunnerParams.mSumOfSeqLensQ = 1; + tllmRunnerParams.mSumOfSeqLensKv = 1; + tllmRunnerParams.mMaxNumPagesPerSeqKv = 1; // Assume same headDim for Qk and V here. tllmRunnerParams.mHeadDimQk = mFixedParams.headSize; tllmRunnerParams.mHeadDimV = mFixedParams.headSizeV; - tllmRunnerParams.mNumTokensPerPage = mFixedParams.numTokensPerBlock; + tllmRunnerParams.mNumTokensPerPage = (qkvLayout == QkvLayout::PagedKv) ? mFixedParams.numTokensPerBlock : 0; tllmRunnerParams.mNumHeadsQPerKv = mFixedParams.numQHeads / mFixedParams.numKvHeads; + tllmRunnerParams.mMultiProcessorCount = tensorrt_llm::common::getMultiProcessorCount(); // Set the chunked attention size and sliding window size to INT_MAX to disable them when checking if // the kernel is supported. tllmRunnerParams.mChunkedAttentionSize = INT_MAX; @@ -221,10 +232,11 @@ void FmhaDispatcher::run(MHARunnerParams runnerParams) tllmRunnerParams.mSumOfSeqLensQ = runnerParams.totalQSeqLen; tllmRunnerParams.mSumOfSeqLensKv = runnerParams.totalKvSeqLen; tllmRunnerParams.mMaxNumPagesPerSeqKv = maxBlocksPerSeq; - tllmRunnerParams.mNumTokensPerPage = numTokensPerBlock; + tllmRunnerParams.mNumTokensPerPage = (qkvLayout == QkvLayout::PagedKv) ? numTokensPerBlock : 0; tllmRunnerParams.mScaleQ = mFixedParams.qScaling; // Set it to INT_MAX as the kv cache pageOffsets will ensure that there is no out-of-bounds access. tllmRunnerParams.mNumPagesInMemPool = INT_MAX; + tllmRunnerParams.mMultiProcessorCount = tensorrt_llm::common::getMultiProcessorCount(); tllmRunnerParams.mSfStartTokenIdx = 0; // For mla chunked prefill tllmRunnerParams.softmaxStatsPtr = reinterpret_cast(runnerParams.softmaxStatsPtr); diff --git a/cpp/tensorrt_llm/kernels/indexerTopK.cu b/cpp/tensorrt_llm/kernels/indexerTopK.cu index b9a38494946f..dbb0d659e27e 100644 --- a/cpp/tensorrt_llm/kernels/indexerTopK.cu +++ b/cpp/tensorrt_llm/kernels/indexerTopK.cu @@ -20,6 +20,7 @@ #include "tensorrt_llm/common/cudaTypeUtils.cuh" #include "tensorrt_llm/common/envUtils.h" #include "tensorrt_llm/kernels/noAuxTcKernels.h" +#include #include #include diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/CMakeLists.txt b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/CMakeLists.txt index 3f166f5cb6ba..341aa1d3e577 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/CMakeLists.txt +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/CMakeLists.txt @@ -15,6 +15,37 @@ # the License. # +set(cutlass_source_dir ${CMAKE_BINARY_DIR}/_deps/cutlass-src) +# Point to the targets include directory which contains both cuda.h and cccl/ +# Prefer CUDAToolkit from parent; otherwise derive from CMAKE_CUDA_COMPILER. +if(DEFINED CUDAToolkit_INCLUDE_DIRS AND CUDAToolkit_INCLUDE_DIRS) + list(GET CUDAToolkit_INCLUDE_DIRS 0 CUDA_TARGETS_INCLUDE_DIR) +else() + get_filename_component(CUDA_BIN_PATH ${CMAKE_CUDA_COMPILER} DIRECTORY) + get_filename_component(CUDA_TOOLKIT_ROOT ${CUDA_BIN_PATH} DIRECTORY) + set(cudaTargetsArch ${CMAKE_SYSTEM_PROCESSOR}) + if(cudaTargetsArch STREQUAL "aarch64" OR cudaTargetsArch STREQUAL "arm64") + set(cudaTargetsArch sbsa) + endif() + set(CUDA_TARGETS_INCLUDE_DIR + "${CUDA_TOOLKIT_ROOT}/targets/${cudaTargetsArch}-linux/include") +endif() +file(CREATE_LINK ${CUDA_TARGETS_INCLUDE_DIR} ${CMAKE_CURRENT_BINARY_DIR}/cuda + SYMBOLIC) +file(CREATE_LINK ${cutlass_source_dir} ${CMAKE_CURRENT_BINARY_DIR}/cutlass + SYMBOLIC) +# Create parent directory for symbolic link +file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/trtllm) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/trtllmGen_fmha_export/trtllm/dev + ${CMAKE_CURRENT_BINARY_DIR}/trtllm/dev SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/cuda_ptx + ${CMAKE_CURRENT_BINARY_DIR}/cuda_ptx SYMBOLIC) +configure_file(${CMAKE_CURRENT_SOURCE_DIR}/trtllmGen_fmha_export/KernelParams.h + ${CMAKE_CURRENT_BINARY_DIR}/KernelParams.h COPYONLY) +configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/trtllmGen_fmha_export/KernelParamsDecl.h + ${CMAKE_CURRENT_BINARY_DIR}/KernelParamsDecl.h COPYONLY) + file(GLOB_RECURSE SRC_CPP *.cpp) file(GLOB_RECURSE SRC_CU *.cu) @@ -22,8 +53,44 @@ filter_source_cuda_architectures( SOURCE_LIST SRC_CPP ARCHS 100 103 100f TARGET trtllm_gen_fmha_interface) +target_include_directories( + trtllm_gen_fmha_interface + INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/trtllmGen_fmha_export) add_library(trtllm_gen_fmha OBJECT ${SRC_CPP} ${SRC_CU}) set_property(TARGET trtllm_gen_fmha PROPERTY POSITION_INDEPENDENT_CODE ON) set_property(TARGET trtllm_gen_fmha PROPERTY CUDA_RESOLVE_DEVICE_SYMBOLS ON) target_link_libraries(trtllm_gen_fmha PUBLIC trtllm_gen_fmha_interface) +target_include_directories( + trtllm_gen_fmha PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/trtllmGen_fmha_export) +set(TRTLLM_FMHA_BUILD_DIR "${CMAKE_CURRENT_BINARY_DIR}") +target_compile_definitions( + trtllm_gen_fmha + PRIVATE TRTLLM_FMHA_BUILD_DIR="${TRTLLM_FMHA_BUILD_DIR}" TLLM_PUBLIC_RELEASE + TLLM_GEN_EXPORT_INTERFACE TLLM_FMHA_TRTLLM_COMPAT) +target_compile_definitions( + trtllm_gen_fmha_interface INTERFACE TLLM_GEN_EXPORT_INTERFACE + TLLM_FMHA_TRTLLM_COMPAT) + +# Link the TrtLlmGen FMHA static library +set(TRTLLM_GEN_FMHA_LIB + ${CMAKE_CURRENT_SOURCE_DIR}/lib/${TARGET_ARCH}/libTrtLlmGenFmhaLib.a) +if(NOT EXISTS ${TRTLLM_GEN_FMHA_LIB}) + message( + FATAL_ERROR + "TrtLlmGen FMHA library not found: ${TRTLLM_GEN_FMHA_LIB}. " + "Please ensure the pre-built archive exists under lib/${TARGET_ARCH}/.") +endif() +target_link_libraries(trtllm_gen_fmha PUBLIC ${TRTLLM_GEN_FMHA_LIB}) + +# Link the TrtLlmGen core library (contains GenLog::getInstance() +# implementation) +set(TRTLLM_GEN_CORE_LIB + ${CMAKE_CURRENT_SOURCE_DIR}/lib/${TARGET_ARCH}/libTrtLlmGen.a) +if(NOT EXISTS ${TRTLLM_GEN_CORE_LIB}) + message( + FATAL_ERROR + "TrtLlmGen core library not found: ${TRTLLM_GEN_CORE_LIB}. " + "Please ensure the pre-built archive exists under lib/${TARGET_ARCH}/.") +endif() +target_link_libraries(trtllm_gen_fmha PUBLIC ${TRTLLM_GEN_CORE_LIB}) diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp index 5557b66932bb..fd9b8c415c10 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:70bba5f4c14962b7d8390a447dd30f82ebca1257819496d82ce66e221116f368 -size 628736 +oid sha256:cdff75044ef1dfce27ee1ee5a08fcbbd692f6223bf4d4826542bdbb015fda286 +size 648592 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp index add3c8b15fc3..08f21e4ddaa4 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:59a6183f37a2fc9ef2cbc9d9cb45d351f3306494c7fced322e56a2e2ae4ab53e -size 563631 +oid sha256:d7066c5a6d29656fe3a1561115354c426f813f492489add576671610d0d488e2 +size 594021 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp index 3407d444f083..c702810dc482 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:24e51b666aff5e0c9e870919dccbec66e86136db7feea81f05501c3e8801c7fd -size 477853 +oid sha256:f661af4428f6c7db810c6d569487e6711e56bddf49be89d1ec6bed0fef133fbd +size 489051 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin.cpp index 6c98e148620b..dec3673b070e 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:df843e2e33057c4b5301ae4a98bf0639878f5b9d65ef40861fbc14f9cdbafd9c -size 447363 +oid sha256:e56a974a56737d021246ae8af27e5a1d4757b416dc34f819c16db42e99e7bb13 +size 456193 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp index 78125d35733e..2a0366de999f 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fe8dcf81808aa64b51cf9d08d956fc1c0702d1e64415e6befb95ed547d3f8a3c -size 464773 +oid sha256:1864f7ff2e585db34f394899e1aa179ca0dbba5ea82b15bfa123205b16786387 +size 479893 diff --git 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a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin.cpp index 0e7ae14ae360..7c5272e2aa32 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8afee28997dc1a5f5170a0190bb4d17b99f4ab7f455c0e910790d98d6e7de47e -size 562939 +oid sha256:e7faa76e4f076ee4a20c944105d8d6d301b9c8a179a5641c5ba172d755509497 +size 590887 diff --git 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a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp index f05d38e94c85..c1595b9f3bf2 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fac659aca6ae785efba786b3a7a49738ce6fb62c628491bc18a57e4412637210 -size 714736 +oid sha256:fb4254a4ca8f730513b95f588045ffb1400ed8dc6a174de0120fdb6207963903 +size 715130 diff --git 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a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp index f066bbdb0ed4..27550d2f2000 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4d187dff1c8e00c4e3d7c701f1a2eeaa47e282468c1d94792c14708844161ade -size 726052 +oid sha256:0a0f3fd488e9c65d6a855c73dcdf0dbb2392abcb845344ccdcc0a20ab6773e73 +size 737546 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin.cpp index 9073d287b0bd..7abb3d28defa 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:43ef7d77685ff1611e5bc2f202137059c20501c33773689b136a4bde839a76aa -size 770336 +oid sha256:57fa8094d23a7ae53a83b06341cad73354c81afba184f20b2281a02ba690d106 +size 790364 diff --git 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a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp index 109ce3330138..b712e11eecf2 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8010da9a9e27d5d42a4ec39c441fe3b6f730f268833f9355d6c672adbac7e4e5 -size 814956 +oid sha256:de24cc10f5507fceb8326f8b10c85439a6fd31c481b6848117dad55b9603c003 +size 827784 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp index fdecfc65538f..abbd43b9a38a 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ddbb978f0d9daa2fa324367f732f1e87503ff5c8859db8ee1d80a3799319b4ff -size 732414 +oid sha256:a1e2ac104915e61259174479c4bdbe6aae65f127e37fad9426d415a67600cec7 +size 743564 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp index 3c15f40713e6..e9919ce757cd 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:536cb6ed7c9cd03e923fc81b0b985c4a9eaa72b518d332de06ac08fad846be7e -size 840570 +oid sha256:2478b38b5a7df1e4bfb108adf53c985ca8b92d74efa5e8cbb0b88f92dfdef30d +size 855814 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp index e87cc070413e..c8c0f0864515 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5a9b8d13beeea79a25a2ce53e45151adb8505071fdd89ed0162d0c56de4861bd -size 756696 +oid sha256:623d48336e1a5f5abeec14a425cd4e531483074de6f9cd74f4f9c2308f9cccf0 +size 759952 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp index 5238e1bd9793..730b0e940606 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0e2193b7b8e0607fa91ad11931b3711d426c2ba5c811183a85e79759e677825d -size 878878 +oid sha256:d883edc80d6b5fc22320a84df6892fa01dc25b735f6e7513685034abf9a55c32 +size 889534 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp index d3ab6395b789..98553f1610d5 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin.cpp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:66d34ae750b43e63da2d8d85fa8edff49a15605b5e09e351f4e4b887d6ae4437 -size 800528 +oid sha256:3e8a1e56203b1452b8e100ee3b8ce5c2f5c066fa238759b61fdefd649efcf301 +size 801022 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/kernelMetaInfo.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/kernelMetaInfo.h index e76581644c86..01edbb970b6a 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/kernelMetaInfo.h +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/kernelMetaInfo.h @@ -17,14 +17,14 @@ #pragma once #include "tensorrt_llm/common/config.h" -#include "../kernelParams.h" +#include "tensorrt_llm/kernels/multiHeadAttentionCommon.h" TRTLLM_NAMESPACE_BEGIN namespace kernels { // clang-format off -#define TLLM_GEN_VERSION "a04a2c48-dirty" +#define TLLM_GEN_VERSION "c240bb58" #ifndef EXCLUDE_SM_100 extern unsigned char FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin[]; extern unsigned char FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin[]; @@ -6208,3078 +6208,3078 @@ struct TllmGenFmhaKernelMetaInfo static const TllmGenFmhaKernelMetaInfo sTllmGenFmhaKernelMetaInfos[] = { #ifndef EXCLUDE_SM_100 -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d2c57db1f78de28cccafbae8263c429154728e40d2a1151a7199ecf6f9f0a761"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7bf75460a40a496ff66c246734e8d11676c01c6dd9ca09046e952e8bbf202dbd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "84c730e90e852db64716b0ab75a62cbc2636621ef48e483064a534b3ce1f2b8a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "715269d4689d7bc60640d6b07b026ee3e49e1d2e39db5695dd00a5d94997aa12"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "1a555e5cfcb07299db5ee316b5c8dfc213454c6bfedfa9b7eaf1aeb933c8a0e3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "fead844fe3f0565762298162e7dcf4b44cb89be5e075388f3179cc3949abc5b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "4658d184e626e870c27ee29df413b6470403004b1092aeae67cc8e9c48db5718"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9bfc517cd1782984fdefdfddb75ba32e77ad437d759de753ec5b3f7fc9d07277"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "dab3cf01679129314714b65f41b221bdf605f2c3482110165f2469817c3398fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "01b36268e72a98a90bb4e838b4f9d434f4e6fc3d0d84d61718f51eedadc7393e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "f8763924a466c2604772fe477b855a51854109908e8d1af16bbeed4e8b1b9f4e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "cc59b18e6c834a456c278eb3f42763774c6e53a5dde80b168047d208bba83227"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "15c98607ff56e1bd8834f138ad57efb9044ae06aac58c07c23b953295357059b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "e5e45fa14940d57363fd81a5af4282d226ba9e2c8749b2b2691e68fbce06c716"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "a26c0a38880b711e039afd10661b0d074083084ef6956e8925082abc57a28d67"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "541bc2706dddb34ee44dedb64499115126e8c6e405906f152a7eef54aa732331"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "fd102a9bf8ae22f708187d911918dacd218baf85167c5a12dc8ad31095db3818"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "12c85fba54f5b35b33451e61e89b2277f6e93e8a2905534d8aff669b004590de"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "1bf1493d59f9efdc8e13066b30221a966ee8797429629fe59394a6fce567b7f3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "77efb31ebd82ed5ba8abd65a4e1725ffac79b107587075f44fdda806a0a6eb71"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "95ca376edb5fecd30117f7547b15361d53fd8dd16df57c5affaf440471944568"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "857f77afe0f773f98c12be170f7aab2ce9f8db4cfd5ae7559581d593acdf755c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "16e909d73afbab9115801672aa9745c41eb3f42b9c7b949755782f542ecb4aa5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "4d1224be868dfb0f655f36639a22655e19e0b718450f77fe7ef11876d05f415a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "0abfe78e7bf334747a8638fcf94f479ae3bcb87652455172cf2c8dbd095c1544"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "ba28d4b82d597c34de81438168c2ac62062a821db3ffad77c9513bd2d8b75cca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "d71eebca7b13ab5e8f173a85bd3185f0ef1a7e3536cb64afd68f470cd43f4302"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "7f9c2ade9665200f7bf618dc6e97b7d5a691ffedd204ed66585d199a0129c8f4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "10d8cc4fa741ede2eea5f304fee42bea65d19035d4397565785914ad452ba52f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "140254c114b2cec1efff1d182a526bd2e239f3ac329c9b8492f082464fc83054"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "96461ccff2fd8f4b113878c51da90be7f42ab2334fc7640827358517aa5446d9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "8519eb3254dc4259bf2fb3faf53e6264f59df8bd93280a3156d3da675af92a39"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "53656684ba8910a079c56c03891040f88701d25e5c5673706e59984f747bd8f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "f7710907568c8071a95d7e6828b9505fb07952e7dd986f8114be0ac3ac812746"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "cc0f8c8140cd7b65539abc1cb2620e8de312509f6f12a78514f16e8c5ea6d5c4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "07645d010d171f41ca937c128ee2a095356c98c0afdc458732222f4bd6178928"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "7a5e052cd7aabaf387fd39081bb5338be4b0e354759b3ab3c7154e660648a82d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "21a64b3f2c692c1913cd45d4a7cb7cc67140119db36ef72c2615bcc3cb5f9c73"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "62057f5ca77ec01fe0c6a890c905468d16ce3c51e55166343e3a9f49f120c392"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "a8b89da2f49de07e0c372a8d6acf49691ca55a67cfc37f1c552cd78dd0533ee0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "be33c45785f1def5d6371245436966a7e5a6ce122c63fab715cba1838e670cb1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "32691cd1ba609c07c22893864c693c8bbffec69abec8aea0dc412bab0df38ec6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "bdd766a247c1959cf3f0e83cf3b14d0025c727cc0642742ea73b79f2129987c8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "ce7fb95d77fbb6a8fcc0fbdba357689d7be1f6a1357acfbbe057523ddc708b0f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "6bdbd29f9013855c3a9948c7a129299e51e4bb32bc618771da39de547bbc2da7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7cf2d8eda8f53337a54cd6e150102a86a1ca22ef2537ddb3b39ac55094d93b18"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "a23c9688b394efcdb58fc0fa0b76b10109371c7b39db434902d998ccf8053f29"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "bb3dff5019a616fc80745290e6c27162e3c66364cfab1de4484e81be78c5dee3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "daf35c5b6369d2088edbc8832c6426ae3bcd8410466edb26855258446b2b4a52"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "b12444812e065b46fd01d136a8c99e4fa3923cc7a9ab2f56c73ae490b0cc201c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "cd520b53932363f9bd2ef697bd2f64a490e8b207d3a4aae353e785e4b3cc54f1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "55679493e02ada3e9d80833a3b04c66209734ada1dcb79b4e7e1a0993f7714b6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "cd8bc7e5b345ea42665625b5434b94178da4c4e4d1e8ff60f73ed9e71c0fe028"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "830418706b15a9698acb5e4297cb9d03ef2c40087794e8cc5eaa8d43d9d21433"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "401c0bb36d6df0dfbe820d41e22a4724f251ea6adc784dbcddfbb20737362805"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "fbbdf8679a41043b1ddadd85fa9fe6da4b69e7f96dbfa97764672a5a636b3b0d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "2fb58f9d067bad8204b56ca1744336cda4640c4744b5356c98d2935491164469"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "b74550889f404f78f963aa7f1d3407c3445f995dd611c5459939c4bf845022b6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "85c0e267b16977076ef494ea432f7ad34600fe4cc61ed363d8293c79c401dd29"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "4bf89313e53a0c97798b70d2453e08c0d40e5817ba7ef1985f48818f74fc804a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "ef02002bc2d4bc98f69ef124f8aba13e8e6188c717bb951973488d85f5d939f8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "db85d8ecdf0be475ca23a6484b60cc45e3bf9decbf4dc8029a4bf81cd76e57d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "c3a373ddf7e6765e63d9d3e5c9e342d0ed3c3a356ea970ed1b1eee386ecd1813"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "6a88cd3fa526bc531ad7d0a1dc6438294987ee0535effa68119d0f35e5305a19"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "81206063e821f43ee8aa4209a974a109570bb8e458f9d96e886df62d63feb324"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "51151e19f7931ca93040af30e65d04cb57acec2e37435d3b740132d104cd552c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "2c627e10f2f661bcc600839f6a8b1f3e1aed17c08705992147706ed90987db63"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "cf322234b9623c7b6323b700efcbfa596ab30029eb4d6c4a7a76c730843bf376"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "bb59faf3b87e21a887fb4166355fb3df8f448ce10eabf8af810f071a8871d960"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "b9713ad1d992f62bae1574663aa1eaeafd31f42d42fccfe6e7c23f0db786d7e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "8907dff7613f4e3c134c8b806b572271618687942b3ccd8a6de0429fec25a4ff"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "897502bef59ffb61cb30d4fe0ebbf7ea105a66f17f46217557cfba4b281ab700"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "47f943071b720231e54ea16077c48ab8ff622df4efb17819b3cc0a24318b1c0b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "a89d96753c1e94050080d2c633f35806299ca0b11981fc067317277bfef3d15c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "50d706f04e650c701399d77ac0dde620c3d3cb444be034df8ffe11c77acf030b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "df2802c93a39c30cbb86457119e5aceb6e9c8ed1b9d7b6d5e73c3fbd5aa66bf9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "0d9ba17c9a9074ddb91d20425c91cbcdce70d645e98da1e224157cb37ed244f1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "52934b70a6022d40626f51726cfe59a1552c8998ed76689516e1c8e1f33330d3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "37e41f63837f0536434bd1e1d64e7d422f8625a9e5d42fee6735d59b829d1379"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "5fbefd0da3e3a2387a9a01e73a316740d333123c61ac59552c5bf1c4f7017428"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "75d0f0ec5d4141d460bfc125a3ea20be44685d43018313efc75d4aa39dea6ff8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "2dffb63e15456f2a8d506d087b6ac93dcbeab4d78208dc8ec33754f9b492e879"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "d4d2c91fe00fa472de15e03a05b29057a2f788929fd088ed557147b971f21201"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "eb0e34bb2f873ac68185738aaf84e8d5cd32636c18eac56dfb3d03264214c1d4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "5fa882bb7481c340cc9473ddadbb8fd13bc1fe4d1c151e2586c7f0126bf1ef98"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "9c8ad3412d594cc5de53d4f645a3f939ba0f9aec1da29e2d92bddd72a20babf8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "a2554fb8a30d9ad09e83bbe3594344bb9167e5fde2482ef5378ed0d762479045"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "3e166590b1b413b4ad892d3e05633a14ed958fcd014942fa21393492cfbc0abf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "316b130f1273005961e1f46393ad3e965211637c3047484a42a1db381e990f1c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c5e5337402a5598c60d2afde332dbf8d08e6ab9bfd41e817d5d835f7f2b664b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "df489b0738dfd100468a9d8ba4f99bc9e1af90f63de37ce267f34c19aeb7a57c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "efec408a085b8991a49e18092e8b966ef4957640bde5e0cc68ed70df288efcff"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "2967e54fa68c73e7285df9a00767094d4cf4232029778613e5a011c0ffa76739"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "29422419609e64d10c72d8a073a0584dfabe7251015ea5b77536479a58bddfe2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "c2a38d823c5c5ad6e41b1886061a38ca2a742172b5ac5c4c6ca31b01398e4293"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f0ac48d6a46dc8a39f6e64b319e933abfe31dfe354ffb55e546136321b503fd1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "965c7edeeb1af66f820b381896bc1c62d17b5228c7a8893fe6a90716b65f16fb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "d24806928cc265595f214117ee8d2de2ff6335651d4e172ff5890d37928b86d9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "df7eafe716ef373b7833061de7dc20da62ca3672f63d6033fc0c229eac206896"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "2fecb9d9a0d5e40d27937f497e38e305cbe4fe4b986b78315fad11d092374c87"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "aa67075372e2813ca4f7f4f7b5daa4e9773595cf429d240efa26329170ce3771"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "aa5a3a6182e5d2cb101c405508d819532cbb1535bba1f922578a57b9661be0a2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "1e14dc1b16c3724e38c6b63d0a98fd52c3cf5ff72122f67a36e2a7d51f2832b1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "90197bc2259878b81f7458a3381c0fe8a681f463e15e1a0d951db424a2fe810e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "a903a8da6c55377c51934a8a291e84e52bf022a5520f0555786b91e11788aa5c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "003bb1846af6fb5b217d4bcefd2179ca0f65b69d618af98e064f5e40f7871c2b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "f1542a796ba4ecfb805313fcc1b7283d6c8164e37616d3edcd88e5e62c698cd1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "f6b380bf9cd7cdaf45525f705903d61ef8c8fdf561fb20e11e2ba51d2c0820f7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "a9ad20d01660f91e19adf1913cc16f3f92c09db370a02f0bb73dc6807a617ee9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "5b763ccdeb461bd4b41e123db53a5debd7049351ef9a1da95845e2a5b309fd82"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "7309907555e00de9511cbeb1696c33ba69fcd8718b2a91bd518ab765deadd90f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "a9d24eff8b0056ce4350b555f7550f18744837c10fd85a7c88fcae8a153c9780"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "9e79d6304842db6cc04f4de7bac0187e12ccedd39e460f22e11676746ab1fec7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "e0874a940d50036af7a4e3de0c053b32af4b0479224cbd5240e3c79bc20c2cf7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "9874f213b9fa309581e192a63491386b94476123a64e0ea572f8c193f635b31e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "95f765d47a703482d0c819a6193cdd8d35c5cdc323d98dda81d405ee35140f0c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "a795711949254910c9357985b4599a1a4f24147c2be42cc93d709f824fd05122"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "15fc0c35d511b2e761965b2a6b8100fd7c286b98d219efb28ffce5efa98de5f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "06c0ba6892179e1578a747d04058ee290dbd0bb229b5d2e1136fcb9b1d404434"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "167290c60c08dbd09b7e7fa9eb67110b63bf1810b89841937fe1370e05c254e6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "2401609cd102cd1ba9741451eaabc3a458767c37ae3f2c67bff2008d65bd5ea4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "c6dc1b8c9f9ad3b9204ada373e6508579601a50ef855a650c4761040d756c2c5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "557abb4f6f871ed97008f9f239fa67fa4aec1bb64ec0b90152b716ba78cbad9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "36456030578a9c5fafd1830a5481c64c902b19ce5b90053b73105a773c850ad6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "a6fe0e792670f590734bde1b0305adb149c86ab43b3ef7b716ee750fe5ce9f5f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "0772774354cd2e61c82e3b6fcb6593b44e6578e8705320dfe621bf049c08c335"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "2bc494e7c21603f3c3246e684bb1cc37d6e77839f11070c1f7b9c998c9a62c07"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "7b3fbd759c4f7388d62107209dfd99197db7ca14df2e677f52d02775d7c1917a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "bd48f948ab275ad6c1f2f43f1078e57ac4c8c64d68f799e697e3dd4d99db6cac"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "39fa1652ac6fa84fec7e3e5e65e29c62a391f2e009aba934938f4cf630528b7a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "7106b29249f03c6674ddb9eb957e6325d3e3f62570434edeaa542cfbae7a7422"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "9b409698b356eea77ce26f37f2d74b4e941764c0f51601cb5960b28114791dfd"}, #endif // EXCLUDE_SM_100 #ifndef EXCLUDE_SM_103 -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "3b80832d5805598dcb48372fb261a01640def5a4d81ed602c1efda738540fb43"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f461679653ffd87ad705f97786da8bfe4a46f30f0fca909af211b2c5fc6ee6c8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "bcfada1c8677f1ae85fddd667da8d2764406961a5bd420b0cf1647a8a7d7ed01"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "6dcb53154c8e6505d7a121187248f8f6056786d05a524fd233c2e0e630d38f19"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "f0df4b7bc6bb77d3e718017f0b678cad5d481724648c7a3fab4254b00c1b69d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "fc64aee22b3b027f0a50c2b9d585d24cb955cd09755dbf3d112dd754df07a9dd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "6e733af2b156fbcf25a15c06fc7a98f9081fb48c286ca2592d35fa050bab238d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "51cc0f41ebc7618cc4ce7d19efa217a37ad95b8f16f055632498898baab8936a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "0e9925480169a82a885461a133cad4acdf32269cf8a1ecf4c0f3e4b0fc7c1d6f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "3b489144cf13a704aa945382e00d9f72520aedb70101fc7f6a14de3b6ced2f7f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "f491422e0943c635b05344e2624fe178c5aefa50c3bbf7d581b1527939cdc31b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "0b0baa6409052fb590da2dd4558c876441024c1a12a7fb8352bc74a2c3444d14"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "ec6eb83d9243a445d309c5c930f11cbc982b4bf4ea42e800f607b476fe32bd93"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "e1a2c0b2a3b6b7b0321dbf7fc7d289454bc46aac9313fb7070f974ce0d8f4fc8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "a2cf1eec20b6db1c70369c251fb1739e3cb8260112434c6529b45c0968eaa3ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "16c972643f292d7e6cd134d48b07d0cdc5508b72c4cdca221eb12fd1de8012e9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "61eb5165185067e24b2cc4a7bbe7947824c8977aa90ee24da0e47c3e4aada618"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "56dfd6bb11b8f8f9d96c3b7549db1e2c8de30c38db31981fb6c6c99fa226db61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "adf0da2c49f0a1c65b4a3681fa3bc16a141a21577288a65f36ab8705c3bfaa2c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "382a77d0f60539bb96929b87c4ff93e68fbee3a1d27de05049b7a046d584ba49"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "606fad9516c99865202a116c1cea69ee355ca1b2df8d00ea784652d870279413"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "7144549a0a01b7c9fded4cb1745ef7809cf38dcbda46abcc0de26b2ba7432691"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b8c0d050bf6476254708597cfbd720021bbefc69e3ef11fc9bb0300d11c1449b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "06fd8b6b950ae0e9b91a9ec9c79bb1caeb1371548f9b72e2ecd0142d236e4705"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "05e8537df97666400c7ee1f3ceee3dc4d51f8ed45dda831f064ef76b044933e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "7d07fe0c4c72d51b81b24d42871d70f50e0ce64b5e33f0ab707910192ad48066"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "fff08256e08149db7b803f2bc0a689a07ac2ff366992903fc6874f9b71eb24c8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "a50cdee93a663056b69b4f6ef7775f26b9a096d1275fae7d2cf1022bd487bdf9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "03ae6be4b725f5e07bd43b586357eee51f13edbc20eb8a4c4024f8beaafeb3f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "ad74a81201b9b219dd884d85dfa5f690f221bfe68ab8e6c6a7918c7aa6906b4a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "4739d61bdfc4e6ff440a41689e08cdb657ebbb740f8841fc08034705a2c18de2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "5fa8a2bca125beec57d25fb5d62847f72fe80b9e987966cdd131f7ebec33e354"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "96f40312c822f2312ea2d46878abdb6f902c2154cb9543de424ca9a0b2ace01d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "2eaf66d3d05571721c3535ede663b507feec1b7a4ccf6b5ff0442bb8370773fa"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "1d888b0d5ee0f5563b35ba3c34648e219de1b29dd038ab8360f881dd6f1c493e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "8b6f0f4c9bd2155057a212c66b784e22b447ae74d72786c072ad6912ece87b2e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "eeabe8b16eb8d013013579027d5736250552bd4a9935e4148f02ad4116074710"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "c6535a45a919680302b24881522b80bfe520dec7a136635c8f2f1e2cb8aef297"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "7fcb15704a8530ef0cd9f359c6331f7112413f314a13663fba9f99bc42f28297"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "8cf2022f4d7d80dd902b86947d1dc1815019b2e11b353e63c9eefd9dacca8728"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "ca950f964bf377b2c937d6daeecfa2f0c15dcd467bbc6172c19cd61636864cbd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "1c0671144990fbdc0910922004482d0226774fee0f877ddbd1b83ac6b515f6b2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "4201c7c2204c2cbd50455ce542c28b103a0f8eed7e62b5cac6f6be79901e293c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "94c1ce426aa511d9acc008dedbfd35ab989d3b0e9d93cbb55ad31a063298ceac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "60d15eea9f53cef27b51584fd5218b9dfc6bc63ffb70c6e1c6e7481c09c3d80b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "69f0f9191223e83e1ed6c76820af9d5082332f1e58b5c65d973b85d58c4823c9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "6e5f245dff0b6a3f6cef8cbc37b9005a243d6f745d2a5c6246b962033d303a61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "4cde3f8dd8b8cee358ee3f79a41540900bf1e2ae755a2d566a502242fed78967"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "bc4b010dca381ffcfbb6616281c7c8aff4a0f71c40a19bacaa7af8164f4c3c81"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "653903642e034eb8cc124ac8b51f16c789244731bbfb2ee0aac3eb62d56d50e1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "334275e325b8ad01819bd4d7024412aec8d818a40e382626a5b786cce908a719"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "5f5ff1f3551ab48e4e157f8d0422339983effc4bda1855b4add24cacbafdb5ca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "e06aa9577e793cbfc1eb0d337bddc70ba2346497b38ac3bacf4a0a633f31e2ea"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "5ed3d823091fe3961dbf5be37a7f07db6a01ad05ddaeda3a388ba258b4b9cda3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "d3ca9641f56fee6ee3b71adcb73d8e8a4d7b5fb6035a9d595c2f774e8b4b8463"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "3f018dd5183202c3f6b1a4ea887b0c7da57528e2101a3dff9077af4a3bb9c6fc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "86993fcc04a9334865a78575c0550788d5b810cf4e62a500ce23376746390e52"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "97623a3b2c4aea18754c01d84969382a78bd96e5344c09cac50c5cc249909e61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "1affc0985cf9fac10a85deb8baa7a7b6367322d5f9cd81a27a853d9d75bcba53"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "73ae608bd37bb6d71ae3995bc99ac87bb71db6fe15bd62d17faaaf6c95a70ac9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "091eaf0b041e850b7940e85185e05232ebc66b2026f8153d2ce15be0117ee53c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "a6783ae3d505bdc871562ecb412f2525754a0c5c578643df7c32b36f955e6a2b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "d2b6dde6a704ec8339b60cee24e664c4a5cc5db8fdaa803bd9b1c6cc95e18ae0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "e98036a0dd237763e7c32cdc809d1fa12f124830f30a3a901858f8e9b201d376"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "af08292b608b6d984a6668af7fa0f2de49164ef0b2a14639a6a142dfbf19ed6c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "db8d4648440568af5849cae2f477a28ba61274f041adabaf38b3c5f070323b6a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "f32cabe79c2dd1f9ca31f9dc98db08bcf6b8a0e47790c75c77642736711a90b4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "4f64e0b2c78a7fff1f8740c13c50bd1de4dd193a1a3a9f29ee0ea084673c8714"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "246e63206f3784c9143710f29379e382fccb036b7b7efd3b390d435f35dfeae0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "38ddfdd9d86b50c710b53b7a59a272af616977d3bd9d0bbedab85f64682829ae"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3f4060154aae56de215d5455c65d5523fc02ff3f668ed8e8b929c6ada7fe0212"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c977f1acb6392b8f036758ff77c5bab0367529be9ad7a91a36d58e146a1efa40"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "83f809f92be2c6bf0205761c5980c212b86fc7eed00779ad73310040438a57db"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "02b8b053f828d6a762785130aeec93250af68ca14755e16d034684ac09ff1b96"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "4afdb2d1a9fcb1adbd1d04f249fd55a7389a25801b66f55d244d5971434042fd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "74d2d0bdc29808435db4e23ff1d9e80a2187251864c24ea13031ef334c0a82b5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "6b637a83fd9bfc66d24100c815ac42b2e977b28df3116392930d2946757c4385"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "647aa95795dc4c6e9f5a342780b7cc802d73592ea2aef46ead7613369997dfd7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "858c560ed88a548aecaae5114a0cedc1deeacc7027ee5f5804e73a76a43f7e6d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7b9439b895f93969d143d4fa33697c9177a8b7dc0cc359625d7bdf0cbd15409e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e0d306af91c7da1a95e02e3c13429e2dba09ac2a022d2836c7f73c629cd4ec85"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "616ee0a3f2a6342f9ce6fff2c71e4af539858cf8b98974a99171e5442f7dada6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "d7e2fe868c4e05d43d62fdb52a2b7b2fe55958758855117f15b0235af30fe955"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "5db040a1bd90b1e6deba5994ea4c23c689edd75f29a0098772966807f251a395"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c5291532266652b69e755ea535367e0bf4e9f42d9723e065ce1b5c43e98a10c5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "8dfc4b52950b6994db0190c537bb8513ce8983691caec03ab909fe948057393a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "322ed80506e3a57fa19a5a12de0ddc173cb9cd916790e08ec938697108ee0417"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "71cce39b138d720f89236f3cfe4782091a23b315e509969ab1518b038244ce34"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "59c17b6e77083907bc70bb065d6ca511701bb969d969702802a3c91a9d9d0d49"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "60349e2b6e2c40e34780fdd16c827d7ee1fb4999b4bb8f389b4949e57f1ab5fb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "6e9ca8004495fd655507f3b0f63fbc0345f29a65c07016e9e9925c8b594fe66f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f3085b57587429e9610bcc9874ab31dd25653c41d83ffda67c707fb7a96baece"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4fe27f0cd58af1c87dceab2cd986dfc6b2f2a30b83899012cd96f01e8ecf14fb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "9fdd2bda66b3c4e208cd5af9d7870a6b75ec426beed5e6b746901360fae60fcc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f87b369aa69ea8867e1c3f3b65bfb7692889fd8406d2fa0ee2e0e1cb56817e77"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "db6ebcafd6a23348a2b632f15780fd7d4cb33d39f8da4f20b629dffaa20f2265"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "6cb016ad8da23228d5b453dec755d99df8cca156ade49f6591d1e13e2c2193c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "eced01f5f2a1445e6acf34ca15ea029f4ccf2dc9afc79e3b6a329c538530c6ce"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "3a93fcdb39525f4d6f2b1955a19d54c093125c67190e7931f9660e9f13285f96"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "0331a6bc4bfad54faadfb9463ae88ab94acb494490c29d21d7ea0eadd2c95566"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "dd3c83370f5a104aa8fe9daf7ce3ddd504ddd1872778e034af6e41b8b37436dd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "baddc5ae650e5d6ea9b4370164c1436c6cad57ac9985161ae51fd01aaf9827b2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3782e02c8c2f1208e8da820f7c0820f37e59454fcbfb9a7f230974606a5b093f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "25f366d316df34227893575872cf23510aeabe17e2a2250f1cba907dc2190d81"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "f4847be0ef21592ac1c3b45f00b7cc2575e2424c2e8c13464d8d7555a8bafbbf"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "14b5e669a103c0238193f2e43cef511f56daee91da0e61c7f0d1b462d4b89a07"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "2c2ef0aee96cbe4277a214e728b214238073f4ca999578d6251ac62def725528"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "203c75b520a92fab437c8ee191f1b5cc51694ec47a024c20f10003240ef87556"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "ffc8e6cf113191e68bb249d397c5e31a613f9119a112414edf45515c2367ea8b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "59486d30ec1aa2e61bd74b2694876f9753733b7b4351569d0b885ffb2bf4bbfd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "44a013ea419af52ff14d81d5bbd2c81f1f51082c892ccab4d00d7c8475172569"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "1817a87ebe40565508ff436f51bf126417878673839861e5cd89cea6574f130e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f6776438f5976ee8def1f5e69763275624ef7b35dcf6370796ef1c657e89a3ea"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a407c9e1b9fb46f466fc03b0f2403686dd1d5ce2ed5e64b50bda5f1e2a1514ee"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3ffbaf2997025f9ba5c2b5c6d7c6ff9d8a13726741f9503958d7ae6ceb3eb2e4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "462caf2e199ec26cb9391e08a763a3b18438c26a857e0129633d3037346efc48"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ff344e27a563103ca619515ded280e0349b3ea6e0e16b39cf7c78d187dae4a3f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "9efa8fce37931fea66813b67aaf402675ad7bbf3764f33a6939009c655dee7e4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "f8b6e6521dbcaef78dd457aa0a096d8f10bc59b0cb90e2bb24d9b2566f33f022"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6b5d8c35e4d51bf560570235b706a492124f972a8105d961e3c89e088af98c8e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "f315ebf6224ad1fbd4f2821591acc7d8b5c224b1dad79a88ae84db8692558654"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "f597305af69988190a3d6c41dd0b58dbeffad2381764d5b4908b44a2c3aad359"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "6fc1e8df3fc3e4c0279588e470f956dbe595842fffab9a00ca95188a94d8f796"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7685e6ee1409c90e7b68ee139ab6231137af0ffc76e05ab66bf5173f38939e3e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "53f00901a1cb7e56eae8006cba286b31e0b34dbbbf5f7cae8d3fc58b125825fe"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "7e9fb4ea967ac1a210e0e22af681a1c2ddcfc9c7ae0a13bc36803a1137700856"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "097696f150cd9f94151b6cf621e2b1d7fcda913ba606de768e6ef153cc1332f4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "99f321f7dcd15f3be9180a3513e8bb4bcf52f8db4bdbfa4a93eb760cfc3bbc4f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "076bd88e9e75f876709b21c3475569273039da56c04874130a9e72e5d5127123"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "8a114b3767dca0360a0c311c1cdacbe6805f54d469493c7725d0f8d3deec41ed"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "5d214896b22ba8d6cc5395be6131974d50c6cac25cedeed6da169d05188f8733"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "28991f112e4606811193eba7050c6e0e16016bd17043f50c3d5cb3fd621c2687"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "2eddd60affe0ad4abeddd193b3fe3c3549105c1f6236558bdf5fc2d8542c1c1f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "7d187cc89b9dd2d92887911ed774cf3ed7683e40ef9f310e4cd19b331d762956"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "2fe24e3a4bdb5711bab7360f7cbe5800e8e00dd0b8ad5882c748336804a39e73"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "82def42aa46d793c78cdb52700f5d3eaf55eebaff5a889167ae16f251ae2f02b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "64ae42246a37290c91254a4fb24d3d556397f644f0d1b8d0b8aef555b9b35245"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f5757df4158957c268bc5d3ef2085ce70224597dee5116be3e6d96a1dc87fd61"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "165fffee206f92f93d9e09d7e83ea9dd56bebb0310a65afa4db9850193777b06"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "c875b38c42da3cc1578e8976d3cbb0238bfaf9073fe3dd19f202cc4ec007fb83"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "75ebf73ffd0aa8674065af384449b5f4e6eb1dcfe4bc4115ca9f9d2b02e590e6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "84d9b774d1c4b062ed7ff7a45d2bf80f2cd29084a42d685988b3932d235ec7fd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "7e8893bf84ab82a1623d88c0441fc09ec219661dbfb0d477364d9a2f9a99b363"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "0502a4d06f1c716abad841d292770400d3935843b38a72e1bbd857585d6de78a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6b0a77dec134c5cc839b363596e353f47825746226ca9e5c5f45a67701a34fc3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "9917addfa9b1d6e8763c7afaebd395d1e8f64ac6302077a45a6eedc9f2a93648"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "15ae78509acf15a36e76f331dea8edb8cf61fae96a91aaab51254a5e11b120a1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "a0c4cba48723c9327ff3c351d936d652522d6b6a22988c014b58b168177b83b9"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "acde673647f13938e076718c4bd7e0ebdca3825e8b0d324c048f8e18e3a119db"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "b199b170ffbe479c08c4aef06cb1a5a33d4f97a5fa53af7a51e22119ce032b88"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "509f5878bfc767e00df0fd8e3f5679dc401c54e46abed6b9cf3f214c68856bb6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "b6d445417366f9ad34d2863a5cdd116d09e7f8cb70fabfae8eeaefe9f2d05796"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "652f7968220a7b587688b08175f9bfe1a8156227dd09817a86296d36649d33e5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "0532117d2d5f8304f8951deca323706851f8ad6932f30c36038dcecee9522721"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197056, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "ad988d52a639496d393542aeca2e05ec53fe8ed77b56506561fa74b3aa46221b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196880, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "19055ce3a10739936ebf3dbcbdd60f20fef04c9104488b1c7b51b3b23aed14d4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197072, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e2b3a662181720bccc1020a6d205c0c8a90eb73cd522d62dbf302f78c2a3d07b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196896, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e251b18ad65674077cdf7a256ee7f6e9560c5b212f03d41f130707204a8c3776"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197056, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "6d38b27ed007218844716a836c07ddbd8621f0330b85c2742fb43a3d18bd9d91"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196880, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c376c724c3573fa93a12734c905f740b87133bf0cedf3948f343d5812fd0bf65"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197072, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ab16eb6950e456a3948ba42ea080943af9c75fe8596e93f83390d1e8e7bbeae3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196896, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0e2975518b26fff07e85f02b1959d7189db7778e394e1fd76ce60e237868763f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "31c70af186a5dcfa5c95ded397dd309b6c64dea36ce0f566e9e6990600472d6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "72ca13a89531008a23becdbdea4764fb42a6d4a21f039cc1587ee7464b07acf1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "eca487c223b581d198ced5b7d96a9b82aac87f8f831d06d8c531ab0f594ba54c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "4a3243340f55950db597e9377905683478ef80a437dc6d2b3119c76c8d6214f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "80594c9fc38c24596521d69202c943391a1927bcb0f9b5587c2e68a97897dba4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "a5643f0d2ee70505b421f27d7eaec1477561b845ea33fa174c3fce2c0b65f64e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "bd70afac64d725242843579cf8a287646aaa31acbbeff5d469a043becec71e87"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "adcd8ba477c85f1b02202a3f1c7ead98c5ddfa31ad2ffeda698c02ecc3d31d82"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "fca505030edb954befa5977cbc4704d939df24f0a0f6f47174fef8c26f87c30c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "e05ea58aedc926d30fc685762acf9412583c8a8a7a86636ccd46b3a9ee3f13bd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c1da60f7ce835e3e3a209a9c240b9e4b08d0fb507709d7689f20ff09ffc7c436"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "fdc832524584be8d31267c99a61f99917b0ce336b87c551979018997b0c7c520"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "efa004b5473ef0aa9def2f1fd5f7b601aea90a6a1f823d53e8accf7307a03229"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "4009eb48e53239c7a190bde52065146f26e312a6d6bb881b34ff5aab790c755d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "aa3863ae32148545724d1c13cffabe45d8d2bf11855df29a99bba71bfc22d5bb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e9a7bb7c637fc19e6bb2b22da7468ac235cd1b33829a04d6f4b0a0cd54941a72"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "b1c1387a2e0ba092996160edeedb9c8fad2c744c87690bff574a10b1bcf0de16"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "59c598c753599947defab01d215403eb7af813c6a9a3cff99600c60b1d14b48e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "dbe5c2203df61e25f308b84535a27fee0dfb4545320836fb4f71ad35237c6088"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d83fe71eba0518e11ed500c1c70d8e5e39fe26d0efc323ba5aed2766621dfc77"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "bd10880d7b0065a18458254bb92d84b0be063dc87148e1dd0983767c58f6296f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "25c54e1df8f4941ca78450c4faa1bf596ba0dc343bafe33494d98053e80405d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "728fe9ee39347ba6b5a9b93710c6f947b41a4fd9f2eca5e3b02bf859dc4e02ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "a69bdc7af3cb85c3cc40e25f59efeb8b3d166d84f28906ddee4e3576f99ddef4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "f7e5605d05b7ff5e66fac7318deed82ec263bc9389bcfe51f5c2043be642cb24"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "a5566a0a342b4a31eb627a1c82b6d0c51aed11e8d37b60efeb9272469615f55a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "bf550506a2d1ee52fcb19e307fda9b2187c3bd031a6dde4d48fb4460d81000c5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "fc09bb8768c20655d30b2dc1668ba126524bacec829c1b0babe0645a9f53ace6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f84be671fe05a7949c546843bf5d1c8446282a06433648a9a84c616a65799412"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "1867fadc6e6f424104b56f4539ed604771c93c8d769716e78b5312b2c078bcbe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "9db4f2414be18bc1a2ab6e92b16770f17a299a7a0e9c9a4b0cef6623b87b610d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "6bfde8670b193656b1bced26cf7f9d84b2b3b015efc460a6dde5451d598d34a9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "19297212661b453273659733a77efe764698f5d436ddcc3839c7c436faff5908"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "2cbe2a82cbe01cdadb98c0af2c58e421234b7451064f25aff68104e1414a3956"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "148b3c32e131efac84489b9b4a63911bbc5d83ac9b94dd2173386395432bdff9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "212df773f71a62d0c41d92dcfa484f2d7ace72a2cc7cf066ae62fa20b3c5f5c7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9871c148a239df9828f8237db0b34b6b7e2c9466b7c3a89aba02892a3f7bbcf8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f3936cc246db66eff4e117a40ad9e6e733d0a288778c2aa44e112f6fd073e019"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c8bdbeb931e0be77c94aee58fd1f174bd45672e668ae201cc501dc1219c9ba06"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "548859bd8e462570cdab0ca144484e37a590415696411b139e335b2cf91932a4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "8d20342c1762b4cda7f4990baac6fff280e71ea59b23d2054585f98bf0e2906b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "7acefc8af34707c0248923f5e4e63c479fb70aed7309d86d5d7f8086eb28d59f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "ac2ed9ee75955471921b001a881fbae65d0562cf14652c76ad3f8167bab43cac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "f103bc2f3d29dd7a114f0d95fee39f1ff080273809fc25b6b2939fb30dbe253e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "5e722779a025cae4ebfb8154286d9398494ffa52fe30ff03f695141cd62a7f38"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "6e8434dbe5bb34ce6db4c9a920b3bd2a8c36da8c113b686c05980c86adbf7ed1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "85d58bdedabbdd9f96bf26d114f1cdfdaf1b67a9206329c32843295141f7254d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "03224dd7089ebb002aecea740fcc3ae22b0e32d1bfc62bce87b0afa7ee799d12"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "8fcc38b2d721b245a61f409dc967ec8edf98a23d2be66f63f8ed7d4be4e0c897"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "acbe13c02cd4d38d52cbf757f5ef8a3ab234f4c0477106209b467040ac74d0df"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "5f697bea3311b2d8fceb1adaa198a5a16b32499760696c592982b3fc0af6e8fb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "7d41ead745a2e447c5201d92880944a2a74cb89544f80e2736892d587d4d2807"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "93958133afb4dbf8f2159089366c8dcf6f8d00d463803dfe39cc2c9bf109b111"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1ddb9aabfd9ce87c681cb9bd1a695ca6a71e8095c649a4e3eb40764d9b74abd0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "bd78dee34eeee3be55c617b963653dab461d494b98802e30258c996ff040dfca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "b0bceea73aa982dda821b9b9c1c961aab298ecab99c009a9b50430aa1307b736"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b92ed452aaa56d6c4f572f813d7a6245db02eb0a4d029704f9d38a44baea6a4b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e79437571410d65507a3761b89a4cd0ca4b655392937732b1b5ebd206ed75093"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "cae81d524d7a0686234c4191647570e56549d6f5bd71aa60bcdef19a0f892ee9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2d2b171fecf7928b3c4a7a62d53e7a7d6660fdfe4c9551adaa0b9fd0f4f75731"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "bf3297c33225cbfdcb27b0ce2d55efb3b3b636b00832fabb2ca5a094737de7de"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "1c939d978f956f6d2301c1b402dd035bbd7857741b5473f4be5e0cd52e5e7e5b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "3dd896ceb29d39f1f39b49f68e7af12b0e883434156e7a8fad81c1cf0ce59745"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f78bc126f4d5286357e023124e16d1df519159d212dbe4f4b627fecedcf925fd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "7638d35ee2a2e9b605fbe7b2979caf1bd047849d64d656eaceae2750d3f7968d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "dfb31df6d1b673e164a80b67b470d722cdb049f5682cbdd9332cff3da4d79b6c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "fa69abbef8e762cf382bab207a85fd1b11a3dda844098ba490a491e1aeee1777"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "81f8b553fa7fc0588e0de542c677a84b9438b3e5c20d6fa1e0bcbb5a6deedb96"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "fbbb92efc8a3c21300306de809b879f0f3d2ddc2c64eaab2a01889498c30e88c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e69005d530122d439cd7f1ae3c6d68bbc5a16fa8f3caa1aed8115ecbc7054452"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d24bf3433fdec283e155e47e2b55636c5c60fd3a7e0e1ce59cfe792e19bc9071"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "96b7173c1609e759229c64f09aa0ed58957fe7ea4061cd42dc3d088963e3a4ca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "03026a9fb5e196d679ea0d2d6d4628b59837751be001824e556fbab851250418"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "bdf12a5d65f82281c03f120c913f4c048ec0a2aea2c207a00a8f2820158ff96a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7cbfef5a05ff85144bdb149395e9448dc1ee3ebdfaeaebad68c0502ecb7d1cad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "e96f1ece60a2056405bc00be98702d31c7d52ef16905873647583429e916481f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "382ec52df4ab584cc50aa372d46182ca046eb1eb290ad3e03eeb3757b0b04f1d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "502c86240218942338f6b94b77d51c8c2ff1236070f5bff674ee0f20bc0d9e03"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "73a498a5fd55935eaf4506ec7186d50eed0c9acfe6b73ed0895f10ab4a3bd28f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "776e3bb7d45e0d4ddb6ac086e5aa7a4b31ca17d2e2b1fd06495b2b932e6430b5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9e05a597edaf4a73ae0ab1fc9ed9c2f9565bb3e6ed4781eec1b24dad447106c6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "b8f68e6c7eb233d67168699ee4b2aaa986fafc717ebd0233ec83f47e3389a84d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "94fe1c99461baeac526d7a424a23318b4b178e2b13e2f48ba6679f725dc6f33e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "4541764e60c81f989b6bcc123c9e94f8c0c73074c59915f056ad359300ba1e42"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "0e991fe06aefee27420b35fec1093055340e73367aaf4019b28808c72f38f58b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "4c89d5ac4af41e1dbfd2a81513999fcf5a08ae5ed1ee6461af2a110308806ca9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "eceef769fe23c891c1fe5c5bcc0d5db4662c09181026e95a236eb10417a627aa"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "6866a8a85d042238bd1107907a0168e3d2b1fdafe45762458ea0ee9eff826d46"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "519f2ea85ddc29834a90b942416b70de81b39bd3e893c2e9be57eff21fd68060"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "64dae650e7976e9214d64b28681035e029c796f43d49d8032985d9f5fb9af05a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "be89bdb90ad5b6aee01c8f9e07f16d71222ffdf4a0d93c8795cd481c2ec39308"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a3c9802ee0abc6724ea2fc94286c901be29185a914a3334c88754c2babfed2e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "fb5ce3fe4e173fba70477e601f40681e19c1439ec8f7b805eb8f83798f7951ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "36716879fbb882ed460052f88e941068343a9d9375ff79692856126aa8dfa0f7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "819f18d8b9f5616d016e3b7d38040efd84234fd16dd232804375b2b3da9abff6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "27d07aa423a5bef0917b146803471c2331d5227358604613395df180fe0a954e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e97ad97491f009e4333aaf24cc7cbf41a029b2138ce5d9bb9f69788283cc1d8b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "83f048cb61650d26c978301082d601c76faf4398d36948bc6db2393264e3a983"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "0b7822c34d11479a953743191427d1e128e448af4a4b533ad5292b85c60c0868"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "6ebcfe17fce366fc76576e993a145181460d6a77046244c0b2793ebe80a56607"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "916e682c31f9eeadf7d5e39a999cca91b9729b263b7aa63faf2276ce52e5f611"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "8ba838cd5834df145ee76e962932e939c3cf4416af6b7a26ba7bc14531041042"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "8030430ebdc466704c6a6015a6fd791894223e367e5ec078e01f7ccba54513f5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "3d04b142866867d81c94bfeb8acfd6c3e435091fc0596d999ffe9a8937961625"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "7d739cbe56004cf7eb18040e58496705203df96db94276989eeab56dbe461b6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6e69a8ca329dc970820769199adb71c5b8ef91179fb711b1c741da74668128ed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7131c351816d0bbfff7e98aa8d31bd04b10e4af47fdcf5b18cec272b8b373a29"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d365cd4db1e41b60addd95108f9f5a0115c80f13d99f04f7345b2f219e63d34a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b6cf012567a2bcad925b324f2dcda27ad98c885eabf9edbc374c3edae2e0934a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f2fa2f503f0e61bc4f4e807b61ec09554cf4fdb8b941578d5e616fba78a9ee8d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "90c078ac80d0f70d18449d6214da6aed4e63a5c8e7ac2c3a22666f6a658586d3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "0ebb4459c0aa33069ac526b0f873aa3b59652b8df4c5dd5b37517be3f919d755"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f3e3eca93307864915cf94fdca26f3c523def9d150c708ea14e5413b4582cebb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "19b8bf6acc36cf989b84364facb9a1be1ed20b8a6ab6cc8de46d79fb0476b86d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "2107dd69a78637520a667b1a0f5fc38930c99dc403b74231e2e3b03ded39a8a2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "98985e9be3f2f4407cfa8fa3465ae7736f8b25fe05e3660739811006e8b62949"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "ad993e46db483f13b30a286e9867e93487b8527a5e398812af4e43c183ada78a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "5902587e68cd9991a4d36ab4ace750134ac390080feba6f66d4b79add5d73a76"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c2269d3a2ba48963598aeb95f6823b7fb5f3162927291b5bb008d3757324bec5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "9e561f6840a80c075a82bb6fde6f2a4ffc38527120c2456ea54c78ac7e43ea54"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "9788364157799fbe49406d7bf15da5f48c6d8f961d3add9ee65055e7cb8c3714"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c53b8ff0ed1a7060b073f42c90d0b0013733d5b62936ff344c6cdf95608bbdb3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e9d81a278ba810697bcc376a11284b120f7dded63c70f36befb20e36bb654b0b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b9df66dcb1a38a7ff740a96e9544e5227afb48dece1532d8081014ffd30cadc0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "6853f4713d91c26ea02003526a6eb97cbee99b20eaeca46923617d7c85928e09"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9156fb2cdaac768b85eaba6816f04d8d63bd3c26d6fe177dfd3a584bd1356a79"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "72c48351e3cfc696cec4722c9d40a9e8f0286abbcd864403e06f028849d6cc25"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "fa730e1a4065091c586b18e2670c1021b2c04f22f9ba98b0239c46ac4c127b8c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "49b4a4ee3664ba680f4fbe4e22d2b4e8d94d4da594de3ca6f1fb265bffc32b3b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "78f9af5156a5ba1ae8f2f5959999b1aa15bae9619de3de686d5db2386304cad5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7f62086ba686ef88fe1eca6fa2e103a07e2c39e5199b08fe32164abd688f7f65"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c4f605e68a66390c4140408fef8ac12d8d819f1b316dcd3d001edb94a71a03df"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "664394c4e7eccfea67c0249989fb082459a1fd90798981710f009fd6d041ed87"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7124c14abf5aa14de55815c5bdf034ac32c407bede1006958fe018dbe33ab11e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ccf1179f9528c219107197676bf1dd7cdf82b904bb8300e861bbdac22c3dc18f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "5c25c6fc481021489671411473aed482734cd195ee82b23297e5330915e382b3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ea357209db2850721f23eb7a4261f742379c749ccbca8760ba523617aa9b71a8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9b769c4a3c017c346e8e7413b04739e1075202fb87fdb3fc082a11de66800c6c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "232adc4e50fa025d5b7c0d3337001061ae61e10e26e38939d78999ee7e16382e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "390e1c65d462e111f159fa3971fa2335c49dea61bc01af48a1cb5a848bb689c5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "f450207116596bb6ab78956345e8558301104e66cfe3f877155933f350ce203e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "7b7978d2fd98f3f445921b4dcd653c7402e03932e4874a6b98652d4ecef33d00"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "42a79a0e8d4138ec1544d0890d6ab225714ecc90d87d50d8452ba345cdbf2929"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "e9f961da6bccf59fb3a65a198e5d55b5cb90b2aeb9bebb8e9da254b2dd7bfb22"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d09f01a6385f0181308015dcb793237ee3694dd51ec6f69c0cd34d13fd6ac4d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "aa802fd11edaaef6831ecc6f1c96ab00be33bae69017d38361988accd7da800b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4433ac80802db73d738c1d4c2ac9e1f48c02e4bd30be95ef095221a4f1f95e15"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d26e3209345bdd2ba251994adaf7b7e87aea01e1784147e2b937b00063909201"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f6e57378b2eb34a3318fdbe6cb083068e4dae122f0cdc0f1be8828eebfce4f83"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d34fcd37495f214ee667b968f5ed34b7cc25c34aecedf63649e6a06e8ff9363c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "0a10aad01bd504ce13c390efb2acf045629641085c88267359f86ce0c46ddee5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0a61b99e3eee765028d45e609f9e2740823289960a181a567ff4d0329f0e8f6d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "19fa5476939e28d82c4c3a24f4bcfa225f1d827fc0cb331d6d8d65ebad6f26ea"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "69d181c3b7e7382f355f087ac69b0ae3f375f94664a33c96fd3023711511b0c8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c7aefb3a156bf8388a14e91e347ee5c9e3aad08824acbc8147154843b12fad03"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "55b616361c3acc7d6752505377cc96e6edb03a1ce336ba702aa198f7b78f36ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "15e23ed1371918fe0e579b798eb167961f17b3cd3bdecd9ff3259c457663c4a2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "79471751f7a1246ad0492456487d537c9b8e1e083d635acc81ec4cce78fa4ac1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "5d93651d91cea53129da03dbe7a2fa56dd7da2c067bb568c36ae2370fe987b87"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "721de343f0d9325b2b8bf6cb1318687b317546c66ccbf0ca9d0eade93af59f20"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "2f609a09e153c708be204892cf9d53385d28a69a45ff42429f3cdfd89ccc2ec4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "7b5ec1fc9dcebc2a60737929991a764e6fcb4c64bbba8bca8c6f67cba9d1243e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "4db5552f13e09aac2d80456ed83e62b900e7a1c6be836418c94c708bb4eff88d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0e690eecb9b3071c6db0a07ed493bbd408250802637d520327da0d1d0a2c3f74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "b65633bdfd952212112166ffc4032c02140e52ac27ff5a7c5db9b15d063a6f1b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "9a3a52924361e5c5ee4c9490884c1065e56671d28a8dbde46c405e9b6f8e6b4f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "3cadac0b37bdee423dae91640911cd6d33d98e6003e98f5a6bd08053c115b190"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ae5ad8bd3aecf40609409396ac2ecbf0bec1194078933dd37b0972737b4c49c1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "26cea2fc835d0a9b0f824c9d43a542f5e25c578216477d2811237e05dc409380"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "5a16f30a8985196143e6ff673e26fdcdc6805a8a4ec8b9285111b119a37ee775"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "08d4f7a61eb4e6aef6ed30097932f23108c1b7d4a5b4a1951091fdac2155ffab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "9ab9ad948d79f5d969e039e359e440f5bed84a7f29ad25f52edb09346825d69e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "1d98fe1317c482a5ad910257939e1568de0779e481d30d7d9c11aef666cef77f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "4234d98bd6150a3ed2648efae3ac2f1cbf950cb5d7c7840be8099fe7743de082"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d9c6c871bbd457a09764d4a4c4842547e26cd9916882b6b5d8ae107904273a4b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f18969c7326a8ee7288a5756cb98ac6f919d99c083139be3785ece4d3edb25d8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "02ecb7a6604ee4be6327efa7f8fce256f0661fbb3cda04c2b518d750b44f5742"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "873c956a2af8f4ca711b8e698970ca32db61952a62064798e5a5bd4a2a15c5d1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "82d1025fd16fbbf99764b228a6af37020f563c37adf99da90a0b368fbc0490f3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "4c9b70c4c19568d78aedfd9381a08eb480e29ff1347e7dc0f838ed57590db3f4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "fd09d3facdd916ae5684ba5965f7630de576424dd3bd18c93afda5b46cee1919"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "0c557a38a9e609d2507eea81e7622aeab7552b7271aaad0d2b93f9fcee6f9e03"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6439dfd2593602614654108d7ce35c41a4aaa9b4354c9dcf5cdde759ac3e992f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "fbbf62403f7b06a299e82c2534dc3187467042dec4efd1790fff99fa22aee7b8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "1700c66208e684a020015905a9faa1e173c29c837628a9b79532050c7b616958"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "88d0ff3277e45e4afe50f6b28e8d929b25282973387f951eb579731b7470667a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d945286ffc2ed7c9df4e04226a312ef1a2619f14a800829d4d5ee49827ae8a07"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "cc0bd310523649da66fa1c317656f7deda85afcfbcd2dcb37e8d4f2e985944ec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "7889b45a913f3062b2d60c8a75df43a9d42a04652332b27e87e9bf9a06792fc9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "a51f69dfc7838752eaca3aefeb5f8fa5dcc7e604747187347a6a426d1e5c83fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "8d542718ec1a0ae0e80b8c5f1cc68def88afa72e755e612e3fb0a0cdc1ff9934"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "bcce49a3bc6493870041a73cddb9f516b57743d266833e21c6173c58280f2d0d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "ad8c1206e50176f5e05058cdd409a5dca69f8e9c3d5a03d4b63710016fb35a98"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "2c42637a3f86892102c69e60dd41735c9d36e407bef8868ef113251fbb82d78b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8f767b4269f19e3bd9bc4ff483beed7fbe2ac911a8b045699c1c96d5415ae937"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "c0e08f466e81ef04b7ac59c86be578fca3be7448c1baf412b594b55d9d817ee0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "8f03cd43b43388e2be4cdb9830f54f089c7e589fe7123b6528d87f112296f552"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "8603af87c8338be6845f970bec0c2cfc84ea141fa2eac78d4e27df59a8969046"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "189fef2e7aa94a7946604002404bd85f9ada68ba076dcc529d76dc924bde9e19"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "aee8c9e79b7605628f72c0ecd06e020097440c81733f44aff457c21119707606"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "de698bd8dc4a6db003f78bce31859f7836b3fd02a485e14affea831f3bf438e3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "c48b40d0958840e4be27afb397541cf62b3dc8d5fb3e1bf8400cdbe3715e0160"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "8d0e3fe2596e526286c753456701cfefe0a45e761e193403d4d4a0d38704b477"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "4390699497b06ce375529457c73ef948ba519fae436957362a3bdbe26e9e3721"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "5c1b337446a9956bc3def2e295c5899d0a56f60be806ea9fcbc5ecfab92d52ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "1426900dee641729e38375cb671968e6e753cf71639625ab8460b3c1a04c1580"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "a653b764d3982c42a92a227a7be4954ef9f391fc2207e7fa79f4eaa2735de4f1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f205a4ca66ee681858a70e12364686611682a821efde5d66095a857eee3edf16"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "747c033c51c92c3a977be600cfc69fd2139a90ab1bcf506d8c4f0600b34e575c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "04046c8fea73fead5189b0f2ecc9b24705f5553cee9668396df16fc4c8e48684"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "87d5051dca58717044e3196b8822b0d116216179585c0b235c18e30713585efb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "8680e8ffecd795b21833f2aa6d471bae4328c0b6095fcefbf5463ee87daa5a91"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "bde0c2d3224560f8ff4995d92bf0c25c59a3e14e19aafbf591cbe31d08f2149e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "a4e193535f3ea7c5f523d075e8e576d27d952bae0be8a9a642a08c3983967295"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "6d8581bb2c5e7d9660861712ba5777548845fe2b871184a19bb09f8b73b91548"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "04670477b74bfbd82b7612edf7e616731e4a038b0190f73410fe9880f2d3f54d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e057c51f3671af43ca5461efa8621a8da3a14c2bba47cc4a0b6d1e1b0141abf8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "690252b20eb84dd683894ca98a02f098213d008da9a3b348b3fc89158dea224f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "c367e0614e95494e290b4e65756428612681e159a78eb33e89ba8c9927301f58"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "5e65e1ad3c3e235a311611f9aa9d4cfc8d67cfe7b0af556c62a6f9d6ee5c2c80"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "c7f3660fd13f256ab6fc2d3691750afea79a6b85daae6fcf0e3a947144365847"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "058a5902303b0586ffbe67340f524f5d21a8b6e2f3b5012fa4b7a0c35905eb16"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "8fcc9cf87e94db62aea543576eabbb9f0d0bfabd3a77850988f0f92bd1411158"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "cf0bc57d5bfc694c536c6036f86ae302640c12413e31920e849cef7ed408a7df"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "f509e1062181d6f9f5645a22bd6c557702f90634bde9564b9aade4e9851b561b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "4677eed91ebbdb07a35c9b711c255e91d77ad39ea5676fe023221d972592b5ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "889717280a7321b2b9699217243bb645f44f29de3c8f3940a6d8e648123bee95"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "5551deabb13738b13a496f83af8759e94148129034675846ae39b90158f78058"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b097efe4ff82a37cf0812ff63f8795a1e9511485398d052a687ce5cd1cfbd64b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "23550f2373f5b46dcbcc865aecdbc4e2c550155457e3b32ae6a72033617de523"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "99d3d78a733f20d90b81e949a17b5220d7921eaa67ab1b3f2feca9af617fce01"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "22fe5ae534e62a16aa69f815050613d91ac0d29fd5d210518dccc37143e9c229"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f2533f8859f308d757ebb04803f1331318269fe0bd506de05778e22285081ec1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "272d772ce9864dc9202e94f3bd6faa48bb6ff00efbc82fccf86ebb31ebfaefc3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "899e3b4ec755d1c6fc75225a54a9bdcabd2785be6fead8f6d1eed0cb4fd52f0d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "a4fd1d166a047064cc08ddfb9a2d0b817702e2af6f885bc8a3c041a10484f77a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "b24c37c0207912ec19f8a560bf77d32afae649aedc4e3131a9ce9546f0513d39"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "76d63725bca3bdd617142dab1ce488773439c92b9232cf56edb51b89f123260c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "f658476c724f3e35f1a6b747783efa5b1c571bb28168772c75fb6d5b41570aaf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "9f0dd41b6573612a6a3d4cc073f3007b279e6c6d0cbd3f18ac7d7bb3b4f886ef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b911fde19db3e3058d11f04be69cb3b3848a4e8249f60bd082efd6100ec519ef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f26405a8cc44daeb0bee2732f1c7331da901861fdfe2f5477947a35535c6f7f8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e559b4a4d4285f479620c201cfe5dea95ca5d512273aa061e9dfc32747f412e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "0c1cf5f61386301cd2f91e0306ad8063cf69e98c8367b753de8740cbcece15df"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "58643a12a65427903334efd9049dda86330eb6d1d0c258019cbf099715d71f0f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "5472c3b3c1f2d7a617e553ac44761e66663081ad9c932df8ae6de58fb0aa047d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "0d400ce85b9cafa7e7a390164bd14b4796a9cc8dcd671e54084aeade84871577"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "17d79fa3169c4fe69f3b93dfa918c78f06bb2af72da66a906a51604333afeda8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "90a878d2f6fd6d571d1bfa1f0a2274ef186c1dd5c8e1695558f9e7558bfb1865"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "34e472885991f599cb679d69976278e28cefa318819a9fd05291965e8b8f1818"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "a9c2b1b11de0a1d1d977782b2577fb3376863596d8567fe137955fd128c47606"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ba08dfd0cc3096283d6c715953d6e9569d9b0c4d9003d4d9e841c972ad17b8a7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "cd035aaa9feaa448cf8fd8afd5941f453edaca9a77483049e3800ede56eef325"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "8be6e50de0fe1386968015f5d287b5edebf5d71c63bdfb8a54cfdcd39b3b7869"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "5393436f9e47d06ea70f018469d11921834cd8f1ee339975e754f276dda4b86f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f764e060e4eaa6c4e035506e5faf71e5275fdd155479189309368c607ff016b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f72068e8070cce8901dc8ca9c0d910da7cc101fde58dc475186032377860d5ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e50ea8d3459e1e3a2fadbf0fa4a5f04ae2d026afcc5631406c108b3157e7a552"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "bfbdb6242e09094b084a6ed32b8803f4bf35fde76a6dac0775e5c92592874c4b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "817ad399c999fb1d6953dc70445dd93a49f235765be94d3401d78f671250080f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "22110e798d7ddd9dd1284b3270f105e1b0302418dd2e29c14f2e13f21d577d3c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "cb7f876cba5d3d99576045965cbcb7d343a2c863a2e8052c72ba1ae642ca85fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "1cb358901dc1fd88e1e4786b18020665d4c362d8391ce21dd8a4a4179c58852e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "64d1a101c7560de0f3cca42d004a9254607e73dd4c8cacd2b8f661034f5d699c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "9fc39608ed3156165e692d6a428a5a1bd4b2a00853784db848f1be496dbfd794"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "3966dd780b5fb756365e81e162ad72c7a0adcda0f7532e0db92b8d26ec88ddd8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ecc9a3d47581df7422310beacebe0fbf555950143312af67c12465a504291937"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a5654d6226c3ac8a6ffa5f788206fb7d5c86e8389ecc0282013b963611a088c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "382cef2a5e74b63bd6f03106319278a770057ffc72151e8299ba58fcd23bca40"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "8705432c8df012f562a8eca85b7537dcb50eacf25db064475271b38d3eb4feee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "adcabbcbfb7bd32e2dd2305ca4c50a7d6538fb55f88ea74673bcb55010ae24e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "dfc0c1c94bb81e62e02556dd759da1d67d409c3f8dfbf43acdebf2c9625d7005"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "64885f836bdba500ce51a8d67321942059ac39f2417a8b09786ffaaf27deb9ab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6684b91128d3c7f4a2bda539922430c40aaf70307ae630f1e3924df59253b550"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "8efad987a63c84da9a969ad48729eaf95fb97c9dfb8b384ffc786882b3cba3d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "2a4dda750b523fa94296fcbb9d65ea764db99b7fa348d1cdedd036fb1c68d2bb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "feee43dd971154f097c7020f9150bb1c2b2bddf325642f45c06c02284f65a688"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "fdfbbd24c037dc82a7bb9a19daa654f2de01fadeeba40c7fafe17cedc046a030"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "1872b889070179be07bcb5d84112a7f808ee5011bee0b2e028c9b28de41655b7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "778a113cb1c96c75020eaba1fb1bd931a12b36bc0330365e6813c2cb0e020d1c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "0a05180154c09a05481c4171d67a859f696c469dc7b12b4255e1054b14708a23"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "6d1d93cad1f2edc0bc3304c12b08d943103a144fad8fd16e384e5679611664cb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "21fe10615daf64fd9307e02c01c7b4e0a7a61ff9728f19f0466aff08b25dd049"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f4caf540c2951b4c46b696abdb1b1ae222a10f8953a7d9f580ac37462db29aec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "4aa38024dec0421ac328c1c7244070c9e743c3933f70b81817cac3c381778ad5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "7a7115dc00d3a2d23ab3814e6eb175a85f4047d7a7188c3156e69da63f6f0153"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "db671b2842efafc472e32211c9d3cba847cfce739363c912b2958c99fe06fe1d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "63c4da849f9caac0ee2962f26e88cad025304757d2bc6355d623fd5fa606e996"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "51d5856c2326bf8ec3d395c823e799a2ac9e193f8998f3b85b5bf4942d6c0674"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "05fc1a0750b06e63667e29f5ea64ca96f9ee64d63a347ac6cab4d1d086cadf50"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "a27c3304aeb3349c58a2e17ab4a94b9249a71e80236c2c48f8b8cdb9a5ae1cee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2ed8144f5f5b3eb2623382dc0827ab8c9abc387e9a670171528abb5ebb4f3106"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "40157995cb65dc1c99267951d30ea1a0ef1b0bdad57425e53591588248ee2f91"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e94f87eab3b84d297145feff238293fe144f3ba8b9ffe3ac3d7afce5b41fe5fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "4be7be80bb50ef7e51a7c52543ab91f5e4b36db167f4cad733e9f182a420894b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "4400a6fb2e33931e7da06f3d79cafa5c0fc8f7c4ff5ec8eb8ad9793645208f2c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "1229ac5a570a6a492ffd9e640a46170033c71e9182c8d043c08e31d9497e0081"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "5b1edd3fb53f10dba4f93abbc9a9b9764c554366c2b2d5f90816a942591d5a10"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "e8c95e11531128e2750fcfb76e477cb43f1d9edc9573e15b422fcc80c28e3c5a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "47d88ba5e73686cc572ef327de27fd0d280014c5399fbc2a40a54461df0972b0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "0f6159f635af5c9fd68c9f2247d38f6c60d587a3ed0e71ca379eed8c29ba4153"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "973f6f76f8bbfc2e05528d5c5d4376f237940d42b8b01d36e98d4990ba27ca19"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "0031fa23ff60f3cd9b807a600b69c7866210d8ad6de10273f05acacecf49e5bb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d2af0aea45e5941e22bfeb8ca6326a23e2d324ecb7cd209474775e870bbfbda2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "dcd13078fa06f4750234483cfffbb22874afb300bdf5f923eedde7ef43642750"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e3c124470479f01163b22baa313fe77b9e197e9af2ddc3da4c92a11eaea87cb9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "5db1cc748a94631ce3c6cc91b3263a4f9ae2ec8dd5c86b25a45f33cd87dc0382"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0bccb9b2b1f8bde4e833018095aff3aa843d85f0d235d0f99327d2a900e6e387"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "27cee50774e3342cc74a4cdd88f5dbc46982d6f39ed3c606ec5b3bc39b6ef7c4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "adf6d20b7fe4c6699787e6c32bd47fccd4b354a7859fa466098c6ebad9a1e732"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "d6e288803b27565321444203be58ca17e0cfef3f4ac103bfcf847a1fc430152f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "676576b8eeeefea775c40c9ea9ec931182cdc1102480bfb8a0a8a5eb012fcafc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "ab11420453ce4fa0f4fa7ea467f4c453c3a82fe37d623266499d282dc8117177"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "25e37bd883c03f381fbfce131a36ce30173a8ba20436be5709fa0b21659bfb94"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e2fdd2b2608a6af2b2e8688a665bc3d6a5efb0f8ef938edb6832a5d12262b4eb"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "8036b685fc06b5ab7e7bb03903965b16b0315c331a22cc2b838c6a6956633ff4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "e8c698ea358cbca7be20d201089a698a4cea3d60290a64090b7f6fa2186580e2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "24a10118b093543e561bba1a401cd50e9ab5dc37aaad46354a205db0023b509e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "3a1d44ad4b413ea200bc2f4ceb2b5a8a75406832886faed2ada00f4b4d224756"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d7b121c70b60934803f616177f7e7e0de52d9d6d4f1d063b6089785355b04362"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "9a3e91ba41f4b63f2224e6e4d7096894df346937fe4ae96a3223076db8f148c9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "258ff537161135caea5055263271b4846214a5365bfe9d02f6d1d5481141ea26"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "26291de7b976c7efeaa321288a3bde639b69385c605eef3dde3d09074ef58fbc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "36900f2b5f11e3caf0960dff3f40d30ad421d24f2e973a115c0441c82990e268"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "c3af0cebec99081081e4d4bfcb5b97ce1857380b0f62d45209d8440d41bc1133"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e6612d47d8fad5157ae381805c989b93c2a386483c8d812b6dd46c274ea265a7"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ab8ad0d251b13d7946a558dc3aef46de77cc5bca1f8879dfb7013982455084a0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "200d17906c8d8161755b35f8118bdbf23d2855878e0ffa25643885df2b7aa6b3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3ee4f4e43ecdea5db76d4137e3d28090aa53cbadb1aacd56220f89ef6d91fbe6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c86b566e341b5a9bbd68ab3af5caf710ad072d32501c1b4a25d53c089b22aadd"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "cbdb312d4200cc65619c8d0daf2bc8a21176b730943065dca0a4d9e48f6b9e20"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "809cc03facb168ebdd2b76319426f2e97cf33fe28cf5e1ed3c809213c618a2a2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "e86dd6b7217db3dcd7ecdab180055fc2a09bdd2035a46cad134043515a6aef1e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "198d9070032d8b8692a1aea3ac139f4170440291813a47d90f6889e733fb01fa"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "dc89fb0579dda0f75632150c2f3fe5b338a6795b02e2fa9e576b7d3e5fe8508e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "f56e5f419377e50d97fa51deab69151a2070219f3dde04165327b62816179116"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "4d6acd9dee3a0f5b36f492ed3cbfc3a5e165210c88a83618b644bcde805fcd4c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "ee84ad0bce8d8d3b651ed69ec0baac62c28408ca50eb8f4abfb532a91cdb4238"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ea7eea0cacd0501c79f96acc8449f19d94221d55aff8744ba7897a64831a3dbc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "c158779ba1cf87b974ed0d603bb38c21ec5f026d4831ccac300ac18715d1071a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "57d9d89eb025b534df95f9c0584640fcea2445de028e57e481962a42150ff847"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "bf67bdba1fec11c992517023674ba77f2d5ebb9d58526fa48f310199848a7966"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "47998424f3b6029cc031a9b1057650d2472f041ebf039832d32b8e0f330bb58a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "18d8ea4991f1b7559b38e3bf95c9d5ff4e9f3ec93a71b38d98331d2ed2a09779"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "39c46d2da253049492002cefbb6b012ef6b28adee3962c2628d0ad2eb0428f11"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "465d34bb56e4c4b21aa21a916b821be58e469882c83cb2f3f9c5da396dbd25f3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "1fa5fb7cff9182e69fd19a4daabd1c001618bdaf946c8704bbc782ef96979cc6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d66b25d69f489ce79bc98ec8238142a60da6fd80f344d1ff2d0665e97611c694"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "7867a28c7054bc23e69de49ae1d19b7a301e9ccea8099b56870eca2773847201"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "ed64d0bf4e3aff420474942de5b27c2a2519a7dd32c9e0365096cd2c36a86c04"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "87c408a921b21e6edb8ca0895d9f1a9a6bef2c6e2c1d866650be2c7687e95fb3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "ab7434d370c5d35520f5271c77f6a8ac0759dd1326fa426a1dfa0e3cdf74bb6b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9e71cb8f36da3e43a49b5e38ea5ef7db6d90e34eeb4caa628ea31285d1acd58a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "5008377107506135b4aaaa4f319defb9b1b83205f3baef9594af1ba077ed3870"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "bb3f477ccd0a5d723fc4485f5574a75f320324728abd473b10c39bdc21e2c160"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0d4cdefda619c9878dce541cc358b74b601ed9a4713627bdc46f7b6e1a9b7409"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "85668a5f800ad49a3bbe510c4198e6421034d834f218b0bf657c80102b60b131"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "5238214ddbc376d85870c34246a7e60a995ddc162a3d41ce278bd234839e2582"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "8a806edecf71ac4274f5df522b396d848338501f5040c2071471b28d4ed64db8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "5ca765d33a96a99a3ccb31a8ae49c3910b30bcf4a85ceca78a4dacae8e33c711"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b9a75220816af40dbaf9b006e73cc2a76cd6aa09680e8b1fa77644fd161f49d4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "cb93f25ba31c96e5c88ee0d44315945ed04672389e070cf3843ca8045369d4e6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "2996241b435ef78c381a112bc7791079e60d1e3dd681a47693cc5c623fa38edf"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "ccfae8d4bad43914d6691fc8fccb082d732162618c544c90c86c8625f5cd3969"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "7e323664aeddd78596ae343e9c326f6145009885660e273a7e6ac182c957a7e5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "7eef7ee4a623650475876f29a769bc1dfbedc4a4fc166bd4b8d98c3eee03692b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ead569ec2bc6363de9b2ec8e9e1a206f10b763830c27baf0b65ef695cf0ff20d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "7a15f3ac8d9857070d83107317f1774ba3171150b026bbf593802b7b5e7cf46b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "23d53fd666d731c09af8e4f7009480b5721fed767df206224c15429f219238c9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "690d41858d98fe011f34ed09c07d781bbd945b311d85a7d3c88cf246d75de012"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "451ff6d4b9dace72392f4cc92b9209b00040f68921d1403f17a73d71d22a8a33"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "7cc1d2f61e03573d382ef2da32648ca45ae094aa9f52d31a39171618bd90f893"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "ed42a9ff16d2f68e25db72158e199f7dbd8c012578ec5674ef840aa76592abdc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e10773378b845f8aa8f17b818d5bab1dbac55f7a34325a1de7ab877cc4c5463c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4b4d75ac2f783e8c5ce5d663c5dfbf1ef389593e9455e7b6d7c04617a48b429b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "20cb3e0a40f6529e0c7b8f0dc3095d9418f92c1215e8180ab50c0225ae9b5cac"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "33cd85c5438ba8ca725c5349f1f229bf1d94cba5f4adcdb940b8de27f1afd1e8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "ce20fcfead38cbc2b33d68b59a955a332b305277026d314f64b6b635eb96d9d9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d45ea1f5e7eedd4eeeb9f46aa107d69619929af2002f0f563364c0a014ec4dd6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "683e827bed139f682b03e6ea39b0c901e67a1ba450354f2b21f4ee76ffa862bc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "ac004174b0ba49753688c9dde1357abef34307aed50e16bc282a7e1e29b13842"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "89f4a9c2308eb536036b97dd194161e6c245ffe4ffe36ff0629d073f4897b07c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "45783000a0e44d048a963a0e70be7e6f1ec8ef8ef84e42575270b3d5cbe2dabe"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "7c1e85437d0f7bf683e602a51d1ec6134280527d88b8c406bbd77a23a52d7241"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "36e25330e93ab8ebdfdc50df8219feb97faf4614b9a34d7634f7c16632699f13"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "3e37a5f3d033234bc54abbdbbcc97e2d18eece9ce9d6f2b6b87528c33c5df134"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "033af48bb0b830b686de95cfe67c38798fe30fcaaa52789f5d5a8931ab61e4bb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "c18400a6a174fe94bf09e514641e54c170c9fcabb26774ce278fb5c4713799ed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "812fba2755d3c75f67c3249ea5e063f704d7ad702ab0c9598feb942ffff19054"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "d4fe8535dac9d292846fc89b239de1a61188f114b8aea420d7e4fb715533bc19"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "53e26c129a1614e9a8dc2b3523cbd1aeef8d10c83f793750d0554e7a8d36a723"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "4095ab9fa5bd660be82dd74b479a5834d8b084cfc60355c4c54d325ceeaa6982"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "838bf4685abd892484e122cf7f83035c20c869d76c1bd6edc356eeac66136d5f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "8eac593528a56b19eb703cfbe661cf33bb8e45242f158075f035165f53213a29"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "40ddd5e33bfa5f592fea7c8b92ddd7533ce9f546e8753e6b738160cd8f393454"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "7817fd2deb6863586a1c15a81a15ff908a76665e6547c2627330524ace21cce3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "8bdce5cdcb54211b1db0a2aa275854c4cd1565c48fb56667bab9002c1c3694a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 196344, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "a4d8507a301f236447124ff17196bb72fbec69fbac19b99519fb8a9bcd5f0839"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "f1319d8bb164870df8af7912330d14a79102f00ac4e906d6eabc2d2a323cd465"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "12159597f77fb6de71ed9b30f7267baeba45a14265ddca41e5252b6ab2596fa0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 127296, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "a6e1d1b661bb3b06f2c72ea3ff2d0c4048e2d34b0fb1a3c40feb2d285c599d41"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 127120, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "48273c798a616e8046e5054299dbefc505fa3a63bf21905a307949417adc565e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 169232, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "34a57ea870806f51f8aa35888e4834b127bdc636c9ffc0567527ba108a7390eb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "7bb620514d1bc85f702d8af966e39dcc76f0345e1ccca80951180e86c34198d3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163744, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "ae08cd8fb218b3e3db6388623be7ea1b2be9fcb6ed5d9f791f00f0a771fde0bb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 162544, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "e0c3808c8419b86b10ac0f04801879825346ba3babd0f1bbbee2bb47bc122f69"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b336208f826cc321c45caa0964db9f2b84314e9478d4f062724920357cdba9e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "6c63b437c31caf22c54cba8541dafdbec8c4f68deb900e4acb1a124e9e0efa8d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "9c9f4253391b294fe4eda5c3a462edd0f1d18623d70299c60ffb663e629daa1f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "3c05f802b4e6f2a51da47863606e06fbb17285baa6f03f28f974b1ae82d6367f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "27ed6b6160582cc6350c72ad168925bfbda806e8106944c700b633d31cc0aa1f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "8356e2e68351193ccab4abbf3eab67888762fcf9d99c3842bd2c74c68967d07a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3f87c2d33895832488a760e4831791125db534ebbf99a6490206556b7058d91e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "05c5f5c0d8a6c7cb1e370064ac9727ff85513882bd2eebd3f57e9d0c0f06ffd0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "831d4492b00b149f200f2b7ea308b1fdcdf5d766aec441d02c0f823cb3e02ec8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "b7390cc568f611353f8ad3e82537a4a0ef55c7b61e74a2e5c5863e6a368bfa38"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "c150b71c450e151de865eb4af92af29281292d0e7e513248b8a3497553fb3c63"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "17579364874292e25613b7cf516c3061c66946c8acd73eedad3639b44f9f589c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213608, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "69959655e2eb71a499ab86e86224c72c1823356fe051d657492726c7ccf79bee"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 207096, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "c06b5cfbdb901efa13d5ade6b10d94b247b7c1e22dceefb66954d9bf98191188"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "1220d17e0b6f62104f3e129db9566e7c6b8a181d3dfc70c2c5bec11fc3eef08b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "61414bc99949c54ac65c44eb8d07585abceca46fd0dfe889a19c16560db02016"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 224656, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "129f73909317c2e6e48a7e12afda06fa005307b70fda3eea48f1d6064791a7b4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 224480, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1edfc85984540e076efe8d93801f240bb5e62f942929d1e56935237ad6d8c503"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "e81b5434952b796eab41a6960c1beb356a110aacc5bedea93a41b9e46e049d42"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 180320, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "4320f20ed686f55e0a54d7c899ceeb68bd88aa9b9b3e22c2c61faee5b59b1abd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 175008, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "c83d98a441a36d4fc9ba1a3b0992861d5d4219657471b730e00af974bcfdd6f7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 173808, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "3d15eee90bcaffb0dda972d13450559bb4d461ef6f5b97d0022f194326b619f5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "1340e016537a3d4898b22144f770d406ac4c4fe1b8d2a2eeef786e32d2b80e13"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "d4e40556da736471152c1ec40c990c04b268166dcae8f5a41a5cbcb670721d5c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "a1086c63ae07d8a459800d2e12c7cee78ed542fd692e5a69555f5fcf44700d97"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "b27dad8a800c5859cc98e03e31ac5a3819d7064987ea8c7e888ad53a907e8925"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "908c7897a51effaea2fed2bae7e908f23f591001f3fa47bee5eef18007779d36"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "48ec71ba7c90ccbe3d683792f5857feeb30b113df3c354c80d4313d46cbde715"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "5f9a38d979c9964df3086f5069dee1be46ecdce615cde8ddd96b6ae47f1483ec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d4b718da371afa2a85defc4d0b88f515fb3ce2a4eced9cf781aef48ca57587a5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "c762fa832daa6073e8918c3673434b1aacadcb7a2b145f90a5dabccac90715a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "c967e9599911193b165202dc3c98fa9ec9079b4424ca8d8600267682afb0df8a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "4e000cf02b100327239828b437973811d99bd5dd1b55f0cde536dde3f1bf8a63"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "15a99dafc20128e684b131c0d9c01109aabeb3ad0673a5c6d5aebe07eea8658d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 158840, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "3343ad0b112de18c6f0f0fb14a8fa64abd4944df9453c1b61ae1de4b895e7bb7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 155384, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "e0392d60d79244967afa62674cf15fe9a9155087a61dcd3bd69c9a3678298948"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "29e7cb55024c937a6da8abd474ad07d846602d592e9c5a9e34e31a000809a0d9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "087bdff72683db9133185910541ac298d53e20549dbb2aba598dc4443034625b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 64832, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "143e751da9f9b75cc42c045162bb725edd8798658e2be17366e31e5443f3bbcb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 64656, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "2fe8d6a700e454cb420fc03e2ba72b2ebbfc2d800dc8e8c0ba2dc393b1ee8178"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 125216, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "923fea6a0fbc4f329db0bffca376bbf6255bc23596d5fc54eeb91fb08e477979"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 124016, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "1c18c96948b5c7cd9db08c065e72621bee2a4461741b52b0de4ce41fabf5b737"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 121248, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "d10cd5a6bbcb4488384df6772b4aae8a94855971ee094e687000c0f99c907a69"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E2M1, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm103aKernel_QE4m3KvE2m1OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 120560, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "b2f1905ae673aa278c0ae45020932c270345d9a9d941214558e8df8f870cb338"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164256, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "2686bc182fa60a62a779fe19b61bd3e0b7b77c7de6571fb8689ef788d6cdc53e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164080, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "3dca343c296f121d16d022af366885ecde1c184dd14b2e4996d1041ead9420ad"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "1ae619cc7b5889c9a217a666213b539e824b934628475e5fa08f6cb0bf516780"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "287a3e03c8ba577e7ce7819dbbd84ae944f08b35419f9ba1a1aaf5db37ee019a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164256, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "7b7e4fa42c4cba498bb6fd8a1251e9c0eaac8515909ab1222c24ffca274872e5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164080, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "03e950b1f9fef63ba34f815f958041dc0440bd2dda84e06959bf53340aeb780e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d764bb668b2033932584baddd4b7bfbb726ed0d8e2c012b1b41421374b75364d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "8d6a2659b7efaba40f1bd19cd7384ee5770de52e5d6e3f5f422d048f33fdd80f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164256, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "0e3b6a35eb64c53b2ec4a360815b7e030269f7a110568e5db20255ceea1a71b1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164080, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "ee27c9b99077fa93a6d4468de7930cf45d39a80f5b3bef12881b42ece428d7a9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "1c9fa633dc56c50124a91e0102b7b262d55e4318b19f609ee68079a3f951065d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "2dfcf9fdea1ecc0108b3fb1d3522b1aef6927ae4d69ba91b7b71e9dd07038880"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165120, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "77fe6d330f3221eeadb7da1afe79e831e40685cfcdd98c5c34e4669a045f93cb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164944, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "84a94c46a5a3fc025f94ba0970f23c06affdfb5162f5504fee40e4a80ed22916"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165136, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e30e22051f67548ed5f8099ebadb02f290fb5f1d51140cf3cff160d058c739de"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164960, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d3f0cd17f11d3dc4515847e663d56088d64d6af97ba4583af93e3cea37016017"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165120, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "80e2b6a8236d727ad2d009af88101f45b2c4780d84d544ba021cf3810c6671fe"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164944, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "94240c99c67a1140a42a1fe4a995ba75fb2ea1e75c895a7edf78db1502a2534d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165136, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "91e2e5ef54775dd7eb4b1e59d19e67ae9e14221690267db136276fae687f3ec7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164960, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "96435d347905436e91ec223934273862bc99a56f07f450d2d53a78bc413c5524"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165120, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "0c34a37e2e4213527014f8fa706fc430f04a2125d7e3414f77f12f79bd9d25c8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164944, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "111ba508c040b9b8733dd6d023124b0de43d03851c0eb828f7eb1bfac0b44156"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165136, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "af97d0d336b186daf48876fbdb598bb8e0f07dc0307bfacca00d04fe21385165"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164960, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "04ff6745d1bc49d25a939317ddf5e2b50bf8e629b014dc02baab58a7a7082a97"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 164256, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "6b18c38751526d1e61f66041587267f28754db2bc9b929ce4091bc092d82d8ea"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 164080, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "933ecb68560b49afdb99ef5657bfa76ca32f9c9150552d458740a74f5fe9f363"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "767d5ab05a6d303eba31099941b412de5cee0d7dbd364527271d87204812a08c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "1574e55804f82b750485f9411a70147bf8c39f5564bdab36f1cf268b4531bf38"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 164256, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "462dc24b41d586afe82260de4859483f51c15be56a17de037eec4c64f985905b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 164080, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "0f5374edb2c630c77ff4b7cf0b54afaf846eefdbb936e95b9383b52b5df5fd0f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "1e067a8f251a136a496e1f7820d7d2c8e5ad8df6ffa6ca4c27b899d0e8367d83"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "47128349e008885c8dfdadfcd32f7c5d27ade6356d6b3e72f148ff4e1a823342"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a511caea4951ca0ddd05765cb09fd064ee23ceeb6e05c7bdc694854cded8246d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "8682dc021ddca738a0c048c10d1b90111b92dc7355a79df7dc3a304ae1a22f38"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "2ddf0db5f19052341626c44e883157d5538635d4bf6de3c26f949ff4bcfba30e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2bb6b7b9216ee625c1014572291a3e451c012999a43e510189bf24b8d873a4fb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "05e1821b70b79a235a6288cffd45d8740abc5c76f53eb6cf6bba5503b54e2283"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e392b713a989b979ecf0e1564f8c09e64ab6b5def52379e8e0b61253a1f34196"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "de659078cf0bed5e1a9f2997435c128c93a1282a15d91d25cdac5f475265c97a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "126890b11756625f42ada6ea500660c8a328fbc7e8983856bc029cc9824724c1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "8c5fac660431918a1de298b6fd8cb5fe418f7c8330401af9ae004d9a5d0096bd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "0d3c6911d18a534aa28a2e2f93d8b8430b68e27a0393dd2b26087fadc9664d7c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "9d93df0f2a0cb9b1d41c8d7be4aa426e29bb9ce3c9e576f60cd49ff7ad31fe21"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "b7ee67a5e1488ef40b39632044c5078a2ab09150460c4e26cc5a0829ec2ecdc3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "7ac22aca195307c98bc7de17407e6d71102fb89b5d27f48ab9c08be02dd83e8e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c3d36797ac0ecb6dfb49164d166988314f6ce6eaf69e7d3c3800d2c9c747c322"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4f3ba3c039a56bc0a241f37b4e0a3817b432314ea9fc0e4db2dccfe1443fb7cc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d7dcdfc683598bad795d1f5bc6fdb7845dcae4bea697906c8473a6c2a9604033"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "8c4c00b9563216c156226f92903757bd6cb81fc3ebfe6729e975dd3605d366fc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "77f13958e979193f04755a374f7516e4ab8240959ed61b503c5ef66f6d5b52d4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "e0319eef4f3fdb4f278861f359bbe391a85706baf9e6425468d9d0ba7fa21c30"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "aedfbf499d69c764d872928567e24a205de21d74276bd5414a313fbf8d16088c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "555a9dccd546c9fe9161731623f4669bb679361ab93733296cfc94f0ea824b8a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "a25612c962fb8bde333280852f783f5aef5c9ff638464c90e8915772bd2a960c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "dbe0422bc15bca95ab5ec8d4228badd291f68cd799e5296f49077830ecf084ff"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "78412eb1ba4d7df90de0161c4e6c0ee5363817125176816d6ad6f31b715c5790"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "2404d44847d998a0450bf2027a3a6b09134b25273f4ed0c479316b58cc73fd0a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "81fde828fcd0c08857257bbb18b38add682d4822e4addc2990df086b78a4b3d8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "a9d0d2dd0e9c49d1bfaaba382a53ca13b633b7f7ada7ad29036a70cf9cf7e57e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d919d540e282d50147c5a61a3567bb55a4488310ebd111259eff927b8da92249"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ae014999a6318af2ccf2d0e265254517239e21d7a55e490ad90f7620ddb01304"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c7fc911ce79a7bc4eef6e4f0e1d973b8757f642df5becabdf8c24e2c6af5bf7e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "486d8ebdac6a2f22591a01f987e78d0f813794d19c034667ea0838f70f48683e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "23dbbf12f5f38bae5b015ecb526565c5a5fd3f7f66565e18187cf3f20b0a7e98"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "eef67b7d8e41993d242172c577b5e600b6d1eef2896d2e06b241d9328550c23c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "edb1e5feee5ad60f98dd60d8691f367677791edfaf3f4f57287d45c4b6ce98ab"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6f3d581e21129530e893849e76274716b63ce14b842a8203e27266840f1b07f0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "924a1d57d2243bcfce1fa1afe0b2bb0a2f2add03b9d82a838d8bdef20e7472da"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "01db39754868ff6c5fec15882ef620a1a24d53305a2dbee61823b355dc72af0b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "726ace10200ecaa98e9e76230dc5ffc243afd132e1ec7191ad4883c913e8c891"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "3a406282988ce9e6371f859c2c94a205c84b31b76a2ecc7ce9e0a021047af666"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "66b813b27b3ede07a0a2ce2a97ded983a1fc85cde6bb51edf7d2bd4623a1e6f7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "33f0adfb94c155257a8d75fd5002e0a78941e800473a74a9864d917c95ef5e6b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6d0976fc663cd96f4791ee5cd61ebfbc673e3f2be8a04fef537f39448714974f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "8fc98d7ca2e0a35db717bd838bc44c84138bc09a5fee53edda152e8507177716"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "13943f2f9760b54b66aa0151ad94eb3d886927706b10ab759dc3e3ae5de43edc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "46be44420337646612d3985749e1ac5a2a4efea84ff550199c412cfa935a31b8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "df176d91b7bc42c4613e1bae2184b4822461899aec0776925703804ed666d6b0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "30dbaea8fbd381a1327464057168096ff698ded05a2987d14b829742ca9053eb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "6140cc457f11d1115fcce165e9eecc6bf44fa686dd6a5d887fe4b9c0a9159671"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "4a93edcc151110398f88970382542d7c455689fef3f2e2b7375a1c583db7bc0e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c57fb7997fc313b1edc50f9f827d9a3dd3cef39e78832bb9280eb7e6b58fd89f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "19444773d3695ac40ff79d203b8dd7212de19ef2117a4952f3069b0c542fac5b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1d3ad768d12749ed96804a49b5de62a7936ce2569640b86b25f1e5835c790393"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "211a9cf31eb253a47f56d69e8eb889584e3642b93bbd6c9a39e10ccd8ad604ae"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "ee811bf47b46eb9a1397a5384d5f206166acb6bb48796b16c89fc348036aeffc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "4762ac68ca98bd5deb2c0fb98516cc83a19490c02e39ef406b8b04381b974caf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "bedcbdfb41c6e5479bc76c10f6256804a0e71f06c9e27ea505d9eebdf5b7006d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197024, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d22390da63b65bca4d5b1d4f219df5dfa376b7c0778a0eebb16674f21f78a7e5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196848, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "fae7ba6d55ee59de28a3ad1e200e2402d482cd222ddc1bffbc0a438e69d61881"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197040, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "22e0c1e533697c7c660d9a45b7b70ec56f4d6cb450bd4e8632730c09ba80b2fc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196864, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f98ad02274e5ad479cb815ac5a2ab5e75a34d0216f8ee2a59ce7c28d187d41e7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197024, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "635e3f8c4ebf891d18dc1bb602149233149bcb4b970f2d45bb3a85a64d238fae"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196848, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "8336aa6405d2884035dffc86b96c020dc9e01bda583532d45c103edb7552d936"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197040, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "2d51c9f5309e4b30ebb37ace3284eab36ff8d89cbf1e707d68cf8457acdfef52"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196864, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "e50843a1379683e7a3cb09e23b8d186073b7db5748dac001665fb346c60dfe4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "67665629792efe14b7cf9c014d3e1d347b68732443c763941a3c7440162f7e21"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e84dfb5ef203f3e8a6e988f0e15969bcb4dc3ddddcbe85486d77c52705891899"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "aa23ad34239ada380adcff97ecffe6bc17cdd3065efa7c2551460e71a1c6a3e0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a74752a9445e706b5925fbd67c85d0f99acee27c69f6db5c780702db93f14517"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "21fc9013317ec61c6d6f77fa65d11ea3e9c7f09fe94553ae6ee99363981f69e5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "1ed77c5ab2ced22db497314f611edbf462c2123a89789f8a2d16201bbb93b0e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "24c37586b802465cdb8d00d7aa21db67f64fda1e7ce6b4bb07868026494b0a56"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "296eb9afb103593d2c40f08ea1b322c540d4e988305abfb7f8489fd3d8f5f158"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "a4eab90aa2872b79a52eaaa314b260177e7110e1435654c34363fed1d599e20f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1d2737fd70730228e3e32ce679a90762c9ac14a43055342c423b7bfb7259ad35"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "06a09b6347e21248e40cd3ee68d97170379a72e4ced2426bb5366de8d8cbf3d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "eb1757cb0c75c696408dff1613d0f001456bf3814ddaf2082ace973a8d587a48"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "39c136d76b1839464b593f1c6172810714c5155963c112a74230083ad7ff7e73"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "6584c9c326ff051c9c603ddc058fd93a448ecdf0a5bde5e55cde844291236009"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "d3e52462ec324c028f8ebcad9d096031786bb28990d4058cf903da1f4a70ba47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "71eb369563daf10748529e48ed44c8a083eeebbeb247a07e7f7bf41cb5fec254"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "79ff1b0288b7ed84010c103ca8c190e948cf1aca10498d51a2659012f9af0ad3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "6602c4a8258fc18708111a706a5cae9b96d34b08cee291aa4a9d9c3a0b12c62b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "03556fe0af2aa0658994843f6ea463265b6cd71677413c67e67314629879557c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "8554a8c301445da0fe23723e32cac2b56d0c351753818d96d9e89ea986d4a6ae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "10b9111e26bd259a5cdd807f909adaaa0870b1fdec6ad18c8be0a490b94a0d41"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "d85fbe7c730f9cf3d4eeaf45c9e7749884d2b9ce59821458e73b30be2b64271c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "065142019a5e414de9b258e82034ed2c0b6df2a3552e41edb70cbaf905362776"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "92145dc19e30b7718ff9cd38478f31e3bd4954faad3fb6c8a8460fd8167ad820"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "84dcdf5eccae839e08a31a2eb58440b636dd8f17c6d5d06963ea0bc9cb9854b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "95ccf9d1ba5d90e79fc0f8907caebb9a0fa4b867f617c7e6b8fa07fc87976365"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "fb9276361c931bbaed216cc9bb655475c10636e6ef563fc9e639354046f917f2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "fb9a7873b74f69a73607bacc99b81899a607c3e7c9ba7cea451c59ad491591c1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "114434ae70350d5e98b2b596ff48bd77340ee843abb0d06a056e1b94456c0951"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "55c8af2dec9d5a3d910a67ce194f97d9852c185f614deb27af4daac8de2f02d1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "78571f248216bed900f451b37bf804ccaa8b7cb550e522cd4cb1a127790be9f8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "536b3afb93d406c65c3e27a74cd9753e9072a31b5cdd2f4a081a5143f5dd0346"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b54a180170aa6b50e4f51adbe11ad302c3348796e24cf4405eb51cd54a8efdbf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "60d84bb927e831b566d5913f76c6a4489f553d92756cd2396d391b2c8a85a4e0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "640ebd445e22704d40f6dd7b33c5ecd3048e21069339f9c7d25e9ed7b53eeb9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "be8fe603d0de71b6e61c089898be96e78ea179d114b069b91e4c51fe60c3a35a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f0194d30dc1b1837ffa609b5218a52cfdc7901a53e96380898778ee4124663e0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "81bb5b8943b093c511c8575a5e2ee93915ef0b7e43ad1762363a323f090e93e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "b7ca057529fd488fa19754b454a6ae8355f82efc2bd7b9a3e2bcc0a9c8e373bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "caadaa7aa7224cb2071bf4cd18146a9f869837cd83e0c0ff980897ccaea3ca91"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "7bf7cea57ce59661a803b9db177cf644460a60598e3b29a8fc687055c6d0416b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "18741f05ebf294f92fa9ee0e21c0502800f17061892a1fdd5c188b89cbec6d5e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "224532e5b78705eedc00005fb14e5eb0bcb9c56ebf097e2469de3f928b912d05"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "b2dc5775550ca2bcf659260264b02de718319213a13f922f6891686c7a04e9a1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e4603b5e2d8ab3055b3f0b8c224ea62ba7b659c0da91e1dbe025f789c7752bb3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c25c870a0ad6a93c0a79a2068c43c6bdc6c03d5bd06713e0b1f12b77e167f724"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4367c93a368e50a7cd6949d4f538e8bcb55122d50a03af8d77af5f35942e3491"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "27e9f281eb7a15b53a5beb5febcfa9862763f1e78a4aa5111a8940ed9e54de1e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3eec7df5918e6c9880a0fa5ca240c33dea126043077f21460e799dca56a33b06"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "2e725d1d26f1b73eb6c324566cbaa84b8a6cda18c441109b9df08898e83d5545"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ac90c1b50be377cd78e517e0b8851052f8349648e2a90d1013cf9fddbdb068df"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "fcc7ef5767b68fbbac9edcfddbc47ca13c08cf0e6d63b5e4e19ede0ef286ec8d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "134eecc676b53b18dc4b216bddf6b19779233d242a420d4de897817a6a52174c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "e33b1fc06c337c7f3fc3d352a86c1802d55d4e50201fc277c1c0b8c080303cc1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "ac5ce68569967a791abcab384d8e6a069e2129a5f16971798296816e28d88dc9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "5aebda1ad61e04d9383c2d5db8af2f471ef5a041908d5d37e92be8b4ca9975d6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e5c8b53848e7ddc80a2d88aea1ed1f34adb17b42196cfa68118b30c02edbd054"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e248bcf1e7efa663435aeef7258bf5d2ff8908de19ea48f407c6e58436b13cda"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "553b7f2c680ae1442ce37a80508539488f9d0a3e9cf5fd46a59165688c89bb11"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "88e9b180827a08c11fda7bdf7e3e0eda11e8a9941b1ae6da3894df0fbc14859f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "7e3fb4073fd2af04b40f34789e80a6e71899116cc0bd814334b414fdcad38f5a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "ead800e978b1a08386564ebd9b079e4647f4fe8fe2ffaef96e1c7c85f294dfdc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "546114286970147dcf143fc3b35a3eae2b533d908040c4e01ac524cb32a17ad4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d07f38831655d3a10b6d8b46a36d0c5fac7ea0755d1b90512c4a1d19912feae8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b062bad894ab411932636ad0ed420a5349926cb6a0ec915a6b0facecd084fd73"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "46cebe6fe684df332304fa9bff834ff7cf98987553a5930b5f3798054a48f41b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "647651750aad07aa7682bcbca9b26b28c0fc2abb234338847e3701e60cc03bee"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "638add9b663928576e10c41ddc5dc2b268625c95d38dd446a300ea7b78716c9a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "58ffc5ea821de87c5b4017761598dd4b470ce09ebfd59e32abef8720aac39af2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "ce8604c83477a534541fb5c6b69ed69d0c9223d3a0418a3be91c08a3cf2a4115"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "afe04b750b7386dd1804be4212dd7f46421147238ac7922ecf747ae50ca92894"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "24370b809abc00b060efe88fb49178b566c49513e48a2d041d02385629140744"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "9409e003c2adb86f5fa00b503449fe6f9f7d7da4dbc7ae355341e8b37dee6264"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "dc22546b1d11cda8ae035cf6234a1344619100018e84d241c8838cc050303a45"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "8ec0cd3921343d41625e0235508afc0c191041dd0e2ec38c3b9f1f822d9cf800"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "fe6c75d1e3fdb09a4840ed709cf983170a1d7b5998f9d9e48502aeaed1000292"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "4f4146385462701cf78fc253180d15e343f3395ac4081681af045bfbabde4bda"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "b080d6113a9c32c1d2baefaecb6f060ace1e1b549178824af5ac52fd5318a408"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "90148ccc2474c24ddab91b9d4e1bc361d373dae62f32917e98c5951e30b5a4e3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2d2de41849bde53dd4ff0c864d9a3651536d4f7ed6d945c040662678ab566ca3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "c3f585b506c18227b4a8429d967b5865f00c4c2589e844220817f4a4f80e90d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "92ee470a79c8491a41d6b08e824ebaaa04c7919ce942f80958ca13d9790ec515"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c71fc65ec848e7bdadb2b5d0ac2d2b6597101de4585dccf8f5b105ade7fae4a8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "98d65e6fcdb546264a6f9fb658d7f2cc6db3542094e03d0311b6239b89bfcb2e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "d25a54c848efdb8fbdf51671280975b7bec917311ee328531c33ae07f25eff88"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "99260139bc99a9b98046cf6e6677036b3068580b4717a640950d7fd82500bf86"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7be8f80296a56320a226cb7c3506f793b1bead9d4223a19cd41d0dbec9893a33"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "7c439c25f18f5112dabac412aa68900927710faecf37520f075a3e2c9722f107"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "3fc7d05a76442de2f0e72a7272ac005e7007422eea3ee81d7948dfc53d5f7d4d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "345c2e6cf854ea651bc5348db05bbd0a89f5d16ed1dfdc28ce355635933ec441"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ebcd84b023587882a29ad080116d7ef0b234afdcbc118f5ab8899536f2363536"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a109a6a30756cb7bf2f9cba24aceb38ca3987104c3fe92e7821bef66a57f3b81"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "00f4db293bcd066e13b9d3aca7733cce2e8856a7bf66cbacff22f8bb80236cf6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f1abb91165c22242cdf58760b7ad675b754e10ac6e92124839badb9e400d63f9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "02ff15d33fb0e553615b590696deec53b630756c6523a248a39dd587308eab16"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "40effe9727a56ad2bd3e5bcd5b92809183f10aee84b54b26669dbb007cfd59bf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "05586b8c0e7e9a076eb1dc4ba6361d57d130fd64dfc802b0f5fddabe6c111fd0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c02f0855b1047a438b2dadaa23e5fa6685da4f740168b331d234f0993165bfea"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "115880d4602ff5f168a32e8925cbd3ba0844f5e82ab7f8f9c9d929cb5ab4a1e1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "fc7d3b0b75d82500f8de48405ead018f43f822aca0693f4bec2a71b49b0a872e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "182e2e1522ce9e900b1126748ef98782b51b3c7f629c938f28e4e80d61805657"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9fe8f3e64b63a1d0b0666f22ef3ebd2f79e886c5331784bc781d72ed5c70dfe2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "4e0125366f81be6a189a6cc227231ec9d335aa3cd08d524cb2b149048eb973aa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "55006b110952c3c995f16dab733d3fcfec297b80610ba88558f1d21b8aadaf2c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "36f775079c4cf4fccd62264fdceebbe2f446b89c957e065f487cc744e450f43c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "a584b88ee9e6f86b3739362a15dc7365c2bdad3690890fec91879a7bc34360aa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "cb465a97318702d614036fd64ee80b31e245a23b9acd1a34abb199fd8180d414"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "e798a0c8933fbd6d7a132f19eb02c36df53104a9926dc77cd9e6fcad8a139ce4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "4a0cfcd26370e6fc2443c93a24c9c43f1910c718bfd744e13ed9d42ed81912a5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7d5238aebf2072d1ba56bd3071b4a4db6ab4361e94ea8b909db5ff1a302ca221"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e824e80ef2e372d29f649b2a2fe3660cb25bb0c29ea28ba0a59719a1608d3969"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "97fe0cf65ebb2f9ad15993d88fdacfecff3c77f7baf132a6ea35f0bb91864285"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "01f27e64120800da69b8060aa9c018e7ceb30d4898d4b048b66cd6e98e1b75ae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "a392433faf49f7b9f43fa3ea4003b75a3f768a2aef639945dda59441f65b1b46"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "055a76df8f36cc6993818fc30f805001711a68a852413c92d6ce5e5f24782fe3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "e40a0d43014d62dddd5f880d2fb15c642b419b7fe3362c0c3f28f20184d88c60"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "55dbeff30e151a5f4b5ed26a1dd9ee9384b73f155944ddce4301eb0aaf18d52c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "53a35bd04cae866dc2c2ec422243c1648098e2dc64437339fa4ba889fc5e2ef5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "94300c73ce8c01059d4700c91e40cc79726d18c73ef825c57f6cc97526fd7eaf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "11546315672766759d9423ffbdce2bbefe51ef51bf10e78804f067b0493f2aa8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "5fd496dbfba46887e9bf9b4c31a668ebdd737d824e5bfe00c498810ba420c3de"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f968eee3ba3061760e88dc9250042f1e4faae14950c6804ddc1ed972659047d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f4052a97202ad7c9cebf9c2e669712c21d20dabe5cd75a9cb7ba5af14140d9f5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "3541a327413b5e018dcb7885b4de313f1396c502ffcbb08e1931672d9fb7832e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "eddb6dc8ac85358f321a6f89399869e11e2e4dfd20293f67cc96508ba515881a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "413fcd386c3d524af2faa926c2336c8d48e6a4938db50dd6432ec5d4fe9e48cd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "f90b9901a3fef2b38ad787b55a8f3011fcd1d598a57368bd05682ffef405aa56"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "5f18ef5ab97ebf9a0568ed6cf767d3da143592868983b55cef46ae7098438b3f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "161a8f2cc0363b9db906c01e3975643ce0ddcb7e229d4d87cd982ab2b0f0793c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6c913ee5fb3bb02af29114dd345d2761c9a1995da6f5d8fbc68ee97a7d1db47f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "501fbd56ce16eed38202d36d2f6450d12bfb303dff5126d79967208be09c453f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c3a6badd4a3fe0c1414b4aa33850e2713ad2810a9c513dc3975b2f8ea930028b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "4dfdef7eb865d3fc6298234fa6a5e196a9b5fe77e9f682b2b1d79587da3ef249"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c54e34853690f7abd2f15dcff4ef2f490b94b0a1e8a9fada04ccb30706aa5f17"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "b21779e71e2c6f2736bc95d316ebb0b0683c8174fe03bf8ae907a888be337fea"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2ac303c7bd19cc4c1345148def5b8ba30a7057e3176b39cd12fc425d1b917aa7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "91ec24f9c5c237e37ae5dc5df194ee5547f96c1144dd85b5b4bd422f8c891532"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9857966726497c4ce27bf57008a3cfbb4e0d89df54b0155ebefa2855bd7364d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ec9444344d1d8d55f3c72fd1538637be81b1903007a5a43a8c3ac1901f0cc2be"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "da8f2b4270e0b85cb96b7281fd7019bcea05e9539eda70ba4f19858554eb10ac"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "ce4eba7938cdf1256b6da506b3ab1f9e5de70e994ecbe1072a580dad154e06b8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "292299246846b5e67a73833f2791bf82b7d587b243aeaca16cc9d62a5b3bd22f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "737774eda0e5780dcdff2aa3b2f9399203ce4e1c569e42ea6afbbbbe22da7875"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "6c735885179c7eb2518849338fa5cefc149bd4d7b9da89ff536560bc347334c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "f4ce3660179ab5240792dab8fb337fa6cf9a5c36ab2b21f429cc3cc0b8bc4fc9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "2c40755c1c0c6b2a086df8f0078a5fda33d55c266f538a94b268220fce3c3b70"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6f826a4b8d528b75449eeace830983387e29b295c194106c93c07e7a2db84df4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "09046c4cfa06b8feee32ab9cc2bf8af98aeb0fa08686a58aa4ffd2f1a84adbb3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "0d053050b0cddb8b45cac83ef759ecf7965b583cee0ee99834f134a4adcd0ca1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "2d6592e44b41a572b85bac24e7a2db74409f98588ac4ccd0483daf3e50551bd7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "67eab1510d77ce70578621765ba42b8dde88761b2bb9d334c965c3acb7b843da"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d7cd8be65560acb7d580d22b8cf8fa3291df67bfe24715712d6bc86e65cb4d45"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "f7baaee2c80c44c7f01ff061427459f84bad2cc8c215f576c2224e89f5633d45"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6237cf0d4813aa84e38f925ee5122ea66d55a77330e0264c4868f6a76914e44d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "6b691a5d7af30881e132a6d591e66dc8cac0756992556349b3695e1a283ed7b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "162a8f5c1c86f10a495b8369f778141273771c4ee90f2387d3e36b5c1fb4e3b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "9170a3d0c19783a134d4d658281078ba066b3a0c541e245ee0cccd2887086f31"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "d4a8a44d582fc7f8c0d775e21f5950df32e59974e7e851208ace14e3d8ddae80"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ab483d3092f2edac524aad89c9410209d55dce558f7941c9c434ae38edd4c955"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2268d0a36e19498c8cac71f1cd3f58a99ce692b07401b3652ece817c935ccedf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "b6f1fcdbc091af45be092e0a248436e2fceebe53a85c88fcdf528cf4ae975e22"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "eb3fdd58a821bb8d30d0fbe7254ff347b1809e2e1d9b574788aaf6b1d9a238e3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "98a6272f3c517a03ed1699e89c352d75e7456403d9b27e7d41c6cd3be68ce7fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f5e6e93b74e71234a1bf057acf68172c11b732b01d89610ecf482808f4cbf78b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "88a1bef30ca6961173e20d560bd555262edb7e95b3ea7343fa345bfd25bf5053"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "68e485266235804ba017739f4de671d17358255ba7a74ea7be5c36e2f4597dc9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "5fb92877d704e36dd8c800db858f7989f0e0c985fb70715d9d0b0553c434f581"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "2829edff2470471b0b1484d80eedc0c3c539e41bca18b304465171c410bd1ec4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "5c6305acbf13f9615fe8cafb327b7f384021950a954876ca25b71950d0c17617"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "d8faf5989b31a1a622c8a279f7c0417b05981052eaec53f3d5a7a75d91e12d01"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "814682a4c813f2d3db5fe12d07faa30addc7ca8a37fb36870d3e404452cd2238"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e727bd9ce46559716f09fe551185c80c8a26a629c7d0e6b98f4f38cafc04b2c0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "7a1676a5c247b69470229619cd43da2a36c2757c39358ce36c869b94622a166d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e04ae97cf7418322d4d23085803afb7cb1badcaed41fc181245b1b89cb071009"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c1823d50d24d2ec3762f3edf0fe832bbf7d114da5f24bb5a224ba6015975d516"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f5e371086a1d93db8834784edaea291337525aa6ce127c9f77c83f955b8b76fc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "48e9b8f56610afb605d7fa10353a9a81d87b22336411e5d276e259f76b45ea9f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "4ce51c821dc362ff2ab291013de2c507dd039232cb89eab1cf6085b5df1085f1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "b2df38b8e3cdf0e2cc557279a0f689aea2a739f5ed2d14d148de022aa1f13973"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "b65af1d6aa4ef48588cafad904343331b41ed3e0c425b8b8f222cdedd0d8eb6d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a371593688fff0cd3b6d6734b2c5b215a5d269557314a88a2a444db3092f9a8b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "bf526e934c94933dfb27bdf0d3633df8d883d684ce2408c47ce9740f8e008fba"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8da724185c7f61883470a5a15c1207ba043a3e545e1eef9d925d81d107b6f1af"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f52bbbf03a649566764e0a890f047394512318bfa53c0b3c85d76b488cf4c7b5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "660e6044f71ed5edbff55dcb101485f56f6ec8c9a80474830501727906dc83d4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f9c6359934d3936172d5859e16feda722a09e268270f2a450486384bf5ef4aa0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "06d0cb8ca0f9a58243fc4f930966251c56ee5a032a0e3884b86946f785ba7c05"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d9a377939c5851dd76d27ee8f51734c1b09fe54529aa387f78bbf50ceb7e1dec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "97ffd31bda171347a050f2a0ddb2de3729ed89d9df5ee9b2a26089fa3707f4b0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "30bc0cb1518729243e89f27dbf28e57c45551e1c870768cc15ef1b203af4f292"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "fed92a9e8e7e1e46d40697c8f0b6ddd849e6a95616e5677317ef98ab4aa8f733"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "175d9821e7f29399c974efa498c86b06b87535ed8db1a1886b8dccb4316065a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "dfd885cb11b01dea14b1ea252b17040d0f2e524d87d7b254c76b42c4c408f24d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "54d53fa051c730fe70d71724a3082c95b529f918b0d04da3e3146f07b2b30d91"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f87788bdc82750c63411a11ba409666ec2591fa961bd90fedc6b6a25b51d1fff"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f15bb2090104568152453a36b58de3e12b230a3d4ba7bd14d808a5206318ec23"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "6d2349bf1c46a0b43302c564bfe433d24f11ef9c114af46f8c1690e5a1cb6d8b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c1e482cf34ae51f102deb89bf0413af3072c2bd1daa3c7728a7b50ebb4b15de4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "0a52618a795e8340ed958449dc6f930dfef379b076fd684ea46ebb0680506507"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0765ef572f39e691a2cca4088f313e7a79c6f21180ce55b95f15426ff6dbd43e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "1356d290b9fde7eef08d97af8c196732d49496986c23a5f495a8183d939181d5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "73f106bd3e93ce74a2c1f6faf839a5c615b7e2a88aae9d46b8e7d016d122be8d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "830404836640df4c0687e5342eb0878eb9bd2db38098feedf09dc2a7d7f44098"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d7099d407ab46f29f37dcbe108bc25a83d0ae69c8bbdaff36cbc829684f01f5a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "bd2852caf997ee02429614db90bc99ec836ed33dec58f65b38e773b36ba764c6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7940b2fad0333ea1b136b42079c954dcc28b1fd9a71fb3c4182435a264ca6b8f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "d5f2f7ab53fcad98eecc26407e647fb5495e0f78e70fbcc557db77448549f842"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b6e3d6ca56927b404751bfc7565ab488917ab61ad3c23a5409c75fb186492e43"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9b3b973f56dc32b3d9a315ac0c4dab6f9b8bc881c649c134e33a7ffc6ddc0a4d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c3073339603959f92ecac916f682ef413626b126f0e52b77ca641b8739cb3535"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c0734a3a4416901df029768b4ae6ff95276c69afb9fce32d8e9afe0a6675a781"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "3a6b916e657afbccae1c37d2978f782ccbda6167965dc7a1aa94ab393592bea1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "736fc92b57a2e91124cfeb6bc343bd8ee23714dc2054276d5ce834804de14ef6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "c7c5e75ef6dfe3f45656eb7a437973ddff30c2f39efa490f1d18a747312a2c79"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "104c50d7c02e2e589ae29544af47ba69ffa89b6d58b41fcd68576b92fb757076"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "8d6964d57adf3c75ff1c3349f690cd7244a6844de76e210f12981df151758688"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "eb618817f533fa92e666e18f75f46a49efcb878c6eb838244f50124d6de4a953"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "23f2e0fcaaf436448e1d07698c20be4034c7c57d1538d7ed2c351b041aae9de1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "32719028802de062d5c96f1a095864f787a37093609d443af34f79773aeedd41"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d80f7a0ed305c1711b612f7de65f29be2ca2fcc47410150c378e259d64f8960e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "976ee03a4cfb336af7b58d03bb68a8f0d8772a50632224e59a19b1a3d56496f7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "cc0019272b9f309a81b5720b3f2d88bbb0a3c33bb33bee82692f38d8f4bcceda"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "202caa01a4426f1c1a11f441307e6cba36b628326f98f1256a90d03442f57ca3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "b736eac1030d90786ba1a22452fc6221afc812b9e61773238ecf04c1871817a0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "d0b5cd8e5500aeeb68cae13877ffa9d6ce0cd173e31b98971ed5bfccea344903"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "98d308dd86bae4ec21c49e269bb69078862678641825293a6424dafcc8a3dff8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "cb1a2c32145ffd9b4d609ef795f5e3c378c8b1c583b879cb5059ebc81f7770e6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "72e297b5a5fe5dedee68303fbae26d4e622ba18581d83c9bd4f973013ea559b5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e20d4ae7c111b0470df44cdfb06cac0726a363f5475cc3626687130ed1ed7e45"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "1dd93bb357ff1f751803c46531cfe473a303990d043bc0184aa006af0079eed6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "bed6fa4e932af7b8a94efb318a6ad338574e1646b3de4196666dc7eb652c28c3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2ae1f837e680d6c7dd58dba1e70760385939f00a99ca953aa4d2dfa1e365078d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "a46eb4f16888e70ea8375ddc8fdae594738874df3b433262012db49040584c10"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "80e91fa182c4ad5aa83f02d0de155905b7414f7d9e18d3c52e33d13a34295af1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "7a7c59b872773ad54937e06f9d914c78539b73edd512dd84377f4d1316a696fe"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "a59d599007e561df215a747aabcee90ef8e9232bf09fcd8becae247014192e47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "770946ddadf4f82e6e5e78b78289f8ed155ed2e66f0f0ceff992b897d1cb6f8c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "65589205edebd5fa697881145daf8a40d2ad4868b087fc9b32b1463167e36613"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "28ae26fa285d1e6eb4780d819cc4c9055ab1a3e77b75924ea2a4f9af580080f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "3e079eb1c25f903578891986986c69db3d780895cf2d40bf566987a5a6b50d51"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a8fc03c8d6330e76b63abfdd512113b5dd12aa7d3dfb3b62393408b8762f294e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "865e36d83834b41fd4ba5388d1643846e727fe21619961a4381e97b709fe799e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "3b18404eca31fdcecba0b2ec4f13463f43595d92c54300de6ac4e8ccd1a007e7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "850afe0d3c2f13dbf59dc1ee51c55a805b14dc3c1cd9916d721e04dca655e117"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "1162f653a48a28b1ae84426634d18273d8e473d83b2a677ef101e0fd222d10a8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c646835a8ec5efacfd87b86546651fe5c6507370b0515aa3ca970281da73e99b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "672066543450b0117ba675a65b924b41fc20a1d059c0fa689d97c9221e3ff38c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "a1fbac06bee756325419db7170bff5b45b873afc74eb55ce50f19aa5bb24bbef"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "273aeb6781deca6cdad7439c41a1edc5fe88a35ff6d0d58f0f53416a6daa0044"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "8d777aa79c3233d6c61b2013f50ade3e7d14b5a572773cfb0a90d70290219221"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "4c929b7a0e861ba13b801bde7a2c847b17636ddb6c44aa1f888f5216e54e2f2c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "afeace581b7ea6fc29a4e79e50b5c0acf6f0f3a1d71386b67c0daee57963afe4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "bb37de8a2b513bddcb80a5c5ebb959b69b9c153e5d80a9632f6bb3049b31eb04"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "16762683ce91a9f8a4e792181cd9d825c080f1f82024176b4dc5d8960a6b5e28"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "538d37b70f07f40165045f6677bfb5593b2244f4d0e51ec74ee56733c4666d29"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b0485c16daf9f8af1c6c6b189589de5d613a4c416e55b81b4e848d3f07ee0b66"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "bdf68dd0ae2c8ed78eb518bc7fa707aef91ea2de4ff20fbc2a21580a04bc9f2e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "5d4e82c643a15d75a632f39a01dd862955df20e1e8b2e665ea9b62b40baa5129"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "2d72cac2c413071b2e6291ffd8a545b143b5f443031792522a33be6a41ec0dd3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c62056715fcfc8a4679f3e0df4d1fcc2103752fe7f0be3fc5dbeabd835f47f48"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "1be60ac3b2f12e176a2147489ea763a29b4d495e21a7a483bd2b8d4727e11f50"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "130c6d5fd7a8565344fa629778df21e3ce38f42bccd61040c7feb91d0fdaa422"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "e492e4eb389dcaaeb2b802018e597fbdb1fc2785d415bcf11bc94a64d0f7c18e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "a19f4c88d14f2c56b56829ebecdf01469f30df9217e23b72026e170573e57c91"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a69d96836009469b752fe26dd200cefa0c43ea2a9129bfac3f3f02342a982c14"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "330eea2488150990c47e0461b54f45106441ccf49224023317e30b88049bba7a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "a0d0254da0bd3746a08c9aacf553a531bd7f9134996d36cde53c313c60cfc672"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "ead43528208d6089faea6fa84bbe07e51f2eca91968080dd4aab9ebe9992a046"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "fc74a27ebddd7cb81d8c367d7b03ae0a4fcdbbcd1f487f781580396d6d718bb7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "68d3f1d7e37d19fd210726b8de9570ab25f94cc18f593b3a1045ce09a42b6526"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "35ba4e4d4c124326cf91add453f4af9b22a28c77e2b0d994090e22fe6cd878b6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c9c311a0a5f91db823209450dcbc54b4d1b5aa1c1c4d8e1e7f8a355d00c40cbd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "7b0e5d2d694ddab15c44bf5f1a80cf06ebda1cb4bfe4682c36d57c00d4fcf96f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "7f3cbb6f0e5446bbdc13546d8cbd1d24487307a166072d02506052dc6df96554"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7af4da28d3f047d3f7f69dda50fc929edb8b8853022d92439cda06276ead16e6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "839f29a014f835b4bd81fdd4ff6c2905a88a462d8c057a95b9079181a7607d10"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "bb7f1e2ea559fc0846c9dd76f42ca641ce81765e6c3aeecc0f841b3624bd74d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "947e0277f5255338516d0321b50b4d7252a5079dd5954d5f10487c3c3c3971ec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "bf68c7956ef4556f4fdba590457f89362f87fd6bcdd6b17d31cd69d78577ec9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "11bda3506c01cab691d3704696658636ed6dcb8249388dd3d8c89600c1031a7d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "0d1cdb8d5b80d05b530f4e97228b5be79a26da5b925c0246a9e873a4f30f3402"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f254f2fd6785c96028e3bba596b8debdef6508acc2e5a88c735c62885b70006a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "21621b11788b8296499f4c397f16599e72a6b6d4567ba469f8073733f731aab8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "cdb5868c6359386d07fb8903925a488db746a5a895071dde8aca3884a035ecf8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "a8683a21a22c171d71171e126409181ef1f038fd5607d39f46c7bacc9616cc31"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "42948cf0bda14e8adf53bd16cd0a1f3a67297dd529a67e4497f5838cb1d5aeb4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "cd02ec57f1860690bca6633124bd684cfc4dd7dad6571b1e9ba30491cea6d1a5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "affbbd764227184682a1de15cb1ebfb4efddaf32ad0c57975c5f63b12fcc087c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a96020f5b2dd4d91051b7737c28ea2c87bd0ec605efd47b0de6b76ceaad5ef6f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "ff8b7856ec0dd3c284bb80cc3da1451b4038f4a6cc0c9e3af522e04717902769"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "26fc53b3e8b610e9bda7bbd024396c946db510e3f6529fa3e0b52ad642c759d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a27805bbab93441da4b9eae466c7bb45c1fb7d2210c552b15247fbe451c90583"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "e774db8458a834bc0cf43e254bfef27088322cafb6c36234b30106dfbf4ca86c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9c2b7fb42d2218420c77ee9eb87d2b2ac470f483df376c91cf22707b662043e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "09d44a22f7758ebcaf65f09af04f826c095315454c521a0c90d74f220db92208"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "6a9a2e47ec49086adb27354a13822187492758ed3430f0e1417e9f5c8ecc1fb9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "8ed3b4336e827d21ba94362c0205bbca7cafaeb3aaf8aca63cc5d2a44b5f3f10"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "0bfd4508f2893417a8eec4953845db93f70b362dacff49d0866440af4298e0bc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "52fa116d5adc64c086f0f16865680a13a1d24a0a229623af9b11b66d2d8c6dbb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d6da2d6f5d29b8e76b3c9ae417e6332903162ad373c198d7db7c6d56b167a9ca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "297ee9d9b8c0a44055131e6c75c97b9025513a8d6262024167abe5af970e42fb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "01294a43ccd6e9d431137bd98b0dd33248c5b11f25561bf841acda128f2e5ffb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8f13b1ca01189961e59396f39342296c111e9ae1f56ee5e8484623977ba0f219"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "c7158e64eef05f9b2f5fa47dffece2396dec799fd39d3e3117a7aaead78395ed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ce676ad041053e2e2016a6391a5791862efc46a9fc621cd1c9bc4a64f6d4a5e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "3b5aebda88060aeb3061f77ad1b2c45d56b8c3abec578296d8e8fb57f6d327e3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "62400331dda10b06165aad2be32b7fb9b7c2450d3ee2abbff69eb2733a14b95a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "9575c46757e0159faaa83b6f5391ae5b3041952f3d2ce76b12bd98f0629e14c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "ce6a359034da22b9513c117d0d1f9e11fe1f257b7148ad01883bf969d451c67f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "955f59d1a99223a5b2328a565d5dea1ecc316260bb98565230049a6684c839aa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "2ff4c80fe753d122fa3670c92968359059e3b07cc55daa4f2451c433b25173e6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "8b8c7375efdddbadc2bc6346694084f7e4f3ea1edb793bc86cc873c7b8f7d1ca"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164256, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "2573b20193329cf542d590b7a6c6ad6a7d76b25f4afbc128f5c12d05e2b76999"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164080, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c7c9685154b956b885ee211dad60d8fd0ea681c8c13bd2bb92e2f438cff4ed9e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "2dc75895ae01b44f873c9c407bb8fd2d21a00f01215fe7a0bae331948c3d2fbd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "749c0c637110d7f31208a255adcdd14c88ec17e2cadd612c057b349b15f5da08"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164256, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "7ff322ed5aded097a8f9bdbdbbc73a91b0332cccd5fe8d2977e0a15c08109f4d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164080, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "2c974759693db559f1d2e3df134046f35c5773046008bdd6e8ef3ed4dd4436fa"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "004f06552a4d583182851a41365f372365554ee559487542c51adc612fd5ac26"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "775b41ef5e4d1a96500c9bffa2877f33fbf960ea791815a8edd8daae35b20434"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164256, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "bd5f9b32f5cd694d2cb5ead8e02b6f67ffa372e1eb55b0f2995d7d289d6258f5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164080, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "39b908623660ca57b28a4beba42a372667d6011b82fde1d95cce93dd308b21a3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164272, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "663daa83616ce03c5750d7ddb276c66a30294d38cd81cb8049c949e9297b527e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164096, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "5d8a02c6194180639fcfa6c2c49c2dc6d53eb1147a2c3c1e1504526bcf7f2ec7"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165120, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "341edfed8901dbd6ccdfcc96b5d7a074c77e1b16dedfbad045b828c9cde378db"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164944, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f75187f0325f64f31642784b13bc1baa1febd566d87d01442ae973cd511b0f9a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165136, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "1641001154ec03304205446cf4d7707097f7f32be3ba29be4abcc30ffd585942"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164960, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "7cfbbd50c71e2aeaf33599dec58231c511df9b4adfbf375471c2a37ed10c5ed3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165120, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "2e99e9ef6aebbf17643048678abbf68a0bab6713036a1e7cb7f9c3ef36be2b50"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164944, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "afee1c9beffa8727dcdba9ef42b7669eb293c8e962988e7196f01751f0e2a593"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165136, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "271f135e08d67c391b52b7a83ca6b4f55ee0ac46171d759529abf9fadc7f8971"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164960, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "2a0f79afac487504d3909c68ad41dc2cf28d1968ed166e671442b70c23c5f8dc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165120, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "72cb2aba0367a17e59474a9920822bc2d2b47632be8b5411c8b63011bc633c6a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164944, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "142f31859160a96f35bc73d0ad4c08946b4da3e326dec8850049d752bad51584"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165136, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c40476929895bc63225deda353c1bda0e0a9befe57b7b782e560d61babab8077"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164960, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "213a3d29275949c746468268448fcaa534862edaae6c6be1e9fcc928e23a1242"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "de82a103a63ec80bb674ba3c7fa06b4fdd5fa3f8e2fadd8feab269aac72acfcf"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7b671584a49d3502f92f847b2536d5d84d8d20135e77a2226584d2c8293b20c8"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "3faa3b949fc45449a65b4ae7c89f15078388fca6e5f566b15e4d0892e79f72c8"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e1e7f27334959b6220bd9163d1be43652abf0c03e67fcba35410eb543f603efd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "7994e4626103edb33069e3a313f2050a3ee66ee8acdf1ddde07fa3709fbf88ac"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "342fdeeaa91523516ad1b4b3cc2cfb28cbee4f215cbea8df599bbdcae4a25d5d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "6eb9c0e428fa9e1ae000237637114320d280d85e4c1d9c4c17d49781202ca6d2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c2e3a4f18cad443d84cc7adb0158b97c2ecf4f5450b96a21a517cd546f0f43c3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "b8f9651c5ff6e656f4ac70d00a17279063a18c8fbb33146010f7b649fa9f9062"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "cae33e2c085e14294fd1ee57d291c4b6f6d2f4eebbeef17d8ffa2e0c1f01c9cb"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "bdb9c21eacca5a6fdc01b36956cbc4411602062052c7b0350df66c3c8e6a072a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "2bd804854c07aa0cd340662a407b8944fe475fa4c49845b093eb70d17676d20d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "c6d492577ed974162259c2f2beeab5e940383dc025b583b09e617636163f9a2b"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "29d4b5b50e8a62ea9d2ae910c7badbfc30b72a5289d50781572a1f716a207f34"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4294755d0d5ac45916f4801630ed1b21cd1b6f917144fd99d432039349dcc3ab"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a067dc7b3e8276a19e47d23092019242c12e20a302007610f0c10ffd896de847"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "1a677b8b05c0ad49285a8f40954b6b981a864712bb88023930491f3302335c6b"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "2ffeca91904a51f314b75079a13d13be624f7576a465df9b7beec3d499d0ec36"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "aa79439b33a02b01becf93683c334da8200ecca24807a5c360e528213ec9c00d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f0e866b8898375b5534ac385361b7a955edda56ef848968c0aa5ee0495304aa4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "63e5b4b7a175cdf58a461a91adac827f88d3346dcc7d4e7cee34e8dcca36bebf"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "0383d49823693fa2960d02f7d40ead86865a419fa07e7f61676d95e1ccb0d00e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7ea4830abaabaea12687cb18e7f78bd8bcdac52446ed105f3d33aca894ca2c1a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "5326d7f76e378dbca954a451e7ee5caf4560a0b1ce4d2e95e98baae774519275"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "1bf23a791eee4b11fccfa3ff1950526d9455fa3280cc1bc96ca13b5557ba0f37"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "2e5a58b41e78c9a813d95fd502060bc668c3b82e580f6b30a3e48fde8cf0e21a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "68cb6adca6e70a3959747af7d60f0a0100986a839a19ead1139eb97d2e78c654"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a2889055f4768bc137dba4c1ed35ad9771e52037447c14479aea975acef6dbe9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "084e28c35342931956127faa0bde5f735b7a16a16b57335ca9f079f11198fc90"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "35ea852afdd26bc2ccd5b6c7f3ea60a2fe4eab5101980a5b5422411495e2ba1d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "9333930599f0c86a4a51bc7ee406db10414387bfa1fd1898fb98f225af27842d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "bc790bc055f6b029798de98554f2a6a87c07a77e7295da9209664b0dac069780"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "e9071831442780ee3c939284509e3d977ddd5d9ad1598f28d00d3687b67f3ca2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "9fd620bc20ea1d50c118babed720c4d8131c8f99fc20b266b19e359ebaf20b3e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "13d407586370fcc4ff72fc69a53fcd005baf74a72c8447440c1707e7dac76c6f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "e714e0143e7651ec6951d91496b311d7294a9a1f8ce108177d7bd3ace4c06e7f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "5967e81ed43e6c1e6566b0c1ce50787e8403dc7b4473137d408238e473a77366"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "2bce36019f7858a401bf8e852ee09a505153ae22c87ddd38e2d40edae6af2ebd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f288feb3a0f41a526027cf208071a056bb6dc5caf4f2753fa2c5008253154f10"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "60d03d88d48a2d2d48763ed0170b9d09015759f8aa042008b1a9660ca1639c2e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "d14f933dfae020e49127160256cccc05d572b17a0d50a7eb3d5bbd63d926b7a4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "7aa9bf8da109c84d05a01a7361577cc9fe8b9ccfc188b9d9d5c3602905420e7e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "687225fb0a51abbd4285071f13c9269de60474e4a7554396e0830b061a6996d1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1735abbd52b2973d722ffc82e27688fa9dc8395242e33866df8fb3e39fd2257d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "748cee1c785af07526dec4473de5c1278120a82f4e0671100541e807e006a759"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1238d2b4090b089befc78d66a4a6806cadb27c972fd030437733d5e44d06513c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "a22d307a8e78e0a6490b08f8567db2fed73b9fb3659765dab8bb3fa0785531e6"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_103, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm103aKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "a4ca52b31bb02a68c6157505506c2520870b5f920eddf33af47d485e713957f3"}, #endif // EXCLUDE_SM_103 #ifndef EXCLUDE_SM_107 #endif // EXCLUDE_SM_107 #ifndef EXCLUDE_SM_100F -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "039e4dc43000b4108b8dba08c5f2846d08f738517f60c1e63ad3cfa86468f05f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "378693a8741b54a6c47f15584d4d71f7add70a7fa6fac4d4fa717ff7049415a1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "a9ccbe8d4882619304c5a1755dc7738dc1c8b1aa743c5153f9c2ba5dfbc2dc81"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "0725eee9b991dc3227fc681bfef4861796f954ed1c50efede33d0b26ea62e61d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3e0f4643c6af6d685833c4ee8fdad51006e85e5da67a928a700f480fcd09fe6a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "3fecabb2761dc6b2218a0800092672502df7029998f304bcd21bf0bb89f9316c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "688d030861ef0831ff8ab772553f53abeca0368e091569ee17da7deb3a60f07f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "734efec9efddeca31ea2f5ce723e63fe85a8870e8189ef29641f17a88e5090a5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "e5f50b6a6f4ccf3906c10270252a283e6208f72b000090fea9fdb84b0f795d89"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "efd1b6b2ed0d27cdb78e5342cac0d405b9173f73cc8a72c7fcba65ae71dfa36d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "a55814fb19c91b5adcc6cf7848087a418935801aa620452303815a4894a74dff"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "256f76400273b7064b8d7192f7394037d709744affbc140c907091874be4effc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "d8396419ff6205eb8ad1cb5ae22f97156f6a5aed37443cc055a9fd0e95b9efeb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "819ec5f8cbd8109c011b1a39d4e03b930b22f0a8d15a56a08cafc8a428839c4a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "01c45ca8fbe9f62686752fe40fb8a31a0d8bc87fc5abfaf17ae8b332712463f1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "2c559cb9fd6548b6f8d8136d16049e07184c970bcfad32d50a1ea7585b9b15c8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "39b5e4463c0704791bb432970179f3f16b759bed57e04e33641967f2f3606e52"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "01d50084eeaa19aca383eb7bfe9b7b7931a084b4b486f7ffd03a79c2f555b4d9"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "8a1993d3c3fc609e6a5f7ee40ecfcf7bb276ead6533bd47c8f2fd83795062aba"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e738d59c7cebee315cdbd852aecfb80a88224acebac35c5a1427b935f82a08ce"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "ddb2daad213b95141e236f31255a5d559c1285386fe590335566cac8d3df508b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "5291b86ba05134fc23647b1b8fc22c46ebb12dcf7960fc423d910660dd7a7e02"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "976907f40af826d0ebd8a81b3b0487cfa6379f749f55c2567217243d6f473225"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "565075c3f79876e5bc2da3c37b9f3be14921a2ec176cf23ebd657bf672953cb8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "15dd76ed0aebf8ef874a16dc664bffcbbc49f28cac56fbe7e0273649f06e3c81"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "fbf7c0414e4c3dce5750a80ee6e8366e3f9a4802d592e44a689fbdb12ba658e3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "2d690122b8b72919afb35148ff39645c4fb9f0b0ae78a92cd30707f98e6f1ad2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "15928922099986f7a6323a2c8e612aa4604cb4fdb714f694a748b4273352a8d0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "c1b176338138e500c0e170ab2969e4054d427b0d16c7a74ae72eedd77d7c1971"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "630076b0eb0841602ad15b8034402e0753d57a1bf3695132b4d23c9c99f1d7a7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "9dc210161d030d46522c059e8af90f7703fb0c547165a492d2d3b7614aa15069"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "c37475ebb9e5ad2f39b93170f4cb32704815ab91ec5dee799e6f53e43871b7b4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "90c95a3d8e4cf0fedcf51f5455e3185373a734e70497ffb1c61bcabb928a67fb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "84e92dae167d6d8efc7214774429fb269e1fd034f3fffa3af08be3d7e3261bbd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "10120c9e0a4c9f8021f650b72e60c2e948d1006ff0f6f26d7186bcd2b3e4c1df"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "fb2f736f5ed60d17c16bec9290084e79f4d53089bac798c1346c6cfdeb3abc03"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "471e6b6251a9b33f11cbe28a8818cee0b343db655a7917d560740e995000625e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "fb0a8759af7ef87c1b8dc7633e6790d09c532cd61f0ff1320c8723d4bd91914b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "48c8ec5250b94ca9fa4dd9a65496aca1d47faf9b3952dbfcf49341e91aad17c7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "326387e83f651e27f48568679fb4b953bdf6a48404f385858c3d0ecc54788e80"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "12e462e58a07a901f248cafcec307df7f437c99a75beee0b12f1bfb04dc2f2c5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "472b7890cddfa92b08e504c4db9c836633aa81113517e920878bf3a7033a0a3c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "e1beb390086510f29e4b91142f9c841c757e6b4ca1f3a3da3e7703e4e74f555f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "d043c6494f4af1c650cce5f9cf39670260a2245aac8be86ce03e095b9cfd49e0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f908e1cf2b788e2c518e7073eb09fe49c81dd215c0a0478f419cdaf077c0e5e0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "98a5c96a988c6e1c66c16376a6e07e567e97d4aff59439816e400c5999756b55"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "8d914d2237214c1843a583e657bddfc509b82202cf6308faefbfb6b2c1ec3893"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "b0811763881aa134526e6e6dd404a7303382552b5fb7b750bdb57359c214927c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "c269d57d84f4d8ab2b79cef41ba40602ed3f977b943df6ba890edfaebeefdfc3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "2bd3d6756d40758537d0edd893157d2a9b61e4289ef26ec8700a1d7e65e84073"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "f24fe829ad216184141de1cf30decc67dcf502e2e304564c4948786c1fb55dfc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "11e91622f6bf346869fd169bf67cd2decf4152e63baa4024c229a2b549de40fb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "5203693782262c3f50da9f1208d908735e0ed892db6c3bcc24b04da8fa22aba0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "9bf46c7fdfa34818191f61f999e438afbb9f772b365cc376f390f0100d3b260f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "e18acb0a237c590bb7191af431a134f2a53ffffa9c157916187416aa70dad40e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "5b5137165223773c99954098ec618c7d6858b315dd98908b7c8a8a7eecd8aec2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "707bf2ac219cb0e11807ff7b86a3e645694bdc3ef20fe56bcb0b07a388e5a587"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "6107d48fd4bc30c187dada7e034f45c7a693c68609d7d732d664133f2505bdaa"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "cdd5b2fbfe3465aa4ad6a751a2f88c04faf49b880959a6ee1f818a8dcacdec1d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "3df4f0a655dabe5d2c9e6f982f72dd39590e5d1f3ed1213bcbe5791873cc99af"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "3a1629a88a001be53a4f865184862e7eab2b37303ab8e614bb37f7d105025465"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "adf78ab48ebdcef5b32a6099193df8f0b401274dc84c65780c1fdf50b31e1005"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "dd7ce8b3a7b7e7685733d680ed17f010b230d6f4a40cbe93dd55028bc0237436"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "72cba3dd483714a847e49eb6b33cff4cd4e45b040623f2f12f0f350d6d8910da"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "c71d0d65764816b999d33496548f55f5f3ad343208152c54715875d4aa6d21bf"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "8902b3444eaefa24c9d16c566eb08625f6f2e0c5790c293eca39cf4a2acd52b0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d0bde3fb244f288931dd6f49abccc0f2db10fd1a8c251bb782ef5f33f90be8d2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "cbd549ff3b1628a7aa54a6880487520f1b97b7b56e071dc15415c521832df023"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "fbf5017a6f719dab629503f72e1016d92bde3309d2d15df61423e4301f7883b6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "f50d4cc610907e22245c33b2fcce4fa5843243f474c30bba40868405dbda6b38"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "ffc3290657419b5e4e1fe1812235f24bef259351537fb013cf6548f2d21fc0c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "e0b673e950437c29ee24bbd42d5bbcea0062e49cbf04bbc39aa0ef427af92360"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "9b71d3590920a345fafa4cf9a3e366d87309fe178e0a5fbfa828ef0f1bf59b09"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "5b25df3502766127e8eae653ffbd7fed9de0d167c9091101c2a489c0fc873833"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "389b53ec16158921deef328ce939db22efa84a656473a1df4575ff8ba12a0ca9"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "a32ce312ac7a2c65f467199c5d2f3f7856f49a90fc6e7392eddd999d49b2e570"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "3d69c3d8915e0ff2115410d6a1da829382bc9ab597be0db82b6613db1c4b6efe"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "84f20142bd28beabd13d4f4e2d17acfea74dcd1ab2b5e9a74ea77728a8f309a2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "156db1738a6edbaac5c11141ea2eccb610b0e42fc5d0353d5f6ac3a746aba2f0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "d3f979ac7418c3c38fb3eedc0d043ed2f693ed581c328f780334092e76c46aaf"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "beffefbafccd8b314b3416c65ae045c8c3303b1a9bc0200df3265844c5279a09"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "f3fe90ceae569ebed46b307faacdac4663ade30601534f59d0226b5b9078cf3e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "39bd6b4f5fa7625c5317039be0c93b1931103c88394e778186543652f7f08b50"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "d74ff20cd9b4dfb7b1daff9fdf34ddcedf7eab2daf4f67b635a48b6b1bdad8a9"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "df152021f7edbdb5ddce617cd37818455326b092d377222c69c1ce2296cf627c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "4ddb7301cb03b4354530acb00332b5a4c8d952d8e0a5139bdf015ef4e40f28eb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "3146ad00a5d67e722b1f15d9a696586bd2969a46bdcf808a0611917ef6468464"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "ba63b00e81e204575d203e087b366ebcffe17b2500395bcdd9eb188fc3670845"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "48c171149df8674e88247d48afd86c4ec5dd85957b61a6dee8ed6ba8f0845034"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "9898a2d3385a5d1ed5cb707b43f7696e0631cbd03a5e95f91dee5bc0371e5061"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "94ca186cf55d6d0710737021e39ce823c248062840fcb8fdae88509d0e66695f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "2081f088842223c3f5d96afc918c01108c32c3e3973490c6c12be2becadf75d5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "7932c5b8fb76ac97c50a1b1870b815bc69d637b967bb1df3c4b5e950fa652ce1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "94be279dec0dba36b48ea14376b8bc204940ec9ce5ba03f5beaad9a524a0dede"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "e5233ce2c257fdfa71bda361cc1744e674238b39b1505662cd75c2075f9921c0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "332f086d7a8e959b0e70b88afc59d3a4d3493704cb9c85ac809574c6da3292de"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "ece4436d7c83fec64352a762cdbf65ca5a583b5219deb0df5b335aa62ae31f3a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "21f170e6bf71c921a4d1b8ce46441ac80ee08fd557e7c0e25cfacaa28ccd2eee"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "283c766ec8ad1366425da5ffc5b5fe49ccc3b2d74c6ae1266c58b4c0b281b23c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "07a905a6ac5dc00893d6887d1c3d38d487d836b5b783cab613891faf6aaa4078"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "3e04056533c3514f459fc4ad6240dd7632a27754e170b2b3907e80abcb16b95b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "fa3696dee440902193913c18fac3dd34b6642a85b7e7a50ace234c4c8defb969"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "42f65330738647145961a6570b8311ca802b593104ec2ba34563efc6598bb48c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "61eeade68643ec5fde70a6833c972ba1591eff08fee7ce51adfd114c8f46890c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "0062e67e8ef13b16c05941b91d77d65d27860b6d82e5f740100393509e8f6a0e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "6a05db6f635159639305b4b623633021766a60508e925183a02ea05500a41e92"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "a7d7c316983e41b6369a7eed432e1ff03cdc1005e8693eba57887dd0202ecafd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "8e2f3691de7a1a34a84f0e8ace8fdf3c15818fcd044ddc3519de75cab0f6b9b5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "7e736ec236e2ae82d91384e3a63396fd783184437cfd15d28bdbe8b922391158"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "d169d6371f9bea1fcb4c2d6b331832154e5c415e6c5995fe7c9c7aeef43dde98"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "5e08e227f2fccccfa42768b93cf8a9cc9cc272f18ff8245782359d93fdc7f283"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "6bffb96b4ef4db684fffae93ae78632c3975fbb997243770dbb62dc2306ba9c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "38c9a3f980335ed4ff9153aefaf23e7918faa2ce70afd18ac6681737a219178d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e8f7397cf7220f78dbab3b764e0e7696e15f4a69f2461d3b6f5b2f79bdcd308e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6d26047250c028a82e214e609a6aa2fd729608c6d002e9d4bb580189fdecc026"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f3ad996df147da2d31ecf34d9f447d13ae442bb4c9dd9da489d851e2354022e6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "e3ade9d45ef6711f678dd61c277b9a49567e9d6a9b0ab465cb05edf8ee9f14a8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "cbad5fa9fa68d7e16ab6b64fc74fc657972cc3c7b3be89017b37a7ba025a48de"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "b8b7ebc19fb789d2d24041601dd25291dca65443f33411495310c3eded9fd85f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "73cacb9c08c65e811648b89216b78bf4491935232d27c13a2907a990e6dd2e91"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "81993bcf755bd9062bc9b14e7870b6146e61aa32d1652855fcc4f2e9646f78f6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "cd0c0c017277b1a510882a9724a7d0c18507c12600027274dbc2b08f6342c840"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4878173a3f01fa6f791bf2762a307326ba050a30486a63aa0cadaf91fa0822e0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "bfb6cb5ff8837b3535577ad7627fe64d1332b35b5cbd750a1e8a6ea34de69226"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9bc90a4c712832c24794073749127e9c05040ea8fb8283d9c604cfa1575c7a28"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "b56d57efb2bb3b80b126b9a1fb640c7de7dbde43a547c290248b6909d3c3dad1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "0256a787d19863f105516dc98adc784138fc3334516a9fff2a0c372ad4de9366"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c818ef98b53145513047a8fafe16b2735f7495bd509682a08e8a1507832236c5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "ecc9df100b0dd7ee8b23393d6a87499e01eeff2333f0a6357de72f7b2a52a129"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1dd1827ec9890d8824eaced16f512cfa88c05567a9cc628a1bf1ee5209ba04b5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "77e5226288e05af93c0535740424dd48c0a04e18f68805f8b9a8aae83213dc3c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "e244e2380de0ba20f8cdbeeebadc6a3a11b72cc6bb683b23110a154108d41b93"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "df2b5644c4a525f62d4e572b9bec424e6079b96ed184edbf8f0ef15497c112e1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "b8a63f62829f708547c1d6906c63000528ee148cd669445a5ca28b49abf68b86"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "8a64961472e9a7b903bfaeaa5c404c41262b22d27ccb205623963da088b785eb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "8f823bf06ed397435553e195fdfa04a6155ab686c52a7c2afb51b665675256b3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "7d79fadf64bde089027ce94f5bdaf6b2736400b66243d336151f41447c9b4566"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "ef64dbde5718202c8e0b6c3b666fb6c0df27c5fe054fc54e595c46888a51e037"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "5e2bd87d67f4f4ad289a7743fae5ffdd1d0a162f399fd04d2e2250e5064cf89d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "ef4ffa4a9bf1b4059a8d27796e49faeedf0eac5eb602bc3258b8372841cbd74b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "e4d9d45c8b5f8ba275e17e87d26b241037999c11f4dd5fb1c81dc7bf80096e7f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "58a8069047f5daa7df2db346d40c93ce3a6ccbb6b01f4eb5edf0b20e1ee5f3c4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "c1779cd61582d8404a6e10a70da007026220f68ce00e0bc489730877711246ab"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "966246f0d8ac696b5b9c65f94a388b68e329cdf702cf9b8b9e404c02ebb54514"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "07d36807ba9637a469f3beef1f7312648168a91cff67e4fd13545dc1617fbb3b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "442f084567891fe50cf73d880e2bf770d12e49280fdc70091156f656a96c5848"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "eb1fb769cb306de41406680474fceab4a8b728af25ab0d512548fdaddeff839c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "ad970a7799e7ec049330fb6653d1da9a880d760c699c51a9a5c9ba6fe710cf91"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "3ea7ceaea186e129e13937517c62696f8b68d93fa87ca5da022d0f9db290d22b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "bbafb8d1816cd0656fd2f5c4656d80e509d1236f3aab35d8d75648deb6b026e1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "dddde626ef858e9f721bb189808533f344db016c38a5a25fc3480d76e5f6ef33"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "7188be444e4197af8a0241deb9fefb6d69f9f97b4395aa2848156a39c664c651"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "04df469a953f5032c11163bcb660582e73d2e5ff0c01f63f64b6b239124f500e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "f09bcf64bf23a5ba930c74180aabbac48e14b73f7facd769869bde4c7c641ca8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "127afcee2035724717aa65096ddd2b69bfddc32068fddae0e4b3b3857cfef4c8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "f556dec012b1ce1eec1a7d018e07f83ba70f66e8c23ac34ebf4fdd3b62e80269"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "ae598b045bc3dc7d1c236f72198934cb5f57f86f09b59d8b0553cc37f9ef946b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "cccd1bb09c46740a6e88d8438708261f45db2202bc8c171e5bbbfc30d48530c4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "ac441447568e0390a1cfe78408ba3ba578fc46f4947eb24f2e9fabf7098a1db2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "3df9f00e2e2aba2b246ca8f1ae1f5b09d00945ba634adbf3884e5815e86bae0d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "ddf5aa8ddb114809c57b6f35f37b1d2ca1b7f88f73bcd24d5bbd4d7c74650289"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "5d28c62696aa9713ef7c59567184bbf46efd1cf5653dfa228fbaefdc5edb9ea7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "2921cacd54741d920e77e1dfbd7b31a05caf2ff35c77d64877fa0156e412241f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "b15d80a07e2b8c2c22698e66eab3af9e512d36a5e6b1d825c41c13115b2b9570"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "49d3b1edddc1d1eca10aa95e146a3a1cbc2f45700cee1210e381592d8d431487"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "60198594f084b92af80e0f891bae98d421b4d0614bb9d4f3fddc131b18f15fdb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "03c4ac91896c822915227edb2444565649f778002fe9dc4425bcb320bad3a572"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "31bc8b19868b9a5116bc0585a6365e5f56d407754bf768f45dfc08ac6a702798"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "30b8604a41aaf3a87be6bd606b572cb4346fe5f1f5f6d178bb713b60fcb240ba"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "996dc17a3574f310bef1c88b636253248b9534725bcff54951010a230a8d0b11"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "6febf690ef201bcd566ef74d050921f7ce57d2a6fa5739058a85bbb8290f7e06"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "6afe6219e0ab4b50857c87c0b375335d50a4d8fc44f714804d24e41a9b5bf3c4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "a64a82dab6b04210f61e8cd4cd059c426566e5317d57a2abd5504a6873d32016"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "479cdb24d820cf2a30aa784c6f1fc24060070e74ea6f1eda3a0521b72ff753ec"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "d7dec5e0a8fb4b18dca6a0b68371bc15f36d21e5594058a2c498126c263116bb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "ae1882dfd9b88ab634842457d49e7661d129132ffce9008d647b917d73958de0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "05ab63c7eea2856828e64e960dfdb3713c5090caa354921ec8e2f3c596c52685"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "1e18fa8d3d24048813abacf13e515f343dc85d8fc378cc8fc5e826b104e35ca0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d1dfaf9f46c9ff654390fe963140cc820d32545b3c588c74ee200e3f695d20da"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "48eb1b9a5eef847c4daf8b434d17626e429ed7f3f0dc763dbde85a50d9182dde"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "84bc6f667b7758a63c12171408d4411941d8e40e97565c8238f5bd5a64103a10"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "94457fd1ceaa7d0746bf4368fb32b5a11be923742d190ebe1a635ee33b25af68"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "dded29f0ceff971da74ddc1424aae4161aae369ac5c9f76374e2e8ff7d9e0fea"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "621ba924c7a1a9a3e3799f5ec0d66c2b6c832da8cf33b5d7962d8b27b30c148b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "e8af3a44db29b83471ad503e2f90ef2da2ca6cb5d828f636110b2299b851180a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "46f1b01353eb687410b64041c477f10b960e2a7af1f7f7e41a3bbabbf964bb6e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "cdce0389f7147abc31230a053c17d57c32f8b841e3a116918b66eb34859dab12"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "2be19240e8b2956e76eb2865c8041e2b3edae1ff692c3c862b1111a03cb539eb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "4e7d19b4e31ab432cb2d28ac64979c7e1fb862b80773fe60208c9a054005adfd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "08626f390b8262e6dc5bdfe4b1d28c937c06acbe9551585552fb6bda8c485370"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "1a2ecbfc8fd4cff947b0da7187d155a81ed260fc07fd27f4b9953fcf3bf0ab54"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "f03908453f73f699f749a79191572a9fcc59e72076eccff1103c7f964453c9dc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "7cbf0c213e2c09185628abe49a9957c16899f46b196971fa5ae3df53afac275e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "44a394646361bd5b48a8bd9951a1c5b575c6bc457b856f1f813fb6c8f7ac0aa0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "9573e8f372e2278b3ba2bfae45973acb79fbcf180536810b5dd36fdc692cbb7b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "df4cbed212a0dd768ca06ab5e9dd8c9e3d585ccdb493251bf0de42b2cf1b9101"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "d01cf531d84604ead2c8750027aeea69b4d7d67c40fde8f72a35b55133ecaa8d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "37724501c44cbaa6726ba693c2db9d42f9c95640eff79eef92fc30a891e2e491"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "8a5638eae36aeb02ebc69b07c189fcc8a23e924f2fa66cd6329bcf71d8bd5896"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "8cc25f903b807a52e7e95f2151cde184861ea84ea020ffffe186d31496314607"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "832ae6faa58d32ccb2019db80ea174668310286f9a2568040dcd2645acdd9983"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "532acd86effa0c1771895ffaa8d8c1426cb4c6e3874d6976b40fa85b1edc10df"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "72510f172fa8a0b4fc8a7c8553f8c58198f78ad0e7fcf5e60f30e18b06dbd68a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "45924a694594fb7c90f384aba903d28f1ba147403b5d2458c77d8ef83e7f269d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "048280ecc48951d7ac83b5ee2f89e2635c81a931f739654aea17689c38270a02"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "3c3fe0fa0a14663f3f8bbacf1f2cd45a3a4d8bd910531a2be39342e41d112ff2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "8230ae69bb607ad781d94661fbd2a9e1bb4acba3e8498d6d6553c19a27a7b95c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "ed5c5e0bd50458b9c748dd01d116d4bc549711ffe5afc6d056f1303021ac3aac"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "100fdeacf32145307cff793fe3f9fb5bf239ca0fa51b782c8ba98605e7dc8ce0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "3be14c44edb9224ea1595b5694d02475657fde49ab7169bcd6a9d8fac42cc41e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "8d59f8d6e6eb907e132c8c06dad7f2f6558a6d9baea4773ac2e48a4ec7cf171b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "03c0102f411fc10bc9982a9b58893eb790b8b30809d4bb474b61e4ebf56b12f8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "654457fc9ae4c2c1f97a1b0da40287e5989c0830f512483f7c33a78663237e48"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "ba71e8353382ee1f5c12ec7a6012487f63c7ba290a3f0592d5cf8ff35b680564"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "3dc245ee58f0def3e2957803aae460f3a3ed3aa7c8b3af6a3af1ed9301ef6bba"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "bb7316ca06b5b7d4231c7080d4bf60e0a28099572d3327f456d9e084c676d185"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "cba53db30a2952b9ea7d7bae06b3f29de7c1407878a7f3b5f05a3582430c105d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "d6f35c42b700fbc5f05ca9a21387b0c190fccf4fbbefdf3d72c892663838a250"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "55d56d34b73e84d37a80fb9c907477e48f9833ab8fa1ac355fab597f013f7c14"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "228ee60d9b345e4dd2cf7a9dc256201fef15966017b82d5a3f32a51e41673be6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "0332f74e0e79174e60a1959c36fb58a582f1a5b97ddb1cacdb54b259aadfb06c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "56ed7c4a544c55dbb6d2c85ef4b0e7947682f4df5c20966daf09ff7b4e75de0c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "25713409791acc0777a200e27be53e0a33bd04501d0fbecad3a35141bca1256a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "43fa6882a08678f86ff1bfc27beca70ecec21ba73bcca2bac007e0659a5460c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "25c3b38fa6e1a88f8a89051373c221c2a00311138d7725db8984b910c9569fc5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "d40deb70246a2f5379c19bc689e6dd1661fe004e0019a0f9f3de32068cf7bd6c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "567af11ce1dd2d9b291614ce3e5f17c95536297e8dc5e466c613215ebf820374"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "bc25786caafee8926b13f241a3155831d57027684df078fbd89aeac611542808"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "186749b0eea5598abcb1421e82f2f6363661638d9178654eff142d302e7963e4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "144c5994b5d454838c63aadb08f27959d82d88a55b6c8a9ad8308d03b3cf1409"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d2f7544d2bf7347a796834a1ef761256afbd1ed7adb3dd4184d4e9bc65ecec4e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "277e8115712ed3eae23091093f09c67b5ab0be2bea8e522830cab92543a64d13"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "0ab47a8abaefc84015ea87272c892236def1133c29dabac420d37b3c9c3c34b5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "db3e164f304900219a3a63b100693eca4c7d46178f2488c673e24b5af8c241f0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "af78991bfa14be2cbe092207901559e8562339770bcfc544348a0d83679c1b0c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "3188c2656bca119c8c61a3c536f4d4de28755eaa03ecf3e5d7349426abbd611f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "7d11a670b042e8dac8656e07a8bc2b0b5bf63898fd5bd51bc720037e18c9b07f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "5ef3c2c19a7e2b8eb395ee04d702a0d1351ad19168a8a15f40786ff68a705c1b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "b9486fb28a7cb2aee1b2aa8d638705da177db862e1fdeb9169a5d7746eabe6e6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "3b1654b54ca2c2baa907421209c224d44514a3e602473ce4bbac684fe8241310"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "84be7878744bfc7abad2e7950dd06f39da2ffb4d7832d36b5daa734b116c11a3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1b9572a7cb7e92134d99b758af5193267159d64c9de7891847b0accd79092041"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c076153068a67094f56fe111dec375be3349d15d7db6a44dc7897a87b7e3abfa"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c2c48993d023bff1404f2103c1d13d8031b5e64fc67a1e11188ad6602a4fa110"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "877d16e5ff6316848124ab22f4051bcaf3ee8dbb3a1f38af631c0e33aef5730d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "a399fc1855d487df7b0d6dae71fcfb49cbd62d25146826a5b9bef4c9cf5bb821"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "85adb32a01c62fc38e2f5406dae45232e5e77d547cd8340c3a6ea51c45131533"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "3c68a57b71865dfd75693ecb062d7e87e608d6f0367cdac19d88f578e37d738e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "2fd7241632964666debb83cce2b84301aac946c44a7eec8ac05fc5045155fb41"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "ac91d6bd0b56101d65567f03a1dd46ec6b35dc0edee97e4442638c5e4d21e3ca"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "f4d9e2c7ae85733ecb10ddaf82efe6b1e4a6463559b579464065e203d7a3570b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "1a6956b2f5f97cf095937cfb994df60109bb45a85c11902bd934158f81643d2b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "b114906b050e2f832c954283592549eacacd1af7bb6d525791ca66af0cf2f011"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "b4d9d6f2e5a57c6d56e6457f2cf9cbdb85fb579669345a3183256da7285930cd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "a8184e077900f3f0225ec33ceda24a1dd7c349e707e69a6645ddb1bca0cb6653"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "ad85d2f1c3e2fd62db74842b46016d3ea9874e6dcc91cea3721264e0d640a932"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "9c42f2fce731a5674ca36e17c1f72872a5cb160867784e8f26451db5159b048d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "4cdbf7c71170ad3a64da42f04f988a2a06897e49cb3d8e68e997d7d8c746bdc7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "05287912dea37525335c45560635c2a7291ebdde6e687106946db6e3ae89a788"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "0941bd55012aa9cfcee991760a9067c901480ce9e49639c60e749cdd44042ff6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "328381428d9ab6c22c129ca3e057f01eb94e5ba7fbafd6d9742ab9f75f877582"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ba0f298e7bb32add41ef1d842d78546ecad0f7f8c5d1c4c10098e37a3c9d8d4d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "cef0901e00d5964c68e3d9e6e56cfc443c7adaed5c12c886b15ceebb6af60591"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "56cc42ec5f1269279af1d7f285329dcb1a456b511bc07a7d55c81228558650d7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "431b344bf48f33d3ad1922f4e1577e83e576a3d7dd02356ef2649d178d3775a0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "b9ac774991760c906aa646fbf7f5c352343d3fe8f680d16c0962a26b9847f7b4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "93f1deedc5b1fe6582b64a9cab1df3f0ad0d8173f0c3b4da52eb11a0da1a8aac"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "302f2e64c0a50e1d03fcbb2fc9890e359f1498a9cd41336aafcebbe94115bd76"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "f92e4036e0ab437d355d80d9a1fdbfd9bf8c9c4f8fef217be144c560c31cb9c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "a55e18709106e4888471edc88234682ee1d2833fd46467acac9ce16bfaca8b3e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "dc4478a0458aba73e3194e9603228d777c07a1d3db6dffc6ad749b389149032a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "282515e421d35901d48431e41df486da3c94dee067661fbc5176d9a9512877a7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "702a8b602ae3ef3da1f966e590e683a747eb218d9744b1eda1c3f3d5ce07dcfa"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "f9644bd9978e529d66e90f2a4188874d1ca37036b9d4baa63b1c138d6817d80d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "91668f4321ef4448f3a42444f23bbf52c56904e84755b626794c4b8493c697fe"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "7f18ebe1d1998c6194b4e45cef2f9a5bc9120edf97c9e3eadc4d78d7f7ba84c8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "cef7f641f1036081651e059bb4fbb5d09c6493b8df56e6584ce31c1600de0e27"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "574821dd943f4e3b4d3567d240f320713010a8083513f678e11a8fb50140a922"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "1f9bcea3fe5300310c83bda088c7088af79e321d0c107d43f4c214161288cf6f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "33569a30386aee52d9579e254c1f2a9534a7bde0b09b90b3e7a7df378f60f43f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "985f06f3de2b424be7aee966023ad7ead57fc32c3bb635a8ad9a1fb3ecbfafa7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "3cfa9288d68eabbb9b880673c0eaa066fc79f18ab434ebbe31153a3d8cc9f0cc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "1197d72d00be7d130bc848754b0e6c7c8a183805c818af6e0874817ffedc583b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "99adfa5a3e0177b66a8277bcf8630bb42908b0e67e8c0272c8b94f70a98ac3f3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "59597c7b7e1c972664effc4325007816e32ce4147b2d4827b372b6fcc09fe601"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "72a102bc3843218fab774d9061b20faffdf756e2d504f9ab88bee11375b8f141"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ee04439b3508e89af9af5c3cb57df560a827248bcf86dee62e7f1665af3a2fb7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "e4169e9dbb37074dc002476ad430bf3d8283baef9617b9517bd20629b3c742b1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "ac45ca13640eb1b1e55711e378349aef84f2b37d7631dddadddcc3a5c5979982"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "0a66c874da9f9fe681897d42296a7404594cb5bb14404b7263d5b78c2f769cde"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "f7c42f39ada7a8de07d92e0a84bad5682f80fc3a253e99a148150927760a705f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "6c0a9de49eabd925a52ebc50db2edffdc3175a5b1f92b58e28501c828ef65c7d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "58ea9852056a5a470a8117ef00930f4fc07c15864dd728e606a9713f183ce803"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "dcb2a70495dcc28d0ec938963797407064224b23844036669db3fd628ab609e7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "b4220eb16b31187d3c182abee8683f0034992d61b31ddafc2ec8d0352fb82768"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "34691e0d2e3aca8a18a53624b70f35845e3e82c14c17365c1786e44a6b8b29af"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "c26a7530d124794364b934ac6b27ca191a2582c581b11218b0d9f99482f3b9c5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e424adaafa682b5b30b68e8bc9747e38b88f13287021091e0508418c3b936a4c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "6297f68e1b793c0ec68e70adbd8821a1fc1a6d00fe72545eb661cd973355e6e7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "dc97e7a9e701f65260e8397cbbd33666fbcbcb69046a7c3a48b27c6a86730353"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "0044636613e0d822c021b1285b98f0b51347f7d34f5fe7d7d012b8d5e9e3b9fc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "836bba494eec527e3a6c383b2c22eb128ae6b9767fdeb130f95cf3e5408434ed"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "b1f34af492b79b03e6f7bcc043ba92a341701a782d1c914302e5e4983f9f2379"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "f7dac8ccca489e117c3e4c00ce1a76141f978bfd82f12adcf293fbf70cf91b43"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "d0ee6623031cd9d4c0d07f32b0ea0a4c30d7ae1a47e8bffef7635f3e9f80bdc2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "f309835f471cb4a55458d954036b752e6cca9f2d43cac93f2c607974b80ed348"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "794c2325ec59cd6a7b7c299bd1bb406826fc92636f4c219491f7faf37322dafa"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "8d29bec6bf7454ad5716adf2e46b98cb390793904e4bc3546c1c5578b5157078"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "5906c6f2bab8605a430b29bf7b071698c3c610eb8535e2e1309e6ccd4b199d4e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "e3241588edd07aa6d9bb37d7464e9f814d87ac2cf74b710f3653b612d190a1ce"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "bc16d08748c323ffbd0e861e5f7160ea76d23c5cfa7d048c5f67537016eef552"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "c5cb6934ccf2be2fc151b47af364d4724196b71a66201a9d1a480ded5e9510fe"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "cae2b0b311b7dfb00b054c4b135e606681cde7b495ad8df90e161bf5350db1dc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "8447a44aed28957c4418d3055c7fd6cf785af7e77e468b2cbd7840961f34e8b8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "8440e00278f1cf384fd5ee5d2bd174a17351133d8c3857caab2bb4e9435ff265"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "47cd58bc70f1dca9243040bca1161b431d6c0b5543d5cb3026c86bfa6e1ad193"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "89d17cd2493173354761af762416c6ba97864efaaff7939864624e21444b8632"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "4d13cf4f648c547498079b765257c4cf890a3e6a1ebe55c4e2ffbefd00717777"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "cbd35b72d4be0506091a207481a3102d05e9a360725ad24a5792d6256a5df1a0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "b51776e07026fdfda79df4a884f57c3089cfff5995dbf899a3ca8db179c84e90"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "73b0287157c009c744ec07ede50d4eb6afa2368869b104b826f6597ac3be20cd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "b35c67d4e6a5c38021016bb26b848b9b8d3a8839e2cb90360c450e72a98bb69e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "ec41c8e8e8bf9e13a1bc9d12823867e9206c2b687b3d0d36bac17d824596d570"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "bcf6353fa3492504893852771fec2154dc4f83e98405d78eec5cdcd7aa3e50ab"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "95a6c91f4404e89461ca75974baedf3dbe45290675926c121a4909b360ceeeef"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "931dc449e295054f22c9f40af520fed37eab604784e44a19bf2130e568cc8b7f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "6febc790ad845796b5775781713d82b7591a0890a2c931ee1d09f6529da128b0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "87edb337bc5b3fbc59cacf6645f2fa026de4d3912376e47d5fdd8cd8a39c9dfc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "8d8644cf0c5c75c7176e5a986c44a0d3243a852e5b53262c29ac9db03f08105d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "00ef1b5e7e5b6e1378a0f7100060b4199ae6a86e529336c21f6161770f1239a7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "627fe83f2a339dc5326b8db8bbcda0a8391ca9e3d34e18007a0a7880374a54e4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "1050f2f612980f19831a01f5c1f35847992f03f84c0252db83c2c23c50e60695"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "3c030beb352013dba9cdf4a3d4b902ce2fb9bcd41e77acd5835c8e7445803c8d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "f6983b1e4d2c7331d21f376302819233589a9cfcb7de8bb8d572dbff6b9351bc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "07b10f7d80bc31c7a853e72fcbbb0d7008520598af1db5113da15a8fcb6c0cfc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "1a9652c3aa3663d1d9d3a15a5d829d6a79fbe9154eeab55c8112679f22c93ba4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "0df068d3f5e06da682b129aed1008ed17b3a60713cbd5079bb429d1c3ff5d082"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "0a9f15ca53b07b4e34f11701dae0cbc45c999eddbcfd691fc1eb815699203508"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "f509872a8718636079bc53ca0bfae0686a4c540e4d2bfef5b4467a00e9b143a5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "18e5949172ccaa5912ba7101f064f5e10d61e66559d0bacd38d8e43d24b873e8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "1d823a1b53dddc1aef23f168bf7c142a2c4f7f105296ed5cf3a0d296378cc931"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "97787d4ba86aa80ed35e99c3a3f32e5b3ee0af269ba9b37054ad2fc699f3faba"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "46203bfc129afe7e1039b4f045dd9e460ee88594639a388ab82e4f6c770175bc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "0838378ecbbbf16e6db58a9a72f5ce79595e5df1d33ab642f09058d4035c33f6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197056, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "39de3de9cd133c6530570f4c2cdba5cc702c139a6973b2e76c039b14421baca1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196880, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "24dd44325fb3306dd985136c9ddb6d5a9294531d6b97a7a3f925a7b5107cf5f3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197072, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ee404e8bd51e26c907214ec4e45a16e46d3eb389bc2d5a41a5cf9d4150cd9a1b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196896, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "6c6597079a026c696a017e73029f403c9780f994acb16032c8e42941dc8af064"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197056, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ff9142118ffcc9003813df5239fe745a58592c6fcfefc654184a23a6439157fc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196880, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e33198787fef3f6754bf6156e9839ad0ccf88f71ec815796d5b3ba6efe746281"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197072, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ac2a6bac6d0542604821cbfd0c950fe492533d090f34272d5cb5ac69c16b6d04"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196896, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "705ad0c196a4483f4a70da4587ff0557e1dbefa091850b0a8045b2b581df923e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "3f56c954e45fad57904a8581e344cce65aab73aa27fc79bd19e4234b1e39b535"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195176, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "87c197164c66b1be79529e409590f9e9e663b1f92e3ed370815cb2dc5fdadc92"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 224872, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "7bbb088b7acaf6318ab4e40b497242fb8f41c0e97ffc58302ac495c895936fb7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "f2d8b2ccf93c7e60c5eec31f0e142053958f89f630a8219d52f6765fb9eaacd9"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 180328, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "4bb146958766def39989eea7374be66b8a22f0e26314ba1cc4e7820215ee9566"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214128, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "be8e802ecd3c36bf7a526a3835aaa7037b095f31cea1b4b506af248cb3d66ed7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 186040, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "9d5fe763fc4612e897d6d784c9fd12ba9e29f00a22ff745f36d59704c6a8b94d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 205752, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "1150a8a8a41c0b85e09610543188c61d4ef9434dec85c6548900d0c4edfca1ec"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173168, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "f7d134184d379a9ae4de04f9c0f1ad8cafe80ca66430494e735f03e814a3f8a1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 176184, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "0b125977b73bcfafba6456bd0926c72340dbc60ffb392061638f2f8204242c1a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "57dcccc1278d9abcead0f347c0a5e42b7009ba1630de4b5126feebe8b6b32001"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "581611315f0f1d10657167e772f83f320f9f0ed0d7fb301d7b4275720ca95c2f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "dd3c116f0bb5e31151a15b14208f56f9f2589a5e3ffb0ea866b573ef1d0eadba"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "96399ef0e15a1315c018581efaba84a3817c4a39b2283e4c502827b40924b971"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "0c4bb3df71a4794db4b3da6661b5c302428d62ea8e8a63112e5a6a0381ec596f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "1ed541ef22c7eb7cd77663938faa2522cd4009b7d9a5148db5033b4883db4cbb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "3f5e6d75d02cae8f39e6956602dfdc5ca7cc958c69f5e16582719dd04bb6796a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "d24cc5c397e486b382979f21b0537c2a292b2350d50430f4dd12f1b7aa480034"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "d36f4ac478fc7e46cd8ad92a5b3ee9ce8c71542c943f979cbba809c5295dfb33"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "9cdfbf08910e26d2f470b45797e620530c0efaa57b598f93e4b84cd224385aaf"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214256, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "24d1508221fd0be6424b2ed71a30a0640a9e4770590dfe6406361d4a9d3a65ff"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen", 214080, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "5aa4b37b38db7119a389a970f9b1f76eed79fa42becd98274f14fbc2e915f9c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166160, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "621510a8b9d313d9f63284ff41d3cbbe2808bd96f36f38e5e21f6dda196aafac"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "8666d4c9f58f48191dd3e1f026037899590bfc9c9681faa4cc2cb0e5b0c615bc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen", 199952, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "2e8a7781ebec51e0faf88bacbb88dc228983cb0ac7ed92abb21436c1da495263"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "f5dd59239a655aa5ee69e5a8dd83b1c8d8e6a7b851f7f8fab40c7c3852c00d54"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 173296, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "26a7af616aa3fb005e449784229b7ba5d2bac4f6552e18b3505f186702257269"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 173120, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "043725f15b277a1bc510a9f64a0a8fb45c43bdc264099b19bf70fadfcbc7bdc9"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 149264, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "359ff086086dedc47e6ea508c375037328ef90daf5398feedad92d126490df23"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "809b8e50fe95ddec865b4c6a051fc21442909a557773db39d5c268c7a26b4355"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214272, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "ea6c87654c185199d0c6ea5719da3d04acc1a945378381e681dca6028852af4d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "da2290cd48de37fff56afe74680032fcd054cbbb6acc4219ec32f46aff892821"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 157024, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "1acc2b8ad80109983872322e289c6dba7157b1f4b57df69a777ac75b88b1943e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "b664459ee1cdfff32498563ca31eb21d8334b2a30175e2548650b13c4a009a3a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180832, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "03dfb708cae145b10da814e2eb00307a91d155a24509cb756bd4f1e8c6ae7048"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "0c620a0604de2c1152f75771c9f77e1ebffb0f0401584a6ad9d47c6d46556ede"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 173312, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "d384a30139254487da8582887dd2cf23c63bf410810ae4b08d99d4d919a4504a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "36655391f19c34fc31516c02ff127396cfa3675e79c7981b59680d14627503d4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 145120, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "6e716ca812b38280c2eb475b8fdd1e8653ff75525eb7cbc5e9b5deb708b46605"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "da1a2d14d448621cc0ffc560f4ebd1ffaecd20ee44ded87474175498469aeca5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "300babba9e858f8350d36fe8724c77e5955cba07b275ba9951c0b31020e54bb1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195176, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "855142a1fe99d2823045fe13749c738e7502ae197581dc2366a940fb77a76a8b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 224872, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "93b82782addbc9fd7199065f4aa4f9ada39c2e039fdca30c7796b299307bf15f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "7aeb546525acef78008eb4cd200e587aed9355f0b103f092cefe07af6f22dc7c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 180328, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "a6268caac6358cbd5e3a55b1b3852ebc92a31a52cfea89f3921e11b2d1b9ec1a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214128, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "9c1d6e671b5b26f6a21fa3a0691a57e05cc21bd9831f488a70d4943c276ab418"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 186040, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "c10ea67f8476bae0f6d93341a152ffbac76d4ac7d8627990c7ae55050a897714"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 205752, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "209531eb9214cfa7ec9a64029e6c525bc2337505a9c6f2c9b893171911565229"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173168, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "e048500b91796b70b8f516e36dea5d5c8a6d55b6d86e8173d52eb60020b9baff"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 176184, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "93d4779ddf87f0d4dc9a57ecfb82d56a629b36d68fef3674a2a033b6f1412967"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "02556c5462d37832bedf5d6a2def92c6c6343b3c1c98d08e14dcee9f3cfbb8d1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "ef80cbc65422210435540eea11ee330b77a624c4284c7f3e9de81febc3d0c106"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "603b818e2317582b4b80af2b30ed1890f9d7f3b0f257736c5cf6cc0155028616"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "9b8a69e0cfe5b23a4f8ebafd3f5cfbbfd91712112ce14175e47c21968c037b6e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "7eefb538ce504f4951edd653388bc6de24f22664252ed9a4e8a326fc78c2c65d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "d1a0d0ce9a0734b92256f4d12035b98c4515d0f684548007fa04369b2db6824f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "87de687e6aac24258b7f9411e1975c025d6cd8f5560ff79f9f667d6efedef4ca"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "48bc85bb457874736c3336fbc21e6cdccc9bb14e089e41d0303fcab49cc0af09"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "0a3fcc8cabec52fb9af3c790337329f4471a993ad149f9f0d2a18246731c7a10"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "7816ddefe35725eea6deb7984cfb2686d163148811c0bd59e52f30a033e1598c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214256, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "de5be428b6087d551cc1bd78ae999c0d187447fc8bb2242a0d4e374b3a6f20ec"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214080, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "50409d58b1ceead3792f2452d6ac869849e665dd828752534c437a7fe11d299c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166160, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "379ee58272b1dba34c3d116d8742fda53eda61db66eed87f5b1b478125d65f71"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "ffabccf9e31aad5f9b1f7c3e114476693078f71448029c95242100e3173741c4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 199952, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "3f3399b6b0b1faba06ec0dbb2da76a1c4726bb5ca4ea09e7dc7119c02adde908"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "4b30ff4cb7a35f9994e3c5f1cc41be007cd6f201d210a615fd7c71df725cac77"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 173296, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "0aab3fc9a939be3d4f5f0ab4ffbd167ebcac5b6a8f8a5d0d07c4a4304db9cdf1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 173120, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "077c5b48a9e61ac301cfd6daf46900aaf8954434fc68bff32d843ba0480b1fca"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 149264, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "1af2b0e8c0b61992d15be792947355794e9031b3e480d4dc27e208b6bc0dfda5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "ddbddf4b4a70df6ac65eb06b46171a57a8233404544a17802111105bc6f1cf44"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214272, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "c74114e6176d272560aa78e586d27c32ca1716a835db5308aa08e1ac78d83fd2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "3ead65b9a253a680d2f5024d5f79d25dfba430387a59d597dbafefa8bfcb15ad"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 157024, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "7a4a943ff3bfc61101048227f0e4d863cfa29a175093507cf7141a655c29e7e5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "5fa05de345eed5ca11f8bd5bd6e0bd0b43dbf7ca077495b582a356ed1ce6e90d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180832, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "7cd69f70a1aeec4cd8024f9114c3fb031b772a8420093cc8327aac3757fa718e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "716e237383db6a0954bed5d2a59492e8e7af86ec8e63fae2c91dbad787edd725"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 173312, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "971934451d5a98762a9f1c11b2a3df37f678aa85963d69d7ffab82a4aff34fc6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "7f0a674233b97cc61ffcc7b1ce7663bd10a6f91db68134c6621c7a3a90deec0f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 145120, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "b4b15dab7a6f6dd2910bdd8e61f8164c393e14f6b50c33a93c87e6e58fde655e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "ee11bc432bba494a4b0d6b4888f7b4d9604dc47c55a6c3fcd5a9f3213fcb6c58"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 212072, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "cb698c0895717cecbaef9be6dbd9b153d642f6189da11575f6c5f277d9a20022"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 224440, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "97ab5622296b91a835178296a41c1db7e0b3b05af45ada3ef87a04a8f526971e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 189032, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "d5897d0883e5829f5b60dc3272c1f1abb306d48f1101a178b05c7c3dd74d7c62"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 203448, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "4558ac2e02f03cd2acd8aad1d606747240174071fa1cc8e40237c342f2339d50"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 194744, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "820be3491bd4c15669233725effa78e7954004c22ec229273288129fd10dcea1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 207112, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "6446746c636db8994fe5e1da8e734af50ada50ae95597022c8fd42b0a247a248"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 180792, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "f1608fe11a642caebd1fc1f8bf1a0abdb3384356ed99849e0550217ac3d469e5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 195208, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "d6f0c303a223ea10400abd513de0fcd540905b313004b87f184ae9e0e248de98"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "8efcbe010fc5d75ab516d0db04abcc85e01129bf9b5c3024002ceb1a283135ec"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205920, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "10beda47c702e9e84041a870e8bf536f8df8b2e1fa232911ebc9f556e83f3764"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "34b7c91f9465eb297ef15f05fe74fdb60c435618c7226e09405b088b7aca3152"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "fcc10155318c570c5b289ab27134554022dc0d587f60e8fba0ca02cba071c9e7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "776024c404b0fc57b1269d6e3a0396e9938af2149c25c53a9bd2d78de41dc135"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "9d87795045f9dae70364bd9a6c561a427455491a1871436976e32c094fbae788"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "d04b1786225bb50956a3937453f52ca9da970f215e125e2641858c85ba9aaaa6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "33b3dcfdae71c201deaee1b68134394aa3a4e1d0b4f613bd7fd779b69a3c0d6f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "e2605a9c25cc3f28e0b388f40f9340677f9e7bb71b5f944c1c94af6822ebab8f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "1f6a96aa05e457b632711308cb65d82462e187adceb74c1a7230f2fd9646509a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "d27e568f719bd1fe16dfed8453e149fd3c02c48b0857c6be9b6c76f052a1de27"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "c2e99eab0bcaa3d30b1c6758aeab3625fb499345d3ff447663bfe73d0079c4ef"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 194912, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "09a300e024e8914ac6874bf12cab080b8dd6bbf0fc0783d78d29420692f85039"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "b0fdaaf2950ecc508790b2d474dc252264c6d65ba14f0b83e20dac09fa264525"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 206064, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "182eefb8c5eebdbed238c2d2647338240ff695a3ec0f346c22c8222f8e9cfc4c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 205888, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "e4378c67bda6a8d01c77d4b60c0d6a71d30b61f278b07a782541856bc501bb59"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "d7003bc54b0bc3c7cb1eb889a1e7425286b8e9db7f695cc3e22ac6e01d8dc430"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "dbff13ddcba28fba61a6297ced5d463ab463d700b00384003af85879ac7196f6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 171872, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "c74e5901e269787d7bd355f9b6a6725a5e6316851daca1d3576f82020a884751"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "c6249d52c70c450be2598d7828ce93daf93f5ee105fc0825e0d2bc8e7a320358"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "26948a717010ad8b776e56fd69c87f9f635db44399796d0121b63a0427f39c03"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "e49d079b78577844a33d902653331d27a5ee3c7377703a76c662e0343dc1595e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "5568b1168fb31614e5c318a209afa6cf9128d36bed3cd6c3c89add0d4df4d643"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "7d79bb0b0cfc0f4ffebd872112a2634ead38cb6c984dbff9a56defcc7d766270"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 206080, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "43687c3c352823846612ab7bf7f0ed18a4ded8bc8c88c0f249c5b7443d237e95"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "9fa95299854eabb2d1500a155c706400ae85bd91bf5a49417938871dd6d8ab06"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 149216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "969e4b8cfff6a3dfddeba10552372c35958278d06e7d6c0ac9fd0f8eb3809467"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "70436138c381ed8896adcbe34798753e1e8151e14faeb25678f6a85be2a327f8"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163632, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "9544437625c66dc10c7012be1f2a538dd1312de562a37d0a5de3fb230f088bb0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "daf1c936781549781afb675ba154d4db193ef396da321c955ff0d3d928af71f5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 198728, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "c1db3d511445fb1aaa5436bc3af4e4001bc923670f783690a0ab9d2217cf5b4b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 185032, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "e4c7e86a42c85511db319c2c0c703e2b8e54799e3503333055bdff84bd5f1e6b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "6c97abf34055d794f6a41682de7d0ef0790bbdcb2b6e252b205e72d8a37ca7c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "e45ac0be678547ca8efeca769a1466adb8051c830af018d98443ec65a6042360"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 169200, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "2faee2f820af39e7fc42cb59e493654812950b6256ef4d283b48c95d737a3496"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "c30b908fe88847e9eb5cb062c2bf84ed228a901301188cca7707f05a0fa0832c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 153456, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "a0536830c1ba66782c51fefd151dfe5a78dcaac772110796d5c633aeb3f576b5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "ae08c99880ff0696081b41b06da0773664504ec46a188fd22dd85d5131ccac94"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 211560, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "873592167b58f59094b1aaa9ba6116b11e43c55cf36724444d2cf0f0c19ff292"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 223928, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "9d415a69af1046089c4eb1e8e5037ee52b346f0e9e2dce121ce4303edaefedd4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188520, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "b18115b6c2f48099d9d9aa49f9d24a76f7a9baef97baba200ff09675cfaf661c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 202936, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "bcb99b8e5506626409017d1bfacc9adca46419387941bc6f5511078a3c141e53"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 194232, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "0e99e7b4f4c5d0672b95272068f1731c20b5bce4e91f9618e13dfe66333d1929"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 206600, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "bf0fbdd1d60fbac41978a796edaf9ea801b24785dd3d36fb751f91d475b64e2d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 180280, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "ab69ec59fd09f87b49511b0a903ce1bd67a70113f7efd35be7b3fdfeade16b5b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 194696, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "f397a6aa7b70b38dc1951a44f6d2c49b740b3813de43d59a7319711f2a49eb9e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 223880, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, false, false, false, "85ba599397462afbfda339a4fc0a045c98daff0cfcdf05c87926c0a20814a948"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "c80f1dcf9bb2a18a4f4e3553b9dfc20d1b646e5f00e13dc12955ead007c1abd0"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 223896, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, true, false, false, "29849b57060513c613996ec468b39440a2e4fa74263d11372735bebcddcfc728"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205920, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "4ab1afd7972291068c4889d7125b4f20617496509ff04f93accdcc20cc5a77f6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "7796e01cad0c34125a1a8d17fc7b7e5e07899a1ac27971dd0a79a9525092dc31"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "cbd77dfedcc2ffc003a4920d39f0462cc2fced2e60ada842a8b5e2b5b825a37f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "9b2377592bc9856ca81498ad6657851da351f4b4a0b4f37dee3934ef2d5e37dd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "369cf71678138b993e7495ba9f2f7f41b28d2731cc30fd3011dfde0db70166f6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "8a17b7e739ff570c2c306e4f4b4a2df3f4c005ea90f2814f18552edd2d796b7e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "276a1868b99c6e7196c42e041e3bfe83bfd9ecb03fe2bbaad509e7b606fcf56c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "2ca6cce1600469b8920694b0b9e13be7126d810d1665c5f5426a0c9eb863fb53"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "3f3b91814d49be15aac83889c94a98e4a5890cb5dc24e844aa0f6e581885c9ad"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "b6720078472eaf9546e60e321a5af2341f407402a3c65405aeec00559108898f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "99bf31a6ea80aeb27bde8f25a7f50e7aeeb6ba3dc4089a5b9fdf967ab8fd390a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 194912, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "30e9370887adde85d5b0f26c9450099e9949ecdc1beecacf6583a51a5ddd33a6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "7b442fd0f9ebbd8b54b536c165b3e98aeeab5408b63e9e37ab61b51244cee117"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 224040, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, false, false, false, "42f99a5f4e2c073a55cbf5f22df587d156be879c8f7aeee050d6f21f55a62821"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 206064, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "32ca30dfa0d51207ff87f0636a23a21b20204be3c90680e69d5920c8d68cbdf2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen", 223864, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, false, false, false, "b6a961ae7c7af25c612bc79b81112e8acba1ce91877c9d65b57dae56c7710a00"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 205888, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "8d8410cb1bff6836204e1e4ec5987f05768268094fe6bc98051ed2a33a63f943"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "d9a24be3af9edc2dc731726c3273750042e78543a3db4e0fcd788e51670c346a"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "7a25ac7a93d8917d9ec5f040cb4c4ce5d6512b8fae762cda8366024ea488e8a3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 171872, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "d03b5cb94191f20157b1c095b016614ac8f49a4f488dfdd87012a9b762da3942"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "1cc145d71e7cc91946efeacd99a06a405500ee99ce919da16b352e8f38adc1cd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "c74a785183acdb266c604cce29b02a96529477aca6bf4648d5e9e84e45096113"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "f7326a22605371cd983de47dc680f77ac137144bb09d71ef7dc8d409e5908b2e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "44c4a0b414f5f03142572eca150bb05795369f1448acf57d194dba76792c66c4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "f8a08263dd8231b108ddff80de869e23447dac4146692ed1ba2b480fbfb6f22c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen", 224056, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, true, false, false, "eda9dba2b3a19373bcf6917893375a8e4238aef5c37d396b1fc6ce6426199be6"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 206080, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "261cd6b8f36e0731975174e57e7b35392c49f70439d1e54309496d708de0c471"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 223880, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, true, false, false, "5ebfee6f6ff34b1022c14cef0489c69177132f84857f7a36823b59acb5f1ae99"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "2a717e957c32f24d12c22ac857409a13d3868c3bf31d6eb71e01214cf9a7f2db"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 149216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "f86928f331f436beade78904119359555a636cfe86e3d03420239b0a16d37cab"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "6091350003266b17b5f6fad66d82ad583db62a973436be92ed01eda4a2596ed5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163632, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "428786a202e70737c1afb3dd212dd6d9b80a776cd647bc7efc2cb063ea665fa2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "cf29747a0b14892a8057a88a52e22ed06eec16428ff3c9db44b0d134b1ec568b"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 198216, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "14c6c0ea2eddf91efacfc946d5491dd8e6a99baae8ca72b53c1102e2159f7b05"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 184520, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "8384e6e10f8d2e525ed4dace36e43c33694f05fcc95e54bee3b883feb98dc32e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 229256, 512, 2, 1, 1, 3, 0, 2, true, false, false, true, true, false, false, false, "e69c489d1d6f43cf03db7f1f20dce7230c7fb0929a549a3805e18ae929bf88f1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "986d78a1640bce9eea016fe54d9c2144908068605e02f9968f59204ad8f3f164"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "697a44b65745a1f9d644d140c5f291844997d3fd9e50f36ded6d5160deba0dd7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 169200, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "0c2200615b6f7f2983018b366f2b0906e52fc5429c89d8bc2e7be85bdc719eea"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "1298858ce3ae51a4e2462265d76137c005c26d79890cfb59bd7e556d7805a0a9"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 229416, 512, 2, 1, 1, 3, 1, 0, true, false, false, true, true, false, false, false, "a49f84d233523b4a3249c42ae49582e92a656c2bd63dbc144fefc8a6400621d2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen", 229240, 512, 2, 1, 1, 3, 0, 0, true, false, false, true, true, false, false, false, "c551d8e9777392018815eeda459c295398a95b7a3aac257b9215ec5199be1a11"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 153456, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "6b44e4c54eba60414d615242a0f9d0bb9e4eb2306916e153a1e8c0f0921f1eb3"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "7a8fa10dfe65cdf6eaf7549763f0e27cfa511e992488fdbab00d57105098ab1e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 211304, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "7b98149debf6bddc322a8838c58feaa13afa913355fd579e7e961652ba94dafd"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 223672, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "339d1021cb94e788f5c632d30c85aa76bfa9a9ce685c37de2456802d28d74b27"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188264, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "e64d583b9a2b021a1bfe67dd84bb0c0170869a6349337edb0de148d91ffda60e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 202680, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "3f9366b90a80f4c4bf5c73b9fa1c6707a9cf159b6b3b5ec8de866850e8582b4d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "d2862c46f255239a0bba9f30d5e1907f46bf74dcb54bb6c71a4cb88f24cede73"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 206344, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "cd7f146de1c57ae10524573dee3613e76802bcafb3e6d46038966054d2e7c17f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 180024, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "ef17c3ee5736517ff2074cf3f905d73e261baed50193b7e354df5f72792868c5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 194440, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "116b5a226f882a3dc6f084b03aa74b558fd21221e6a4bbdb61c3cae63db904bb"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "ae637682b783649e445895ca3339f9c8e42e6b7be78afd04dbc231d9495b9a61"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205920, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "1531424bc7ec33f25758c675bda2e1673f3e5631410e91066c3d7efd8a3ced57"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "fbb5a43ba17fb1213ce1e4a87aff147d215e7124447d85690c4f09f1f0fe2f6c"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "69f55e38dda08722a9705f3f003254a66292c1a5be158b7cbfe48f172bf23e47"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "df4dfc67efd751459015bacf39347c1e9ded0680e309be682c721c66f3ad205e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "0ddbcb374ce8b53d2e2bba3c756350d6d4a87e85595b6e4ab182860bc91236aa"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "e0ecd7c69a6f390633f9c592a565b41c579d2287cf876d04b0e436bb4f61ed43"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "75a5a472c7d4efcd4e2c418362f3fe73c01f87e5a88053f2be11a23c6373df11"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "b687c9d503d245a859aecac38d4577dbfd5a4bffcddbd3d3944c84bec3c21803"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "95446a4d6e2174c297c2c2ca24f0e57d2a62b620c9d1c5ef868c89fb893392c1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "831d7b6f2f761e05166a2fa4c0079e51c9913de18e706c1acb3fb5a359964921"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "5eb5b88e35df964ca7dd8585f9182a2c7e68670485bac34508d078c568656255"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 194912, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "c0ac4732c33cf9db7fbc96b29519d03086ff4330faf629d285a00f2b55ece4c4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "e67b521ef9a16fa02bc4fc5a1c9462c3f029b99058024ce1baf0fad9d150d862"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 206064, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "2e9221d06bad7fa66a2e4031cac138c4bac23313e5a9710cf3a5530503db9908"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 205888, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "0ce58c9e96382ad72a8d0cee38dc9303d8a0b6733665c9a7d28d61d67c5181a1"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "5863793dbbef5cf6d7b7dacd235a663851fe621deb6770b06001a80cb7bb8a4d"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "7378a34ea638326b771f91f39fed187406676745d02d4e0dfe03fc5ff6ea6403"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 171872, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a302a7856544ce9de1a41a0441cf55546dc84fd4af27790d28eab48633b08ebe"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "439ae402719c7d38e2e63d546593a3d02a43594b670210dcc7c02cdd021806ef"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "6dd033e7cd80b5107b71533dc1dc473c9c74f24644b97c0dfaaa55aa531b7212"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "1f5c67430bf3f854e689e9d849f85c6e62524ba3cf136873435af7cb35045795"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "36e7174c573488589e94feefe510510ac16b8bb27c95c226322e13e7a81b1a69"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "116cc241ddf55c19a692fe064ca2e39a24638e47fc9b0af591c8d8c3c09df4e7"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 206080, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "9f242188f02f1dacd33aded0508e10078f9f3c46cf5a60a7abd3170fe7213d23"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "89a0088d04e825f3fe7b854360f04353de4db166410c405f5cb37b057da057f5"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 149216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "024315f46b0957591dd0359704fe6bf31ef4a03b7d03b2a8892443a4f6ec0673"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "dd1144364a9cb9d2c8357739f6b45e6181fd5883a7b85b21bd66672e37154921"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163632, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "2dd8950db665ade69cce7e0498b8730756b8ad213917c9f6997211d875b198bc"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "319f05ab34890fc27b4f99cf5ea9c49f478e56862a080c0400cc1801ad0ff61e"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 197960, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "cc7937cdc05413f79c269859160ee2c95722fe22d8729258f87347e4e4f09d99"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 184264, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "9dd6128f628ae0e70305ea03375b53deccc98d0f17ebff6011f631a3c507f8fe"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "f12e2a148d91e4afcb41895c2de9122dcc72eef73e36d88f85538de832b0411f"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "c719800b9c36b17fc88472d026fe1f8c7add250b2bc0a55584ec5a2e9e287e40"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 169200, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "057e6012683052616899c91b837d6bba089d411f406323827b8c47ba06c477c4"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "e98413506515e66e6fb6a96c0ecd642857c9f58cb572a35e2d99f7ebd9895e76"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 153456, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "509da97b78b5c6a54ee812e4abca3c0721c76130486400a2b61a8a684d8d6ed2"}, -{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "6d5b597753573ef3ca50c211304ee73f8858bc2f5ec339c059d75bdd0673012d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "4edff69c10c5c4e9e695a6bf4fe50da8f7b22d4089cc8be057eb8675e637e08e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "881cb11877717f001aaf49774b6f66e9becf862b069bb7c1979b38d18883e706"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6bd6c109d413896f7f7b60688c1f1bdb7991be82d37150913c77be591a97b5c9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "43b90c6f7daebb65522b8aaa793b1cc4eaa490a08b781e2be1074450f35e5f36"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "85765c41388494d9153b478ee8eaafb33714e38157ddf06d31841a52a1de850a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d4a3168d97a8022dd416f065cbffdeeef46597bb103113856884fb65ec4b5d3c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "3d826c76f8a112f8bb80f5cfc1e154b8e93f336d97984f11fb100d8d37ffa07f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "6391e4125cb4f7fa39f0522bd4a9e704a2acad7ea56a13900b8c01eabf00003d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "6ebb535b7e9b34216385bf2589738511ba2876626f7d3eac3a7bfae4bcf6019e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "543f9925f2d2eb513161d27a4455718b7f56bb171d9e94561b9de124630afa28"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "1d8bbcc72c4887730dca2edfcf788c6482e1039987b7c1cc6329e7a4fcc101f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ea9ae8b0481aa227e2463dc9786f17903bc078fb898a17c09a49c962ce8f83d2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "36c5bf8a7b28ca33a21e1ce1dcc9eca9f6c4c8812be09acc246c594b5b257edf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "68135e1e05af48eab77ba80dfa1f24d165f00140a0aa29949a3375c3a8b7250e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "43cacb2e79ca30dc68e1149c6d15b872ce9b2246042026535c4884efa507e12e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "fa3d51e39ce69c8f5eb8f671e73ce10e1bc7508af15139152722bbb2154e1146"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "1b9752f4ae755dc10b3fbab138278d684496735078b45ef6f3ad5665c0c22aa7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "efd18201c18a0d547cbd0da112bc210f2ae1477e55f5eabc11f29691914989ac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "834e39bd48856d024ac61e55d5dce4a94b67f5f6e47b18b82b8e9554d8b2bec6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "90cfab3768909b77798280849b738d69793cbf4469ad9c4df0c8aca3b6c3cb00"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "386feeecbd644e5618ece9ca74f42020816952036c3cc43945190feb1419b707"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "5a6a57005b9ac8c9dd8f62e1603736a73dddcb197ba75e440a8863c4b1a69e01"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "5918a3d824d305241267439a893e7c9158f1d25a0e52a2e7c3fa2eabe3bbb643"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "d33185bf08ab0c7f6bd53f3f642817201c0cc8e892e8a62d457fc02f217d3577"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "55ad3696145fcfec943fff280154be789256bcbc05daa187107d245fb14fb162"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "bcc803e0dacd65d47f8c850c9a3958090bf4e3e0ad260a9d13ab9063a4943e1c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "cbe7b1bc2c2eafea69959ff5305c803bea25c0914135789cdb3c11f3ce182928"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "36e237df868e654f731c50b25bf6e495541e69e4e84ca83700b79e0819504410"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "7fb922218b3d7d88c69469a1412b43f097d5e2f70afd1ccb14de6d8b56dab758"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "e5d749a061444518bd73dd1c95adc7dfa9bed9b6c6a28e07724c46862f946427"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "6e8040f0a6c503251bc771ff1216511c22798fbf7191a5a99f5c5fe005a65c6e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "82e89cb0d1dee466fe4e28238cacd1bfc65641f7f4e03317661df5bb56825689"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b016499390cac2ed77de6bb3c982475d58b206c0faf9c2e5caa230efbb473c1d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "c9ab2d390c23458669f8b0f88bfe905886a66ca980128d9ac439e832f67b8b0d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "0f89db0a2b576145749969f448e476ed631f0630aa521b9b730f699b78fd2917"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "7c9c7437838e3e104d9e3131a35f5516a38a4443e2cb370aeeba575490e013e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "9d897bc29e70bef14cadaf52d09569654f3b6ebfe01e08a6c5c48baf218d5d21"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "56874271b8cc31fd083cad1ebb637b3fa104575c8a90bf428538c2a82a91ee04"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "3ec69e75968985bba6af5b91cf83d245429e65930791e2cdc63308dfe0bc623d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "667a2db67a6bd45890fb4ab8ff72f71d97305f7aeda520b65d6c5b2eaad13a08"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "bf72cdc822623b6e58b2437e385524978f83a065f4fa7bbd8308000ef3467ae4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "f5c8b7d2ed3d058f2210bc48c9a0d29578c6136c642efde970ec8631e9b1f3d9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d0da675669ccdc6c27dc8f1f73a28004a8951e833d5097872f893d992d7b6732"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "2cd03e98e926a84c8d7d7c2d0f800cb0eaf2a9f7f76ff3c5682161e97197afb5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "45795506e19021f30613bbc0da5fec66f0408de833c10314f312b22ad808c1d7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "76bf60d1359c8c1161d057f547faa76419b19ed223477f00f6720f66c06d4513"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "158a67554157cd62c35754e42ea467f04bf03a4071bf4077acac33c98632a560"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "e157138eae2a387e3e15cb008f5636b98fee2c6ea440aaa8b2d54488f2c350fb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "2d3cb4227a5210fcfdcdf5a720725b0f8f1b9a8fb8d334d5f1992aee0b211a13"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "db2fc18de32791e1e30619131d046fd4f92779c5eaad82a4fe7fc04a4322832e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "72581444be2d5f5b4fe4e3016b866893faf59f8907fd2ae0fb52369181f82831"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "c235cd8a70bce9870186a227180b9378f4af06db0266742278ae027ecc5956f7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "3d6e5f442b2c7ec56738f52da271d20de99b8f13f076611c09e580f3ef6968c7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "5b4a147dba431b00a9efe115cea378408362f539603392324b1eaa8ae5958e96"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "d8a57f895fcf3b1bf7ec07da67f006b4e28a56ef01a99a4bd1dcf88631716264"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "c9a4631b50aecfe569fca37fc5139489b655da791a36ec7c245cb8e0e99355f0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "55599843feadccff15a07eadd740a023dba49bf36f1854aac43e9050bd7491ee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "c46f2e113c671fc3d00ce2db90c900ad9f44938b8989270a0a308be0cf58c0b1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "0459321e91d8d109a94858e6dd471837fc91997bb779a53bad876c3e1333b1a2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "f4fb62cc4ecf9c7d5bc7220231ea99e244f57625d0b54e54408c98acfb978edc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "f57ed1c247725c51d71741b7c16c0b2a5ead3ea8ecf43e71f864092bfe3530f1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "cc10f07865162f9dda93c3d2d1e50b13b530d42198166a795116211ae183be51"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "cdac5e0f6952c4536d8da20fd185a1187f1a9aa9d22df6266b142e87be9271b5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "68904dc11472bbe95237359e289d366ceea1464a7949fd3b5d8c24c3d983f8ef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "82af388d03e262ba8244321c5f6c657470db754b1ac3f38ec499e57b0f188a75"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "873a9f9d961cbf7e659af834597aae66d0253a258b9b7dc983bcdf70fe7dd253"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "2bd55b0f1f9c7b0c54740a7b260db366b9c20dbac4d15d5f44b81cb89ad965da"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1c7fc9012843526aa4a6f0732e633f3f213dc4c7c2908e7f3e8ae388b3d0e944"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "8f231b5d8f44ca77cfc12ce2e4ab61717e297c2476a6cca8b43bf6a1775f05e7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "55a9db9a5d9386e9a741b27e625b3459adde14743c490c1cd6e98a30697542de"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "09e3cdf947e7df4eff7343dbb7f7446ab7fc19eb3ce612a5bf4a7b8fa589a2a7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "100406c0ecc83c95f19499c0b2a03130ccea66195257c74c3f4b04e7da158b7f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "62a62d76af3c4b71df2bcde9eaad2c852a034b214bf45d39ed6e410d2a0e273f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "2d170a9a16ecf790907769c2574ab805e67a20857ddbe4e3da4cf4c6fce7f8ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "767a9e1e37cafb73bcdb6a6bfcae20641d903bcc9ffd199985382e1b3b6520e4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "25b3c2eb41c70f545af36754c53850045ae360936b6ca9cb43549f50b41943bf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "b714f4e46a212c667ae6923abe372bb1f7117e99f437e586d762eda7a9655e7a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "2e8389d8840a593e090fe565cb7b5587ef89fca3a7ae0e666fc52c8c1f2eec92"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "0576d291f395efe995954da38bd998e2dcbf8ea5095c484ec96bd17d139ba4e4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "32aa8b13f6fee12d091a5471ebfc3f9a498b8f429007986fd079405f39a30740"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "1e34bbfe5d235c9925f39e6a945073d0eab2d1d19fb07de73204631488949928"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "6d352933474aa3cebcff7d8dce08f6c0064d0c9bd4b2e2c349d481a80e07cc61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "3f422020187aa05469536ceb04da71be392463aa9a646c61177b63a51e4dd74c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "3bdeac2cf4b1c044fbfdadf08b870fa0343498d5f398951dd469be6f51ba8242"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "a326e87b079a0f629175253a0c153f43ebd0716422e4d023f13d49980b206fcb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "f8748190b495c5fdc9e52079d374da34a4f841ed9fa5dd547e422a45465eedac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "8c7746f2713d2ba08125730cc44f291835604ddb9bafb8b14030ea610e1b3f2a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "469cffc4863b31a1f329612746ea5835bcb431e9795d8c62f6b356cc46ebd11e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "18a14f0387b8a9dae9ba21cec7c702b42f6c82c7a564e3d0be7b4c086b86b9ac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "784a641d0619dc3827ecdd31fbd8bb73579b24ea55dc72f4d6335e81a123f6ec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "0b67f35a389ed72b51a6032979c97ae8bb5042ad78983a2d24e997e9a93f42f0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "86494b1223b870d292f7f204f5387b5b8f3072d4eea448b6063afe4f69c79cf4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "2c23f265eb1b1c74d87ca04b7d285a52628a3454f8f96321a10f57361875fdc8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "16494511fbe82390b48e6f5bb359df50318ff1b45e5ba100be1fe571534159a7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "e367080e966027ae0fb8caf7f0240d15bd2b3048c3598b7f265d727e357e1c07"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "fc66be995843dd86a89a80d9edbc1fd82def8e07c665a891023f588b283b8983"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "dd2129d1e2e532d45da1889c04e5c98f2a0f51aeeac781ec6e03868b201201b7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "fd1d4dc60dfbf2523c17f9a15fa86d6e8a152b0951947a002d337d22484c1836"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "7599ef5416cb38f326df3643e3ca5d978f413b69b11bd98908d5d851d50c5515"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "9452ecb60b7fcd6b5592725325907ed7053c66ab15d06a51e183d6795a990987"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "58d93ff9b8c72bcc85fc9c4c3628dddb4494147580d71dc381fcaa6844a54fa6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "10b707c9c1f948857b396e59401ac918d41372fb0137bcffb3cc52b4e07a2db8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d81ee3f865eb724db9e7f62575589bdb284fa587c7da43e77eb757453b173999"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "532f9d91dfc7ec786e1cd7c707d5f70254be3d2c4bd010c6f1ed78e0ec67fbb8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "ab56c14f6a67e12d568d05d38efc647af8a93e5a628fd53d9684b36c22b49abb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "67f3334937ca3ab98e675685d939f8ca4d9a27cce12c908c1ac605d04fc654b6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "a9d019994c8faa5ed98b29dd092ef1550f46027139d715cff554d5c1de7926f7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "e225301862d940eb714269a610f3bf8637b91384ae15e440ac5906a2b471ff2c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "508caa410ff902526616e819d42a8d618c13b97756eaba676cb06f20ea0aa2ca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "f1001dbe1a1c68cdf98d479da078575d7f593c301409525e88b5ab3e563ab375"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "9c5fefcd7c4811670f16604b97cef942e8db042993d68b5f420916b69b684bfc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "be6303cfe1578d8bda7f05d6f89aa34655f16f43cf10990bee5d53ba90a749ca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "6d54c9b2f77e2d30aa7796cea944e06740b5ce06efe00d0b766cb743f6c1101c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "8ed1e41fde3400f48c81399b02d2a0573deab2fe0dfbd4b428b26cbffd616392"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "c3f5095cb07dbca152c24d0cde8ebc7cd0c558c2f770719c09efe4b326e6fab5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "ab4ab4f3ba4d55cf0a1ada4df4203bbe07816f9a896677d48f8747d13e5bd4d0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "a75f36420773d9ff6fd88635d4ae5ea080928ee35b139338efc1027d38f9ff82"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f79aad523178562e8babbcacc14f0b06c0ff47c675bd04ee7339f803443214e1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "95e14ebf8d372dd7b8865f855d039bd5bbeabc3aa1aed337cf5a0790bc6e0d94"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "5288c9b1150b1d812c1a84144de618bfa8efc2a0e6ca1d037da6d6bc8338e8f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d3052f09e7b508a85029c962e4f83eef78b262140b9928bcb780dfede74561a4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "62b696213121855b8a962ed2c9f14814f5cfe6292ebda7c04e238857e14e733a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "b4b6517d3d557009a6a6bec8b6394f01c4633de837ea7d5328b8c71421265630"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "5fefa2cf90fc964a835701cf227e6ce36676916997e0d7d03b8437b9cfa0dada"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "96757c926b6f7ff5b510c6cb40c08cafe5645342ce9e3afb5eb888e1441389d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f7534a6472a71173f2bba27ebc1df4bd67438160383a8b34019adf6a3d8619cf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "15c4e1c8507d5f08381ff95324029ff35f61a0aeffa868d024c46930d6bbf4c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1f9fa17d37bdcd9e8fa23443b685c74e946f07fb9b1480fe966697e51eb77273"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "6a425c629e47d8eac543e9799001b59269c2c1722ded579c701387cf40c657f6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "7a4aa0e8931abc91333e44afdb4cff372aff74cb21bce38dfdd48534ef382504"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c3a2af376dc23d76881aedc9406f03abcd430fb9aeb0c26a458b7ec6d03db080"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "e30ce7cd9a70fb9be51ece2f355b35bc5b872363de0e2c7c405344b6a82e3a90"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "e22c303b4d4a33095fa06da869278d6c4acb841f79b8aad0180f9985511c9461"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "6d9698441a4b77f6b7bef39b62d12e82f35688b13d9bb6aeffec8cdab7d26cad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "7b03dad33c3dca17ead0f3ae68f14b62df91fb959f3ecbae1c4bff0c2f74ab0f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "a6ba5b2f7475ec28ac426780a5c56591d364353435e7d99c60d3989cfdcc414e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "8635a38897ecc7dbdfce8ef3c19a6eef0b922bee18db3f923c032d3717dd348a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "6c0492bbf04bc64af849ba97342c1b2d1f1894a847efb3fcbf9073960c501886"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "a6e0ebcc9bc97f233bcdfd9ca40e4e70fa589013e73535787e2128083b0c1f6e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "afbfcdcc88e2224eea5dceae435f88ec91d156fe9698a7a073e4ae7a46b7ecbe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "733b4d85afde509cfbddfcd8ae378b56c5841ac434a3aa34c58c25655ec5b7b1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "26e1f21aa9d5f84b26c3608fa25db68da6cb6b23079fc55c46d4bc79227d1159"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "7d6c690e9e7dc4a21761069a3864045c1d135e5eb1a3823f56223ce1992d678b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "0f42e0b99654d806bb81231795e28963da126587ed4f8d87f96e7a36ad5d910d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "153cd204e901898f609de6f5953b31f9bcb744fad050907d4792ec886ab99521"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "81ee63534b0f6ca21a02cb44ba8b1f94d4987cc6cf3c5bc70fc10d7aa93bf800"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "ed95e38eb64c4032b0df04ee4ec9646ccd076ddd2a4d8f18057fc04cdbe4b0ef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "b2552efb147221035e9db497eb8af7968b1c7c32b877965da377b589edffd3fa"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "71358602ad7a0e0f836a51f0aef207b66c7cebab80ebab6978337c35a2109352"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "038ba7e208899d4c3c9d1c5450282356a56d3ae798c4e187bfe2b935a8db18f7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "d57dcb8f14184640be842e9662c9869e25ee4753f25696191944449bb36fefcb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "88083026749dac130cd3e6d6f7b21465d961d5d4c20d390f4b6097abba914849"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e1706f1bbc13fe0481310ff9686fadd503885dbd781594c86d7250ab9b07bed2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "e5d19f3851773d322649cc99fd6240470b63c55576384467b576cadd5871ad9a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "fd3b8a50025c5d95d1f806997620a815a4851b937b472ee832cdf099ce23da05"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "bd8fa1c02d10f8a529e3badd6f4ef21d045c89c15b2bc471c16ad4ad37b9b1bd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "72c0111512c54623b09ef9a8bdcacc742f34fd7d015f33914d9e48aa4bf6b832"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "85cc04d5a98689e6adf40359e60953258ed710fcc71d0076b81595aac99150dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "fc083d5962b4ae4c02d1de44ce4249d7de20d58002a175e20b769d1ca3757d3d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "a79fa89be6bf81d542e26afbfa4ebe82cb72213a4085f78426653e2c66b70262"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "f4c64b5549151126a85202a0157a2ed28929eea7f95717579fadeb7c37122590"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "1ced26129f082551fc7cec7c3f91128aaa9d91d333b32eaa6276e115a4a4a85f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "5b6e3f39b60187767225a39e5c869c61eee26603dc7848844791b7b3c59ee0e5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "be570c6e978922045b9356b4b99b8f28fa9695bb1cfa8df87d82fe90c246832c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8df2a02f85a8d648aed261d20be0559c1e18b5abbe74ec003681d74193d12817"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "4eefb9526aea6876a71f8e696a2e7437becb9c607050061cb7ccf1437ba7b084"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "766d3510a846afcd4f41da6e3c0aedaad38e3c4f1eac08f47bbafadbff2bd6b8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "d5e77b168b4f73aa5e881f8cc7aea4f322618a68377bce659077206e24131eef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ade884d2cf7efd31ada323cb862d69aa897b1b9360fc4807efd8831a8886d69f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "4987cac2569777b0b55de82e80774d1cd289a339e25e308646f5627c91ed1866"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "f883b0a2c9c591456d920f7131599c8c1bf4c6617fe8ed8d036bab4b3194e634"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "05a102913c7854531856cc37ea2df7e3a81c33319ba41c903e7d14cb4c7d7ae5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "fe71888cbbfd0917fe97d39ac6e3ebaf6397bc96b3f5e05abf853398186342f7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "ab556c09ee2c5835a05ec7ce014852d1f1cc0674f3f6c308452985dbb7762bd4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "77674e3b8cce04307816d4d31597f8d48b49e207d3c696e27d1c9be5f4d66ba4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "97a5ae4128e050914ed4c811a8458016ecacaf5c0af6acb637231995c8ff34b0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "6278556254d9f23eddbfc414099ade6b9e8928915b3c06c5611782deb5a97893"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "a444a2422863de3c511c038357e052d756b51e8a3541428ca7d22f3cf78215d1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "54a8210ec23cb4eff06f43e3f9ab2071c708568917f30f0763cfe33d7be4cfae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "b64818188e209e971fb20cf4014f52d98d2d5ff50609ffc24d673466639a6cb1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "fddce56fa8bba6c6dde6bdea6c12968d99ae887c0b4a3560eab3b695acf9802a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "c91055e0f840f7c94751a863d476f2e955183565449c05286077f47d00cce5c5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "e47acdd7b40eac21c65d36c60b1ed5b6a942425db4fea824a134e8a0f77bdbbe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "ece92f2fe3fc5fe5cedfd77b6c3660c196c9812e0542d40c6e7ca8eaea3c3f7f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "50150fd881dfb5204b438b4adb1f5aa3fa1d8fa5342b108cb9c5d946f7214d29"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "e34763ccd21e78a74940cd6c308e396e71c2cac2b0b4a046c74db3610225b205"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "03b3d723d639415eb4ddaca169254d94e2620bce11296106d73e961e38663334"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "6022ae2075a50652596b01af927008ba5ab7abf979494ff01f8ae595c59217b8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "e83b1dc0da03032c5c43592fdb664f82cff64510989234f616e46b90a5cebe4c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "6bf3172248461a8140a58ddb0ed1a1da2c2f8652255d6bb9489baa074e501039"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "478ef9b53da653f2b281fb7e9656a51617390539a8d92ff78f196523e5839a79"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "f034b30e482698abc96042cb0e289ec8a032d392379f6038a591d6da57b2097b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "7a454bb42b885dba11a641998230e420420e809c095e0d1ddcf2b158139a0250"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "57fa82fc9aee3529b6d276c559eba84b0fbfde56dd5c3222853ae0631f972fe6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "b3d1d05ca8190a28ec5227b372e8fd31f7045f86173d4d3daff3d2701695b398"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "5eb600bcd213b442f6a53c8d3f6d8a2964e911eec1ebf0d25db27b13fae09e96"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "f4feca3c082d7c38119266ff10e2a66cd2b474061b58f646625c7a01e366d8d1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "ee09e6e9d192f89352bffab90e63ee07a755ad27d585b7c6c9790487c96d2d75"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "2cec36389518a013bc0c5122f77a374afabd6c322377785fba4171390206c403"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "2de7e615e3c57a827d15d2f4534ecb432a2b56201751c7dfb20668b4c51f40fc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "0c81eb9eaaf172d1ca9749d4c603fc92f83ba6914b1fc77531e7e23eb72aec1b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "dc851567dcd55bdc4cb3610f62493f9153e7aecc459cc7cd1c531ddda5121b36"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "5c56e6685e96040ed494b86c1005f74f7373e152d928ac42d36f32fbf2c8113c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "d4065d51a8743b4ea52949b48c5065299cf296e8f4250ece92fbffd603e042aa"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "82bf647829d4a2675b7faf3c9e99fc7ac11e62ca15d5bdbbdb2b77e28e143cc0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "781ae6fd7620c10e2f2cdc2e0b8ef8add55434c17b823f791b7b90594e0da86e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "26ab135b7a6be65c77f0e1562fa543460f815fcceb8b5882c26fbc3375753ce2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "97d03ced92ab4fa802bb16caf9b0b90df435bead84813c5909ce548c63992093"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "a78f6af2406286ec03eca1e5f7ffdcbf1974f4bce16ae0c84fd7d08d42d38176"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "4472f2b89a9cb1eacb691122ea329f02d59867d78cb4909fc2f10e6d1d7ec14b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "215718621b0fd171db43d826e4a3be7b951c9b6ead450e5fabe7b114275e5ee0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "20af44ea06efe756e8661d12de71e6acc81b5d50d750a5462aebba07e89be02a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "a5ffc9a7b5041195861d64e09f95afebf02aa17039c1c7a6b842d982d06da9cb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "08c17065ff989ab36507a0f22d5d69928cdb4a062ec84afe660dc3661d7d6ab7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ebb4dd4d0be0d735c40549bafed0a7891326c76d4295e1f02a86b3a7a5cc19e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "30380f8c48470660ff605b7a3da4f0bdebd786c5fe39bad881157d4635f58dbf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "fbece3d029663ddd506801d000d6b14bce5df0f4ae51dba85e6dfa0eb60ec0d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "9064790fda9164a2c1ce59465903ff1eb1bc6b6d4c9cad3b39ef0e6a0ba07ff6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "9cdde0ab8061dad96b38c9fab4fea8feed8c8bd46f2cca56eb1707555d8910f9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "511e27699f6a97d80596fc7c7b3ac60d53a0907cb164db3e0fa21ce3067eb2e1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "dc20b3ba9ba5b4fa423b479591c3ad15592a56a1d6d776537a354fa47745ebbc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "766f4663491c63b2256a2d347898c512dec4132a1b8cb10227edcc02b08f37ee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "84a7e55f7a875a8503196ae97a63e773f8bf273d262b68b40c46f46503ba2f66"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "e306ccad06ff9c7421272ae4b5b675d3fb215ed75675edca7d0fe34ec017510c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "226f709788fcf948af196720e7a2cd0a78892f2878f2f4381ced84191f4d65a9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "72f51ad2297af692594864e05bcfe43bd02a54baaa4a05e23ea5e5f51444f12e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "06323faa344608214479a2b63998965fef679e307a45e30adbcf9448438482b5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "3ba62365d1df33a206a73f15a902e9ca61b9776b8722899e483b6f5abcf41c34"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ebaede5e6682b183897a6ecb0bf088713ea0fc703bb46fa087f5e5939eae50a2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d9264b931577d9b34b2060635459c986c48c1f1f82b736dc50ba44c4021d1247"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "9247dbf1b2faed2411e9fa3c7986f8340ceed532fea3a13d21cb81458d9511bf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "581ca383bb5f8a847698f69560610b221483a86349cedf53f05af0455077c05e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d66011498f4dab0dff601a188cdaecc334171da90f29f9472034b595f9ef28a8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "8cc97fc7ba0d7eb7f652350a955417c51354170e1c430df8fea6d9f1bc660f39"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ea30cfc231e02d37fc67ebc58373ea8568584c1acb13f2024bc35c54a35a1871"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "35d0b42c588ad585b2dbc03a1b67b489d39c5c78f1524a4108fe68462d6757e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "51f1ca9d9bda48d956cb4fdbc5406c4b48fa7926a82221ee08fd93058afbc956"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9cf701c832d17b3caf8015307151102792b40efb84320b12148cbcd5884ddab3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "e40ec37a808312f5fb182b0c3f399ed8bf2b549be77ebda1e08850dde50a6f56"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "631af7018a6a9a9914b8849d1fcef855dd02a9878fe0635f8e8fbb4dfb42bd9f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "fa6baccacfaf28580961ef2fdb7c7f170655495b5602c9c499de814cc880285d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "8ae7a07cd0e1e972d4d54cfb7dc4ef53d969d228fe56a12a2a8cfaa1fa5a5b60"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "4a038510eaea4ee85091a6fbd9dccf87ff1f6bfad17c2662216ba4238e3ccc2b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "71943ff5d93666053e2640c5cf6c8b13406b6423f22056792a8d277159252db3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "d5547146dfecadd94d217d107f11d473d248c9be4dcd45da67ad7494a4df1420"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "5f3521338ee8801b0ccfddbca004ab2de473fb1a375117bcb516087b2f48bc85"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "b058d0e7ba1e4809220f030e3ab869f65a81dbe300e09d31faf488d146e61121"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "c01de02b041c81e94bb7e5cf1ef4f8344c02c828ff824221c2eb0de371b07a2d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "916d7773887d188b9578fc97561b0ac21dfb1ee026b436b95fa631e309c07d8f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "2a835e685ffd18dc24636904a432d51c1a5489a80f8310c3317aea40f9bf7f8f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "118221b41b7b646f15e46e08060cefeaeae50ce3e237bc0bc44a8622f38019bf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "5102442baa73d42e3101cbddca88cfc1cef4dce474e69c1ea04f6df1d029953f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "94681fcf8579df2d4b06b0dbd740b0ed6407bc7e220dcd1baf74c5367272cb35"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e1ecc2b7049e9908fe1b015236d908a7c89fcd0c439029f577e88192040198f1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "1b19f6e2045a79c440e49d99f68c12e516523d5bfee7c0ed1e6d17e95d9b78d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "4486e5bf70cab1beb011345795983144d630b6d5c13f162f65bdbc0506514494"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c2869159589beee3fab6a799c08baab04f71e0770c0b00e6e101e3b2fba840f7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "5c9f423e709645e651b18c93165664f5fdac9518cd1f095dd3a4ddd8e9aa2942"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "2f761f137a8612ed73cb6f7b36c62bb0c6a5b9d03bb8cc0c3c05221248ffa02b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "f1a27caa24cfd11ef1e3cd743af4903a02dec0127dcc508e9b8c76b8a67d7357"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "412ab28ff11ead2bc22c4cb1d8ae400fe11ced817d001135f8d841debacfafe7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "f7935f6316ac1b1889c1bd80fbcb652250274df9fa366b02d0e342bf2d51aa89"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "ab5af0e361f5e2f7f040e39c5454fa5710a3b37dba24185e4e95a05cdc3f895e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "6e029003592c9be30e759c6748dd32595e0bf7567a3c5fc05338852b65987bc8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d7b80cecf63885a5e838fb444388fbee5e2501228fe87c6fe039dc0ec2d3252d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "d7b6cd00fbcb0195592d14e6a85b9d671d3f54db9060607c4eb343be9c6d7110"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "78e607b84faec6aef33436604fb62b44b9112b4b1fff150dc0249d54668e3be6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "892731cee405055b8909bdc2f6e93248c1d30bd763ccc92988ec80b859d2d44c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "4283ebf19ed911def646eaa728d01cae4afd76e8f147421f7286f9eb0925b7e0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "330cbae651a33c3199ba9116dfb4d3b0509633f56067e2f0ce125fa87597bc73"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "1d44e1b35325e336d253dee64f003f2df1c650ce21216a027c447af68d5479a9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "b0dacb4d6062459ef9efb543e30aae7ac8c2d75b3537036de89bb623b46a65d0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "febfbb006a1fc8dfc9a450e8ccdb73f19e6dd883e9a10530258d7a9af1a0e554"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "9418df0086c65e34a7b61f7c3e2dba53471b850ef0382b9b9804163dd8333431"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "a8985bf86a7e9d0f2132ce01e4dec6c252acf57853c4fe26deff043ff2f9ab98"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "0669d30ee4c0028c019b99316e886026efd8f722f5a09266d906f09062a86c9b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "fba329a802ef0537affbd82bbd5869c72a8ea7f1846363bbfa24978100491472"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "3662ba863f0d078feb0ddf50b3ebe5c5f1cb7d5273978ede47acd7467873c353"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "091d9a2ded68b01a600c1cfc5dccb645527edc38261ee9b96f0b54b179b160e9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "dcd222f3450414d7ef9a020cd468a1526ebf07714946cb0066926d629e989efe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "e963261370c9e9af852463be1c0b3fb10fa57994df42575b67fd05518c272496"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "ab0d8f3ace2604402e178de70753bd7cb94f8d656be5caa81d057dae47d4168b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "4582665cfb0224f5a6bae3b6b97c1d51532a00cb24c60378ca95229e9620f3f3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "00647ae026cb9b63ac02c6cf9b282afdb671084326e1bb2860df349b1c8448dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "fd758a516e39f77d77f4e890a965dacc6fc8575abaa69297092d1478196f286d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "44ac20bbe2eaf1fdfe899d709b0380d933aff6d4ba20e4d75a056da355155e02"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "1046f81dd3f58e4ebf49632e0909befcd9c54c2cc63eff2c691cb80593db5631"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "c1af78309cdc2b0f8a0afb7c95f0be5468a61d1aa73ac125d82c4e9e0cfd5b2c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "7840ee748d468bb5d02311b5ce7e45720fa9665a141ea00022cc36388bc2a803"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "992edab077d4f90e500733bb91a4e9e87938ecc1c1650f0a12dcfeff0737980e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "91d54c76438c91fb18906d27f5c5ee16747951fec2e70620a72a4199d2965b32"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "56180b932ce20e27b173956a7b9ffe26c779becfb67558aa0d7ba660afc66be8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "c2eb6e4e324c4ac84ef940ec7e04a86934ccf91d5958b81a91e39db23e0a1244"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "6aa1ea7716752d82858d9ed13c655578a6a9d1d5961496e0be9fdda345a62f2c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "5284e8c4ea44fefc9f862537db52055cd2ed07e148c4f5c2191f0dbc1b2c2902"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "75774f5b6f959b374ad45261cae796d21502ba2bfe2f94fd068b6c7cbdfa28c9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "11ee9ed5d866eba61a64c5363bd06a3b16d8e060f76f36c53b8ac7e7ee5b05ca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f3c442bbaa9be24847f5c5a1cdc3242bb86bdd8a2706dc5e9c1cbd258fae80f7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "41c24a78fab06cd4ae2b2efe93cf0bd733b0db948ad7041b8e9600bf853a26f9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "18709b4a59af330cfa95297e8fa0bb1d994085dbde1309a5a2fbcd7389085bd0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "2f5e40489111240a2ca324ce90ba300498f88e6be76d6a3c8c842bd3817a5c2e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "0135ea09eeafcc44fe8907d56b582dedf9c680128b6adcff8a360c1c3ba6ddf1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "b1113119e1b497cc8d55774af011b12143d01da3f1fb8a74dc1de5d92f107269"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "d3cdbdcc6dd03ee517c379ac19e0709153d64280c663b0a5cf65dba37f5ab20d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "787da5803177a1325365df25160734f9ae16f5228f6c923cfe4a8e5e84ffedd4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "94988480e9dd791b29589060bb4cd613807ce568661da1a8b46e4c5ce74ba32c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "f95ebbb4f1b109145a25ef50ec5771ee29dc6ccaefebf50bc41b88f2a68d8dec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "b39fa8b8f17eec4b4bde3ad8de5690af55ea4d4429f13738ce504ffb17519efe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "dd3bb138156fddc4b5d730b65bcb052312c44b649c0140fa1001673f20fd85d3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "6fc04e2eb4cd92d2017e77529c772279a5c34771e029cfcd82fd31491d848ed0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "29b5937e3847873506cafb68375496c3569a8c99dbc4d3e48432fab2b0006be7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "06d14c4f00a883e08e29f8005307bd65018e1ac7184a3fa2656c5b36da1b117a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "fd48adf6749514ac4878b22a919d716164cc42b70cd6281b2d59e7ef75be1130"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "81c2b983f05c32c8fdf8fce911e7d9f875b7d18139f4c07a33b658ada748532c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "a42ba764e852074143ea52c5b1a5828da7f2bfb702a12bad071766356a351a6e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "c33d21d102c46dac138ac666a4257550089691e91e3ec45d84f355d6cc228f11"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "c84cb6f57abb9ee6aee4dfb1dc5277a5e1a04731b4a8fbfddacc6a92c2632407"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "3463c4bdbce9e6baa5ce2bfc6adf0d0d7ba8bd787408f45f09926548f6a11cde"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "8895e3c627f32f74cdb0afb6a5df99065aa90e5a2987664f2adfb4a8efabc163"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "6b6a10486be55097a33da8c42f2804df257167110dcbd7f1cf1a19cd5de8b539"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "0f7b5fa7445b65d0efb03ac6cd4631e175a95ceacf6658fa68459c282ff3523e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "1d9f5eaad757eb94f3953f255f3e862ffd4953bbdfa3f665bdb8ccb578628f50"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "35935a44ae8ce1ec9bf4d7cab9157f182e5c46ac8461436743c4a65367915d37"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "a94630e909e27ee2ba15c528f229b527e97f84b3e98fe69e873d1bf00e6a6245"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "be670491147e0762aedd2dcfeeac95c4a4aeb3913bc5a69f253953c02323dc3d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "ffc7875cda7cf67212a0f97bf2d6b85f6d9d2f04ea757fe9fb7a4ad6228de66f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1a880fbba414467816160d2667805be7e3c5abbe4062e99b89e5c026970bc324"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "cf4dbf48bd759262f3f8bfb0bae4d85d2e488ea51571e7d62bb8d792daafa5fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "13375c5b13c18ac65fa59c74131a27c0614270b1db29380f1557dcb2078c2e3c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "55e94926051239e833c55ee8e1cd22ff3225dc52416a1c89dc0a35db31c9b561"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "5e463ad58e371ae0263858cd50a288d3fc1198d369535d849c1c6b01dd03683c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "04ecd0b3e4030bb719f6be233052b591df96b6e14d784e4085d35ce9461365de"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "3dcf5de5469f5d19a113053067ca4d54b910adbcdd210509db432a050f25fe6c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "7bcffcf7a7edac92a46128c7d77d63a7a126f65a282d42b91e2e91b714d2f6ce"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "be1cc90775a8b90c8103794d5cf63f0b3e133063d66f454dffa3d3cb49e0e7c7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "f12c97ca71303f820c2f3c851acf3ed90a09f9cff2e61c582416a414a4545c71"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "00ad62e5fdd8c4bfbc48a71a320448ee54efdb538e43f3317edda6d251d325e8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "69474bea4c4426e9ed994ef1f6fe82927469e4e5fcad970d724a88b47c21fca3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "d669511a86a87f2403de1a6ee431a7af9821257ca6b36df949e4b3afd5701952"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "31c53a71e30e97180f6fa237bc7bae964bdd0136c57253a608f6d025a660592d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "f7dbe1da6ec8f3f66695cd144b7b6f4668112ec4da46c05517c8451a06411387"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "5cf5d729f545f426c18f0a0c28222e3144b2b910d0b498f2a3f9532e968e1149"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "d132d53f67690a1204ac0a63f6184e1bf0bf0dd2cc265970256f537c773cdc2a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "6c4e7ae8b47cf65d5c81abc94475c5d758fc7066eb453a01d65e25def8dcf654"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "9ff81cf46794864bea4b735069aa51c2eceb2d0789fffd5b38a15a1d448ab75a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f4924a8d74b3784cbe2fd40e3ea420914e96294e3fadd72e0a07c912a95039ab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "d1b107b1287499b75ade4a75b6127f7554c54aa23d21586b48a6200cfa80ff51"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "ff6b3913f8bb00626dcebd98d0f8d8300ee954810e1f21e6d17be213d9781a40"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "5ae3e3969ddcf17b7ead5268f38bd90d942c5813cc65bd0c3d98f9c0515e03c8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "038b85a6ad2b475dd2af74daa515a9334cb710cb08f7f231d2c0859468e2be1a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c274f6623dbca310c7d00251e8a516bc9874dd978caf650bb196cfe91efd09e5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1b2a0a8b02f8ebca7fbdf22127455db08a4d3f175003de0a8d5829bab7843dab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "31d204a34f3c7868148c26b0539e4207aaf79cc796bd232a0f381b3e4d703287"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 199352, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "694001d69aacbb2c125129d07d783f61aaf538a2c65618cae1dbd59196979793"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216760, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "3a332683a4728e42433a76d2ca2045fa93cc4a2583f410443cc10949f33beae7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "1cbec7e00bad6ff5736eb3441a027e0de8bd9d342409d374b8f52e4a91d33faf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190648, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "9a9fa5ce4fa2a517578d40b965e5369a11ae390e4eab93da29809abc66ca6a3b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "8ddfa0f6a4bee76e1a5dd7755f64de9823eeb317c26d16ec5ff0727575cb9115"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 200472, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "499fab41b265cbffa114c1e5bd7e18880739dc4b48ee2455aa9b736a49b6d88a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 218136, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "f633632123140e262b8fcb887926f42591f9415643bada55131c622e4af52f77"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197840, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "456c5b34db4dcae23b322b1f11d8df31dc64c42ec11f6aac2c966d3c2d882b0e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 191640, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "0694fec7213cbd5f51ca90bc13190a4453b81f00de4e8ce9f88c05d615318959"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "3c73a8fd38c5793fcaa25f5ca32206e78ddf4f697a34f92034101f90730751ec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "e1addeeb39ace0f3bbf01d800d5509caab14626e9576337e7c2a59cfe482307b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "f553b21b4a1233d557fa6a3ce762dfc2e9fbe7230192500a5ffa8e0decf48f49"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "c65e5e019050ba3bad022e83e37226627884575e11d3345bd9deccb8183f5ee9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "1902e7efd51d7f7bd232c75a9b80fdfeda9a25a256f65c2511681911d5a07e9f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "804d5d018284fdf1451e168a27561e24afa06435db58c6ae03b48cd9f828241a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "2db038891d30b2d8f9b7de702493cd31c03d122d104f6c68bb20b86cc8165b44"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "c54e19772d27e62b9e6034ac61c43105f47a27fa25af219a91a2fcc11635ca38"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "4782fe7906dd21d88f2529a93e4bd747749a9516d2b915702c9bd2a633f61377"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "a3e992e0dd8586d4aa10aa70b7a00bd268535a7777f9acbae39ebb7eee60624d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214320, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "b65ab96867c515b1e4390c95baac55c85573aca0708049128587528b6e787ead"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen", 214144, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "84dd0c2cb4d252e8c70a3326f1da0c0013be98bb73e0ec467146628bfef0ec72"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 170336, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "817938c056bc3ae0c90c1e7a92a08442145ae56549171a85471ffe6a7061ada6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "c5f23a4492a0ddc0ae02856ac0b8fa89ab7566e84d9402b80f932c09e421278b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191840, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "14b3f4a517ed1d7aa1107965b6c07d8be99b7a777dc5855da4e362caec3fb7a4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "7874e861746d071b03e328c210a95c9d9585fb45f3b8c77caa2a9978a2ff9356"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 197968, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "af9aecdc95d1a8fea1ad324cef6833e082ca1374a3bcafb5d5fd48cb423a03ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 197792, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "4083d0a2282e56663043f70e2ab43ba4bdadac67ce86120b33a4f1db9c38eefc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 159584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "d1557d68aa4350299c3493c25ce54b67fdb242d013b20c6efe2c39138c44fbd7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "78c94ce7e143f85eb11b131cc6f4c31ba35f2cb36e87ea5b9b82b55fabb598c5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "506c8db1ed5e27f6c4257f4fddd0411f2d1928b3b7b0bdba444b25af21f94276"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "779815fc1c3ccb0f3f5745d7989369541145ca5c9f65fcc3d0becf2ea97a7a14"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 171456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "a86ce0dbb77495bbf68b1a34b5ae59529d3ae9fc7ec8e6ea79f7ce3b963324f1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "4dc07429c89d303633e14247808ff780dc5c2ea08bfbba4f11f49c7dba9536ee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 193216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "38c0f06cd55ad02d925f2a8310a49248862c14e083ade1be6cf3b45cc119625a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "8a3c7aabc819a4b71d7b810144ae9aa34261c56356ff49894610d95af9c75ef9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 197984, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "f57028a0c1dcd949d817350aca2584b0ea36104f92b33f024f475feb8b6a4981"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "1694b0c78855a3200ee5c7296fc1b50332f7684eed60f6a759c6c782fd50b749"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 160576, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "eccde6a5abd59dfdddd44bf60044613017905abfe41ef320d1d20b0ab848e6e8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "07267bc6ab64a5226cdbfae33ab4ff2ebbc608dcd1caad07b32063c97160ea37"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "7d85f060eac577931741b82861ea0dfca60c1ec6c3e39d6f5a00070395dc79ef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 199352, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "3d39f0cbcd7ad5b198ba7ab12465c7d8f3a024f436c1a1d0deedf2f50451146d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216760, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "48f0a70a980e6035c33dc42a554eff43bb348b204439a4b718dffbaac892cd1c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "d1e74b7f21e15d4ae0743e1f197ab3b4854b01eac4baef4973f713279fad06d7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190648, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "de77af315cbc9e30bc93710472aa956b3ec775927a720fb7cb6e6cc7f7969ae3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "a1a36e3cd8a4de9a7d6fcebce2f6351589598aed0660a1130845bcd1c9a3bafe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 200472, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "c37b1a50e2e1904d3b594d92d446e3286f8e2833e377c703d2f6b82cae3ec61e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 218136, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "f7ff882569fc8a713e368ee3180463a1ae76c7207972e751d4851e2c2eb1acd0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197840, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "da4f3c1e20bd458fd238a01301f1729cf12977bd74a030dc32d19a984fd432bc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 191640, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "be2ceb69eafdeef2ee8b2ad09b569ed6199d04f1eea947ec1589082acd7a632c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "68e8478a83169ef45917a762c77e3d2811a314617e6a080a08b4c009e292d90a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "81a5dd1f3ad383fcb6727232458c934d7d577408b35ca454b8a18df449204404"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "28e23ec42e02f4ca8a568d1d850b58194c604dfbb00dd00be8dcc4223b1735cd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "ed75b204bbf20b14a7982f5ed7376e48f653c6bdae99afc255a6ca51e6b035b0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "8a6e01482da956ed028cb69202bf5f54bafe0ce5c107298bcbd51232386742e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "86c957aa5a8f862cff7be19991368a453f9af9578c7cf412b509ff443ed4dc94"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "85422da96b59ed80b69763a7e9be9695d1479c57bf4679a691c3d8f81ae7ce6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "394da44b8e829fdb22c20777ee57391dd5144b7b9fcf01f23a086e7690bb9ebf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "940fa86e217611ccdaca485b2fc8765c21e2a43c0d16260cc1239dc5bce7b27c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "292c5c12e522d0fd0babe842f7aa2059b317e763ee9c059faf0197209fe978c8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214320, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "25051596fcdadf6641a992269c6b9de7a6cd08b143a0e6dbcde3d17e6ddae55a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214144, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "0a4d49d23157607f8d16a56195c1d1bb8e8be7905ba59fe6f01dadb6f2d418a3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 170336, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "8fba049be1e437da0d0272e1f557cbdce2bac1423dc97d83a80f6829c658f0a3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "61ff4983af8771182130aa339debc9923a0fc95aafaa1911dfcc552846a31e1e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191840, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "f7472634ddeb3960c2db889fe479f44c4a3684d363a80ea7b61c6fe12aef672e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "c70e609d997f676544295a8061800956bed9eba344b1f623595e2e1f8f14b84a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 197968, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "4ff054842ab0be8edc5c97691b7326c3d6662049a742e322483bfd83b15e0581"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 197792, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "47a4e308824aad6d4efb5df9115227910ad6fc7ddb42738ef2c8f744411d2b5d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 159584, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "08c3ff394b9c3a4ed0c0d1a72b009c0c354b3d9b84f01fadcf73748eb7deb86a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "321dd5957bd728d4267eefd6a04440642b953311f90fb7a24387d06f69afa7ab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "b6d444063c52eb817ffa8fd5e81de7150ba285306bb7d245fcfa0c606b62031f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "0ed6ca71998a8071ddc3ed63bbce48e5be2c5b285526d1aac30e0d7a2ba35a76"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 171456, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "b243f6efee87612e53fc4d7b58af2f5325bc0555be4ca11addaefc6566b19872"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "e2cf86474b56927682c0428d69f780d854d4251c957ba1c2fe00d6f416f8e117"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 193216, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "c4d71ac8b9c304010fdbd3cff1ab07da1468f2284ff7270d53ed0db5b4a3e40e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "1dce31d340c5b4a22d93f19f09414a399d778ddc38d1eee162618973330501bc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 197984, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "fda8da99523e221c66b1e2242fdc7481bff70cb9cd6f9a8d2990250603b5e105"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "6f3884839f7d73927c4e0b3aa7d67db8a824b65359b5355c1c83e4f37627c3d7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 160576, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "8f7d8e215cb42d4d4363ac033da4080f8d63057118e6ecc20eec76b5a1355bd2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "9175076d20a8fd1cb00beee2d1a2b6b1922307122a0e9ccc6ebede48e4944745"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 208056, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "badfdf5ddeb6dca558a19944900d69bacca97f2d1bed24450ce834677b079457"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 208200, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "b9bf4c85bde184b159d8dd69151a18bd6754622aea1ae3358ce10bd50e4caff7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "92c5e644ff722e440518df9933aea976c4a4dbddaadcbcac0a1f7693f93eefdc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 195400, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "5341366480b3ab79328abfd17575ac50aadaced201b9bf985c789be916eb847d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 209176, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "2a33f8277d969e3a4e55d53f327dcebbe11b2b5232e2eb20b5ac31acc5dd247b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 209320, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "f64726a9f2189b4cbd207b2783305b582f2edb8f2b6dcead48f99fe1e63d4b42"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 196248, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "f18c35a729473c0eaf1abddf597ea9db1eb05aa98a8e1ef11c556ac1fac04b40"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 196392, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "9b02d126d4d0fb23fb221f3b914c0608a526f61330763772433721ee02eac30f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "5a62128478ad688007b35025a89cd465ec2a907b12673fa731f31a40f863e0a6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "a51379e3a85acd49ff868f5b76aae78e774e99f94f227dd0ffb7aaed7e834fec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "10bf3ec35fd9f01cff1125abdc3ee275f77150b086280cfa80ecfca8b4f6ddd0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "834a542bbf582062168e80b4d3cbf3888d18ecee6449a967d9a218e1f709bb6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "59dfb355e065791a099398cff26ed725dcc354d44a8514e0454ea2ff68464bca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "062917ad440a05a294da38a162748fbe196bdbfd1dc0506d1ed9dee745499ff9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "9eb31fc74ccdad5813cf9bde222b789d5dee999a8c96b6245f1522edfd37a722"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "969712eb6e7c5288a8e97d35f700ff484695c0384ce8509e639278724b811179"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "97ee2bccd2294129649e01e85146f800a051c636587235de2e22df98b48b6dd5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "177513ecc018489cc15464be41aeef772c1117cd03ca2aa34bd5810a1e9125ef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 178528, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "0b19ea295a14ac0aff6d0a596aa6d7f98fa61c817c20d8da40188a6784b4c242"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "10e4dd321690771f6fc257e35b2a90b18449b09c97ae697040bd6ee24e9e4adf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 176624, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "aac953c93abbed385d2edbc12db08ccbfaa146ee15911b63f7817e9e3332c6b9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "348d88c2fe9ac1faf5b569d91a57631c547df144fe1fc710f721bca94be11c24"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "ae6650027ec061f2454ac4ce98e4364f575da83867d3ba6086d51ff34fdc4944"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "1b70ccf3703dfc41c48d8da094ba76e3fb0a6dadeb254996ca83770e28dcc3ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163680, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "3e45447a3c9059f1896af0843859e646e2bef4bc04ffe7b675500766e94b5b0f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "5851b0e1b9b8046dbe945082aaa650c5a001204909e0fbd825bad1feaa0ea036"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 162800, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "36814d740f88692d94fbb3d87f4fce367c09a21d4ee31b726b708716515b5f74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "53db380e34b876ad5a39d218f22d89d0aca3797c206b3ddedb046988bd4545e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 179648, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "68bc444b2a4cc494a1499a91eb453c7c801b6e0bcb6348df315c51a3a20c4c8b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "2a52815edac110e0715185f9e99f1708863235f37107e92558d33dd83c270213"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "6a938f6d807c1bd7807e65850812be18de6e11f008add822e225ca26deb617c2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "90e7a8dd2005edb6991a5492ce15a88e91a9f0229eda1a18df930f94c73bac1e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "f240fd2b8cbeed685645f384d0f05a5b1f4ef7e9c5dd4c01d5303c78203b88ee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "e12438ad5fe23c688340a87a1ac216902f52c13f68c2557b2e07f0b0933e0ffc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 164672, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "546bcca05801ee59a8d31b6cc92d35aafefc5eb46d644491000be23ef044d4a1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "28e176a4d7082402a9a31a9bfe0227812299b8c09f6ce6297a54373dc86b7a37"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163792, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "7d88e7d5c3b850a3526b4a339666b7986639e847abca6f52493e4dcad4aa2310"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "e22fb1a93b3b311601f7dd7c6fd1e210f4a0f9e5e119e595d289040cd1ca8ce7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213160, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "e6227308beb18c444f4b976fe156ae1ed63b68cfaf95f383fe805f7ff604ae14"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 200488, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "54a6c46d3d7253eccd77c1aa40a4480851e61dbf5ee887681fdd2fceec1819cd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "cd4920ad7c4903272af7d6ff272c803d5fedc90d559305bb75880d7741f54515"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "a8a6764c61e19fcbfaad15e04137464477cedcb23d5756a3010ca2ad595ec289"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 183632, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "66a6bcc8103dedd4689c129458d17f74e7f294c17d0c2c5cd15c03651a80590e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "b94938413f238c0a672baa3850f7a2ff10588a344b7a4d4c6112a0dc890f588e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 168912, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "95111e06c0cb9c1505124cd92ac0c2490386cd0f92b9f4c1c8a757d8a442e98a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "37f053f7cb976d0d5a57f59d521bcf28bdb4fb3c18cc2377c5ff8a4f6aeb0706"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 207544, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "7685fab7b08ad662fe3c954fda5a1b73c31ae9ab2e1586b5bc7d0a8682205fdb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 207688, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "8f2fd37be67f8814a07052d8f371692c774671645e1a6deea7007a05ffa225a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 194744, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "7e218271556930ddb6b5155b0f70fcea5f2b6b6421a2402e7fb8828eb9ed55b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 194888, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "8b145843224af39fd8ad6a83173b62be58ccbf631af9ff2228bfcbefacb3d842"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 208664, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "08429cf6c163c73b12d788d6995f801d592016f39803489a5e0ce6d0ab64a3a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 208808, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "87c23952911d4d63b7488fa47d7aea5aa96799796238774b0632d85cb1e71896"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 195736, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "90793486ba623d478c9e0d3665cbfabf0af680c08ecb2ba34363f7e2571126cc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 195880, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "989d3a4effb4e47b500e6e9b51a5c4b003c4d872d6965a0aa09c74696b59bad7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 207448, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, false, false, false, "f598ce08940ffac65e61f92bf8e9d4f315590ccd490caa9e6c059e1146dad691"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "e4a7158eaed9cd267a36747e341c715b2dcc6cc4f4e80729fb3bd8136c230c94"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 207464, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, true, false, false, "64bd8c3a925e6f37b3b022649fb4567d2ee7010fc97276b2b350853796269bfe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "2cac28f7cf6da786f35ed7defcfe363fffd4e6d20e531731d41854276df4b556"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "95c2d551ae8d8cca5ccee50fa0d6542de3ec64a03986ed1325336afe33236089"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "5536761af43c073d6eeeb7850a229d2bd9713a7d031a88288740eba90148de79"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "48dfcca981029d0b765b676970d83bfc93e7c519087be07b2ae40e4ad974c74a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "f93b12243714056d4d5510fe2c7d3da694c7fb52f84d0685bc57e4ba35db4750"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "4e75f65540dc1363339e0ea0462d4b66038896511fd51a0815fdeaa49dd176c0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "98c1bf36c3cee1c1457e72d9c06ac4d81631aa9545b68f201008219f67ffb01e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "30733f03a69b7f18aa397fa6ff577451d7c7932803ea1bc76196b98f35e4d9c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "d91058c6630760cd3d03b4ccf9be9b790822fedecdb7b6881de8fdd6aec453e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 178528, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "3bbf30df042f600a370d5a4954bbcbe7a0c316980b5b26d24f594efa6ea59e38"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "798b1c86bb240945a1b9cb96cf6237a88862a7ac712345f92153db361ecbd9d0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 176624, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "5023ca92af5c67ad511a2f57a061fc1acbe17f810cce83daf12f9e28855b815a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "a9de5af29ef2d068e5ef79073ed2bfad34edacb5bdf45d316cec776bc06ea1e4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 207608, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, false, false, false, "9fcdd3b740f4644089c42881da47fb38b88ede1c5b9fbfaa909e5a25a0f62877"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "e97171ce720fd44bc03f60d01304308643bbf0548ce446a77a6c4e55e1767f20"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen", 207432, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, false, false, false, "12e5cf4f66b4119bbc76dddc126d99e523fa9872ba2648695518c7531ea381b6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "634204f0a9a52d78d1fbc4ba1102ca66e4986b9d678b6c11b81e2e522a60a655"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163680, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "074b5d84035fdecf8e8e94cf7f362e9fa692a54205dda97509d97deaec09e019"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "1f31b8cb06fe3c1ab0082a0bece09f67a7ba999b93179bafb34a051167594262"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 162800, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "3bb1c619877fd96900c0c0653dc34936f41ed52aff9a9f08637a4da7d1da680b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "615b771754b88ca2cc4aec6e05567192310b2338233b32b5f24490f63d0dabc9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 179648, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "baa7930e711bc3844fcdebee59116b5eb9045adb6d627fac0609f39d3c75efe5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "d41e0ef07dab9b1d9417fc4864b3032a4421ecf1ca6332796b03b4ca6dc868ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "40fe0daf44ba4a5423f1e42d6376dca0abe0d71350c2f87e9f925f849276d646"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "24613ce0c9a64a06ae259acdcb903598153d5a56619250bef693bfdf6ad756e5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen", 207624, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, true, false, false, "d616b6a66d7a92c40acbb7692d8ec5d2fea168738e3d76c96b012acf957ef4f3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "8a12e53d577b8e09425de9435f01ee23373fba0f5e7b9579e0d788ed73db547a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 207448, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, true, false, false, "1a0ac038c239acd67493cbb78afee6a85f145c1c2e4d076ba317f3aa79f3036a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "ef8954c0da9a0a54a0d225bc04b964b5fe82060e0e75d7aff3b699023181dd02"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 164672, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "5b1bfb9da21ef460b909356db355fd1448bc6da17b6cc8e0246791413a2617ba"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "d061b5a06fe7d79a9b0a26af4cd0a47423dc7fe5331f96142cb60075a9c6e5a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163792, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "ebbbdae2d145348d2e1446e5f6dd712ac1c8ff968cfe1839fb41fa856ef044e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "c47ac33d115a49bfe1727ac07bbad66ecc29842c747a0f4d5a5042e4e5d96d1d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 212648, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "837c40d9d84b9e2cc2f9cbc5e9249a0d592fb63ad66e9b7ac5c62beb8580f160"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 199976, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "67f8998587cccaed0cedefd92e5c1b6c162ccd85b961a0a3f458066d020fe154"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 212824, 512, 2, 1, 1, 3, 0, 2, true, false, false, true, true, false, false, false, "78524a9e1405ea25f82a07aa46981140626e555dcbc68788e5292c7b6d704639"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "ddb9308bc045d181794465f251edb99b0fc4adbd89fa9faa913781068f0ae6a7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "ec33481cd4a9a15b56f991d9d203b7c9b34ed563306ea2701a2853bf82134924"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 183632, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "a8acddf8514ab43cfc29235d91f5df18b0c664620a860c92696a479def090426"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "b9a90975b3db28787f52599765e9e3d147383b64f99fd1c5f82ab03115f93ba2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 212984, 512, 2, 1, 1, 3, 1, 0, true, false, false, true, true, false, false, false, "ed4fc3fdfdaf163c29f4bb7d23454d1c29927f1f7effe7109bda242b23b5b98a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen", 212808, 512, 2, 1, 1, 3, 0, 0, true, false, false, true, true, false, false, false, "f0f24bd852061ea7ffe7d4eeb76428c023bc22bd98433b2cac91083d0bf4b683"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 168912, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "088cfbdf64704c26355148f5623d8c0cfe52d0f5c28ae5a6284d9744221c06f5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "f8a8ec1540fa9e7aa1c0f707d475f6d7730d5d1b4a6822215990ed496e473c6e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 207288, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "ce4e6c6a34828835cbd9e57a0ac6c1e8cfb8d79ddbf30af0e3d9716f5c82d9e9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 207432, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "2e720a6ae20de3d040e0d9d1affb52d0d43e2a9d8e7a28ec6e3e2a239987c718"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 194488, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "d33fb20d31c8a57ea31f3fd90d7d947b41e3907df03231ec4de278cb63916a74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 194632, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "7a8ddc6cfaae114037584febba7222071fc1c015da25dc0dfa23261005325b7f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 208408, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "9d6490a47b6a944451ed88e0886b313a7ff3c862ced3b0543311e962da531422"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 208552, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "4baf48d47a161b0f02239a5f04d9a896a92ea0df4945191b64d0958818f40cdd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 195480, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "9187c526ca6700d865af073eae01c276f29237ea2f103aa15b573f7cf02dd82f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 195624, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "40dec5731d1905f7c02292027d3b60b56965a0c910fb02046aa158ab5dd476c0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "531920bfbdabb4e2d0bb765bd3268fb76a35aa567d7e1d7ef70bc265b219f1e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "7434479aafa3d619cbdfd130bbeee28fb254908d26d535e5c1079367131553e8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "131c583e66da27f6e0942bfc56100002c131671a97eda1cbd7f309345ac5f9d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "6150c5140469be2cdb6f26fc66a2066d22fd362467e14be19de14d1e8f9957a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "2e55dad8b383e276b56dfbbc9bcc386e36fee7b486ff605db5c7df2c5fbe5c52"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "fba5076e8c776b74f476bab98c7f09865220c81e52b4ab122fa1a3dc2e6a0d2b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "86bb442e904b059963411daf2cb6b305651ae4c716a19d22771c95002c02c312"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "7ca4f89d4be358dccfefa3e951a6ebc8801601b7766e524c199e80baaf078dd6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "26099c44aceb39d4d2927b1c9733926606f3d50334d724e55733668b072960dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "ee2113f34815f78c9b960dfb25939b25cf3df738c0804fddf14f5c033cc9d875"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 178528, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "bf730ffaefecd80e3b6a77665d17443dc213fdaa2dd47d3a68c5cb6844074211"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "c1877b3f0a7e20de2af993d28dbd35110e374946c4ff6197895bc663cc87cd5f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 176624, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a8b2464346cb92669de8623723d1b21f825ec18c27f918b5d3d2a78ded1c4533"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "5ea6286192c9d5274dc561feced3aa3d0314e80f5db8afa19122bbf6db51a02e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "604a40c79afd9c0e314a36d9a405b1d1667953536f28cba601c6b5415e493237"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "3032091b886a4bfa6b7ff830cb975433c5892ba6174723e7b162f5dcddc96316"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163680, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "6f42692b76fe86cbcb8ca843df6e6152e00c4efc3fcd99f9859e80fc09df6e1e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "cb4b9ccd95a5a05366fbcdf65a3b04560f023233f2148a480c2c1028623bab46"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 162800, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "0708d8c1d94e52c64d156f69c38e36048b28d3b2c3f9d6ed544f52584a433bb3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "9ab2ef32c62857dc6c49bf15f41668f963e78e5f441e7d3ddeef1e1f53a85642"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 179648, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "08adaa6edf01342397cb33be24fca86d08484f72341dcb16cd6427f67cf1e3b1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "5359b3eb08700ea4556775bde25fbfc6f9934a32d5d959def2705ff310988b7d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "5dd62c688fbf55c71af4fb6c0aad23b48aee53d18274393f25a12028157b1ba4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "885a60ade65bb54be704299989875ed0fc8b6e871049114e7da9cfc3a7c8a18e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "59b917f95f6e3d2af1720e04d209cbbbc74c282c957e1bbaa56a5412093d5bc9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "d349dcf7292633d843d05611c74b67b625f83eacd5c22c4eb31ee1fb6156dbfc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 164672, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "6628df8af07b1f7043d0e43f074e99c746952f96513771fd5688afbe1668237f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "16f85ef87bd59e8b9aaaedeada1d8af42a73455a542563502c3c0ca6d38aaad8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163792, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "96f7ebddd9074c53b9f5352a27fd3e9102cc44ec95e7ce087a24b29095632438"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "24a52ae2bb4aa0071033084fa7f3ef7c2890d142febc869902630d9a873c099e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 212392, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "b435132cb629911eeb11c0263f25cec19d8cd9f6d6ca699e96ae562b96d922ca"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 199720, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "5d753fc73775a395e2ca6802e9f722b49f7a2470005f6c9cbfd1e0b7010565a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "5eae9bb9b5f8678880e520bd2b13e1fbd02f78ecb945e86575a5663935eed928"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "33b5a754457d5e7117bbe54582d2ce22ba68415ba90176f70b0001117e263b6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 183632, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "e8d0044c024a87551cf4e670ed482dac33ae972989e6c73355aa03b55f64732b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "612db8eb1408b794a8005888eff2c162d65eb0d968afceae01894e8c27460d2e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 168912, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "1a5ad770b506e1adf026516e16d21fefafdddc7c746a961b42f57449619639f5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "c757039261abc394d5029230359b88acf1783e54670beff25404fb2bf992c77b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "91a341ae1588ef280c9867b82fd4b281194a43707ae13c28df106626499ce885"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "86b4e448bc9742b553afd8945a746323113d9c881a9013fe0f97e71381af54c5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "92005afe08e5b20c259bb7d762c01ebf0bdd5c45cae3f858cca02b51041e1a63"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "7fc4c04e37c65314c623148268b505227a5d7e0527594a18a03f51abc81eefbf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ce40768ed269cdf5128610b5cc62f00cc5e541fa12c5732ad020cdceac13e244"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "cb6a5d829f2f9352901a8074d96e7a19b276920f81be8f1ccc6da7595171b469"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "4a17721bc298b5a26e50399a126afc0fd0d3f12723dd177403e79d4de29e51bd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "80f2d7d2e714523848c93efa652c0d0458fa44b5480c801addfeccad46cf6414"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "53c63a1788724baf065065b800169fa1a9ec243d881ca963d08edfc5c96e5917"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "2e185d3276d528d92f5aa7b1fbbc475371d62ed6b244d0373ba34ee2726dd1cc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "72a3961488f7472d325a4d5ccda3bd2298d3b090010b91a99e178572e8456624"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "791d0dcc1d2ec82ebc7c34026944d6424e53d06c8bef2a90f5682cafd4d64d0a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "465e440a26dbb2be7640c16c35a80d7c349c455821efa26c42d0bb18417bdc1c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "d00e6c38e8216981c34250a64d00f6b9db8f3ec0d0044bc62a6abdc818b589c6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "02e3ff6dead64010d9c2fb486b9b06a5b003252297f56556c732758e05f47754"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "f49c1e0b63229555f6e9b2d90c3fb55d59f494cd78622ad90543e1c5e704538e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "b4449eea83c3944ef09e1fb647bcb0ae0bd2dee9cfba2828db31e78246dec690"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "0e139d9e37c82591a789ede2e1fd7ba142825befad3bcf02196c2945fc5c614e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "09a6290c8e585ad27529b28915ec81bd21775e9a8560243feea114067b74cdac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "9016f366d8ea34f3cdd033fb6f47dc287c5c66b9cf35d5c8242489031cd91e86"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "11a7329166885cc5ad032b44ae376766275c7969c2d31b77deca6f181201383d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "cc7196dd2ac808a76c11d741fc6287d93e9f9dfa5ceb78767310268d0d34226a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "e6ebba3e45113e70c0f8e5070b87dc174658828409e825ec216b338917cb860c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "18891db6249b1630fb9a15a1d8c2ad1ba09152b6c44dbc0700d193a769171fb1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "395a7bf3dd2d33f07025282077f3ef86a4144686e8a0c6952386f225b9c3c557"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "e5572e51b64fb12099b62307091653f809575e0867acc72a9c487c77ccda9320"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "fa042ead1ca4883775c8b75bf0a146461af5ef1ddaef3fca6b6682db392b091f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "6e3375da6c33c35a5da3372fdb54f64847ed1c82e6c4f851b8f51a8b99fcf3d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "3420fd2a5bbb889771ae557bd3a1ba4ec47b2e9e58285d296a837f55e59ad7c8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "0e0a5c0846c47b67281b637a21484bf0c8fecf40b8644d31c6ebbcb074189daf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "7b46d561cb7a41bdc1fbfbbf948ecfc9430930db20e982cc9b8b624fa66ce750"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "037d38ef7be9e9ba7a8faa04556dec7b7f13e2a0f2d5d2d1e91183fc2f2ef5b3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a2363558b9917e7732927b337a7fa5419a565b79f7c2a78ba66f21f384faa5e0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "b6e0913748b01c543d459fe8f022600b8f6f71437460f9d49f9497504f432ff4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "f65cd0d4ef641c630257ae2d8ad4d1187249965ecf7ea03d10b66bfd709fb179"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "028fa1b4e93fd6b2fd95dd24ae283b376921ee36156ed9c21841af2fd20633ec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "83e8e141ecbda2b44912a74d5636ac767552ec13aa829c00249d28e455be6f07"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "1542acbc0be9b896b2d6e73ffb2b4729524ea68338d991f4dd079428af6b075d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d15f59259ebcc1a644a644121be7cefc407510aecbecca5c95cd6ddcc93afa9c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "da4e4f19c67e6771c4301682a3656b798c847e8fa5022b18d6bb3fa67174a2f0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "ef6a96ff9cc71486adf1a6b223564f0abb59ef165098efe27957c6fac56b6155"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "ec2588884c92d5a495288fec8af855558bdb19c4345d1816aec3ac7fc5cbae2d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "75c1f7503139da149d462a4e33d2331601c76f2136e891a0bd69c1fdafdaa408"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "4c9f399f5fa740c91cf919db475bc67392fc659318e6ab6565e3254cb16439f3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "47293541b97eeea1f1a1b9cc378f6f13d7722e60062ea2959c447aee4a244249"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "2c3aef8d1c648212ab27f1c6df8a0733750e65e6b874613524cf5e842656a6f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a7f4009cc17c2acec1db595f723d1556c3a356c605358d075528658cf7ad39d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "0d0d6b877367026f77fc245adf3c13ea63ab704c2a7bbf7377ef01c3a23cc95d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "153d1581d02de5ed23ef2bbd67e867621aa93c8008711489007aaea578cc9b09"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "337272419089ca89f8fb424e4d3e170b81746b6675be93d9280e566094be4031"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "bdcad2ed435da7c8fe2099f6c3e3063e0e03c41957d202470e630e028d25cc10"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "30128becdc6bc6f714ed00ccaf50ffee194e2b9b8944bcb3248d3d3b43e5f621"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "b7b128b016162c5d9200b903c30cfb72b42795bc327f6cedff54aa7a210de1f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "ceb4c0ff33e13d4d685ef85f952655a053a498b74f5b0ab3ac4fe9d8cce28431"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "58bbd90c9b1ca2ac513e1aa76e5f07efb98ffcb005bf260cf3aa0a525037aa0c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "d4cf888d369242ab15a0eca6709bbcce8a68cff5c6c45408e2a9cc1b2c21c4c2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "4cd48935b7e88bb2711dfd2e82d19d36f7895b5654a5563d0a4bf442454222bb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "accdaf49dca3d5c683700542b3bcd71f8309a0085a80d74b7abf5061a8895f84"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "992680f1ed1be4142062d739419afda0ea8fb37ef3dc597c59570964ead3ae3d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "fcb0a29397df9b27512e631f5b019032de0c0258f1ce6710ea29aa3d3dc71ac7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "4a4972b3b297a1952fabd08139afec9c8d7a42b30b35291e643675c61b2cd6fc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "249d307c213e5c61ae4f2238655daab83d026a01885e6fc8c176a01139b72658"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "07f78f383ad0caaebbb0320f7510525fac72d3170c69f4fc6f05f79359e74937"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "78175877ad66084c253404effb819b2d579f9892a8e71053bbe456cc6a4a88cc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "a1ca81871beecf28bcae1aa4e8cb9fea6ed639953c7231b0076f13cd4aa2c566"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "95c26f2eccb10878a7726b79581efafbe7fbc0a2e8dc92ff6b0e86b46a357a2f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "c32315e1e508338694e3d3b68c87187386fdd850e7c3c5dfa2546ab00f888240"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "8319c0d3597f6cb6554c57360b2606bb1f37d05969516ba230a51a07995371a0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "178e9e29234da9045150c89632b89ff15f3c0136f5adb4a60aacd55438a7efec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "aeae3cc4093e8633f4fe171070a24d7f0c135e07236a993335df62ea2a8e1512"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "13883c659814baab08dbd56fa9f5d3e2ed48e19231d676d0ed952a9ec3e78118"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "80c12ec73e00ccaa73df9dc4337b50b35d67b0b8ebd038066c233730e814af20"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "b47272cf4d28ecbaff6f55a3f56a500ca2c9ad67f15e399607da04b77f4a785f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "531b50c2415a69dca5def0fb99c9ac46948cdd534a5e771fc183849fb00eed1e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "3e8357b2ed6f00cc863a3356daba373bcde4c0ae300f63570c97248844c1bcf0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "9795334d7a0e2e63f7ba9cd160c12824712dcb20462de78d6e42d006c2c39fa9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "5d7ea34338d6b08e958e8e2cf300ce686b70504800de7c49f230c03113ced5bd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "ecd24179112dc018f143e556101b6b6594c761c83ba6eebc8a63754bf304f5ed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "d757e96750b55cf408777be021fee547828d9d142616940f7cbe2b0db7239a62"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "a1860203d6cb352658a9ba9b099b31f065e85a5e7ff6bc09378eded410320f9f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "fb8da06a5d559a30c3ac458bc73bae63244904bcb6269e6110d076106e6bf70b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "a32c3780f14e3516ec561c90ef2873b828e1aba037b052279a358bb85c0c43c7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "569e15e45dc8c8c85ea15b5e4f1390c265c44b4dc2bf942bc7fecd4352f97dc3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "78ff6f67df0ff1921935bbf58ff975cc077306e7d92738cda90c752cbe65c7ed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1acd3e9663be9b84eb8fe148813a24d449cb488e6329f306cb5ec4531f6d4d45"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "52561f3a1c909784878cf957c6008948e0d5563b5f564afb0b908e80870bca30"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "ddfed2ac0debffb465a81e23fd6a91bea0927f87ecb518d64111edf080f2c23f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "09c63b4eeb64f9bc9b3d417a3257ff3f4b0b5dbf5520c4c4d88dbd8aebebd636"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "60eebe85187039163980f0101dc1c42a0b9ce0e8a667ede4998f14e086cf74ce"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "a2c437a3d728f16a4b21b8fe0d41ad1654fccd733e2a584b96541fb13ca66861"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "e4dbbc8f9664f0ad6e983881f7380e07dd88a535881ea4706dbd5b765573f527"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "c6227f2c8633b58e8e95489b4dc335f3534d06d68e3fc9646cda3dbb2bb1a2d8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "a32f7a220d5259b85ed4231fea43ad6576a109ff26547e9834f1df8a0417e795"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "cfe39bc7b12b54edf5869104c6b2c7c2540258ae47b1458ebaaf822eea90c815"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "5f5c23e917f236df635c1402998f2ef03f5f9962d4f7830e83c0f952a37069ce"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "cf40f2219ee0c7408825e03d2d6bbd10246b2baea4af0de2130ad52ec4f227a9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "aab000c4abc493824a357ca3bec2bfb63cf47d061d7528d9440ae9fc74cfeb08"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "5e18c7c3a9985b35df0df99230af1b2ac41d593c0a7604578e75dce94cb11f61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "675214bc91cdf75276d980a724d85a08647416bd933a70c3ad1009047c761dd8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "117ec033631f895891df98765058f81883a03f7a61170aebd8ceaf84abda9e44"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "400e0ae519edcb2db4def2c0f081779215a21304c53467c70cb5ce13d27cd270"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "4376a50bfeb6b85988a4e52361bf652345a251d7009adb1395139c9ee28ca1b7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "f39f90a0a22caacf71bc9a5907ea64eadd57ba70bacc395918231aa5d355f3f6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "3f522059d403477a0e74cefbdbfabfe5c1435d8a39e66e05be70d657b2abb420"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "15c9ee08e502d213a64390c818f0a8891565951aa66cae8bd588121bfa062c7a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "84d3df39365c396d0268a60a7528028775ffc20e9e4ba60f696f36abbc331f20"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "13de820d0c0e3352ba6fd0ed8c8786dc73798bc88fbc92328604bec30669de98"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e26893854e1141e6fac360e1e9415e16877b759ce9d0b01f3feea7ff9229d9d3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "0b546b6b9724ef530031dcd281c312468d90c5c5766d083b3ded7d9d43cb09dd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "b387f233d3fe726b2582bf1e0b09475ca2cdc3368a6932cc72c2920955486594"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "e4ff5216643e830eb4be5fa0ecf9fc8069cf1dadc001fd384d16662a310731b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f1a7e302da749dd670206652ed2f8d82f6dd1fce6fa0b2e731820891e5c448f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "a67876163940f8172754e6514b15f7b02a19e594251f00a7a632f697d6529a34"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "03e54b9f01316efe3e8b5f54645766cfe2df29f7e583fc02b161a39957acdf2d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "f2606c1d4deb4adae110d6180a448212cfcdf8b967feabdd546899c823165cae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d26338268d63ff9736aeb2bc093b3ab23eab7d679cc252ea051e7832a6b02f9d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "73b184f01fa0c8ab9916870d1cb5ff713792e644ad55c34cb40aeddc16e24e5b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "65c178971b8e5fa2fde86445678944a7950921cb3346b8f9674e55da1d98c540"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "011090fa9ba777f98f064f906f74e5607e145d503412496cc262bbb8c06d06bc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "fb28385b4b43cc452fd1a552291a3b069bd4543b257216e9ca98559319333756"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "ab363e82cf960da58642fdb5b2ea86861c04e4cf98db4593bdb1d6d9797a7784"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "1eec1ff66f3c790e1c60743addb8018100f3e97188a3becc7dfc8ac47399664b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "354c8c8acf9f0709ffe25c5ec754301686cdf0a89ed502dafe6b489e39b32257"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "79a6ea02816f57c000bb900cd7033c858e3dd76a40a9949999e1686110434bdf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "02403d35972043e143243e2c2b8de7c75a2b3a684c2b0bf6b3e9288a392eaf8e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "9f440cdfdb60261a6cfe93b68b3f37e7ef5fdc5edf14b20e8f87d75195170b1f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "5fcbf6800dd811672ce9133686de1e0c2b90b38236875dacd4b25ae286583c4b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "0af2c2f91d0e24efef303cb60f95b5c24f1ce532a9a57960332a64641f2f2836"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "f37c9574852b049b383780d0cb79e847e070ea09b677270a20b557d2acf5484e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "4716353b0d5865031ac279f5374005fc7a5e3812cce3e65cafda387ff8ebd3f5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "ed284092ca1acaef1c1267f2ff539eae144c88fa5dc71526e053ee61f470c892"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "4938db32275b69ee3f17e0513c9599d7f8db5c1088b54aec9501570db1408231"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "125d709c0118a691d1bbdd4b1ef33390c0368c7f9352d60b917dc3b1bab03da8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "2db5a428a85953d105d20b3768cf62def1b6b2c50fabdd8477a02bff62c9bbfc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "52821df2e2a198d24ef6e99896efe746a7dc1eabe402932311f46e8df5d08587"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "7ff3014af2691c59349915b878b9e59af001cf414f3807dab2206ef7a145761e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d0c70860ad0ad0515b41b484764ea1584d861df72eafd3a4882068354d2abeed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "caaa3ff316b5f1577c0c8859cd41e74b3c96819fb5660be7a6b4332501bb2d4b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "deaa2d61004c4c2abc5d4249e0ae4ea66217f28b13aaacc934eca86a9769abe3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "9fd81c19be70d1a99b0902db38f8009f389ab0e416a4ee36aa6831bcdc99b25c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d97aaed38d409e156ac85b2f97e45632158898f972c0f9d2d6a2c1540022de79"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "569854fc17bf71aea91420760fc2af6748188b2d144cd5e3153a98ce38b53954"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "8153e67d998068f1950ab4e71c7c2c6b70c42435c49e7e2f72d8b84abefbdf67"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "375da65e2355b11daf878440329989ba74ad08519378e65ddd3c97784be63946"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "308cfa422139858e32bca8d410526e35a2441f5943448cb14b97565ae568c5a2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "8116dc5ef2433408d9b5ad86e0dab2774e7febdd833def9502ffa103dfe61579"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "3437ffc44dd90ba54b71d275ee9d18bf574bce50f6eed4c649de874afc6f71c1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "6b33dde1a581b6c5f6e44fde9a73e6197af6c194294d6a0fe27b78c1b489827e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "43386e2432cc694af320fbc4b8c65ffc184f1edd1f71e06ae537b8ce1bea3926"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "0eeb115be9bfe86ef345883a04eccb8bafb9193922b8f63dda0b52008d169727"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "9c222a1d3b7760b92e1559d95afe720e0ee55e716e94dd5db059d886c3e6d03e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "e38295b20acbae3a10f2e4bda808df74cf7a576384703621ec566c72c646f0ba"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "59a282e8ea7fec6818e83334db1ca33647174e36ba083e10188dfd9a9f0c9cff"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "093c04ee07c8dabb8e51aada26ca5202a2caab16a7606591a23c2b1ea07aca75"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "689404b42509e44e42571d654d82f0707b4e776942fe5a5ad7760eb92fd07efd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "56fcee8aa4970945ee0d20dd8a23dee613d53c2f82c5face6d09dbe1a4b002a6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "12409b2f2cd634f94a9bcd1aa6a6555444d5d426fd2aae299e8729ff12d831d3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "d154a1194bdac3094d3f47faf9feb6a7c27cf58f7f2620ff1843e4a1d47f4b38"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "784ceff20f82810fc5560e81512564ee1938d05868279ac86a4b7d74ffed424e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "56238324ea0e854d262cfd90930f522cd4afd7f5d0bd64a4ed9e25aa5012c5db"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "5f40ab40984266888e25bc2660d390b28095b1876750db0dde035510d6718563"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "a17cbe41ede5609ad4ebd0dafe5a0588d6f311a8135443102d1051abff6df4df"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "4ea16d65b4ef4ef0177e2c4243260ff73c7aea677d7b2a01887c28708f1fdd5f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "ab1439b25a76bd6a711b734374eb473191a173b9bd8f39e5efa17e63685347ee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "c24c106daecfe406cf9b841791da3e51afbb430e438c300cb7356ba6c3fa3519"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "e6f236e2aef74c459c0264b4c806e5bfd5656cad03245ecff345c5cde50c60f8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "68800d26ec575d994593c3032014c8b9bc1d06fc68f04f4544a4f5e3505cb348"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "106f98d0b437fe43f949aa89a9348d0018a1e5e7b4dd50f69ef6da8de6f39c24"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "409c551efa632075ba98df4f038e03e3d7d037cd2e585d45b5a890b736b3ad6f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "32136525d74e6381150e4b0529c462b60b4b460402907e5d3923089e04c63c05"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "684bf03cf5dbf54e7863b04a447b3645eb96345aa7a91ad5af6a668cbe472fc0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "85a77674ce5413d9adcc51ec6f53f1f4c6e71557ccea793ea51e4dbdf22a0cc5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "27d4d354c50eecd81669c85628333b9cf3d247b3824c98edd4d8f2b291241b7e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "d5a458819cf89a71c662ce5e884fcae2cc988a9351ddba3acb9eaa136e7ed047"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "9ebf5f9b2df0d1027131965d4daf64f8174497e4bb9f1e0b39541e0b21feb641"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "6c05c3d2f8d30a06fe9513fca36be02f42954d421bb7d8fd08f892315a506837"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "2d79feb7228de2431ceaccdf36666962d2c67fc9c22f96c77261c0a9bd615b7b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "321abdeff9010f6504dc65df4f4d598b848596e8aaadfbe1fa1acdee1e0915f3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "d34315d771ada1788c82ddfac01d79e6c84e01ddfbb7b509083d854702e74d48"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "1e80adc252bebcd1a8d00755123e875c45b463c7db957e0a87409fd7e58a74be"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "0a962c29f629d6f8575b67948d454cf3831992970936e93a782e1e39e53caada"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "79997439dc550011c516145f9b5fe894ce96457ac30e3d690c23aee5e21c5778"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "9462b09e3ccc190f25d9518806786f3eb5b58e230b018d8c1f888e0831b8ad02"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "3bb982498bc0003ea630706d229ca3899fda9083c008db7f6163e65dbc108e53"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "6e8dd6634be42aac07771b5e41bac77fb708ea8df8cd6bfde9c983a17fe103fc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "847b27b1cf7149d848ef8851a0f43100d219490283aa0b4d5c2f88e1f2277992"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "963e4e7621ecde4c767a9129c3ca4db207c23502a99da73facf7c3163aa4c93b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "d0303f1b39fd4196ba587ff61c701488434fbcf9d3106b5827cdb55778304360"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "78352672b06233953e3bba3f5b5b81b3409cf0fbca857cdcb0fd39a028e7b31c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "2ee7e964a4512ddbd459ee78cd3cca372985a79ae30ff8d3e1a217ced609e86c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "dff078144b9be8f7bf0eaadbfb45d4b4675a3d86a686f699ab0571ce3d30ed09"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "2ae2acf2f538a6708fac709f94a472f7bd742b620ac5fee230cfd08523bf1861"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "7523f582f82106d77e3b71bb20d3c45822ab0ecb14dbce45a5a42e9da0bd2c1f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "ab0d08b7a423983e3ba61deff1536dd24e926746b15c55b643067949b76809fb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "025b9909b9ca03cb32db9401d86214bdf84c69595c9dac62be3063580620e985"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "6bdab50040a8fa437a55f0b056f74456cfae28811fcd5ec7797620d400095a60"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "0f27db2de791fc05a67f0d10634e2fed77b1eeea3c5f5938ad477807138f6a7b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "3ce3b56f960c9f532027734587d565250f85124ea26ef7279fbae5ae33a191fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "4079597e8ec272244872da316cab6345ca507f87754035c85c48b99983dd569e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "f2c00ad6e857cee1c5b8a074912ee02aad9f8271e64c33c8da1665eb915d4c77"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "3a7181c219bc75a8501e7b5ecdceafb767e7ec431e2405827cea0fc50495db30"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "4172913a24c35e4ead0a4e3e1acaf884da62c9e62ed2e9b94e3943106a8bc785"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "97cef5dc1b7ef491674b030799757d391feb82491b9c78b88159a81a0453ccae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "9070cfbec3e2f871760b076d13ce8637212ac740d9bc21eaf3a2e44b1bd25612"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "64b4ac1958351f4feef4263e413bfe80d007599d3a419b0135b4960f32bf6b15"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "3e79e4bc9d2f3ed56c705dad1a1d41e681a8adb17a2522b64c87e3f2ff2ce448"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "b2102eb8339bfa9144da9487b89f20c7b950a181f6177913913dd5366f79a34e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "edf37f812cd7c5e6c7266aea5e10f88e56db1536feede83efd5b436bca2646a0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a04def50fd8685c3bcad04fc45c29bf19f2b21934c37a624260fc0b5713f2d74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "97b6f3cc5f27e6d2a21e5843f58838b16a549aa459bb5b5a792c5b0780380c99"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8cfe818f2aaf237e5e9f854fde1573cfa9a7ea64bc0417527d4d9ba913a06bdf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "abfe8f476b29cd4df48c4f1c5686c474bd9bb4d289e062b36557ea8f50b0e696"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "557426174a1ddce907b1d88c311680091e24fed61f31cc0b2946adb2b43054ac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "aa42050ddecbaea44f7b26e665e68791138036312d28ab65c2dd65a9e4a4a66e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "664559cc6e703b3ff6db05abaada7ae7e97a524bc9a048cb87ce03a73c4cabf9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0f139a580e48f14da99273effe1f318333d84ec4a2acd113cc15eb3fef29de68"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "93625ed18e58444f07a1afe3e07a39fa7de260b6763fb90aa3ff0217af21442d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "631e327f20e3f5535ac01556de8748823b55e61478960b0958bb8e9fbb7a7577"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "b5a7350697281ccef0ebdf29f686da34c3978faee790fc29341583cf37fcb6a9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "17f9397d591da6a4d78fa631355f0fdc2d36698a34eca26030440b0e89a0bf54"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "5d70d6aa9e802a6e4ac2d5b8ab43520bc0e28bd5be51c73deb98fc6f729414df"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "02ded9ad882d3b1674498783ad3f15d3671fd9ecbf0a7415e474e7772dec7e7b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "f30ad86c24032704c98a130fff2e76252bc815ae3f3c9d96091eea01915d807a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "85bd13b7375e7ef03fb56a2afe526764d7d0632baf39e23fbdd308de164a0aaf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "fc82de648ba35cd54fbb3f946ab3abfe28fc6e51da8755027fbd22029756d4dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "d5c4af580354caa0fa236ae524461553c0d775963fc51da762cf0a52671d7a3d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "63597ed034d9e1eca1ae9b805ace4c57d28f33ea5bd4d33d51123ce2f036bf5c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "2e067aef72a451aed715f16c57855c268bf1780be5f111b6e5f77e0625c65e35"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "807cac035e7d5b2fce2c11c89c0e4df2ff4cd13ffe995e18b244c5264c5ab924"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "810f89c7dab45d5e2d07b544e79d4e251aaa9985f9df22878b4f0437e5758d25"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "55dc0e0b97f37ad34c5c6251cb812c53bd8b701b8a99efad5aefd99437681895"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "5d2adf3ebe92c8550a992c36e002526d1836fc5524d6670db77fbd83dc513493"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c368a7583c2e734f9df60ec1b6a5d1b97ea74df1c1ab6628797f3752600518d6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "ef663829ded3016fdfaddb69f74ba3056975b71a9daf7bf4132b995d6d527a9c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "90d158dbb73db0b17db0f43f1c42558824599d8c9804f27b7370b6945eb06716"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "d567de6900027905492a7bf127449571c04c6bb449e2c09e773883f3e01d8755"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "b2cad1e268611c783db2688c71152e58132b7c0c6d72011f872a68effd5e26dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "768b6b0f80472de7922550e9ab5ef0566fa4d6b740d555335a7a7e31fc17842b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "dc5003825be40d514597dc4bf6c6cad4782068f7481d205025dca89dd660b15f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "b83eab3e67a986b74feb26a0a08ec28984bee1a7e652a398fc862a743888c1eb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "47af2a070d3ddfd81378d484902d13b72525094400fa7eca7cab202b13a4dadc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "64dad3231aec32efe84504f6d6c2e91832674f7dd4abb7bb5f23982e78f13bcc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7d30b03950dccbc0d4b986f7748424fc050acb790fb33c50457ef7062eb59cbf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "2726b3f727ced1a65d9c4b7970ddc8c2e398eb563ef05000b935cd2111b450c6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "856ef05c314abe6232390a5b0a1136843a490bd712e0653e58e617773d4103bf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "c7cd3bbeaa73bdc8cf788dfe32550baeee137a4932d741ad3bf73d8f5fdfab39"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "473bf162cdb747eca8949f63628dd9e43085db014a5624aa73daec22a7d8b1c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "fd65368143eeb6906bbe4816f63f6248308275b5538a4934ed786077897a23a3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "2d055ba2b32fae2cc55d271de89b600b880f510cece1759de6816af5c837e591"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "a24720047c8af28cda0b19aeebf8d1c578294208f4a455a0c6d95171c0b3952c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "e1ca2720028e1eda73ec06ac8c8389211e23f72da6ed702149535e4e5bbdd17c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "77f7694aef890bac5f0306099ce12e06fddedcdb1386feb85c2ca5fc7d16c625"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "b8fec3df1cb82940e9442d98ef301694157cd3ceb525ac6680ea4be1244928cb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "e2ce7f8cb7ac22bd18c97ef3ace43e93e912cd27eec85b2e6e7a5413cc3d2dd0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "3fb791a6fa850052ce71ac3d73f64f44b33bbecb8fa377ca7a03548574e44ba8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "217378801a20847e70b5e3fd8edfac5d03552228d8cc2143cb491e304dd51d35"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "49531b897f5f3b5bf1ef3b0eb689f7ae439c26e8605e73ff361654bc664e95b9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "930ca734594ebd1a0adfb47cb451fe8c24e1b6e5d73b4ac936af41a721cae363"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "9bc475956b50718beb370313a4925aefd4103094306c54b6418d7956dae8ded4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "bc109cf5365c0b347df21077011a41e08bb2f86bcbab4553e6c2ce38157aebd2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "b7044866682bc1974cf5f32b5c42cdde3078ed8d271f99e4f1199254137d163d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "b80c4683490b407736605791ab8174bbead423d3966a2fc45764822bfcd1b70e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "a135708a000168941aa88cd656083aeec71d41b85a168be1bae7d608b6f3870f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "057529efd4c5fa5605cd3cbca58977a72edbe8e0ec2ff5b3863bf7fe37d00f58"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "375c1191747a6dc64075198faad200054974b1602299731f16a45e961e515140"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d67d41b7abcba3109bdf4704980eb18be63a2fdc6c7db9d1571948c395abe932"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "cb991e7be648dd5a35ffa200282c60a133375bef12904f5873161d3cb1d256bc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "561aba61e0bf96650e0e7eae4e87189a5fa1d87cee75a14a341d2c38f080bfcf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "e2a267ee0484d35a7adae850a2fb689497ab37c834acda4cfa721b7013f2a251"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "0968c799adf44bef523e57810d7b3187f4441abd9909cc73beb5f20803f0374b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "04fe78173f4f19e6bdec60dcde900759c2144e51d1fc6e4638e018bb8e0e5906"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "802474b1bc2e6090ecc224a88a326c1f04309ffa23df5fa3baeadf2be4c48339"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "80e90b2a244cfab9aa8966e5bc57a5784a0b68789eb6ca90cae8e2f503944a14"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "c19773002d65d5e58e307da0b7b25d3e2f950f657e69bd6681914104ab7d68ff"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "b2accc5d025d797eb9369f2df6da836abbb5ee5fa84097ed2316fc1818a8aa0d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "c72dae4dbde02ab195f66797fe2e5145bb03ad9270854d95bedb9202022acd98"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "aa8a7754302efc8d63e3c1ed41f6842585dfd77ff1a173b813b73bf025b32872"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "2efd874ce4ebb4fa157604744e966563889b6cd8cccae38d702d048887eddf1b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "08647963e72692cb039c54cfa2a26afe7ae5ceb1422e5b965a5fe37c7132ad00"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "76a08538b7762a26d98dfbfc8e3276f748da2686e088869dc6cf78a1b4cc98a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "1ceff3ab7188bd1211f780242f0234c06a57ffa59dde49e320532df694f810ba"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "398007986a2b9d2290d6c93530f5b7cea40813eecebeb22e7e36ddd1f91abba0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "9075210e1666348f02e78812f0d053075411409b7d5b21574fb675d3d2dd17e3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "e0abeea9758f5587e536acbc3da4dc597dee90bfa5feb4798310260b99773fea"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "04a972a6961984fc8da2ed7947c16005465a0f513ff276676c84e336e68d31c5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "3f70a223c1b871365e49e46af671ec6eeded2a6fe333ff9f80350815334c946c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "75f4071adc4bb3d965e1899078bdec09e2c5ab9fc1839c9da9930ee2a5a7900e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "95ac53b9977e1e087df2b637c15eb369162a451fc7f1e316552e4baa4815396f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "8f9f89c5ef5968c4aea3ad2362b5346688a1d083801db28a87b11cb899a88926"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "156b527633308bf7f3284c582d8e65c81e1b64a4d8fec6aebcff029c4d6d3ad3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "adcc118c15173bd55a1c3d7ec848ce77f5adceb372482cc3961be1487530dd1d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "60b5500f6726277461bbb81f5155f20878a199a1c3a2e682dfebfa39faa938da"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1366096572d4ad05292806e4f3b9ec396a966e59974a18668d9c21021973ff97"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "52f155f5b5104fae718f28c86c1aec5ba8a842d7e769aeae3530a0cefbb9f513"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "98d445ccabc156761bc9c869d1436caa0ec803594c76e409a9df6d9d63263163"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "74c179496928251c11c4fc4137ac174260e7d418bb23482758e9b284bfc9cc4a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "40e9e13b0b970f81f1842be2d0e28e1416990ef6447f7f0b595e78006f0b616c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "d28fdff87b96217bdd84597961ba144fe5ae541a9d708cf83abe0faed8595fc1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "5eb6beff234e8bde08b62d23113bf69f3375d807639a3b21c91726691d1a1e03"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "34d81249dbadceacbb72727cde3974f15bddf7081f7c36e4350b979bd1611378"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "01881d2344951db3255a3d3ba49b88dffc2992e727ba13bb5f0ed633b732f2c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "5a1526242448ef14ce976ab3465cd325ae865db63ae96da0248374da60da8636"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ae7ad240b5bbb4d28be5ec8158add02ef7a7b81bf992e7b5ad9851783e9b4515"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "050c1bb5ff2b9923f14347fd4a7bba3aa27ef814b6455e3c8ba1a6becd4831b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "13ee7fa5a5dfd1cdd97805a51633276fa6e3016613f4ec2003ae4f333c3211a9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "ac67d01422fa394aa2b1825f08aff228c2f8b66b688f4a6b143a17d0d2292089"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "f6fcef1f520863e4859be83e2b46f4cc7ae71f460aa1594af9993927777c4dbe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "166036ea6ab67ee59339cee5fc653caac17dce5125f4d2465609441d6916e51a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "aeff09c9a3b71217fd0bb065827bc5492a4e5c4a9e9259c111350804890b85b0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "c1ffed84b98f73c6c8cd3f3bc39a74a008711e8a5c87c244c7f030e5faeac2c1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "c3ff8d8419fb414b51f8b807f1978d4a395cac4954b2c78173a4507fa3e2e7b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "e5c0e5bb4796865776eceda8e05c6afedfc462de58a1445e7d688bfa89bad21d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "cbd2eabdb6fce53ea51e8c07a19e1e938636974a185cb43550360834a902a9ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "6333184750b14531faa273c12e56f04c9285151bd50abf63c72a58837ef70ca9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "34654bca827401115eb388429428daad76c876f25c232678dbb6a599a89965e0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e508c01a236c3c7e6f2c07c777d86634c1cf5772acfe3e634e47eed3e384ce9f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "bdd073c93b14db25b8f025ffb74002ae967549840d23e288901b728e4f366bdc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "ac55d39ca7a984fff3493347860cca1a42034e3005b4aaddf4317e84a89e6a93"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "5a28b913ad5016066d9e55e9804973b2e8077f38aab8445ff35e9dfd39fb81c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c1a720b007a8834b71f04709730ec86aa2df897f924460315e7a1d40b4fbf960"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "55772665de64612874f34678289f209f50e9f66107bb2cae697f0ba76a51b8be"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "3a07229d6b6c2bc3fb25fb8443987182331298ec5781b09d70ad8446a84894b9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "3d3bc4345da4e3948192bf187fb4de9bc03ea7ada8c24e221deb3dcc4d8fa7d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "864ee5317309c552575a8517fef9003fd0f326966d6f7325617ffbb365a71ac2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "a760f524e8c95d2e6a24dd8cb68e4be1d5aad7c2468748cf64c7645c8abad310"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "34f322b78fa13bf18dbef0e050e7b76bd920e5ea385e78821e6ab69132123749"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "9e3695dd82c678924a54474997d4f8e4c7c862562b8ab33205689fecc64adb67"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "4788e8ff004e98e413daa2318c43af5f46d2961745f8e590d37c0f91dbfd2152"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "c085c194ba4f61c4b325d3e788dc38b3b25249233efdf4d26abab18856cc0c67"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "75f4a243bd356d849a73fa91df773852977dc95234aaab003a25b8e27ecf927f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "66fb3ff6846a60359c3d819fcec4bf6965b9ddd9bfb60d3039e4fbe28bf1147e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "ac5a46b2b934ac36b33e35e6b29391edcba1dce2b3dd660bf8724e5544bf09d1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "0d1b1d98489509c96cf7735f4d25f7ceedaa872bc479a4ba8933aacaf1320bc2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "642f4ccfb35f16064a0c31a3793d42d62259b6f49e2d7622e14d3bdbcb75dba7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "27756e4a533c1cb1b5d1f07da4624299f12ea6877817dd40bddea43a428df5c1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "0c4e3e3f1120f62e4d924bacba7c226ab1757e8419e7d5bd39a8303c4f7e951f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "b69cabbd0edc60be58c92a4c0f8749d61db566056469910e058b261d6de45765"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "3f5e9143bcc0b6f184917b178c762c92e2f84b66d6db8aafe4508a72dabacc74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "e108072a573b19c54cfe694fb03050e39059da32e8f4ea60d3145d5263d94794"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "4e96e5ede7a9f54b87773c619743284cb169c9a96a1af4c03d449e02f6fec0dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ab1ef5669822711e35eef75cbd8d466220d66f41cc97a3a09060935a37444411"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "cb8debea989a815c685c465ece2a84778eeab9568e53501a49358e456ceb9bfe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "c6e0df90800183578fdd7c6cdeb5a803a911086ca3e4036f0d0e53834f40c915"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "abbc5c58023ea4a568f350bd7d406095c510ce281bdfb70bcd167d8dd3974185"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d4412bfd38f9fd0e07424fca1be0d6fd1e3c88e3a80789a5c40a447e97732379"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "bc91cd53d4bde2f6338e35baf94afd9d801a56336a847e5503e928a57d062ed4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "0cc72a9b18cb2ed5c52fbe263e32a2bd644a38886b40278a6e9eb26c0a22ecb2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "98d9757246dc48ce8b39d3cd8f630a6b96a2f415fcdd5f506724d8f0f5657fce"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 160096, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "70df9719b62f3f87055d181e759f8f044c1b420b9936363da054379b45b8ce78"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "3439429ee7ef15f9b6b76225fc6f363c2a6c43fb86ff4b1b32a6ed3d0b06bfc9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 171360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "a031ef477c2c9fe9592aec9ac7639ec994f7d4415481ce908998eae985adab96"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "0f85dd30056d55f5fe5861e0ed4e557686a12cc05f328b687aa66b5e69f5bca7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "e29f1b5900ab5799f55a091c30e30d56dfefc4df18f4c5830e6f277a56b6c1d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "83a1d5e420e62f333f0408ecebfaa53d5aff0387ce04d46e1c016ff3d3be418d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 154464, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "1165907b59f917fb1b051df72dedf12dd4db8387a1b2c19003e2012fb2812b25"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "747973bd27e10fb468139e11c8d0d5ef0ee1157f25e2666acbdd0342fd67ab15"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "316a211c31f1de948c477cb2480bb2ad3908f9f76bbb7a8dbc079be4d731f3a0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "e305def9e7e72416a7281d12438c10fa0101b8dfdbe1a32c44831aeb9ac930d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "8bd71d7f26b1892560ac85057a87d52989ad06fa310fba2a451df50f789facdd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "1f3d72bf343e3dec059afc1fe4dd21e99ee5d9c41fa288cb68d60d29dd20f495"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 161216, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "97d9dae4920235b604816fac1493dde5ff81de5f60ef7ba2ea911160a45c3631"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "82649b3af4d6b877bac9615dd9fb3e2ab7f264181596afa3305392961eb814a1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 172736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ab0f879dcb584e5b0768c027f70561a331d4345159b22ce28651a4a0d8785bb4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "ee5d93413e5e6794df169ce985e8177fb36290842e2f1cb914e993fdc3243dd2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "b3b652ce9a23c30ddecff770a3504b01d59739de502d40c12ce3093b703e6707"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "7633e6a04acac0b0bc5fd57ec9ebb2145178d109875ca92f80bbe47a29ba2018"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 155456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "d74d94584c70b285220fda90782a10e537135ece6f190d7ed5b3e6fcf634bb32"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "9552a06dd0a714bada4b3f1d44cd542d09fd8bdcc2ca18e1f3e5e4cebbfa4ad4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "6f8514acb5a60abe46ffd0c90404ec0eaf6ded8523534502f503a1cb3c30120f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "c9a7c843ad374f7a72e47ebff76988fcf93459f63a6c09b83d056d7b080b778a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "dc838e046bc3dd106be5d7d322ab0b859a3f15a100706902500000fabd65f169"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "f49ca26ea004d92494a4b96f0dc7c8e2e570bf25b2c9c0b0eb0f39ca6dd83c7b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "336670f4be7009ff0557521a064e0a32928e61d3f7c1586cc9215ecce4414d6d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "274770cdca4cb597e5407dcf2f53e352d0253cdcd3abe01f069ef5457ff84cb7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "dd431f0af0f492da616f46e9ddd81ea75dc3480845d87eea27c1fc255909bd97"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "d6abd5b93e1d162a91479a6cfbab8be08467d9dd8f3fe73c4b8c079da83b0b5a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "4ec6f4966e214d068b3a4735abee94ff095dfa4a57b8c9c6f01b14f0888975ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9bbe76782838ae5b8048334ddc2585013daec00aa9094da057821c9b092d6287"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "a2f0816d8f125b850ed4879bbeb847092ba8d6c869e981e02c6cd572aa597498"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f76591303b0feacd6cff53f594cc97471328f2099feccdece2ddb05f8a959113"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "5f09cedcad36dd6a2a8e0c08926bf4306629a4fc5408ae04c1a13d0436f4186d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "de2e99d86713d264e2b4e1f646db727201baf3e2a0d90eac1f697409353330c4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "309ec628d9fb440bc54c26cedaeb7034cfbf4ce43568b028f375157ad9ebeaa6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "1020dc073230a047ca1f0ec1c7a0330bdad897eb8d2bafe012652da8823cbc81"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "684c23ce1cea298a13b174668a248bb7dee79814fe2d14dc1ee35e9527b1ef87"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "8e7e02763a3153b49724f08d02b9da4588c0e8e8bd2eb1a5b6c5df52819c87b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "ac3959e4834c612fd0752b96bb6a0a112f031de317230fcbed1ccf2d0b3a864b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "c86229d72e69eb6f20a38cc9b042ca67698fbfa2b4043d64e5c3d124ca692c17"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "984472d811d8e0c6fbab68e6eddab9a632951d89308ca5d704ef02e007a1b34d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "14e1d568103a6868a8726347c39bea18678450448b48997e173951f804d4f6f8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "1d563e95d7a8d05e57041ba405093168e3929bb8cea97850a03eab40d1546b95"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "0f9a03ae03f127a8cd455f33ceb045c8499298d09a357c709c050df7086ad0c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "abbab34fb569a81cfcc5689334a1fe7bee05fae14761960630a892cfff4cc2c1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "2230bd5699120816f7c05243d98d13783867a07d5a85af38bd0e129391fa32c0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "ecd5d045324227aa902b92c50d934829d107d5bb242e0d2fd8bf021f380d4167"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "f487474ff34506d2764c176b22d06961da5489ef29471ee3fd0c9c3b1e6ca8f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "31a52d400dff0acf3d677aafe7bb584f77c27600dc1191e06d0e15038174d4bd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "9404945243229cb875c15942c69fd920e2c57fb40eb750d4e52573851d47e308"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "9863b1cb73fa7999a7d7794ffc57466b4fab830a5f04e4c21c89a03ffe7236b0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "df7cc9c013f194d9254bed63b28b9fcfb60f49d670a70c81b85778f4c3eebcfd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "5196dea49f5f1e8076b04100a76e124ee5cd63a79c46bef922a17bf1ded1e9b8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "9c2021a3e1b1afc71dc9d43884218c525690dc48d547edd0f99071dc757d8d4e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "34f0915eb910abee0c6f98c0416b42766b2b8049f33dfefcbd0663f76a73bc0f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "007564f7be71b3d67ec39f1520228d21c5ddd4e3fb569f682adb7217bc742c69"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 160096, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1a5449f640b231eb7c78a5fe48a1f8a92b22b56b8aef07ed890f11643ee285c2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "0c659158c48f5b08c595c4d8fa85d9695e0bbe52a5b2837aae22f131914afa5d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 171360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "4a7502ddb9047ec17366ebc206e3e7d816c1368b66d21cb16bafd3ccd8ea40e3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "8eeb00265aa054dabc8ca96c39648244840c56f57723dd1e1afdae60089150a3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "ab57ee9c464373efd66ea8d562eba50828287fd14a3b1b860105fba72a4ad6fc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "7acf91a14af29a3da439c4dee5cfbd965accd90c6127606e32b73d56890417f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 154464, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "07bbf732f9be48a53738958823ec6205eeabfc24ab2410eefb356a23bbaa8026"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "08d670e054b44eb260c6e1cc4c7f9934ecefcc1f5d766a7f770089b475ff5be7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "14ad6342ec54a260eb1ace28635c6a875be15887e8d78d3172ed684c6910077b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "7b7cdab4a81c9d47cf6e9640ff343fadc3aaf8c97231fae2926cc9476547ae87"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c3515b90dfb352d03dffb8a280e92205ac4ea307e1712d309d3b10528440fabf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "10c7fa8eb6b80fd1144d203268743c42a2a815a2d8079c88fe719e73563404e8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 161216, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "f53072adb80c78b5a4e7a133acd37bed0005a4f5360f8203afeaed2628f1fd52"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "8751552ab150f86e20ec507ab383301fc5b53af53a2258f30dec448455acb151"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 172736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "49a9b11b254386c09ea4806029d17bcd09e83e2b7e0da67523f64c66fbc012ee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "0f1641039377e100c9bb4b030d977aafb0bf7903aac0ac1261ea914c2b0225e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "d868532f6beac4974f5576e3ad35b0e2cde38cfdf455616aedc0c9827889e280"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "6df7c8ced940a9a36c9889b3ae5c0291a0be696e31e0bb89b0d9309fb88fbf66"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 155456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "7a592a2a9c6dfcb11a2614c436a2c7c830f01d760f8f988c69ee8612498b758a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "69f8981a372b46fac6bc8d1c199721830889639cb73c0528eb5232c9c7f4a5bd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "852b1e016387b60bafce05672d4925553f473544487caa8616f6a8e3dd4cb4ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7da8dbd30490a2729082a17da72dff5861c064b96f83fe88079eb11907e935ed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "0af27ecb1c37481b17bfe52fe34bd231ebf1b2cc846ce7ba82261e67c0974909"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2a7e0e1593cefa03fc03d83f2add38f43376149011ef0682bb00920ce21f5fe7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "f0c962dab70775f0716ddfd48e0d552a14d5e61aa83b149650785c85fd47bf06"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d939da52c5473e41c3f59622d542cd2d7ac2ef9e427b7f2e7f824fddb37fa99e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "efe940f6dab1e8ac32b4603c95cb65d8ed7b4a83679a5768b6be6470524b2e41"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "6b8612c17c9cd2bea2c65a8ff374e964d715d2a5cd5b793be8d0b1b714676ede"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "fefc506f6c09e00fdcc4cebb34e43ebda6f7c7ac94dabcb07c4c77791c46e803"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "a169a299d5610ee06736e4e48e3319d779743ae33db63354833f84d647ff0c98"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "4b2bef63870913f08110e11c56573793139bd58a4126ce02fe5fbee9f8645688"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "a5574783c87e63c9293f5698c45563a833d64f036e7f780a9323ce838f94bab4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "7871fa33dc31a9c3156cc125a38758488da3d0d6cc3a13ec23ad2201540d988d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "29bf82d1f75169438201e9ddbe52852cfbe86a7a2d67c0d5e875e5370913083c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "b3fb50771496eea5aa9896bf4b576c91d9db4e4931b4459a065c54781e0d2fb0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "339fee51dbfbd7a92614c0d9e46f8c3921f62711fdf16dd3c4b2fe46a511c0f0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "0df3504da5714a3f6001403c35b0053278fae0c22d7cceb01f09b65167eb0875"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "f79dcfb9ba37f5989127ec37a9871f931f6ae5e25b9a9bbb049b95a9927364ed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "313f6109bb12a82e73201b2fc950c3c631df4a301b59fb1b6d4ee115534d05cc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "049031986ca483365f4725380a827be0c0555d8e550006065c95de8f6f1754aa"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "e0121ac47941426b21b7a1c8b712bd1f93e661cdea2fb4299c4975164e6828aa"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "05655c6f61d4265bb923af201037b45dec324ec22446e679b93b85dfd78e1b1a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "6c00266ce2e8f65a616eb5c834cc120f01fa76f7ddb19e83ab5315e582caefc3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "766f1f7abc2d4039dfe64a717bfd7c65600724351077b7ceb68b47f55a7e40d6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "d3dfadfeb93ebdd302d2fbffba489bd10763db99bd91453f840db15e8dd613f4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "3e73be31e5619cbae089338c52ad392bea8402636aebf0544d32806062cb30f5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "231ac8a19fff7b059d88ebae72b1cbde0fe93cade88d5c8a1335a9f8e7948f7d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "ba1532e8b2136de779b514b76ae1b3a5e61e74b25d886dd8045393c56a375b18"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "228b09a5fd63c724c27eba831b387a4c742ad29bb34cfc8eb77f5e3b1cc397ab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "68d66d3a261b44604f98fd1c8ab41787ff0d10a3ade86218e14536924ce74ec2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "cd24ac0040d5b30f7c409c764ab27c8b515659b606e00806b5860ff29a3df408"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "81084f82efd43cc95650ffeb1468f80f57938bda226724da60ebe96c57652d50"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "c034593beb296cbe883b427516bbf07dba66b52e7f194bcfd4a2c171f5cdcca5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "6478e0cf86029cb04a93dc8716086cd37465bc50ce3045640bafd2a9835fc6ba"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "1e4c8521d0503c9c3cd096540fd12f839b8ae39db5d446069139b97b8c8e3b85"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "e78711d82393b868a2626a232c7f1a6874368dc199751318da2f0cce8d6a7b4e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "90a512b06ec8538db1d301c0096b6416fdccea9d62c065b34b8ba0c3afa1a719"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "8c6b54a31980ef14120f1ad7b28d57a2500957791ae686dffc6e147b23692a45"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "a8416ea4ad7c711ead16a173e14bebd47f8ba498853b9f26b39f132d0adfb817"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "41c2a28f974d67c4478b33974bb363013c4c63178a246a78d0998f8c9188ed81"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "3af8e9fc8b2949141ae23c4915016a6e41b3460f5fde5fceb9214a72aeaaaa7f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "8628e51e3eaf50ea92ce302ef6d041f881cc43f4d4a7fa19e6556e4419d0f4dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "6e45aefaba23b807d2be6efea0cf216ffebedd3d8ca41214553c17d71ed69872"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "c4906bcfb87934385b76963efd1066e939aa36ee32def8fc242c6296e8bae570"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "02b9cd7bbe52307475bdf40b2ab999a3311fa2cc48d34f8cf770a6a9a25448e5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "642fb1e51faa08b9aa25a625f6c4ee468e04de1fabae5fc004e30ca76fdde687"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "5b88a635975b1fd09c46105c4e2494deaa7ca913ff9c0ec43c61e6dc2d6448b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "e99d9b5185a96cf0ae19e1671f91e646d54de3a3f46663739bb6284e19e5fbfe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "4e84aee6932474b824df271bae724149cd655fa91a2ecbf7738fa5a5670222f9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "575f6fc6ae58ad3050b675fcd446297b91aa895ee07d25b88435bf5fea7b8c98"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180928, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "2b627b81e7512a1fe6169f5ac0c5f8a3c9feef533098a0af6218a6d371a43c31"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "f6ec0a6aa269436223d97ac685db9ce0f7bd66cc76d636212be7a643ecff9f68"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "ed19493725fd042e16c1c72ed37131d4f68b4c991b57ca1f277ee034b0cc0f70"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "86f9fdf570cd237b354d1f64d5d49d7c15387f469015ecf335e7b73a0c475131"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 157504, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "27490661c20e985f6f1c46e4ae8925ccdd0308cd79356b9f54baaf8f46adbf20"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "62bf8eb42fc4b1ab9a82007d49f8be1f7fc639d13a495e1ca9d0773f6ba6b8e7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "1f2c2786b3766eb6eba223c3552b079aca5902de855f86fdfa8606632c4f88e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "3aba274b87bf108618803a1b4b8cd5f5395f26cf0467917de3d94d7c5c03c30d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "516326c76b5fc13eb5c4816c6de878f8385a2caecc0199f85227be9e6924eb9e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d217918013dfa2ec01556502b306951996ceecff46a8644826ca0a10429cceab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "e172c6ab84fff2c87889f3c74cc50c9d5b0b0b4832b979b60a46c41d3da0254b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "4e8d884c1ad3d12be5d9c2a6c6e1c134ab6fcfcf34c710a4a14b683e5883ddc0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "af9189a5323109e27114e583710e718669db3235a88688a37dad3158b97af151"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "aea26adaa535bd05c0f88dfbd3f80f0566bc3cb47568fd0311a8c743aec81e6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "76797e01eb3b7926a66e05f7129fa201b44ec95417bc159b3dcfbeb8b8b99a95"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "f655684789eedbb482dd424205103a9f351c2db521c61460099bb45c44d25abd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "397e690fd9d943192713791d4208e6cba7538b938296d4c656763af7d1506f4e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "103bb65fe3ee91824d7ec6a76c37f4392f31cbcfe5d3442e22d0ecffab6cc2af"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "e2a330893b8d50d6fdc68e833ae3a97f35583c5d75675b473f65ca92e0e5216d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "85e2c60240cc3a95973cf6cd97672abbda0c155e9b3aa537ef37747579660732"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "0892e6bb850c26f722af553d428f351988901ccc95f4d7b351626828a8a46662"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "b750e5e7ffb455fa33e00ebd96214eebb2833c95bae9d698dc3928367a8c8d4b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "104eb3c3cb7d661cf53b398ba2584de2f59543b85be1b3c29fd3a9e2cb028118"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "6ece4467ba951ac43f0be6efaa5c8e23c6090f3eec9396425c931c94fa334982"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "e997a176cd1627d5887a10a07009728ad4845d65959956b85b7d13929c9bd7e4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "e8a03ce52465d7592b63f1d2fd4a45e96d3c75d63bcf1da36ca7e48b7a320b51"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "23840c87138f8ede640cbc24e707ab893df2d2044a0875c0debce24af0d0eb43"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "f43b42aa2232612ea51d2ba3a4c33c84699babd0a0c5c81ef9996f227246eedf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "3540346c6adb86c631762d8a6234262148198f4d62a966aef04e9b702f78d878"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "036d02565d5cd074fa3e287fa230bb18e4c98b6fb67fc42c5eb15dba4409f5de"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "258a6dcf5d18ae26638c95e779263922172a94fdbde6b27270debac6e171c1d5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "58cfc20ee31e5354b21dbab13748c9067887795889a1de4826d73100837c20d0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "3f15fb4033ab9031303ac8b75c1922b842756544557874ed6a1f13c8d810fcfc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "7b50f56ff867251677e76de7b3140d3e737c1e1ee14f30b11bd4eb1c2514bded"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "a61161cdc2d5019472997b240469e03f361770763f2cc0a46ac6c725485fe138"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "9f95249e9f943f63c28e827adaa1e643d812774920b969139aaf49bd0dc542fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "224fc18d40131a666eaa04329bf7574482e9187390f8eb596cfb2d0e5fa5c7e4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "3ea3d0beac00f794e9522022ca83910e46eed49ede94c957d1e9320508e6e74f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "6c4bc180f6650d4873c70b6c37c531f8147a63767d7834dd9e91bf005fc92c3d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "23bd98aeaadcb79b8f05e2b21a4594abfdd6f75a283e1a5594437116fc3be1bc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "d3bae571179feafd84c1b62eaceec98476b1c3773a17ba6d60ad6653d85933d3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "9c9659834ac26367b8619ac4971c404c7eb0d53bb7253583286fbfa4c9ed6fb8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "d2e6f987da58c5246d785e4aa033639a28a971372508f186945e3546ef3703ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "efadb25024f210fd7a5b8b77f07b35b41caeecd7d20ed69f763a6d6e0c20a22f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "488cef3d4dca33e4317238ad69b408a0a3a39401d03be3515234d14eb4ecf0f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "75dc875cb30dd900d45891696593db4a395f51ea77cfaf75837a9e82fd492e5e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "e8cd205e37bc2eb1f0d6c2df0d33d6e0efd9da5bd609f77777b86dd3bfc826f9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "8fd2f48ae78077df8f31c2c2e452787c9cf252057101a96a91553d13599dc969"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180928, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "707875acbf793e3b8ea3645e799de862bfaf5f6816a0bc8209ccb9007ce5bb6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "898f6a8010ab3771227f4580d67962cfade1c8d5d342b253db5a3e6a97637a61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "e5626cf1c187f02e0158a47b719a6e50e9946e8e5808b4710db1fd85a0388892"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "6edb81fd86e4d95a0c1a41106a999bf820bee54db1070914979441f20c065cda"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 157504, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "f015b29edcc8989a5f52edc0d97e90f849f9097f2be09c0348f811dbfd47e2c1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "f656ae074474a71bd847a654908ee0bd3b8fa154f00289cc96bfa8f71b3722ef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "9af0451dae50f0fc5569aa6af7759aff00fb9843001d4343bcc5ffa8416aa38b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "be5ad49c523c0adcfc48e7a3ea88850ef0008e4c82c90a37fa8a08dbd18af984"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8467c42c39b2c9801718fddbb5d427c5fefc5c1809d708430c3ec3db24b575e0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f74ccfff62c5ba7ed0e4797359c49c611524dda1b4a33e0379f86717ad7c6e13"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "baa8332efb87bdd5147dd5db81372121d319a9251a9b2c0baceb433bd9afe52d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "9f9d6dbff1e3ffdf41e4b85fb1305ff13cc96e7da15542ba6826de41fa4be96d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "4525ef648cf161189273c9d1a94c04d6575f146d277dc39d56ce09578e5114e4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d3da797ce14a625836ac0c9659ccefc5bd8506a3c0c9daeaf8b4dc8cccab9979"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "9df3d63d00246e1ad2c11c6c5e7b66c7783964c621ab5ef621c241691e2f7828"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "4d8c658f24ab8d79a03941a7fe8ea8566de3e984253dd725548df2b8342d64e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "edd71647d73c32bfb692e4d11ee50b495a64572cf57115b26f8cf5a5b91908ed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "f03ac09e709e987902dbc26285abd2b90f6d4d64c7b9558f1744ce227af39480"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "d7d6775077252243b80e0cf4eef08911a1cb8c2d96950a513e36ecc4a5343846"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "e451cee6a0b53acc403b983a33002c873d3067156b6db5a82a327356a59d1a08"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "a0b941ebcfabdd447d473b4b662a429c5e999ed50663e53c564b2806688ca84e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "f73f510dfed86eff57dd69f77543cc9c8b05417612f741a1c17f671299bf8419"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "666730f9e94e048e33e3ee59ac67362c3dff974787a262d5327bd534ec69eac0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "0c72a2f5bbe165d4e735bfef9c9b2ba5bb6ba4249e6f5c05c14afc5b4d3d3fd7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e1eedfdffb7bb9a635a51518c88cde5d8d49b8068cc1cad26b98c6f60fbd7473"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "60c77f563274958c719602173eeed98f1a1fe6a572d3ca642e0afa4b90bde18e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "d7392b9de369ff179aa7edb073d43967582ef2ceaedefcdd0849fa35aeae8a74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e463e5b2c258b1e7fa4c9965eab6e74f4e6dc8fee0fbdadf173ba9809abd8e10"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "280fbe777bf8c5caf5b7528502b6e02f8e7b05c537bb5be3239826ec7b9885ac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "6934867f4de83bb1fee28771e1d45ebc064907cefec424f11f70415167efe675"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "0d7b0f0a96b534da6a3d19020bcfc8919f59036fadc9f287710f8c40cf04e953"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "4d4bb41641d94c7ccc442d36eb941eddb9dc8fd820606344089ebc4493019478"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "198a0a4d15f004e42295d068b6c3f46013aef59f928ba4ccd59c43745822134d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "4eefd42a20d5458f15635ad94e298280ffb465087ba25c80226a17b6aedb6d86"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "a8c412cb66e1f8805974fa6da84107078b9503305779220584b2f6ebff03465d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "18fe29bfc3704e733f8e4cd18b8b7e6aa6aeaaf0e8bf9cd772ea74c960e565b3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "62cc2a54108b25885e71fa8df3557d33a7dcc8d50d08b3e357ac5de9d99a9576"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "d5302e48735edf8f1720c90b97984a744ae756f0902ee2e5d50873e1eaa6fa25"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "601e53f294194c86fc5f0489273ac6e2f6a620131eea201661b6b9a237a82ede"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "5bf4a6f08aaaa942b8b57e1cd00715def200ff0ed940a09b199faace04d2677d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e3c6deab04a66c93afc49a3bbd247b4455bda9451122620006bf2da4cfe4f41c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "9017a98a8427e9cfaf1993b05110593b4c2e0f60637ef787a12b932e8f75fe61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 157168, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "0a396d9192f2a3876f6d96b8a7bd3a286b28f2f01c9e44bfffdb134742f9f56c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "e22b9eb2f604a44c8fa7b3a0a1f9191735cff036fffb393df9608ab9b3709268"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 165360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "11ec16f0e84f25663327b47e6ea8038c7296a47fab0a2f45c8319159e8d515a6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "8e96ddb8a77462ab77e6307a48543fb732653b6576c8009a89e3f4c73a040672"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "80dc658438adeecc989e15219b57afb30e580c154c6ddfa81b800d2f685148a1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "6a54ca62bab62192dd10891f42dae942818f039794de3776a1453c0b3925335a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153072, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "b0117b129fe7ba8d9e154d5dd32bb92fa915c1bce6a7abda2cc4f14a3a9d196a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "9d0c595aeb0166250e15a7e1741a609f73c849ddd9d3c4e8c66d0db88ab62e75"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "60f474c8a5a69f8bbf37c25f46a335f0452c6bb0e563e3a3802ca947ac70aa85"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "81d00e8f6c9710bbcd73166ecf8acdd33ad52c7964431def0f9a84461c0dec1e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "884e81bddebfbce460834e6e36428439de8ff7d42ebb4570a51c46e6cea73e4a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "fef4b9a499753315259a845855b18a32fefff1dd4097b79609134a2518d7cd6e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 158288, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ae6e22800b0879bcda9d2a0a2ff3581dddc19950c317033637488669ba9ea754"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "52bdcc0ef85110b2b66659972a589dc2208dfe37d5aa8d025b3a2f92da776063"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 166736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "04b34e6f3ae4399992e26bd385ae721c8ba2540b7dd330de827d322c53334b6f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "82f5e5d2a63b3fa1ad733206d3545058759418ed80f37c5bebc8cb42505fd85e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "fff030a6672f293260798ef139393ea54c8f2424d73cb9d27ecb3fc956bd069b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "75c19de1d52b638e41442cb6711647932c94c5fb4389bf8498b7ff0c22a291a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154064, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "7dba6af049a977cd97eec2615528010ded13aede92e26fc432e412636a183956"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "9f8b331a2b33ac8606677dc0d24c4e87a50e369ec30b6580e6483fdfb910c358"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "c11b6e99a3c0cc210807316c9f47d3574bdc243f0774c08733f255d692e93524"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "c0da72d17df187b83e3e1819394e994a0e341943dc15985d055f126df0d93681"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "ff2c99d776a6561eb8ab665527eaa811359cd8ecbd7da56a317d8fa3741a9b5a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "695ab9367d381780d3b90fcbf6e9f98891c0b437acd8e5b90300137dc37d1cee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "d4a99b8b47479b288c77f09c281baca9621ea7e06575f76654b50c018b4f235c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "218aead25930e63c69aa1e0f3576c8cc239c7c6575a8a00c85e9f6f517d1ae86"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "4dfa2486edc781980e42dc2f8a8127d20b09c5229cc825ed0b9a5c914f89e150"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "50ecf386537fe14ff5de2e64bcd25c2a90f1b31f9d0d55780ab1e2a29716cdcc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9d22a43164d8bc9c3852bbce0f47f42d111b1bacd19de4996e6a94f9a1f84718"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "06c9d1da96bc7eaefddbcb87ef0635c42b2dea762394d80f8e2c9d86cd29e95d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "dfd5b5f567bc52de3e1200044e392ad905307fb3d575b6af6497e58ec53f1016"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "2bdbbc65a563ed7e55e6a409fc56e31bcfafb560948f53cc867d525f3181f926"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "77c0751f29e907ce98d87742d90461538ba56ac2e4bc6a3dabb32b5487591cdc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "37ef08b1360f92407fb209d3b3a75020108db4aaa2fad41088286740cd9b390f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "52db6464b8c5d29ad28acd250eb9f87bb7ab364f164ce5af6fe3b30ec56f3cc8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "538e26acfccba38daca047f90c1fd0031ee89e79a2844bf8a933672402fcec91"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "583151127921c0dc858c677b971567627d1e1543afebbf7119e9d5d6047cbf25"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "f1ec5a28a95f60d6e8c932190c185e6367fdea9f1dd6f4decc5b5c5885de40e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "2aa36a1b5bd69ac7f5d97a6df9f555c69f78c4dc870234fbb132a9bf81d98614"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "cfd6f45242ccd0a727baff7618d5c8e556fb48e7033b979e4c8a8a78932a1be2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "a475c3f93093642453b47ec3513d544cb6f4239814bb4acf4132738b39ecd57f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "29b83feefc7f147f96ad0e805a2875730054f69efb94becea9a2467400cdbaf2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "07a528423d96666cf6fecb8ad6885fa697db79219f3d64c71ac2a058b28ed517"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "f18b08b1300a90ac84b8bda2a02756731e4a6622ea387c41fe3763d3702b27ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "b8c1efddf48e18e64247aa84b5d0d65e92c14c3544bb91f0495109c834bf465c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "46192532e9083a17ee45ec26d5bd5af47e657e0a4675316164e1a6208a6df896"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "c2b3cbbf82e749ffb71afbf53df41ae87952d5737a39f0b2ec240224212f776f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "54d52785c08fe6789212be8955a5597d7e2d87adf4c39e16a82e77feb7c0ae6c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "67a6f9c5272f4ef0666176797ddb4a3b739dba82d25e35165ec2837635908efc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "57248fd39050580dfd2f0158cc83552804f27c338329984a08fc62130fc6ca4b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "7ec0ff52f1ddc5dbcf32329147fc07b05fe4851394d7793ecda341bb3aa11405"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "44fd95ec0f2dd9ff512bc36721547082812f2ad9ac9d72d27e93bda52fe872a6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "6f616c5474af39fccb7a04a210336d6edcceb2b907b400ffa021136ec80a3e24"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "ea6450ae9ea5b175d7812c8677e9b3911b08fd4b639c836103c91afacabec5e4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "3d2f9a4c3e6f8b4ab295e3290d60eb14e1f60e6ab9d0255ace8a453f0526b227"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "30d6426a2ccf042c41d2a5c14352af1da6c59fbe47b3ec62f2b91e91e687d4db"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 157168, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "a1c4fa6386aee052a387224f9941c46bd06d1bff3f4d22ed75fcef9886069e1f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "2eeb652b6c4226b7eb02edb0fc43e68af2fa07d6bdb8c0c42706d1d15f66bb12"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 165360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "7ce5e7756b8b0204b1d003296edf6288039234c432dfd9fdf7799a0484d9cd31"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "97b1872a7192ea6e7a6d08230b78721f2a7b4f42172cecc6c44fac4a472fd213"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "2ffc3c766ffa8cf1e9eacaebbacdb5ee3ed3d6e2540cfc4d4c5877babf9ecf37"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "91aa2750d08e46ae39a454fd6c35b4f071308b16e8f9fdfe0749120b0eb951c2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153072, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "b818870a68f7b0e9720fb9dc8132c58df895c85115fb3c560f0471242d3f1e23"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "3ff7985c6763ad1e22555d2fd3b4045b0441ed14a37c02df4b8a638b4af4db80"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "f77f2072cfdc5201918b5f111d81b3c730781587ddac3928181d2a5ec60af914"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "0ae255822f351a48ddb902ca15fa8301f37c7731a8bfb8ed1253a526c407b927"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "bf4d12bc9fb1c9e327e3ca49f9902a0de15a8cb78c428214ea481c764e82e656"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "bd3491e771e5440e380196f9753a236d5e6d8b9117f159313ea20ef0f6544c6f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 158288, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "733f0dbf83cc1b9a672b63ce885782e61fe14cb82df768d25974740a3fd576f9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "8d55fb51fcd6c22e66381c66bb80f927864739def8c5bcab56d78f7ffb52ebb4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 166736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "36e249f6d14f430ef67c7b9ef5e77a3bfef4a34e4f0eec18e694636e33bf4992"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "7435e9c35a4c24ef7c9b672cc8b3b30eed1c23e75c9be06a6ac26e8776a91a65"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "938bd196eb4af68e7c787754a0cfae815a247c737797324af30038adb8ba0ae4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "a8be7648323fb9ae931116a71579c9cab7cab1c31e1c17209be84b65efd0f0bb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154064, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "1018908a66417b37416908cfeae1f65e9c903cee7485e31b421d515f907c72ad"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "8891099d4205dec80bddef6313dbd9112c20527bc624071dad490c55c71059af"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "41cb2c3f2aed87d94c8df69bbe53c88764b04a274108dcd185648d6c67b4f569"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "9d26177d0bb24a30d44ae4732a215388a9cd3cba85e273a3a36daf0fb83c6a89"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "024c9b8236a5d0488f4ed008c911bc20be832024eb4173b3981b9329332ec57b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "31e1b40cb7f1d8c250ed14f27a002475b17f23214acdcf2d843007a217561eee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9e81f8e96c711fca84da7ddb0edf28c9c86f912a4d5f1a644a355c8bd7f5297d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "4826ddc8a87cd1892438dc4c060b8427374c1b5b164152d1e2158ea4ac611ea6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "980547585046f3aa192396126455df0cb0db2fdef9f516154605e9a5c4b482b6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "2f01de1c9b683af9f9cbea45a035ba247b792692fb001d6f720aa23cd7e475f5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "be146a78fe0e1aa8c6147cdf6f66341769f6dde173772ddb38dc1a49b4eb29d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "2cdd488959a161175118f1671a3e5cc698065c394d57a7d61abd8bc94b57156f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "cad7581d59140f137ed48c171534aa2f782cde5c407c30f70e30bd6cabc075d2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "a3cd5e48a889ce115f07b216778d8c913b15ee8963402499c06965b70b184515"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "04300ee879ba094c7d1e5bf37eaff8160f84224b94607bf671b7e7e8ae2abfb5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "7e4210a630ad68ce058760fb3a6ed0421363ca4666d636812db0271330dc2158"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "c5e1395405c88f5c803b84c6c2fc228e4a6704bdc776fc7a1298f48e3ca19c0e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "9f4e01d688427e14963ffd53a4acb243ddba7543e5b65b4e2b9b5234a9ca9795"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "afd5a9fd8ff3cfcbd9827701a9ea14d062febe5109693f5f1ae50f39f8551020"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "6ced1b34753bd112828d41627d1ce201312553cc3538e45e53a2684105ab3c68"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "1cb27f108dd4bad295fdf87d6344ad55df2f1ef2eec340ea31756fa8de0cc248"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "a76fa85aabf509318cdefb1f734ea82c595c350d15f708a8a2bc18528ff036c2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "ae0016fa3912fb089549efd18c036b4043e956738ac0464cf57c7c86a1311c1c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "13a7e3d5855640be5fd4e2c8fec0b2c56cde67c54824aff27dc9778660ad2f89"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "aeef1be07f186c375a8378834f4dfc9c9bc25b97c1917796400579140a155e21"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "f2733ad42c9dad6af167070c6b0c6da8b9bcf01257180c90b551455bbf2608a6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "b3b8c9d88d4c30e501a8cba80a644e7c4ea2b1ac0e58c09d5aaa6de2db53009e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "170bf8ca5df51e2ae73093a5bd6df82b20aa5e51301bfc92df6e79483c27ba0b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "cbc9f0c1202889ddc6a5212534878283d990f6ee63181e3490fe8f1b439e3e33"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "6d9b8b4d324ce6edcf88373c916c5dca6d43d89dd31dced705e199619583ea02"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "52bc220956c528cd84dc6829824005519f2004121f4479c40df838d9db4d9d21"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "e16e956cd16f862d425357931176cf52be25a9c706d61d2376d928b43591657e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "f83e9d7a1f3aaf9d0004e4fb962922fbf15156385ad303c8b9c892d761d88412"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "e8d2261375b340e14da3624878d55112bc287bdb42a98424f782853e200b77f3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "76da1be044b5918c812cfff5207d63748b57143d4d5a169d58cf97d22b5cd1b7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "18d307cce2ca1cbfb2aaab074b02a53ab914520fa68524024abdf85cd8745143"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "6cadcba37d2a81b4e28774de2eef99e6e07547a6d2b1113855b8edf4e33f2899"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "9737932744a621270ae5dfa1c7ee52321f67f993e820750d551f29f3a74ccf73"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "085d75f7986e7e874c4ddbebe2091c554eb54c89d9d48cdca3a403c5c4b7fa84"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "f188142f81e60f0537982f507322c5bad922f5927c2007c444cf3eebb0c3da10"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "aa83a3ebce4313bc05482f43d800cba60e19c331eafe8963c339a0f0bfa9be35"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "37ed66c03bdc72f0417dd6697c972d1ef765b72e571ebf1207eba2e230fd41f6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "630a0e3f3ad8053fc7e05096464372218ff4664df62b77effeb3deca4b382f9c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "977fc213b1d249801c2913b37ecb00ce2f6e6b09e435a6acec319c647c2d466b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "759fea34f7bb3dda6254d22560d7a4269f96f0dc0c430095135722669ceb35d3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "41ea41a79e4db3f2abd98072434f2fc9d387766f5e48ccbd754db5296edd820d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "1220a8024624f167ee0f8992360025b01ad74bc57400ba5cbf8b32fc235923bd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "c830f4c1dc476d82a9cbb9af9129425449c2ea6b815891fc0ae9c8076888e441"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "283a105eb6dc654db943610efe9695fd45f06be0c2d77a0a1d36694a24794f0b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "2122c04f4f055abaeb07f7eddc45c80e2d44b0dbf7943ea285555724b52d6074"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "2a227d66ac216b185e6b55e0093e4decd8d746708b1a79abb021917a608214e1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "6e5bb07d60946e99966289b4e4774e33ad4394c07e4297ce65f0979495a005a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "114246c634f9a21ed408b150bb75f842a4fe454ba4b5b0aa3f9c18a23063c17d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "e123284b808fd9b69f46d532747e16676ffd8041a9b9add5e2d6c8a36b1cef78"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "24b5ead14b967be64a09935e59610c37c2eb4821936027d30053909aa65d36c1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "0f2c96f387089625e00291898e6c5a09dcdb96f541e07cb83088252820b6b0d4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "f96c390b378eb2c98d5ee3953b6f4fbe7320c194da01b7f8f5c9d0a7948fa5a5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "2b736ac97fca87d473c5e45602f725b31f82c271233214e2e159428c5cceed71"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "5bc4e090320bd5fa38866bda4a8ef55c5d9d6cb0853b59cf4ebd70ead5068685"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "145dff8647dbbe26d086f48bd9fe0e66409c090daf266039de6527e67964a474"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "fb3ad9d0149dad935c26c0452b01162d402dded37ddbb471dd6fb99b43d12c3c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "2dc403da11cedc3bfcd076f011c45cfc9e0101c701ae0b46fb4e7bed3410224d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "5af0848e06a721befefa970f0d9f1d8e0c89d6f0377aa3176c6d5c042b68f4ff"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "8a2f743e5efc21d6aa8413b56fbd8ba6671ee12dfcf4688da9adb74ae0705beb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "c7922843d1fbbef64091e34a939b5afd09a81207ae1e03862f8872e28f62a495"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "a410bba0d1cdf1270bb96358082755c9e612980e1df4a4222ce2b12da0911eec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "31655c9b69b19a31293e6b96f18a9623513f6ab734b3c209c65013cca6ce9eb3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e4355bbaab398ba6ee20265be6eac9882da9a18c1e92f5c1a16df46c3dd235f2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "a5d7075ea82e5bded350dc99e211fd5c7bd14846343298ba301a6ee436a6fb02"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "cb099575951685162dca4a95f510c04c84784d561652f4aca3c2becd90c31ec8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "e650245dece1d65c4f3bdb9733d4e07fa190f19149ed14185026a5ab507b2892"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "9f91adf304f3225b0450cbde9911c21af5529d4e05b3a4adf5a49f54cf7f7cda"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "938ac742b7f5c49ab63dd93994c6b5bb06d8512a66dfbcae06031ce5000ee0fd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "271ce574fa3e2a437131373d299c06ce94ad2d6bf1ccd510beae19be0fe71c64"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "33c78f31afb121b6d96f285e172bd6fcc6a65802c0a39076f84294088bbe1ed9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "f2dc03ac64828d36155c601894d9b10fe24624d4ba5909aa38702cc3225473b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "1f9286e3cade71519894dfcb03c806e973525bbc9ee69713b6efc353ce635597"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "b3c692a09a55fb40c3758125ac84e77b6073ebcbd0cd08811349be52bf550eec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "cb8888992de535e82530da494b6380ad2129af488aad2cecc3c98a3699a002c3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "1a142a8216f93de503e3968e2621c47cf504b541e95df349a8cd10e508f64c8f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "2e35774a6bf56585b49f538956a7374c8b4aa54136bd6d4c8967589d1efc6933"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "43df3eb928714b477382a89149b58f7a8643e564cd61d4c2a8c46929466e859e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "dd056509a2021e7f733db8ea8a7ab3ed6ad7bde2ce5da9e9c0810cbcb50027a3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "72338b47db64c03b7c4703f515a648c293ea4a118ccd8de1ed836b9f3bd2b769"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "66ceb9a6395316de1b902e88dab2e11508453410611ffeee80a95d1d62c790e0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "d52ac9b7946edba37018f3ebf07dc197be849460c4527318f4fdefe62e7234b1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "8f7571d482ba363ce0abd3f25dc67cf3427cc0350f22a240e8a5958d803db968"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "07ce272d6747c9248611334b2a4627fbafce9ab5614e6e6a8ab105c311782834"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "767ab6684da1a3ba5fda938d1b1e344639fa9b440da2d634256627b9bccd0cd7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "f29b7df48ef505f8cd86bcf9904b186022aed5fca58086fb01ddedaa48ff2748"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "77a2bea89c3baa5eaa4ad17b157b3ebfd0e967417be1ba63a2c8e2206cc40eaa"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "f99fd1032b6f48837fb6317e4152f196acd1463fb6afc0f2ef485b67f057ab14"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6a0313d2f3e5040115686eb0fd83780ec771ce0e8838b856e407cb8ff27cd290"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "635d70b8defb98221ffc521d0a00add9ab81f9dc1b756defc0547f7cbf05f576"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1061861303f525406a512480fb8172bb849d4072f86fd731935bd5966aab70ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "81af8f98854c06bd8f9cfac44d1a8954b635a8710aa1619af3c9cedcfd531e74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "e39f46aebaf1dac08a03db14d2b2072c5b3f0bba430f904f66c4b7fb7033dc40"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "c4ecca2fefcd4c7761ee9138b7546446f4c6ad3c159d29563cd1038dc977bb03"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "b2faa47350b7f9e21aa9f83db25c4d39c3f47bc276ac257036f84ec905ea57cd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "4e90a15384741253808c72a0e32ab74885a64b6dc20272e520e041f013d8932d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "3635305fe754e0ab509609d3995d8190e09a5018db6023db9f8016a3d94b0af1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "d17f56393de70d6e48fa99718293049a808d2b1bf7ba0777ba83f2f80dad23a8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "777f69deda93f15906233ff95816894345411509b2e48ffea91fec1310b6b60d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "3b69bee1a841ff06cf409125edb7dedb24747cf47248d315be9767e3cbdd975d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "85d7e9f0e9ab2bca268a4b2b1a0506cc61800cd841e84ed99d8667248890a30e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "d4739783bf237c8e7b4ff23b0a24a82429052773ec4b1389a58c79c9bdaffcd6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "002e2c8532937f1a21a64fe90e7e05ff98c7f4573c1db7325a5c7e7e9d603191"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "10e55bb348c25bd6bdfa7e068620dc19fd7238c1b4c4e51e4795442bba6b4ab1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "fc182f634c587efa133739574b9897ea2b6cbacd384221971ae82bec7e1ba5d1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "4a6c7a04c2c7e037909c4a92b9777033734614f0f2b55ea9f69630543ebbe37e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "19d6732a4224b247ce4b97d7f3df87a835dd51dea0f519456b7fe21dbedbca52"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "9321de2d867a02e0120d820bc3ec09735775790f0ab3225bf1f335c4974de0b3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "718f6b4f881d4851b8e881e9cec08599e1f71a91ba7d3eb47953563bf069af74"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "ddbfdcb0ed0ce6cb71faace90055547c748a1a303d0063e5561d1eb9de140282"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e287c52db4ec186173448e7f9d402297f6fdd3d16833873d483898189dd3d116"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "a9201f486076a655eb1a9bd59a2e7ce4b888ee7330d86791370fc50f77c80cc6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "5be6e101173f510253c34b3201ec1994919440b995ff9c626aa0aa1ff1d52708"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b0a92491eecfbe206be2cca1482acc9c66bf1b88db9e983447e2cd3a1a6ce951"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "e62b11ccb1689dbc01ed2e65e65603a69cd44f7742258481b988f8d51f546f47"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "ba9a27b878726ec34639b1824d722bd4e7a0e24719ca6d0dd8cb78126a4fb1e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "86038e2bd8c34386bdcb23b5d170e0d4a1a5eb064934101eec9276a90329f671"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "87e8c310771154c863cf3c6e1fd7fd94f9432ca70eaf80f976c7c202c9ae84bb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "d988bd76bcb211d589ed6e95126ec50604bb10b9b499dbb392d5590f79eca80a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "8b85fafb3758728f4c3f5e2f6a7922ac2752d1c413d288da3170a4e83efee10a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "ca13d4cfebf8a5466d2d2f4f7a9761592d96f54892f42a21990faee8e644a2a7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "08f0a7eb5eb238a69e758651e0ef854aaf4dc915f41f1ba6925dab531de0ae0a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "111d76c2afa78db12fefc1b75214c26a4dbc1c4faac64284273f24cfda36ff5b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "cc4a0aa3bdde2db8a923af45a1b58842bc4fa244aac57627eeae7a8697c1befb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "2b89f6626b8336b9e6b184be9599685e75b37f54ed3fd9238504bbc35ffb8aa2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "fcb8d5ec625e47506e15072950b9700f2c49c0b115cb9767e3af6c9e76b9a0ec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "bf44fa200380e85f404bdab1aaef945fcefcaa572694c209606365bb8158ffd4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "3893047d904693a3a50bb9c885257756b5e80c92ff690079cc1b7bb7db360ba8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "a79e0c23a8a414440c7fa3acfe74399f9272d7b96a6cf5855397ee7f76584dcb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "39bdde7ef5f03745dd7904f0fcc6db4d3935b299dd8cfee5c1efd546cfa168ea"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "22d344f7c2057ac30090e84d6f5abd52e58a4eb75f9e52a43a67439b4208a87f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "4057e8095a87dbe6b7f6c2d75b6f4a309625c241aa78c84507f1af2e89f08632"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "45a54a4837ff5c642b67d60ca03941bcd17ccf723d442396b6c4a3b63bb0af0e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "87b8c00a11c0966630c3854f5c438839449772fcdb30a43b046c326fc6dd223b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "d1a31925292610222553c1804869ffd505c45a8ce4fcc3538850684518759b6b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "e7b5970f5a93c78574c1c2bb69976fce877d8cd86eefe1105820d089c35dceaf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "41361ca8bb7289e44f057e7e5d7f1f658adeeb3e0bf06fabffcab60129cf4e45"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "248f470731156805cca1a97a80f899a70cf0834773bdcd9b9cb9a427de614c01"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "64622e5e7f81f8902d54ac7b2cdfc0170071ef276bddd09704557fb255e14af0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "fbbff75ff766b41d0c10eba330aa29aece078897802bceca2af3651970033201"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "23a852d926b73f5568102e708ecde884f77ba6a5e74741ccaef3c16c29d1d4e2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "65a1ae1c32c4133b09da2c31c71589b14a87351a14845673e83f1f9d1ee898b2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a35082884551b053c9761453462ee301489dbff82245d3dc3c964088348cfb58"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "02e0e9d0129e7b7f8aa0c920dc2f4bd2b0db6bc152babd48b7840461a22fc01c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "98ef8d230dd48ca0c46f2a8a69ab7418762a3ed604a5534fd51661d337bb82d1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "d74b50fb97fec4e7099965683bccdbf5cfb24fcfaa13f7ef2a549634e441324b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "2a94ba504816d16b687075bf4487504b1c13623b0ac0be2c7547c90d42dc997f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "ec886d658edb70dd02655108a0ce115f3a90a9241370789272ce32f1a2e9198d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "615774e47f719220a1c8f8e11c38e838abf29f3e5a8a42fe0bbf0b006c7b1e6e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "e88ebf055f6a5e461a46030bcabda32f676a71f69ce62e22f99824b2dec32c02"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "c6431c7ccf5fe9e60b387099260cfae791301cc0b2c6b1906326704f9c9128b5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "b7a6985b13ccfed0d2bd301409cbfc9f57ebbf23d2e66ee1620bea5108fe2e06"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "aa7cb5220f00ea0554a50e91c07ed7e8a1fd2e3e24d84624e25429f1ebfade5a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "9a2925d746bbc11c382f3d5b77967e3e1b679dab553caf9027d698030d82d581"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "cc9fcae5e72a0af93d150ac585a862bdf2034d3d5e20c0d7be75c5a4386d9e39"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "ee2bfd09b5f796d08f0a172ee775a4113176a97a6279f890cf90b916144bd0b2"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "5fd2955173ecd68e0395b1b726128d4cfa7fa72681bfccb6fb2cb15ac9d73e0e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "7f81e8c70c42fd8a015ffe325d08c6f37997f458fb5284e706689acdf21db506"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "4687bfc2479fe7d22ecdef71f8415067a7847cb22aa308cd8f7153e20a4fadf7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "4a38872f7793ff4b561aaf34adc66b3d311ff9e7450488329bef310893d4bca3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "976923299263596190c62d9e1ce5ee4da9cab1992f65f7c41bf102b39e331a59"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "dfdadfebcc9c866f61605539466e294e015284a4848558380d3d039b55502825"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "e6412419522b1c4f1d233659b94b0bcb33fe93819f630b1afe73b33e330ec3c6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "04cf42712d54778ad93b576e20f04c89b27a3e3509beaf9eea88b60cea04ccc5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "cf157763921c57841c5d788a170f62a5c2e0bd205f81212cf5ffa3d128e1f1a7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "58cf5a80546bb181852d2e1a0dfda0c713475aaf98b4f5edc8e3221f9826a1b7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "b18ad5bf98f98e05b39690daddbbe62fe3addf5577ef3c6c7c8698d3dd437f69"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "3e2bdaf8787df637dcd43bff1bda6154a60d7afccc97cd0a70cc9ed29d6dd5e8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "a8cc7ce38cd322ed09cc4c8b33ba6f00bb2360c441d4fad4606c3ee9f2c8902f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "022bb7c018bf4e99c4c4c30c1b9f55effc17b4d9c79d71aa4a03801e24e2e4ec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "bd489e7c57576a4ee72f95ef0aec23e48b4598c4f42553704b824f603e6ddc41"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "aeb1ce11a0e78adb5188c4d8f93e6979916fe13b1ce381f0276919d85e740c35"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "3b4ce23e99bf5ca39519b183e87287f4216437acbd6c661660357a02bac87688"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "7313edae0838b3e7f0a92759f3c1e80380d7858cb0ab5a002eb1bc13028b244c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "a1bd9e376dda0e85d86d8f0df13f982b82dd5d63e0cec76110f77c1dcacda73a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "97270e50d95f33f21cce82c249d9ea9771a706be75a54f352704604d28f0d844"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "00397748acfa33908549ffed3f9eda52ab23ee5a6e480759fe67e72315e35e39"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "585e48343a2fe1318ae8ef258bbf1abcde8e366550c87c2bbc2825223497bd48"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "77886b3f5a5bb986f6bb3be9fc1852a4719cc44e8c01f54e9af813c3a8b17282"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "f0bdcc4091ee858ef039e70364bb4cb07010ed13178272a5d8d1a163c346a488"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "cd32e56150a794cb029687208706515150fdfb99341d52abde5565d5ad82e128"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "4f3fe04e0693eda365eeb5814b69d19c0bc5896198d149f27863a6f65bda431b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "e50a0f1f1faf591b3fe3a9d4274e027dda3165c417f0860c39f04a16cd56ad2c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "2c96dff4b964cb061418334219838d900e1686b2d2e3e0d0212bfb0b8f50bdc3"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "ace2e7c2ea7145a584c653eca24ad5d01b2f49f4a4d8c6691f0fe0b8ad3c6d36"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "84fba1061391040028e4c525fd55136d7d68e9f8b32937c6af936d4b59d5412e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "ffcee026e8b4749a2539082e733e83cc5374ebd7674c33af443d5db0ad398c9b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "e2bb67bf49110e46b5c108ed4860cc98f3459835c0d76562e61e6fa3b39c293f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "37bab58006268bb5d142a0599cfa11c9726279109624c07eb523c2c2a7a1b6f1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "b1c0e3a9f5093c7ae0de4e4f7db89225fca724a62e8f17a15c5b87b25724d655"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "35e20e4f81667762c92c5ae2160e1c1def6bfb3b12841c7f13c55033c9dd7fd9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "ae0295a92ca2339cfd043ac2597015ddcc1410bcaa7ed4daa9134904c5eb3380"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "9c3f2ab4f3239b34e1b47fd8b1a5a174cecf9a302cad5b48ec05c4592a28614e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "a0f8473a7cafd176397c1139435b95795ddd91e549c1f431c3a6c41723a1d73d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1f528634c6f5386d758a180bb66312eee1b29dbcc21a028f1cc749a3b5a73e4c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "fae57310991dcf013f2a5f1c1dcd7c6f7229f67df8f080a56988637daa0d3e34"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "962825de03414623f325d4f05ca2d6f74d3e12d78d804703ec874f082612946d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "22bd778896c9412769211d6e18c8beae396fea511e9b9188f5c4f9d98054a0b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "74c1a1db738024110092a1cf88e95490d4515ae4c6c3a38fbe9fa727bf400ed1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "467ba602a45d9353f360d6423f267db9927f1f9af29f5cd47a6041973517cd14"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "c951708a29e6194ce2f96d23fd4961fea708ac5a160993a96b23659402a85da5"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "0081411f189e35c1d4b3e219c55fea8b347f4cc4bc67bd27db47270c2ac27eb0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "331e1800506c1fe2dd02d2f08bac52c38ea6182f9fd2b74c41b7d0c8e3f977a0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "2c0e91ee8838dae6bfd29b5b3e68c564e4f75b146349d0a791f7196e5bfb0b42"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "37b50d6165db7fb5da9ea1ba5762aa295df01f80b601761004977d892c477d08"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "8b5f070bd39a272c7f993f14a8b5c03cffb933dca8778a26170b0cb462541118"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "acb9a56f1a1d4106728aa77f79c1f7f68f36050a323a93dc0d774dc5d35937dd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "f9b0fb83571d4a4767774bf5e7f7146e5d87d9aedaf554f40f6ff588ed6f1180"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "cd6bffdf58545119239b179a569f4b448e582edd58ac633091efdd6ee03908bb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "f0399557687c54bdbd471efc1edd21ed13310d020218133aefa9ff008f9e8071"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "4c41389d012209d8fccadb5772724187cafbadcdd15366fb56203d74b05b1790"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "10513d31b2490080bb886b570482dd89bf27806ebbea797f1e86fce84fb0de55"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "d3761eac04f4e851c13da8f9d746ae6775375e684f324c1bed5f19570eabe98a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "27350b991b5de069f206ca37307ff1fba14f670ec6ff3003f50b2c85169d3749"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "f42a19be8088ef4109990af98a04bd34899ac22753e07818aa31b771b2df3d34"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "161cedff12f233df3b69fcbb6e7540f6226eba47d4812a373cf4804692db90f6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e1b022a215930b791efeb56302b9bf34d5049770aeecfea9086ff275174c0b9c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "29f957caec039c3dcb62de5582a53b1e8f273f0fdbcb437de109d7df93fa7442"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "341e6399f41702816578ff85f45560bbbfed1507506997292c2e1466fdeffcef"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f0287a1b9b4d6f0d961082955b783c57577352b6fa0acebb24baa92735855e4c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "a88e0029cffc36498cfc513359c6d295167b6702619b993c47ec7c58c1df0f25"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "9400bb16895986e470512c867da76eb6eb7f5d0b452ea6e74aeecb28aa826263"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "01e991890191af47d54344caefc736484bf26400c34fbd61a6bc9da1152a8693"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "3aa060e1683c537fac3734b46e08bef87daa17248cfdfa84ce138b615fe66ba9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "1955d2c48ef4ce63e92379e85f09f6a2750bd24d4405fc50a2e6f5057ffd83df"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d85805ea347bc5f039bffeaface451f19ade92cf365d0d376d151d465a1bd3e1"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "1d7d23e4e4869c981e4e6cb8f24da8d4cd24aa737864d01267c56e9ee9092d30"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "eb297958498a01083031ed912c106a3e8a4858cd68f635f4240f3b998521b327"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "cda7642ce638aefbadb9516f68c47a43f57863efc395879a89503cc4d7dd1a62"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "c62e7cef19672d8d7bdce7fd06c68dca7c30ef2337e09b5af0e125bae2850438"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "918ef65c2315440002378f67f529a825d3aec6f63ead173a27ce2de4d081dcf8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "baa8fe2fc27e4e2d279d2edff7a0aa83e49e4f14d661bf4df616f3f28349c686"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "3148e3f5c82ad9eb6ecb92950635fdb1488080583c949bfa0399ac72f9a1f34f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "1f538c73e290f4525da9313efd59c17fc01048d3984c4d9e5acd7eade91b8b94"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "b6a621657ead328e52dac0c393c412e76b0fba0ecff2cba01d29d3e7b9a504b4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "dd88d09fdd22bf55247f7ee221d66d23bd7b61f8816a34048e65f37316c22108"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "00b201dcf52a7b3e14c3afec11144fc8bdc4b89aa4b988ec900bf9a782932258"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c2e3a34e986ce44562e192c24f2b25e7546b3a2fe696d24fd0cd75764f7c71ac"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "972b2b3cdb6246eb39c1d2f0e053eebae55a10779e7e7f8cd26830866b05b1f8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "cc92319019456ce68d82288bd60d63ce919f42e2d8bb4e42104af604df60f887"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c1271d05a95a06ed1c35e82ad48687585fd01076008b99b837568aaa1c5500c7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "13f1700a68217799b2591e5d2691cbcac7cd3fe4772a974e2ef7804c0f59bfde"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "2c28c7ef9cf712e365c4df324df59c533025ccf2deeeacaae2da52857392e608"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "830f3807dd74df99539ad00428df0589b5deab6002346a953ee2f6a734848aed"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "dcf1c71063de88469ba897cafb102adce319853651bdc6751961e59a482d974d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "6b209053032ed619e67dd46c28a88582f9a667d07f843823481212958cbbb4fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "1142660b02ad9f6c321bfc2fd006cbd6306b37c3eff87381e301ad4a09287f69"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "13029d8efb3a7594befeeeedbbd196eae7e51d5671312646822c01768d8760d8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "ed030ec49f7426b53570ef13b7e6b99a9c3d44939ac7c1ce94e111f48f1f7cc0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "05d2ff9ea9d46d4e5d186831c47a6764e659175b8a4b5462ed7af7f2f2442407"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "847e1f2c5fde2e7ae8a6e5d52a742fd47a1469b939dd5584403791c618174328"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "3287ce298660153795ebf3379a52585d3579fefd8b05cb345e4ec4dc06109a51"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "463f3c110bbfee2a820df26962b46438c6661168351e1dbcb6373547a44e7b6e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "62a8bb5b0f4ddd8e8eb31d0c3d1d84a366a652b0141b907f4f60a4a509d41e61"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "f39986ae4448806e29415d3a2debcb58fb30f995f86ff190fb4b35446735233f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "9a80879d242eddf992e4e81257ad0683870c1cac186ea058252ae35e4a62ca03"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "8737bb93a47bfbda97f0dc965b110a76ca1d000bd4e41f0adea60229de25627e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "c0314bf75448285e6fdba996a7979794fa97a3706cbc8a3dd09be631ff365b3a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "c26a2b98ad1926ebe55695e4314d394b3a5e78489fc03653b621136cf344b35f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "b7a4755a996a0ccaca41053a593f51499fe43cad8b60f15945ae4ae3ff0806be"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a1ce1d296aa57a3c51f0685b4d40bf769f30e4b1281f9d253b789e8a87658ad6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "374beacf35571cd6c6508bcf979c5d389bddce845eec04bdd3a67c3be59f1d88"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "d70ad5050669c965a0b2e9f89e06e1606d1492079b6703c757c964d11202af79"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "01f0545cfef8d99928a0cb57607f454ef503ad5632326e76599a82c887f3393f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "0f0b2ed5d2144757069bb485bb29984d82dd3304d6e74d4d9a5d64779bd229e6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "fc4f02d7b74aae308a3cafd52ebae2a856959d9324bf4fdcf86b1ee65443625f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "cb5044a4fe01929f602fa394f98de17b586170c0717179a6419fdcb73f387463"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "127923720a41925f1f5ca9f6e04525b5ce87dc3d2a86a3d3960d0a41f031bb60"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "59a24ed4793c4e60a38b06124a12c4fa9c855f7ae4f09685d316ebccee0b4224"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "da42ee913d08b9d2e6494279679d1150db632b8e1a87f9a5c147c1b6a553a7a9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "b32fef81582d8214fe67c16c89586d632b880f72d093e5f5f0e019b419d50172"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "9ed2c872c4471606bc418931bf952099f9f5ae236f9fae6026478f5e65c0fe38"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "541216072d519bf70aab2f5133b6b32194fbd97ffa97656a90ded3e3248cb17a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "dc401dbe84eb722cb32e764f5bc210e01257e77af7abdbc86aeff6fa127420e8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "d8cc619fcd807af52d42f53b1ec873ebc949151c3b1376bebb6f079ca8d15b46"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "e653aa71897b682ef22789d9cf46147d90eda6be31bfef4ffe5032bfbc65ab17"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "ecf7075ce386219ee514e54a6db7da7d8043709ae28a0efaace49e4f4d4a76fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "ea498d61a34c44ad54d2e378d2b6d5bf35d1d35138583c0b089b4642ef86936e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "841e6637ab9ff5284ae18e1fb5d1fcf8f7a39cde6f10c37d2895a5fa16fecddf"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f253281f24315e1e4695669bb9e40c1dc8c5d9c410d1b0e970ccc877c7b93a60"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "596d680fbc5d365ff88932f622873baf72ed7fe18e98a8b5a1651cb76851afec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "36fde6ba98063e1a2717213a618d2d1bd19dbfa6b1f51d7524f11a6601dc2d6d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "65c584ed5b8882089636af8b01f410838d943e02a6a76b3b95e1e6d7577e46c4"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "d1255a0ef710cc625dcf432679593f085dc6474d37f4f6a04da85312fd97a6eb"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "7ee6fc0141c15c424ae8a16ecd0db396944d2ee9418b841116e00f0bb981fc68"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "b3d99a2ab7548684dc0015058a926cbcd4a1546177f1293ddd3f2d7d99ac4b78"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "8c98fb928e1cbdf1e2c370f4d8ab32dbfaacf926799463706414e896b535520c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "2bcea366c1a0487a5b7f54a31e4d4cb724444d61db4ceb5eaa21d3c0685e54ec"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "e1a4c2a9a8f80ecbf7c411348af28ab4b4cc316fc4bea164c222ae4354ea0b57"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "c2ba605882904cb8305ea805ba5c6130c7bccbce2bdd625f4edca87f4c1aeeb0"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "0649d772d3c64a1d3a8d846056403e83c6550dc0a2f23ba938d9563743c23bff"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "29138d35204cecdb5ff0f6c6531d841a61680e1ba0c47d24c0084c6f682479b8"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "0de2f4261ffb3e7d705f4028f61f2d8cb00bcb66beec403c879592528f9f69ae"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "92aa77767484e46381ecf47191ab7225b11284268cef5f6adf54560f3b2b61dc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "8a28938a4c7bef3b07c3cb53efd837478b887c1513c75635f18c6f5a17cbf4b6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "ca68a3fdb3948ba9e53c946eca64e27943d3364e5e276ac7da72867cb52e2ec9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "9379afd2dcaf38c113d71ef570322b123bd3a9ee5f7b28b51afe1e7033bc4575"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "36ab347af1ecfcdb2c16bb2ff29d34bf77267447611863c869fe4a1525f7be1f"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "879826097f7448e9b6b64a622cb6b7b1b72f0e0572eef7c778dca0cbfcec4c3a"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "178f9199c5b14715cfd91945bc2ee288fe9fbb93ad59f7b8e270d16a9390eb68"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "9f78730f908ac4de8ac5c756d827b32f4ccb4547f849fa6c315f3b1c56be3804"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "0cdd9ec8a43873cc4bed89d99bf986500b9ec8210c49edcf1a5e9d90c62c5355"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "414500e9461c2d61f1664575d45ebdb3877026d8eda51351f4dcaa6c39a0ffc6"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "a2970a19029a1eb5b15a2a492a63ea2834e89125bdf770c23b15c0873cf3a9be"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "08f1ec413903ede7d95a421ff134bf070c1f80afd223286fc366cc825c383631"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "144ae28bd831ee5a52ead8a9fdd900d69994cf8f4c72c7df143e4b2e6d5c493b"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "556a806f871943d89704c87512ea057deccc15f537a626b6fb151e3a355f7882"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "4cce347c9c7bd0f0ec0787dd7d927dc227320f65cbc399551f078850433728fd"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "e760193ea78e23da2e12118e346be4fbad42f051696afd10af39041b143df3fc"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "4c504e78144b96043d87884314d79b684efa2e3a0277858584fdb17a046678ee"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "a740299792e640a74834cdf9196ee3b4420fc3b5f95f927844dd47a15af2a9fe"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "b09ea9120b171866009bb38bd859ca4560d11b7aa8e07edad48b9ad962ec767d"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "247e479ed67b842788b023cb68bcbbff1d52771076fa6340b9812179fd961da9"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "ca8663931a1b30ef38a81af36b2890ecf82f47ebb778f8fe5a371f069484ba3c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c2da6715bca16b46540ac07055b6924886ebf7f207d9f8a81d6757d7eb0bf8ab"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "f240fe73cd1badfcebf578c5b1d3f73f68ddfacee376920f10a34090a5821f53"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d87668d37af725890ed28e1e4bd0bc6344beb3977c4353edb67c9297dc55c22c"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "e9ed471b33e214cce0ee8f2e28fafed582192adcd153b85f8555852b4b9288a7"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "3a2d0b64ff0d20283d2910ad886428667ea2e3a613f5bda399cbcbdc6c069035"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "b1888746b3fab3b5b7208e67e1066d122f61a048376478e01d505d2fa018d227"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "6a37b07e1649dcb5b25e2f61d4f036f8c44a34d34d2b1be4616e119f574a306e"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "84f7d3bfd003f59da3fb13417c11cc071bb38be0a48f0949d75d6d5601971073"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "c7bce3edf9a94b4adea7e8ae0174665343047912c3ade9f64638b9434bff6514"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "a3fdc5f2cc7a1f6ba7fedf54e673b86a40ccc28bfb1fb1385dadb8af3dd4c899"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "e9f61ead55531e54d65cc69819f68a2b526a54a9ab9757fd3ee664fe26e49588"}, -{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "c4a4fb235207b47a9bd26e7d618507c6f53d73dfc985219d26b7bc4602384e72"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "59e8990669fdcd1264eaf17137c917bf27599c5b9daa792d5eea76463b3a33a1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "ea74ecca979bb3b22c313228adbd666b454e1643767d2d4922563076c1d9a3b0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "d3b27116fea720bcc88288ed8625443a8de83fb4d8b12805e1c71a64dfb57829"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2a75024b45095bf73e3160fffb7fddb27c318d346b396168047886030174b2c2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "98cd95b09b3c7935d01fd1df01407bf4e7c6a671370da4327f9690ea24de1d16"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "c07b10737f20af1ed9418ab30c06a61b3dbde794f103a469719d1456745185ca"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "b6e8d136bfa45a7e21590a117ba41a5c229c68e1a8598d97fc3488d251169921"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c9c9a61302c969e8ecfc5004447de46ea6a064cfee9421d083444525f88539e4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "4e1da39db27f1755fc245e7cf240f3a46789843a2bc561721d45737dfcaeee29"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "2e3b7c11c7968bb2234a2ccf6e04acb85d030d27f5173a33765ac5c21b0ae949"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "3de7e53dc567fcebc7fa8e336f4ba3a445ac677fbd4448d37ef6320672854e44"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ec39fd31422720a82734debc8db1ecf3331951aa4abd80f290866533932e0e90"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "3da870c2bcab6097b02bc47d12d445759f8d6fdc4a48c2e56efc41bb851ab04d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "08bcb0b3504029b4fdf5cf527024fd4e199bf814d25acf8f191622adf2caba24"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "04ad55e92b1907a14a2c9c137126d92c3c25a41241f303bd21d1b7af8256ed27"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "a64ebf887f22885f283703464c55503ab200e167abe42fb08560d6bb2bb9e236"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "dc73ba7e41c19b91a2460bfac56381cd9e3d0f9ae995c136f61feb7081089076"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "186006cada6cce9c6fd924f1aaf54fad3d65c1c9873452d7fd70b5db6dbe6399"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "de9425cdad3deabd17a8a8271e38b8085ef796e0a0ec2b120391d2e327d89fc2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "bd6acd4aad2d53ce52fc2714c6807e3b43eccd804ee482485a7516821c36b672"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "87212edb0bd3a0d21e813e5aefde245af833dfed3e339e106a4c6b0ae0a7737a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "ae79c917e12b0f2ce9707b362e2e450245a5bbd381070acf35e2fc365b7a3449"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "a8846752cf0533d7c81444c714e3a714b268668f0337959e964618f71cdf281d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "505c6afe9d742b5a00bbae0ddef3e451d94fd5006b7004be84cb46f474033cf0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "1d77cd27c574520059991fbf8961edbac9b546d541ce14c80189cf861100b8fe"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "70c999f6baa483ff998577e88247087bd9ff2dd9fc09c3f8bb4dc7f67c93c189"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "e41c3d00cfabcf15c0ff09f1d6957339c727cda5a42b09a7fc8ff105a4da604a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "773394492058fc20df0329dd8c0c737d6c8dcfb6edf5d1de6ab57beead48e0a0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ff1a034968bd887a5094fb05fa55295cf0a3051ef94d97ba4da40003a4690827"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "e7ea438ac5d5f5db1562587797f0235c033a26fceaab90a89374c700472fdd72"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "d03b5def6008a767a75ce77d6ebf0f9fb3eb5d14d43ce43df8f723d634975b30"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "b4fae59c8681024d6c83319a97ac5e64f7b3d06194f97b31a2ab58a65e47ae98"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e03ab6b91cff4aa1ac2df6e0e056e9533d79589a381c3eca2cab172853401d94"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "24fa5651095030bcbfdf3d60bd103aaa0cd82803ca551446f0ddd53a59ea0e99"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "ff70d1ec7ab89243c318180fa52fd51acc2d0358988fc3b69c74907fe19c3b4c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "60060b632b10488419feb55371b27e5f2d52a9d6e9c17bf1151e1663bfbda805"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "a26e9f886d265d5bac7843809df538cd1af4b5c61ccf0981aef976af5b34b3bc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "fce0bdd1a22f565323a25de398687a929ef8649f33f08b243e9945bc9531b9bc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "305ccd095b6efd68f433df7f4e936a7d949d4b39250b62e399ee6dbc6e78bcf5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "b5de4b36c895f59c97dda39d9bcfdb38efce6c707e7e3e0aed3c0e694fdc953e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "f4f442625c845eb38811fa827188b3fd3b9e24c3400b52c53ae2419112f2188e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "0a1e538c66bb4c6a7fc2dafdc39b9ef2f2252c65760857eecc652dc7557f534e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "50ee492a2bbf1e5a8bcf32dfb9e9fc911021f30fd3514d27c7cf254e248a2c02"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "73f2dc656735a7ab78ca324177734ecf5a6c34b49266573263974214566623c1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "9caa300f1f4bdda9c5ce3e0b5999e1a7fc0a53f178417fe34f1b98654c374a73"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "39f30140a5df931f78004a84a5ed1bd4002e14e859b16e553e1d36185a53ef82"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "659b1fbb28be6b054022a5aedb25341c23cf04b6624e5f9b331fe523927d3369"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "201e80a35237e491f5af4b7dcff70b393288f238a571dd56bf8091630ce47603"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "2a94518a06d087ce694c83b0837ea305a9d6c8c1d70dbccf8f2ae103f1f50c47"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "a045d202d615b0a0b3ec13adb9f53b1423e6da5f3b352a5b8cc269e321113e4f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "88bdf91507b7da78bd9207041d3340e7073545732cc8aa898486552321dbdc82"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "260a807f4e66a32d7be82ef0eba35986464055d8f79543083d34b942e0b31cf9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "98c96da84891183599d62a113bc7a20f8923db9c39a60cb31e8b2f6d97462f6f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "789cba366d9395f678e744301dc7058a288350b27119da24fd5ddda94cfcd46f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "e5c238de776d7eef93d80a2787c69e6d4615fc0651ad03cbf070e5bc31773543"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "fc32e224657c24cb0ac6f63ac3af23e993654e874b38023f5e84d86bc3cad7ab"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "fd46741403f3d96413bb1e94c44837bfc5967ca4201a8858fd08fe423600b09c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "92377da5f4c22e554321c1b58f00504c14013525d6a11f2e4b35d3aba964764f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "42702d5931ec32120db4dc21debd82871d8dd74a60d46f5c22613ddd57f480de"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "e81b427ca2254af0a7b7ae7b61f4edad5fb8f2fdc506be5ad8b27e034f5a08de"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "a509235605ae65781c569ccd6b8d27472e84fb269c84a35cca26c8f0dd2f89dc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "e7aef233befb29d878bcd1609ac86bb4d4d83e64b4a3e0893b2583d7231ddb49"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "a0f8766c066f2a9fb4c5806402f914fb47378b1ef7a5d523e475a29409bc6fff"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "3596c0cddcf6fee3150d8b797eed6368a2a203342349187b0368c77bb514f944"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "d2a7aaa163ab5762d1f73d8c05c31dce88b6f930f21e520fb7631710374c873b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "707dd1d39f5640aba0272dddb542bdfaf82628ec0d63516020f1f5adb8e617e2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "f8a8c03f9135c1bdc361ecd8915123a18fb70f6b1291ecc401832e378dd3fe9e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "6c42810c3d22ab030ff5df96d619161b93f72b559d45b790b72a2b067140f7ac"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "f2e1650b52d7938cbc5253aa90cc98530896158ce3a62eb29f1d706eeff5731d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "102138c353e8a234d1dd9d5e5cb157118a0e01486e6b202bdbba2f5d0f756d2e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "6d7755709be88f624a51d74befa0f7ca8b3f6d7bf407d3dde315092bbaf69e1c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "043f872678dca454500df37a32201501f76e567fc0a96870552710110f539fdc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "14e10cfed50ec32a41de322bb2d478ad744ddb4ed5cd82012c86a139929c5127"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "8c3765ad10f89d7298fb638bec011fedc2689904e6dd721a476ef36b32a4bd11"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "7ab860914b519215cba70b7c942dde5674f46cfb3a6ac0248d8fea8d0e612497"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "c7a3ee7667061de992f3996a610e792fc85347f82fedac323e5da82405f02e4c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "042af4430a1ecdfc60ccbc5b0ba18103cfbccaac74c011534a9930949bd78a82"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "7fdf36f57cc4edda66c99d9bd5f1b42f76bcf2c2eeaa4ea620863c5655793205"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "70d61fa5c404f3fc5cdccc1d1cafbb96aca06d36c742da59f4aee385a79a166f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "62c940a3a3367e2f155cf6af608faa3c1a235edb9e62cb74690888f5e679d8a4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "2fd5b94688a4dbb7ba5e9836dac9ff56678de705eb36e58260cc05c5f2b3819f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "f8de5536b07bf6e04966e7e595e6aee5592411cb3b9746040e3bfdc1ec1b74f1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "c544c86870eeaa13a8914608dc0c8692b3a08f08e65eb41cbb42347fd29eec28"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "08cc3d7177655a2ebe366a0e5c30b29dc563b6ec05c2326d6872cbbaef6f35d0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "fb4522f9f3ff9cd082c993c7262bbd822620a8bd33dc2d9a08668034c18e491d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "b5dc2466d3f83807e1c9992c74c8ce746ce0d4c588b71b190eed9ede6aa90dc1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "d4ce2cca8ecddf40bc8a01e91cbcb892ef9b79662d1b2b715d749c8311f78ebe"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "0b2254b48cc49459c30a52a2bce4440f618e0f45838ae0955ef7afb0c676a6a9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "04e96b93aeabb85f73f29a1e5539c10ddfb226cd9c18afca2b63f65a0f746b35"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "e8d39d4078ceeaca7b8a7be3c22cc972839faeaf6bd0a4afc0c161d5aa7365a4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "8f6ab0605c4477e19e76699b143a52f1dcbdc2df2d14a6e54e17bdf244e2e9d2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "8e65729d83e077ef8fdeae315eb0fdb6da903b35f40ddd78dac70c1761a33d23"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "419dbb3464fad29bf2e9c9f17b1251ea50824116390cade963ab911ca9e21cff"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "9b921f0acf1f417c9100d3bcef142c85319c1ad34fa2731816fa6726074c0490"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "b58f48d5103476fb02b21979768f640e5858a93279ea7062a007ce4873531d29"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "5208cdd062ab17e9c98f98c0a8c4af9f12f68c81f8e9855da2a9b88f58d4b26b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "73e8a00e02e68df14a278229a21e8ad4af183ff47ca1d74105d13dea32029a81"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "26816379287a0766210851bbd4db76605af7f807972f1589c3d71575a5208a2d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "8c50eb1c23f707623a8eb29cf62b26ad09019e1af9e847b993ce21b588445ac6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "63f956ed36614650048c439a9037895484f30021a16d71dd1d6fa45b7018da45"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "8f981d98bc7b0288f5b205b9d0d49912c827bf563ae5e7f216003980cf76635e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "218e3ec2f11966a597550c7e6e6f6eb901dfc5408e16bedbcf660d82c131f4af"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "dad262ad4705fcf6f54332e315360b370d543447b49f8cca9383ce7a3c1e4469"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "e7deb045ff7ff5ee56db29e6fd44ef4ad0b5c3b31f6e1af5d5d7405d58ca6295"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "e467092fab8b1d087abb70fdd51c209fa34d3757a262e9fce0d335029ce8f262"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "3d5cf752e1c27d35705837d3878374267eaeeb0fefd8abc9f5adc6fbb45a2e15"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "e3bcb1addf12193c1797e381bcdde3f8061a7df5116b05c9065eb9b431890a0e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "4ad6c845d7ef18c48961bc1a9c241321f10a3e26cd75ea8156c21f6d6162fc80"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "f674b82b9c4f97c3abc5319df57de7930390951d37d0806ba01e627a7d43015b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "7177f856a390bf6793dba5aeb80c32d81890cc609ef9469598cb5e838fa06c18"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "17f3e37ce70931861e9bbfb1082f44078ccf0172a5e504fb5624e3805cf72144"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "d02af5f99fe509092de5e82e19858cb9dfbfdd22b2edb784cf5fdee9cac947fc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e19ab6eef830deb1b4f48f4709045df8cae5fdb643c4f28462802692ce05b243"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "4400e6f75c9f8624a1ce592645bef340dd49bf37c9ba404c43d93ff84c3507d0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "fde5cd532befba5242516b13430df053425a2ee0336acacb4c09bf257f1367b8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b7bb1b820cf9acf82a1061ed1a39997c4d48aa55538027b0e418fa9205159a1a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "5d9754f34553cdf98a01a1c4fd4a82e66a2ed516e67bc469e97d3e20591b03f4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d36159c16a6bb28152831c1ef1717e6f752dc716bc28f06e8b487cecf0a98c38"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "cb40b9ed6abc66cb0b5e09cd8f8a7cb8ca3c140949c0883a7f1a63e260030588"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "56ec3b5e22e9b01b1c3c4a2d8e9eee77ae163fb5d3611a7696ef87a3f9a3b73a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "cf1653413cbb10a4e6c170899e670c01b2124da9e752e8eba3e3b33c0bd9d21d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "39777049bd8beab4f9a3ec3ad99bd5f94b22f5830359e6cc30f94e1cf24cbdf9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "5925e2a889d37eb1851e54b76c1656f4e641ca817405614b579f84b450813d9d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "84ce5cf239769469a07451daa45a7cbbf507862393f51f0e18053bf6b532f7eb"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "e3df6864e58b638012599dc9b77ecd2741a2d6af1663323f0d3a6a45e5691adf"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "f48ddf1cbc18e975f74de2426af1ad85c5d1d664ef8a6e1d759e9846241925ad"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "69d78a9dbf6359c48a3c4961bacd16a4a9ab7d15e3a374736d4b8fb0459559b0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "4e73fb1ce4fde0bf608dc0834fea040ce3444acc1d67ed9ac2d1a88e59bf98bd"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "d1f6a302b7ed647b454bfdc0c8118e75f6668555a19ff89ed6990b3441ff394c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "272626c23d057c79e6a89a9dd94e57f0ca182c41510b4a4681be8860280acedf"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "c0ae0b83d394ed1483a9f933f931766476d225698f8881c3ac331dfab8bdd9de"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "8040b3b3ead6cf83a7ae59c826aeca115d199f4dbda16b6fea658708a860566b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "14d950b948a1d3e6e4ab8d59be1d02877d10bc75cd3ee4dc441e3705953a9429"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "d6fc2893c7ccf6b655f9a70ea3e104976fbe7c012cf1e89b5720f7fc5db49e53"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "2e1d2d16b939e0a01508cfd17e05b854110d35e2d74c06ae0f7476dcdbcc192b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "4bcd0113f9fd3be67985ccf1719754bbd5759b9fa9e0a42bce005cb969503cb7"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "ed3f7ae5964c33713805f2356fbbdfb09e163b4b6561163fad3c5a7b943a7127"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "14cca82af5294e55a106f88b8d3dc65a7bc69e3a28c72e984aa3e104b0f3c14e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c7fe202d4307a99bfd8847003a230b07f0abdf70301d1aaa7aad085bcc0be704"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "82eaf99426870e865bfe997599ce53fdecc98a99b8b15d98c79bb9eeb430ab2e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "6d9850e80229345d8f120e21c3807478ecd16e3f55b76d1a4512d034d9b9222a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ed2c68f25267017cb203a3e4ae980fb3ea522ce3ae918252fed1e53d433b1760"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "6ee7963b01be7e30fc472f53b559978180a098c833fd06b9e9e79f26ac64096d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "de81afd6455c275ff653322bcb5e3a2fda014fd347ecf29c60713215336a1787"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "aebb99b7fc1c73bbc975c73819f62c51ec6b8f5661e1ba996fa06f2ff309baa0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "76629d04cde3fac75f50e493a0fb83bd4ce8b7e85bbcd4272f0f95339a54acec"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "d4f34965cc1b0697280826a14f0bda0ca6e5c583a6a0b02f7c633651b1216014"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "08e70308f307844584bae7bfeda8ea1a4a851cd1292e800e8a2d9a0a940b18ad"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "b68c60d2229ca5cce85544995a7734a0aaff4240017f33798d2f7bbfbea305d5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "cc3f333480200bf957fda4d6a7fcff7c4d8db92a0523d89813a3d15d62799869"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "80745d3817473aa5962e289f711b0ed1f4b4c8fdb67141ddaee5b51cdd6589ce"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "f118f2bf8adc7de168ca255e9d92640031b2bcb4a7a9622372102e9b3b48702e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "30ea7b10bc022dffb2c35ec05df26fdffeef92b1e42061c02d38d010686e9aee"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "4bcbcbe32058473358cdf2029c37ab6c632280f8c1826914e4fa35e7c1bb66da"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "a08d2e6c8d6390689d5c6f2c60b07610de4a7767f8db3768e5e9843b77b3b351"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "0f09880bdbab574fdcaf87bb6368579c1c12b7a3ae9e01e693d5658555205d56"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4d89c1bd62f90733013b39fa12404ef46775b5d00c37c11cf1fe802c260b1009"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "89f52fa5f53c95bb698c6b93f917462335b03f7f8713aa9a367fc5b32616aa9f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "c111ad409ca72e91b6e961242c0395e6a49d07533dc18c1550971a9241af6410"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "0416f98a5bbf76f65aa37a9b56e580398ebb65c17ae9fec277df9dcd1f9cd17c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "6eff9794a42425e010d864789929a3b8217081d77edd3819d38569ed699696dd"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "c45903759c509fd3183a4cba849eebea4224ee8554b7ea6aa86fb391c909efcc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "a8905a39d3ba96fe9b84059e027736431154267c950401765c8e1b17be913aa0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "c6cc22cd53a0fa91771fbc49dbcdfa2d522aa9bccde85125cc8bab64ec088041"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "ab5513e625c7994c48cbe0f41a8ccaf6f69978c74616929155d1d07a85aa7f3e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "4106b1dc9722cab1bb9c65dd65e8de1002e27da0d029f30629e7a38292393f35"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "e20602a5a22082394528d3083cc2a6032d0bf4bd67e1655ebade8971285db542"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "fc77ef39dd1505c063ffe1ceb1903607c63eaa7c61cf11fb1cff314dd9cf330a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ccd0d5174ed6054819c3731c36e8185df0e5a2b44458187b0732f2c629af7bea"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "68dfcab418fe31dad693084dd57fdb1ba413664eaa3c2c74a61bd003109025b4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "7fbb0506b1b78de0a2a8e20bd2a6776f75ec4ce061c214ea70eb19ccfa8813f2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "9a9cb669a7d3daee87b9588c3bd1246f272dab1896c19a7a289828ffcc8e49d2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "40eede4320f7aac5c4e5e7c9b671b46430d5f7e5102ab325056c875db95787fe"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "ac1195d4b07b17b837b89aac5d560ffc60099079f94797a3b5801ceb8c897357"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "451714f7dc6ce374ade95410acf9b4aa90b99a2c154829a7bdd4ce3be0277a71"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "87e9aaaa4ada37effdecc6498dae640e38c81057bc83b28039ad9903b8302ab0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "2fd545c27949237a8ffc916e426e57e74186d47313ff682cbaa232d02c3c7e5d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "ed08f8ac9922b5fde560bc686cd5ad3001f65a63c94f5717390234bba684ef08"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "35fd8b8614f21d907686e5416b0748bf1c494ef8971e13992045e5f9293588e7"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "59d8ea47f8b85bdfbf3d6fbf5f96e4e9f3741855e6ebdcfd2e853afae1d59559"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "2e30b104fe09f7bf9905a1b26558e0848abf9a44c006279f2e6bcd9023ee0c1c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "6c7e9f77a569d5327b448e3376606e2ab68f0f45aab890d28ddb7843df8313f8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "efde61500b5fbce98f04cb7e1c8069c3312a0337c3a85c16d56d828fb6383e9b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "b30249ffe6c1d4cd03d5efa2b57d36f55791fb9964da7a16a9a99f948fe32492"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "bf4080f290e8d50fdf229371ebd1804630cdf85a7cb67f0acaa68082b682ee8d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "750e76dbb4cee89255563de91fb6bb399c93d0864cc5e0803ea4a2fb292a1e01"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "4bc1a51ba803be6383b20167ea1dad02c83292fc5560bf73f0192c7ff8eb29c1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "297e7f9d78c27fc162d7765a63ec2e97afbe11be813bcf114aa0e49b504cc1dc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "e682835cf08701663f52e6b2f671afb7ea762a572fef8bf41b4a11ea60d766b0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "990af0a3e3ea5e9a32ac77ea31d98d0b746132df717859f3d1d8e8870cc095e5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "973a4978676527ac1a4ffc6afb84ae87a0487e99cba698ba276aee045f45b1c6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "b76a8f450781dd00d8bed367334807e2c1f11d40f9079913dd14a38881e44981"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "8a420946a3083fe21b68c8ece7c088bbfdf8d178411416892bb9711ee4f44bb7"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "04b9ce8617fdad3e2f2a90f44c46cb99cea47849793797550354beb0853d94f4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "8eafd7c1538d2d64324a87c4c764e234592edd8cf1acf0424b380f5072646df7"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "783fb82e2192f859679a8c51ffa7c8ffda9ac9f5e187d7d120d555de768d4c79"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "01aadb5aa54f6597b33156679378ee30f36fd4c24cf21b36bfe04cd53b56206c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "33deaa079310518484f90c1e8716b83bff6067fd98f02ae732a2c1a9f0de6dbf"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "0d3ec573beb9c3fca91773158f3166cceae7be3d10dfcb26a33031dad135428b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "983def400d22ef89af55681851d558cc4499863e37be051063965be174e8366d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "2b247ad182b72263cfbf9300af40762b1ea4b49b04142850bc24d0f970c9f1a2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "584b2b20626f77d071199ac96065835b8f1b05d63f1354a280573a0fa17d14c3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "6cf52c6536e3c2e18d6dfcf7d603e52b642ec20a8d09109ac8fe78d1cb81087b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "df5c1fb06b7f232a7e91b1f731bc9234d6dfab181f01bb75d7db6a8c9290d3dc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "9ea60d6db3da6ef40c94cec4259ee7a0f53336b1def9936b2392ec484b375bbd"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "3557005a9936d5cd405596a9fbf0af43c4cd39acbef6cb16fe210cbb576cdca4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "0ababf1c11fab52e58f6940839c534b284d02e842b58c277fd5da67b5645274b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "a02707d9558c64c427bff709d3acfbcf7e712fde8354d84fdefd3bcbcebc2080"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "02ed5ea3d3c7e3d353514bf153e2c597c4a18184f5a09cb456d1c8eab9c35137"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "7ea363afaf1347d6850bb37161c1398262c2b0002a8188467e684827fe18bb56"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "eaf42252ffda9064e58896f24159824235d9b5c88a0d1b5a8a154696dbd80092"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "4710a5ecd0fc35616bd449ad2bf82e6e0145f227ff1fbe1714d9bbe44eeff25c"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "c9fcf657e045bdfc965a705aa6cb8d1306c8417c1c64ef1cd95a6be36f3c56a3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "b2226c22e14819086340aa66407a5a18630505fdb36d724ea3a5b6566d5b85bc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "c42c53284ce066fd8eb4a42db7e9c5dc20bc300bed4f6a5b6c5a8a8deffe33fe"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "07b48ac3405ca7fbdd67b475ff64637bff8e3101f6fe3509adc14600af90c41b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "9c661e2a5830baf94ebd66d7efd5c450b0830d4f1691d3ea0ae54b3ba50a3c75"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "85647705ae6f30d41eab9fbd00c89cd943bca079835600aa7c9566fef430a1b4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ffc3b646d61002fb8640bebbf7b1c2bea7fd474156a6c7aaa7fdf5bb593dab6a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e9c940bc528d620bed6f7db04ca5673ef7c1ca896cd3e1a57cf52566ddc52070"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "1114a940048581fdb5fc0c10079898f98125a2079014fca4a424736808ca8ce2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "a07b886489025821fb6a3c2fbd29ebc0aaa99bcfca42f078e7bad28638945a4a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "2fcb1b510af68b3d139852741dfc7bf4239bea39815f063cbf23cd46bc5de8cd"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "82d70bfe25f386e365bce394843ae31638c3626542b346121b0be1eb29a3ec16"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "8fe0d80fd9005f17bcfc1c83568979125595c4696766074323d249d473ccd40e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "716b32a6356f949e5b48007723b092a2a5301e4f10b87927e5bab6b33356b50d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c5a85177877e964f458318b1295696dd871f2be317097c0089b5b00fb102ddf3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "8e7fca55680ae8f3a8db3462f6e7bac576360bd45bc4bd0d6c622d91522818eb"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "36ddfa9c85468078015dbc18b6485d62f34913fa7c3699a8caf1e7f8b5ab34ba"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "dc2453c198c555c59f55d6b4f1511fd9c01e090f571be02e85df85bbf0ac8d35"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "af8c5d167e3b858a1f94813d2dc68d19d8f15fb5982e5c0fa8996aa26d5775bb"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "8220272aafca3b81d2ea550ad2f0d9609c6f69bfe371130cc8011b44bb980a6a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "01ac47d5e0fa60505be0247691c87cc354ec06bfad44dde4633c7817344c9fa4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "214182a3b07d5a8112b72da82ec02d860fc444f55a2a94b198bdfac7f8ce8087"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "4fa56151617314050aa2051773ce720c1c1b7fab7bfd2d3888150fbe1546816a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "d1f5e22cbc5ab894783181b51dfb51350500804e24ec12431ffadf53c3499dc0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "5a7c38acd14062ec365df98a590575e36f9cec0e1c48b1e395c70e34c1c20057"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "08f41f9540b64292ae498e48292e986448b9e1cdb3bf3011121e46d1c4c39f90"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "c581e8da9acf59fa91b9123065ced9261279b2b06eee33dabe6ac2ec828c193f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "661aa49f80f3ed413ea254f775004e7f83bf6cc27b853f3859f30c199087f5d5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "a5522b7d48661a9fb5a5ac8b440bb566a99f9155a60348fe0fac475287a27551"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "4c92a0732c098763e6d7e3f8b9f857b10464244e421c228cdadd9ce029f01274"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "a289437c3e3444e82fa7acb282fa51b8da0fc8e9999bc90c9832516967912505"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "905b38247db39646a302dff75b451682eeb4a787c94da4c2598a7306f92ebde4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "6f1f7aee9ab2d86a9a9699c9095e0d27682d27cd3bd112a8948813a7ada861aa"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "067815357a567d634fbf9671263b8afbaebd19fdbe7c8d1edf0b3e38fef42453"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "029df0fd72029539946767e6ece107371dee428154a5a36a6b66191700e10f15"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "b15d806beb97139a44c683d17c1e58b95ad3da1733335e0fef5e651f176aee3e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "8f73a74899bf92709deb72f8c915e47de73b16d81dd241fd726aca15d8ff8f65"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "db16a367149df4f5f9a5a5040923859f910ba3e3aaeaa3b528015042854940e5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "19bc9ab2b4111e2f1d8ccca3e1d17158a7c2750619daee3a0a344584d047aab5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "173e66394679c5ea8b7e255c9c6684589ef8dae699a83f3b87a838850d137877"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "fb365988eef48651194f9dde8229c0d9c4639627f5fcdcd98823d3cc94380c8b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "454be9c49c2ffc957c592ac71547926744dba6de18aa5d0c4b95599f778d89eb"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "5c15fb54cb6cb1139d9545bf6b4884f684617f7896bc017318cd77c38cf7d79d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "09a232dde025a7c0e19df34208bacfaaba224baee89c79379fc2b0eec45a9356"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "9e6a14063f7e7a3d2df9833adfd6bac0eb94d1aa845669939f9506b1f1dd232f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "7061a544ff7f0feba2bb0d948c1e78dd9a892229fc64fbfe8a7e03c343aa43a1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d19fbdeb714de42c85ce949e354c32e041da7cfbaef183ecfa6ed474bfb6bc9d"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "f9507d92e271ffcaa8a53365e2c27c973bd5b917b7761a38ccbf8abffac9c1bb"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "21c39490fd70964a05ceb95b4ecc46dad52bc339a3113f7c3c7c191b4655ed9b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "5d775ccefe0724b1bdb05af82e34e4af9cacdfa3e48b55996daeea4fb976b2f8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "278158abd7410a900dd80b8e827d958082ffc6e30f6f312621fc13d321879c31"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "3eec9547c62836bba22f04100a516e777d99c0a18e35b7138951c39490ae83ea"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "bd0a45151d9ea7cc790939c9539dad3324f1ebe1a9cbec0bd670ffa15651358e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "034e3893032c90b010631a601a11f9f90e6c4d0c34090d8f867b2fe7fd5c275f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ab17c11afa24c03fe99240bd15ffd27c79e7a0184474de4bed14238ca100d235"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "6a5e1af513486ef5cacdd67b3568dd95fe7ae26a6f6ed82a2c8db586ab77641a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "691270dd9692beafbbb6771e77a67792ddebfbde18962b259210c76543848d1e"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "5fc5d367ddc86252f281b2f967027ecc1798b1e9a558135c1a29b9bfedcbb8f8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "e4a4c22cb4ab046c306b7d74db992186d7b78dc0fc6566d56d470433c2c08c6a"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "9fa314575afb038ed7481b65003b0de53a698bd3f92f128ae6a9632bdbe1a966"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "603eba18c1681e7c22cd3f9e0e3a74c3c9e0fa080702b6a46c704f4fb178893b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "05f208d361864542e31da9fa080709f05c102ae044f6a1d0ac54a98f107f59f3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "55cfa251056529ce945e4404a864d8f84831bcf3d2a83de1b1c7c8abd72ed900"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "ef3463ddd018e2c5e6100eeb8bed1bb92c211f8662b39d5d94cfe1e5c1e9dcca"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "d77dd938779c3eb79c4a72bb25dc794b77fe33579fad8f3cf2166e400ab55c6f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "1f074f8d1f5ba3087f0b92b356dbd8d4fb6d29eeee8f8530baad0172ba7da0fa"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "5b6c861603d6d10d03375fc7698fd820916800a63c7643b83db9be83074d0204"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "2fc35a8b8c757366197686d510ea11197a72a16262b60359276dcbb0bf5bf9a6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "99d052ea4a5d762872a803d774235aeeb706ea84f61c7123e1909e319c62fd16"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "eeb17abb8c74bf950c3d2e0c4ad7694ab2840cfe97aed97a5e599f1260ad8cb6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c571692248c1e510dc2889d2931d4e9aeab56db534ec7b59e68086405b6fb3a8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "dd24ca153fba3eaa21d79f580515b17c8e39776456f47d89b980f32f0eb76046"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "3ea9a3ece816d29331f196ac96a8624314df8ca268f6f8d9ba45c738aee34afe"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "85c691b96df70ef5d181878fa3011404eb0fe2e532de0b086ca52675452a27f9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "c3b368b156ba3c6d094e4d6208f8cbf0108f7f40d9b1bdc6f247430f5a07f863"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "8b5e8cbd4906c1685ea15489dee0c52840047ca256cb4d42f5b057683aa2c4cc"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "f361f2d44f300015800e4459d99e4c1b25ded2c24026d9355549056f89a60fce"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "49d8b1f9b894ef218ab4e673eaab7d160e7b8b7caa3ab6e46565ec829ef9c6a5"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "32703dc80a352aff867b7df95b723ad7d118c128981d3807c544446aebdecc38"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "380fb41c305e96c335ad948bc04d416e5fa3a0f7a05a63c785a68071d0d56e25"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "7d7d969a1d1847cd99d382a40e8bc433fbcbee296c7e155849d816a0c24556c2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "753efd176a7f7734a571018732b3d23d30150994c42d37592ae8e8fbd9114a8b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "042c5c997a5bda544e0e11d4d277bafce5ec13099296f043a3f5cc4451bb68c1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "d040be2f8cf3ffce3eeabfc7139eed2a092a539fc2ebd4c4e79a4d3872623c0b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "ddf76bef07fb1bbc46953eb77faad03786cf95c8a11329ed4e1165ea5c8c2ff7"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "5e5865957206c2af98b04887ca51638897a5cdad6c955ebdc5fd917e9259dec9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "792feb6465b484428fea3f99f80b5e1194a5e9e4384ef630b04b33251075fae0"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "fc5fd7f4cec1bd1ab146f7a10834f45f943ab56d376147e3fb2f06f1347f3494"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "61c4c7be5f156721d112130bb58095de9d32aa09f2c8eac9d5a2164de3804c19"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "bf2d8a91845ad3a67d2a5104f81e49480c9af981dd3872346a65ab3e911a9bb3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "10337814ef31734b7eb095e6dfbaf31e0dfd8619d9d9433c09f10a95343c6bca"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "4b77dbc4a4210036ed4c46e7145369cec3fcc0536b5533e539dd222a0b95dec2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "9475e5205ee49e8727c42bb6497a2622268a297ec3df0ae6d18f3dded3ce34e1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "7960cdf195cdab3dac8a74eed6330d193aa72a0f6adafd1d57768f091bb5681b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "0bfa0fe3cc6c039be7ba8ca05e66f6363ea3dd8351b3f9e82c637fecb06b7dd4"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "a1d4e3a961bc35a513c8f1daaec0b5a6e2727ba3e13462fb4913fc0272160ff1"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "35c456ccdfcf976299058b0cb2b94634293b622435de1ec21cf340a6c1fd089f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "ab70c7b9abdf50c515d015a69b686751e648b43b54453ae5b5005441b99ac7e9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "c431f7f89514efbb8a57d2fa696816cf9a06e152e0ae83710f9544dda6ccc78b"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "10f337c22bc1bbd6f1be2a3ed25edda850e764718edccd5ff92de1c21c52ebe6"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "dda1a77a75968dc0ac1408ce09218bd3013c8d7785ed6b9e18e2a6477aa50dc8"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "a32abcb51c410fa9ffed51fd6c11684635ed2e7034b478ae756bab96c42edeb3"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "235e3cbdd645413f0a44e20de17326d08b0461ddbebac4eeed25557f0bfb313f"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "586a1fb22ed3b0492ce1a3941610c2f9d14905059901501aa8dc3af76a7c91a9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "b7bc7860ab42e659bb107cc3cf74684bc11e09291805ba530f527fde7a67b637"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "14110320283eb77843febcc4a50d887c6b1d50fe4902a3ababbd72672514a8a9"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "b9eb24e40f1fd18a5b2209b774b8dd3a1e26c759f18dc4bc0f6b00757d961403"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "be069756419256ae8c22e951e4e8619816652b6d10e9117d7db9af0c1a130809"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "b464dff33fb7ed90fd46b96f1db516774910f789ea72f473dd9c494d69abe0ed"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "4e0f50c485746407369f76e8abc4d7dfcebec7c57a2f590fe9121be6bfa8a061"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "360eb110d1e319534eec974109efd839875704180e653914c84827be67c3e452"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "64733a8678e7018534d5bdb5f6ba4d3a44b9be6c6d868b0da32a35554caed207"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "94f7f74dca2fdc538aab7918148a212c86bbafc507b5b5a2f1826faa05354e63"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "34bbd945121707aae4f1e21231d012a033a69bb94f04b7204c7551ba956980b2"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "4819b65fddec9849734bef09a2ddfb254c49b2c354827dc38b7793b3e2763d81"}, -{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "ed524ed18d745d288d5b6e4d23eb3284dce3e4e0893b48083494461230289fbd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "de97a30550ed544678c153cf1f2de0c6213cb562e78276d8e093dff829e3f632"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "8ee11ab97bd0e142b117510fbe257fdb3d55d6cb4fc0632660765c4fede69838"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "28b91a712efccd151f9e358700a257c7f1de706954f13bb8ed31e264b6ba4ad5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "200d25ec484ffb68d3cdbd011a4a0371e20781586fcf0abc1d6bb0a9082caab9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "6eaf12b907eeb1e88a0b9061f29ceb9389fb2f66a4c98338c776190741232684"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "51d361631edc6ad126d6a30af1d566f7d71ae3de9f1c64bdac1e8a616bebff70"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "aa93c4cc25c4136c60c977dda17f004f03df02acf0ebd158240de493fd2f668b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "a97dc9d155c1e83ea29c8373b3a020739b4fbeb50c8ed464130e6bbfe8486e27"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "106a1ec1544e24b9d36311ad560a8ac53651992471a057fc565bca024f042c89"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "8ab3a523fb72e6315777273bdc2e977d59f00c9dbd0022f2e7fc6c1927a50f65"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "83617db226a2af244b0b358bb4c26bbdcd8cae34acc4a7984a68e49f8a14f29b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "83f7043c65dc66705f21e5bb0c2aa74110db3106ed51e8e2c57d0d7208a1891b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "d3e3c42cfb38b16f59e4800d9f1e1c1e38f1a679cab585c31664b84e14743a2c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "d67557d1b64011f534ef7ef16360d767fdb1397f02d5b1902df19a00cf9c1d41"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "0343a6ea6177b10debedd25e2e0c1b5fa2fd79d207a41ee0964c7d4c89c5c01d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "12ebd410e51a23e7a56db0abcd39adf78031f55799284a9937b544f39945c0fe"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "f0fb8d4a13ff6e794a5b21b370131dffd415bf57d4e9adf39dd922d3df03a058"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "8033d56827324362acc16bc903ba56a8891bee8d30d3a678787f5e06bad5b88e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "972c7528983fe076b0eb078b899d7c1007a5938b11b7f3e351140c52da806cf3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "1e0f894a0a43b0bc84b99288626cfd40b6269f82521feb33b2d5d612668f9b0c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "fff09df963ff8f6985b8080f581405b450bc5412a3334d076f3e1d32fdac5bfc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "c7b544da38224533a756923e55984e15e0cda194f446f2f30c9dd370742ce56c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "b8ef322c436976ca4ebd24bd4a3af762a7b971858d525a37904a95ddde6c376d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c6947dd67f6b70b1119b62e691ba4f9e201499590c8d938f43ffa8437da7fbe5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "187adc244c66d700dc22a8d37a752dbaf9ea4c6791e154b238dbc3f257600200"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "99de7d0e804d68b0a1a0337b1b4fa6becaa7417dfe6cf18f52cf885805528413"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "dbad7277dc09455aa16dec839144b2d5e03edad81cc87efb4289a96cffd79729"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "08ce80d3f701d1ad8f2d6c105670faba77c5a63bedec515190da6e0562a126bb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "9440c9bf23ce40c808ec2b95b4e8614bdce1ff86438fd83763d91b697902a138"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "bb48e5069f9ab2850735d26f7d526940045f1227c7d8a1a691d2c8cd64da20e9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "1aae04a3cb3bae60a9bb17f153ffb44d6951e7b0103baaed89443b4272674cd5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "65bcbfff0f814d2eb98a559f2c65f43a22a9cef19f1729c407098d7c92635420"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "bc21e3df8f0628c1b1eac40daa59c8cf4a1fda8fecd155b2226286d9b08f856d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "df9088c425c9cec23a7de49bec1a6211a4962904100558ea9156fa47101e3f08"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "b6d4bd0a8efc3e2ef0c61e6b996fac66c211fc3e74c7a6a31a9c19ce9ae7add6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "6d85d5e9e9a6078586f16818f6849fe2fbff9e6d714f013af1d653f18d1d1b47"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "124e3fc35f8072eebb48eb35910f684a50ac21c11c02c611d597f2c3645f4152"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "7d9d3a3ad6434fa294cd22b023037385dd03e28aaecc07ef3f284ec42c18b0c9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "9ba61777fb1903ef0b7fcef1e8b277cc297edfd3efa5e19b0eb4ec949a3633de"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "82ba0fe4b878840525c6e4cf1c488c17495d00194374fb43815f05f3c698c1fc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "0c3f32136d76a44cc352e0e866c2d3b62739964d9a373f5873ed37b5d16813fd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "57b8ff944bfbe6fc248078f510873b06004fd05be59fb2e95277018e700badf0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "68525820c24812d7f400f995c5ef999233d2361c6209c0b826ccfb91c20fd7d2"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "7a185f314d56fab7f971e057f700b8a9b37ba1aa083add87717f51eabee0607f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "11edfdc9c7638ef946507ee57098a95a672e071b438b3a7ac4411760a35a0ddf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "ad5b0eec2e6a30001429cf5e0a3957a05cc24b76bc18f0d9defd0260ab690dce"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "23135de92d2a4cf727929bdbc637cee7cf3d8ee5974e5f631dfe67d26746027a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "78f3bde31acccb1648789392b87bb529a6f6b72bb6c405d4f9006ed0818d52c1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "fae882a540fa3741e25ae74184bd60387ae26f4fd9ddd53b41f2b47764c588c4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "fe94bc36dd81c243859e8cebca36a35b391999136bacae5aa6c6d85177a177eb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "2dbe5903a0e426516ed16cb5fcee7710dd472bcbf052cde9b5b0dcb7a7b07295"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "81f89d26af78cc699271806edae0a1ccc058547b53ce9b2ec061467dfc74e913"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "c44987bf0756cdeb309a8b743961e49bb62f62043be86520a638245279ae71d5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "44f178e5bd45c95bf33f523bb59ec662b87a7356e028fff97430d0bfa08a967e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "9e42755928cee2d8f4fa1e71a0e44f606afb4f5094c567d1cb872ec66c22f677"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "98e4a63e0fa3bd3c8365a7b8690409945bf33bcec47cfe10c4c7e984ab91f890"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "92089aea57f67fe1eef123cec531e7bfebebd7dd25a91cb5f7d7d880c17d324f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "6d152ec62859d25248d86d2cc337d99324fa5c6fe71e1df5e12dcf842b87e60a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "44ebd9481ddfa6254ca3cc3835872a74f7ab8189fd4db8dc7f58e6c9c0229fe4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "bda31c642d38645d707d2cefc50a12d9fded8c2b48a2a35ba980766b61dec2d0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "82f35404b33caefc91e6502386a452a096a1de7bd4a30bdfcb9c5b23c89024ef"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "65e164068e533570bd27e4203420b9223051fd556860d9fc92fbef40dcfc2d34"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "b70271fd1368b5878833f0faf70f1c4249c6ef1a05757c9950e0e41e696164c3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "5a363e6fa435f3590466b48aa5b87332300dc8a2d3142d5179abb8da0bc87197"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "86116f4cacb62b58c3da58da50a385cb6bf48c3abd1b23292446274fcc55dc3d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e30154b1ff37cd14ae058c9a2b989187d72156b0174639ed015d9367006688e8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ca16cf7b1ee5e323332a6ab9f96eae5367777153b9e1200304eb9423428c65c7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1c6e6cad1b61a30c1824d71d122c22d1dc268d34d7ae1e8ae3ff13d872540b76"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "8913911f3814cf437708128b144854cdde960c7a0f79eebe767828f2f29b3b02"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "713100fbcc7090efc8510190886548a0b38b6755dc26d1bfef9a5d599e243940"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "a09a6b2604c8986b0132342be2dc477cbca7746c8f815b1e0728736dd5891c20"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "325d220c5f43754c32a0ff04343a3262a861849cf5395d50d8874fbd3058a69d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "8c92b8cacc25fa8de84a169126e5220f6f141a30e5d3abfd2f5ca966d5f90cc4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "5166143ab367ea55c0e2562861e91350275d5f44d2736e8e40cad3720e328122"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "48ddd943ec0c0aa6c5dcfbc13f8c02873803afc1c976de12ff9f1c5786cdeb24"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "5ea7b07495d712d9e98025186ec76007c282b605d2ff0e0f7148138daae7a7a5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "431e83734222edf95dd204e9b4e293cc768dbb6d3c3ee66e12e3aa0714c58d84"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "44b949f6f82ac58950b285d466102533c3c265fdd9a0ead4ddf8f0c1efa08e22"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "13b7d985fd9c8863f115eb3755ffb0c0983e5d0bf49ed1a7142c8c50f8be375e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "58433c1185db83254e07f625dc1694639b9b1673b6422143358bc6ddca30312a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "76746bc6ce5943309597225511d05ddf76916ee7ee9ad51f811901830f5a67c5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "39d89bc072ff5cf77d08f9be1936a3bd44aeffea2a7f06c465d7819a2ef8ee57"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "d6a4d0c3baa61697eda1ce0b3c44b12d4aa3bc801d34cf5d49b241074c432801"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "dc1e8c469fea5292284c313b7f7be540d3d1ed29eb58525406b895782e11bccc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "e6580bd3d368c3bd75dc3efca5f6714e2c84827cbc54696b227a1a7b0b475654"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "9c28ea13846a511313b1955c52829bc6a40b3018a98fc0bfb4d0e3527543260b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "188063e480f8d60858972ab0fb430cf5938519747ee3f2ced25a2361e037294e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "cc4d0c474f15ad50eac1e625359c05567915cd049f00a23cf575c7c274bb0750"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "645428f11346f468b66ab9596aa243d8a6ef0b7ee2f7619275ecbc47195b0c4e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "de618bb86f5d59199afe8e3ed1b6a6b3e0a756cff0af3a67a3fdf38938678417"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "136a567711c32c6caf6721477bc057c9c0c08db78db56254bb97d5580444f5ac"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "87ec8fa741ef0cd3d4894ca68f1dc8a47d5374d707382eea3923aa58dfa0798d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "c7ee41614456abe5f0e315242cd4c77889c32c33f3caeb75af830694c7a99a43"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "2580c3c0a13f239740c981165f5729573fcc601245aa8dc1e894d101ddac25ce"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "2eee87888e55d4ccf91debaf306148bed6c1964f52a095b9c88c391a54a87a3c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "c188655326a136de623073205d541d1bc955f6d5649dad805a5db0e870abbdf8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "b47bf879a8bf8d3f4c5c610ab754e4f658e6cc3710a83afa93daf6ff938c34b4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "d2046cc6563f5aeddf5dbc09263dbc1238a209d481967ba4f6307833860f8122"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "62484ac9e120fb16150231dbfdee3eb3406aadb331f3842e914a54fbc3107a69"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "0a9704dd1dfcd9e7aad5e3171178dfc48cfab10e56503e812e854b135461892c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "24cd3c356900958f23683c360de7d90d948f4548b234c7a6ee614ff40c05ca55"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "c4bfafc5136b983f6e6ae935e1b344f262be170ee420a6c7f62d3a3588f487c3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "28c962e05c744b0d7352352db2c96d9bdf8e66e777f08e1869abd2d3939571d5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "b10bfb190eb9a040dbbb3d96effa42f60fe687910e45cc1f7dc9c1e0f1c6a287"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "4b7799b601961cda479e63e0aefca957ea4e13b15d9c911c3e5a562daf8a5298"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "f474b889b58f50499bf8f569d0a4a32bf57cb4d9b3afea25f262d7952a3c81d1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "887912f4483fc9aa942ca5ecaf2a179c2d1240f09e6f8c6f85f7be7e3ea77be1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "daa5879b3a3361a4b44c9687b32e1d2e18f6e3631bea1ea305ea396dbea2ffb3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "76b2008da26790eeba90ef4d1324a18dd5afdfc803027d4cbc31480e7e19577c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "b401ac9aefb97da6ef092d3a10b17a6d0f001bd7e2240f526631dbfb751322df"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "423835eddcc45dff7c9d93adcd63b134c6bd6aa3c8983f6829243b6c8c11afc7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "7c8be0e46582a9c6069adfd0d02e42b03fbabdc6a0dcf08c1abcd15c5a2f3775"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a94e386603600613b25785673952863c0dff090dd0cec171df74be902b4f6d12"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "5d93208c0dab5ca044c05d833ea3969ac5a9c95226c067ba42eb49b82879654a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "23a305565b991aad961adebf34bfd7a8d6e4c7d9e63048c48e117e8e244caae8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "cc4a54b98467f30e2144ef8c37730d4ef84c348ad0029be8e6ef3df8f7528bbf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "041c76992e59543c899e21e43d79300227bc4d15d5265346cad3630b6c8ba11a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "0a780ba340ff99da80f49013f3472a3bf194bd0e789600bccda4e48cd1623a45"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "6dcac6f51379ff113b1453ebe24a1ac020682107c69e8af990946b3738de3c8c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "b5c0bb5e31c2bf32a6f33f66e0f8246a9cce9c58ad9a1bf6b41ed42e2e0ef647"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "ca6fc008360d4bdc6c9c9d6fd9a35062b96f3c6e935da3c9f91321dd9c3ab1a1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "0c11b2778e2a7da1f01f193b3e5e86e1565dc241241b20dce04f0fb870f0565b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6a7682a82181fa987398413162c51fcd63f934cb574ca4c70dddd64b29e329cb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a0129d4cb2b0d1188b1c60559adc0201c367f596cb93ec67d75bdf2cfd212e5f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "8fd3707bd0be5e422851c4ae18f478ebb9c28d29a754adad037ee26a7a36c857"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f74b15cebcb49a47ce50a5ccfcc97cbc68cfa089674fa4189174195cdb83e993"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d85b3260cfbc1f0cf9576af1e5b365a78ca2c398a2832d0e81cc86ffd14c36dd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "5c5df4f8bc34e8893345251338530f34b88bb279bd86816385869e3e90bdf8f5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "4ab6cfe71f1ef03bf2bae85236da9b89b24e437260bea68a5e6de081c0d99c6f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "fb943aec0fbf94acbd74e827c79f5f9765f377645fbfb1ccfbf39961769591e6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "fd15ddd11d883314511044853051b0fdb5acce31916ec9ee04e34e10e767e141"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c1cae8c75bae90080f8f415aecdca7d755c3890bb95bf974bd6b4082942b8108"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "6068afd8d5be5e5e64e08c06c104493315eb4f4e7839a84576a223526c921a3c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "9af23769ad0a17cf4273d6e3e813656bdef09dc0bdedb8ac05ee934c1de251b8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "ac4515031f8abacc59963af684bf78df4cf708dc01fe19c3c7e10e5c1b3dd2cc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "0fda0ac1a26ed7d55b358f0bfc589365b7c3c5eb3cf9569c5fe15857a713a34e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "0ab53a92de1d989f1f1888ab2b0b7ecbb1cf49cd19da46b1d1213737f329eb5b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "9acf094fabdb4cfca889f6adc1bff3719fe4d55ba933d0ec21415f568514b6c1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "c84e8bd1f8583deec476cf8fbe8b3e41a5cc7a748be6d6ae852d98011523bb47"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "09ddc054cf4f7494b574cfeebc0046498ee39178c33c6ecadb669379eec155d7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "6800dc8a27011bc3e96203478da6e0e3734f89e25f0828cb039b13078fac8deb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "75c444e3fa2ee3ad37797c14dd786a789021a372719c2bca80172537212198ad"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "a020389aa9d979b65f1608f75f8d653c2b59a063e4072509f571d395230a473d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "5269d42cbc4a4679170a63ee84da270478e1222f7057b3c9fb97554edf69f1b8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "4ca9a0b5eef1d3d85f7995885490e9e964084234feca989d2cf0f502977089f6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "2772387cf4d2c810a47d46e15ca8a5e256756938081219b02258696855d9b986"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "1ecab6a6ce34816861635d59099f6af51ee81831a6f4a7f8c8bb607c48d5f1ab"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "4caf2f5f7df1d64e84001745a5f9865b870c9b0f9a7e0fc8ba1099992f24e6d6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "5ee49bbc8bc0026ecc8577a2a7df0ae03208fc6eca9b1548c41e263a8977b9f1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "2f1dd5a3e01478721d4f7029049215835795c228eea4882fe6bd3cd02f2cd6a5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "5154d4ca9b695f5b11d59f472b91f70010d13fee40a004f98c46220bb1c00d75"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "22210febda10ca013d821188da6e9f039e402494ca2ff877c7e8737db07e5a90"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e873c70116434011d3f20331287196dbe93a6601c2a9db657e3eb5f85df71f1a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "9d754c4fed53797cc2a62aa2d1cf77944d3966c835d2217acbfcce2e9d8b63cc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "4777e70efdc847f0c7fa3aec1d64bef899490df25c925b97f4791b20a4e0d9d2"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "435d6f6341140886d4a60926b6e8d616daa6540197519acaebf87007c327e46e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "03c6e5904809cdb8213b85e5c709b356e2df529f99585d46161bc775aa801437"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "632c5fe47ea25455f99e51ff7064d8ed619411c8215f421516e380cde9b59e0d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "8489ac6699cb762f6f2e88c0616c38b317e5339d39f830fd5c4d9227d99cede4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "06feadc02aebb6f4647d36d186cb8ffaa46b2a5e5deb57cd077831f0db83d35c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "8f0fa8fed9d9f60fdffc31735be81c79b4baf9cb1d03b4da554cdf31b4a7c7e5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "d628f5dee5e13f45505cb626adb898ea653abacb3b76b7f44124486da69217aa"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "6d2ef294c2257cfcc7ffdceab45f287afa4dc8f8e670434732918959120fe3aa"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "3996cb0815e8633cb2ec600cbf0524eb1df56ce705e9255f3e78771d88c19a54"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4c0604300035737b7a4a3377e71acb5edb20b988cf035297fac8c5ed27ecaf36"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "77a23a8e1f714b5c110f4b91ad300b3d9a6326f008b058ed36cd88a2cabe4d28"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "5474f1a454f39705e551902cd896e0ce1a390de70ec4e3cb119d253cf98b8a4c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "743c036d08636fe146bc05b7404889892ebfeeb6f00b5ae63de9cc9225fb1301"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ac0306275c95100f6e353985f3440d8e816e6dd1d3da3dffb8e6d9203d04d031"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "a1f40c6b9298c21ebf8ceedd3ece5e067c038422b27912ee08e55a1dc6bf8e27"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "fe8e31c04eebfa8130856ac13980fea4b5fa93f832f9a2f3e45cc0e2f32e73df"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "6fdf9c699da8a1f0d72153ab0bb2787d6857fecb7d780c114000bb439dc1a565"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "92e44909945aa7d7300a66eff5398ad0ad37670dbd916bcd6ea2bae41b0eec3d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "083801ec83879f159bf2fb4be9a62ba6de16c0aded64be12bd59b88649465437"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "03dc2088054eeb4a30a20b07b853f7508dce598f28e57979226388c1f4bf2173"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "65ceae8e296301c554193fe27cfdd15f68b51b559de6212ea1a8da58ab6b5906"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "ff33f9f9d281da1296c350562930b643c21bef6a9ac7f8ca3f0e91f2eed23c47"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e4fc159f8fd8f4dd7118fe161c3507a8483c4a41569b358d492996b1a15346f5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "afbaec8c5084cb4be2f557ca1b52f0cdf7c25737ac3c1538bdc636187555235e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0018ae9459cd28827a023ecb3bb95f1fa12b03e2535f22d3bb64509f3f86a256"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "52c1884c706d3f02fcbfa6047bf646bbfb197d6c7888be4b9062d52eb473c16c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "b1290a8ff516851fc9fa5c0f3a530606681629f851272e59d0b48f585e894f70"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "c37b70f4364146ebaae650fbc4fb9108846ef3edf3103b9e6d558f5f1c789658"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "b26f4a0ab11ee541018ded71c0591ab29568c357f83a6c3431d7072982ca271a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "c49de668c47640763b16fec4226cf5d94166636037ef225c65eb05366d5c1a29"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "8e7fb9aa49d755a28d4a56d57d88034814a447c853d8fbab6c3b46cf44f7e78c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "0555d5b97907a609dd14107c7f4dc0d30833622bd811567425d085e0a8a52a2b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "4e1763f774ac71fc4761ed52cda0c2106d9107684f314da99ba703a67edf0abe"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "b3b60a3a3894f25342ae8de27868910a9be4482a6add91af8725ab1ade1a0b40"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "488922e245a2828ed1d187b25f39ca028cf73d8b0280ccf9efe7d18d7b06c6fd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "2fe70bf208689b596e5aa6cca16e02fde76fa60aac8f27907eda9bce1dabf318"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "a6f02a65808aaa7970afd547a9ef9e1b73d778044d4770f12febd6fd2f8ab286"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "df37658a84271934e4f885b3c8b393b2c710178da959263cbf82e32f61d4eec3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "9a98ce3b68b71776844b3b00711cef5912bc1258cc74858dcfefa0479837ce91"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "c2a7a61c1e079619a390cbba3a8d271224afc66fab3787a41b333d62e4a63851"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "a2e15970266f9e6d7f1b60711a331fe2c78fd693a43ab91a9fec313684b02bb9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "ec37bfd04448e17e756e04e882406077c294357055a3441812a1d2ccbc6de4d9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "5cc7207f98e8fb8f80a95a9e06b1ca5d9d1571c21f8d492638f31dcf0e2ebad7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "7aa888d1e35eb42d3d48ab0c642e3281d5bec63fe2fd9952e8e8199d04933df8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "da3c4da47034f6f6346affb695d8f2a809876fd14f150e2f543d07bf715a69b6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "7aa42402056e5af304542da91bdad5fa597fe9dd17e444ef24c29048c88e6ce8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "6f1e67f443208df8216df9bb35084ea6aa03cc243a69e988e6d6d2bbaf555dfc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "0adaf23be610908e04606bbb6335b8023ecf9c595086ccbbd6e704ddaffa5a27"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "065cf5677f196bf2f965fce3ceb2f67b1799d5d1d6aa1a876df6bf7bfc019a3b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1878d8472eabba277f88aae6172b2a1c2ad79a1f5bce6c41c35cbcba0c30a75f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "f1347fdc47b41322942aa45b99aafaff9f89dc838c455fd8eca1d3dd25d0adb4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "13a17fd8af59e65932c4cc5baa61d0c077ba63d642be4ded3410d1237c60bb1c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "6d8dfcffc15c7351ed6a7d76c187c72b21d87c20d852fb4c57ddf117dd460fde"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "037715b26f3afb63e44e9e43902bfece1293e923969b43aee0341f62f41f733b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "37e12bd20a2707044d43fa72e65b45d6da1530d503d1c05617c34810112f77cf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "0eb1836904cb7e8b441ab1c82dd9e796e5ccc8d49fb762e47123127069acd7c6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "efe927fce9d09478b7dfcc829c409f4feafa5f9f056cd8090df5d6c02b6a0c21"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "e9a5502c0b837e8acb4d0449918e8f66d7eaf95d1c1a49d9a9ec26b9f4185c3f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "fd0c3460f8b1d80ae3bb78a8a4b85429ca38e292674a09a7a057edf7bd4b4bba"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "355c25047e534c7beb4a14a18c0e49bddf9f441429472351b5db500b69addaec"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "57e03c453deb973eeff4132e05c27c255a34ba294b79450351553bf95519722e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "a2652f7a16e0463cb02d270a46b6a1810eba4ca21aab68f0fee34deddad5320f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "63ed21a633c5e13472d077bc98751d08d652c091fda1a7efee1ee9e7c2d4f174"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "32768e45d8bda05742e15491191c1477fc21bf7a02573b6a651d14edca0bf07f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "d4309e3700e33b40d9f9f08a46a3b0e5a5916143ba20cd493c45eebe00d46ee9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "8f96b8d8369f400956a827df9a87b3bec8b107190cf463a6852cd8574655153d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "d19fa9e59f35970de1d0a98abb8b75132c9f7b772ec51790f396b0afddc112cb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "d32f7a0fd24fb796c518859ff529a3892887590b20169c625528cd09b9131554"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "b1d9800f52e4d186a8605542e4059fb0a80799311c6d9e63f5b207453b48b181"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b511f2f38c65655d94f7c07e6c5a599705876e03f2517ddb8b04b2c1b8917adc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7d77f0b2f7331167fd02f941f7a450e3b6c56ed7c9239ed38436111418bb56a7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "59393918fcd84912c7376ebfc3dc13b9cd357b3ccb9ef7b5164003091b210341"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "6ed3888c078526ba47e9efd5b97e2a471cbd0261ac838e8a55652da6b27a3d12"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "b005c22e4648c04be61fb19b55af6e245f74c488dcc914acfdfb56e9e332b7fa"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "97cfdda914fe779bf36ef4b5eb1185d26d3ffe178afece8f04dbd9f7f692fae4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "1720db83688536b79c4a59710b03dbadd9486e70b3867967e6b8344f11fc9c5a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "eebd4e25c59e39efedef778fdbad788b27b4b37a959e8387509e331d59c5c410"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "4ae9627502bbfe034fa5efa7be88b54a914004262fd5a0dbc3d7fc4ec414de6d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7009a66409272323430b1d33cf05d6b3559cc85535a68cce36f89b90a484024f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8ad3c3258d26a0c36028a45dd808b02266820d2f4d18c9b18a6ec2b438c582f6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2262f4bcc451fbc460b5e54e1a584f73c835cf6623e419ee0dbdc025200557ef"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "58958234909d20463501cc18e8db1c80861ea05ece5e82124f06d98f400bb32b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d8f00bb2d8160ae7719a9a5c0ed74ea5551dd13f7f44c6e3cdbf6430677622a9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "b6bf966009acba0a862f543a01f182e0277cbe9868c0df610599d7a0ad68a6fd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1f50d2c1a841452376cf335c94b8a8b8c90a61fb17d9ca0683292a99b38aca8a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "0b75628150e94199aa267a9ba05ecedd065bea37089dcc7140a40d4bcfe9b24a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "ce3963f0f25bed3978c72311fb9a444e869929952ad353ccd37251288b920838"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "b0695056ccf316dba159a8ef95ab21dd545dc538c6d20f5e32510c09df8fcf2f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ca7cbaa0435dde93edf85875e60b217c58f91791d366c438b4d3c7d083f07ab7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "068b64d46281ce5749592ac60c19220c021677017967efa0420da9525c0c0182"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "ce4e2909655e4617d148b4bcb71eeb5443c156cf2bd1b76d1da793e94123d2e4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "e3de19269d2e098f31bf2d93faae57aedc8640e4105896414ea5162d1ec2e5fc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "0d0782341065e77007c6a006345cc91c53fd93cdd1bd793545906a9786bd412d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "998f4b4994bb05c64eb22a84af22a5d3640fe623c91832ad1bb131a8245a6830"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "4e6dbce30538dea73edf22a2a06a82c5b91d763897534987e32bd5feb70b0221"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "608eafbc9f7e929c9b0d1dfbb636772c11a40080e9ca7ec9df85fc09bde7e6a3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e94f4ea0da5a1bcc0ef3b7dbc36892962b11153310709f57fbca08f88cf7bc75"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "7015761d9ff72da016fd2ca2c50e38f7b56320e38b4510d82525840edad6a465"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "eebbddf78ff39620c9316d104d9edcbdf4230966db3bf2612835348182efaa22"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "b37d7cace30f9330915a12640b3fd798485fe31e690fe63ffa05a8d848598d07"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "f4a94f10e168c9b561f547107e746e77361b28cd6edb8be0044a42b9ef203d7c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "72cf2761aa4cce49639ecd778843b3c5906ecd9f0fed25bbcc7c57ce29495ea8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "80e5f3be680e6390566f2642ff3192736c36a6a2d03a2a0c2213599cc3863e49"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "98d985790ed2111ad1ea8eee9c27572a39097d1dda5bc0dfa723520828d369bf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "2f50bb339d5f8281257420d78b1bc184aa3cca9cd23f4579467d5466e47242e4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "872efe49e310eabbebbc6fc93f6037c783da90665f5f5e9e0d6ac8fd59c3e2b6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "9d0d5d9d36943cdc443f3f8d704d1162677b87bbe9e29d8ae430bd3302c7ec1c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "3d1fae014c750e471f499b75764b75ca15915445aee33b260b59e0418ee3a821"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "629ae9127fe47f082fa931f776945c0fa408d27a9bd451e5ff5848f2796e902e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "1921f37d3d626c3ebd2f6022f3429741df3f898aff43659709a14152b4fc1c66"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "3e49927d6f9f2d5eaaa76216ee672bbbd10b7a7d735475f269748b16ea5d014f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "53a705657fb0df38c75b52d3089ef8914fae2d4e7ff95edb732d915e81369f67"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "93a9d893caae8cba5f93bd9aec6e90489fde10011c9a5677c8af85f96f8a69cf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "f91affc6e2706923131995155cc3da6064699aa31fee9646775b339e5cbc8b80"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "fe6db78ccd0ce277496d71e994b5aea2fbe634b0b9fb8bc7ac41376c74e9ce6e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "e88fef790f7bf6bb9df382b9de6e6c7cbf7507e6afc2d4f8aa997528c34c7499"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "078872e2fb47051d341f5187d441f73eb743042085a489608bd0cdf4ba3a88bd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "795d1ee8744984a3abbcb4fd25c0ffe72f600d2f3b02328d7b8c9367ca8078d2"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "df1296dc7c81a4776b81ad97dff6472dd00f69f80263cb0b79a1a7abc7da27cd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "b4cb08e5d74943428b6d9d1e6c20a381b3cbbbe22c23506eb7a3737d60bb21b6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "a8272cd306a1bb3601ed2a523635ee49ea940050d374497ee65e435385d84697"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "71ad8fa411e8bd4c0047f2383b4247d6c9321952eaecf45abe74eb901c5cdeb4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "c097c2b6d40f75ecbba804ab655d40a7047f8161c84b1e4e30d875c9abf9aff8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d8e991d1307243f215f41d8c11e447dee2058e63cc92155bc94eddf76df261df"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "df07ea1b79eab900f9923d6c88e2dbad7325a3941fa28d6add9e9a050a405fdf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "00b41444bf47b04b44dd409f72a6c0f852d4150b3b69a07621064c275c0ef220"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "ebc465e87e4049cb4b57a2667eac3cb01407dc37cb96d80ea470201fac70cf92"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "1732b21dc5346b6e8bc127852433aa26f6a40f8fc39ea919f3778ff56c6415bd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "5577c0f672b08f6a3b9e4a84d3dd7fc81e03f577501f57ba14ac1d0b21a3d5fb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "6217e333a125e73b69b3d8ccb40c56ee732a756fa9c127ace8af739f49e256a2"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "d135b4368362062fd79cfcbaf2e54efc6d01d332341e4e0a7158294138a4d3e1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "c1d22271903fc64c973ac05a13c55580c4a6ec47dc33e12be739dddcbf1d5c6e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "f9779ffae029f90522917e2160489f30ca2f9b4d137e007dcd60160b71d41fa6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "53355ea839d3ff9aa0d8477a374a74e6f38919bb7e1bf2cb1275485c71003dc5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "a12180c7ff77bbc9ab3829fe41566bc360b58c55ba8c0d47fcfc81843b3df299"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "8169d2d929097d7a89d86b0861079a671a083e35f69023bafb2370ec148fd48f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "066ccd37291dbe7436299a7b989eb4a882f3f6bbf95da3d3d428e1378320eaf7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "bf5304cb7c208683fc5290fba4f8344f879c6af9f8e0318db4aa42fc013102a5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "f46a7e18133e982d16734b8af46d4e206abb3c40f794339d11f43f1bfb159117"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "a47649a5d426a7bf6c3bb1f3945ba79daf3b9a8641309ea98e33a0ae7d4d114d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "4b3b07bb383db9c578966f40f237b545f9c9d6e222903b7c697bc6a33f54380c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "72b85e2f9bf12febef1151532e42e8a4fb528c0ffbd8538d66656e448b3bd099"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f71f2d746f592864ffb15e8c92f2763eb9f831518341452e37591697ed0a2a5c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "28d77b333cfaaa44bc05d920accc5240b914b2a8bbaa829bf0151a2000072e97"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "e6df9bf3073a30e79b1fa0d74f28fd35f9bb9d940daa92bd3fc1100799e1c3e7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "9616411931cdeb9f5550317d883ffe25a363459a75f3aaee54e08c804c39fff4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "8ec54b3c7b6f0c200166832cc74d1620e62dd0aca3968ac8ccd0d9f292a40d62"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "5f5eb725c666d46d7b8027273ca43b3fcf58e62d77d59815837f99179fb638cb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "7f19f8bf5f5e0d559b1d995c14bfb6caf3c8fb72889dc35389b5d1245a19b9fd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "b1855db72c804764bdfe45df198df3a8c49f2c6bc0bbb2e3a913593db68ee227"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "5a60d4c7b018a6626e893d6040ab4562777e28702375b00ee9e0881ce14bef37"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "877d479b43c6ca5e0bd3b668e16517d5394a50ae3d4e565679071023310cb079"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "3d71d8881316ceeb77b9aab930888a399d3633dbc7b9338387511521f2a41fe5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "647fe71c5de2a23369fb8ff37c8b0009c6f71948a399a02bf2a37f5168147f01"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "9d91e28e12c244d2360442a73d850dbf415d2135b03db4da61067c193089eafd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "9601521a54310705fc54f8d83af757ebbb1228afca4ff654d9c25fbb7b29d716"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "a5744e6093bf9c95ad36e5f328bcc386415248d98cec9e6f34e83ca62e63e85c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "9ab231cfc7afea5e5008857c6c5929525bd3d1f26ac011d75d3e56982ed98905"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "4fa184faaf39ad7021727168b054b5573549c1b565f7172e68a43c1cca650913"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "8e22fa945cb6ea6a5ab89241219f952d503aabf3cc25fa0acbd36271ea35c31b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "c66e11e45c49bdcbe7c25897ccc9db3fc07160aa95a2a26ed3b82a2d5b81ca31"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "d8e58b0e4d6b38e0d33ec342cb72355a2afc811c3e05f4ab7b770a62a44e7cc8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "20596eded0b6589ed4c1018a87548855f7a6741e84a478dd29b8e0b75c781651"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "e6b5a1d5d89ee614c74514054b9ec4407cfb904af662753f209ecf41ff6dae46"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "4188bfaec8db4c2160fba126b04f8a7072ae8e46a75fcb9728d9618dd5206f84"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "f5294183926583f73c83b9ac0b95852399d3161942c7f2353cddaf70901d2b7c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "7cd78bf331c7efbb96868e615ff61c6f1544720eafddd3ec970ec3ee468c7afe"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "155fce0a298de52008dac09ea37061eb87f31f8cfa3a555aa6a0c638cc9430fc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "10e8ca38aa40769e2f98dd1816788afbeed4d2cf35d5e1684ee092fc2dab3190"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "bcd5612df2ea24270699ea0573ac7516f618103e969808df34070b29044debb0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "a9550fd4d27c378dfcb3c6403032f18678058779372b76d003640c4e7081190a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "7deab474fbba5613c838c7aabb8e55946745e9c7db29d83921f438006f2874ad"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "7162c357c2377e0e35986566097941077cab17db09108bcdb7e1df8064426f5b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "09d26b1631b0ba14247102aa74bf9a01ef9e9b9150836db94830033f7309fb74"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "ab6f4059620c6fae4e9edc574346179c993d6fc6bc6ef580f8742a083512b8e2"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "c3f5756b915daafaa732c7ac75cb6f3404bafe9605998bf54425b5e0748dc1d0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "93f3bdd698f698568aa815e215fa5bdb954059f9ac330a3211fbe3e84f70cdac"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "60e06f7d7fa589b163890fdf4edec5a90696903f17ef154fd1b8655bb799d2e3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "b323f5b88ce0a063b249540b17ded56a34f636aa1a8071626cdda77d4fe94fa8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "442f27ccc53ce871eda4a514290e612acb3c23c56f44476847d08e7e62be0092"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "95a96bcca7173e0ed5b93d108b7616ca531275ebe7e8b5afea5213c7411b524b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "7518fd4f3671b4dfc9ed97cac7cf830c803f8eb9ef836c6ba2925a422e72605c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "da7a5d21ea60fd7913860c219123c1e69bf5279a84e70c4301911c42976ea9ad"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "67fa40902e4bf73d30cac741963183f8ed1851e7c71b72485c71f3cb64e885ca"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "3149ef39d5ad22df2d3bd9ef02a95119fc10265f4e088870878fad5afe4fc7fa"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "9862304d664c16f628cba522db2f0182e475188b0cbe6b7ee7c764d75c979a44"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "ef13c5749649e51c1c1ba3b43ab035ab16c3f45f2e207f142217ddbd4f6a5ace"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "c3e8c297ab80ad2563095af418bea9be84d364f79758168f5a166bc619a101e0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "9052fd026665a7a0cb34220d34c944f064d66a148de752b8707e798c4a5bb2d9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 197056, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "18725edef3fdd4fbccceb33bcb59a78b5b5cc10f6c66bd1e8e509b715552d75f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 196880, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "3a698a6b41a9d04fbbb561c574bf9dc4b757166408c8b1f69a7cde6fc5e5cb38"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197072, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "d92d1b607706a6bbcedf0dc6d12c2d35207dc9076f039abdd1477138cec54ede"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196896, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "25ebbf00dc30ff5879b375e8cddb8f52547ca9f606f16d0c8488827901eee1ea"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 197056, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "3e306ebd3a481a21faf3e8d491168980b6897d5f30cd4888e32eeb5e6e34e40c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 196880, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f804aaa14b5ef93a0ce02ef483ddc0b95e166942d69d0c046b678e123dc0cdb1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197072, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "7e711e7213a53e41615336021f52d76e980b3015fc4094b3bdb67ba310b73534"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196896, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "669a51e1a4a2517ad3a8b13c0826c0a263203b23b86b39e8e73cca0068fb91d5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "dedc1892bf4e6ce76fbbd5d688112ebe888521e4c785b42de5cf54bc7e8a818e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195176, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "3eec0077cb01d0e371caf0fe7b30b5ded6f5696f03988f7d34d1dfba6875dfe0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 224872, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "d6040f68651f43f78f34a538f79dce03dbde212ea54ffee062f89d936a05b508"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "aee213afb7d91dc7c8a852803900149883f2a9a6e079a87bd9b29d39bd119ee4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 180328, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "3980265cd53217748945b295fd4bd120eb43279ed4bba6dd14fd48748d960042"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214128, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "af1720c3c109b56f391870215deb44329d5f88ab062c28069d2a9626a393dad8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 186040, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "aac3d797ce1b65f0b016f9f3d706539dcd09d23849d2aeaea41fce5f0ba9802a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 205752, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "0f98238d3a59ebf608cd40fd059177740c362f33d2fbb952d4451406b840f560"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173168, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "aa1b6d91db2f0af3a4c1276d3342c0bbd51e9b19466c90703bb77de1c5095c1a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 176184, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "f0eeab610f8657ea444415dd56d8797344aaa010ac5f3197b8636396cf783115"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "76c28a50670cccea807113f668bd6d96d4063fd87b4c45473cf381e40ee4ee01"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "9c4c2e468bb14c04099783505540bcd1aba7ab92bc629454cc772a9962c92412"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "f1647635bde23354237dd936b9466e1e0a5a348dc5b01540236aca36c8677303"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "72afded07c9a4e78dedd7305accfcb7d7aaa39d52362c346bce6a471d950e605"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "e574395be7a5f8a7b839b45e67142ab22a853fc0e8c3223127109f622b476f1d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "08b754f158adaada2e960afaa573644ada19513aaaf671cc538701b7562131ea"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "48661d7eb142d06c09a00ed7af64e49b2b83993239d036004859ce4b8054ee37"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "ec963ad4f0438f07ac99f01ccecadfc1022eec8cc6982f337671b722f3ee53fe"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "688654e440093dd8386814f49a59ccbca621c79faa22390d21c16ffc4dd8589b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "06edbc64937a657ca3fcd3d534c2c249d7a95ef40d8b8e4cc777f5021da9fd62"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214256, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "a57de98d1b98688a00a685ba8b7f0fb13f6e8a9011d1b2276f6c4b0d71a9dea3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen", 214080, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "279588cdf516c4896aad4b714612ba93c7ffe86579ac9d851e7a1a2dc82c5f9f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166160, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "c385c3193118203017bf1361f72ae53590d6b41475e84e22cd544e598e6cb33b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "f675265a9fc316d9183e71dfcf0318b62acee144c2bfb8e31a472f198fb3be8a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen", 199952, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "e5069c63f51c7f42543b74bf913264d6336866af5f1ca70424a9ed43fd652135"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "2391accbb1c56541e537d0f13b6efa61e9155369c0c4718fa943cd2b7d1db594"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 173296, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "8cfbfe2403954d89afb72fb66f4c4d900d5e957fbe8626f86db7f4c2f00e8e99"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 173120, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "fbd74c07a45bab92163798cc02f9834fb3319cac2258a028d0b6e4204dab2eef"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 149264, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a97000ea6b242393e66b2157f5c9d3ec12edb074efa13efe14f96fc002cdedcf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "e97dcbbbc7420a2ca89fa2f778a6ff446e83499e6bcf0fc064acdeb7db30267f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214272, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "0641703fbc62a6f703282468afb460b427af7428ed73fe2694c1d303a81233c0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "04c2d14c0ce46280030b26595e226282a8de8b4cdfd7e18fbb39d3dbc932c765"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 157024, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "c537f356775bde261c2374de1cf3fc17c7ca9e2c06d39aec6864a1d2b7d1c9fd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "a4cfcc31f890ba29f8efa90cc133a714ef6daea437277662f51d7f53a64ea602"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180832, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "693c5478a1d35a533e9067daaf8c2d3b979d0ed0538ca257820ab45c8a48e098"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "d9cf155ec8e5b4ad2e0c1802acb69121f9b68158d837fb0cc6eb870713f22ef8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 173312, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "bad5f28a1d6e3ac7670705e3d46da2fee35965dd3a5fdf58626fbcd212b6291b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "6a8b0c69504823e55090c95f60f8d85fd51c33236c6fe436aac0267fe6d921c9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 145120, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "3dd50b6230d21a28b8599ca66be39c4226411e1979d4ca18db44f286fdeb1e01"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "c21f51febaf501d20e6d0f02fcc027c3bc10a1c1b79ad2dec3ee75a8e60de378"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "4fe07bb61172cd4a31b1ef35dbb174289d1d9622dae0f1198bbd8dcc948b676e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195176, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "00702253810623d5cbcfb475a74af628dd037f420763787dfc6acc9358a5de29"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 224872, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "fca1d645528fbd00673808c46371460fc9aaeb61a430186a4e0815e822d510eb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "f4869fe6b8659167bca01071c031177a8f0c3c1cfae45f7ec0b1fdc1031f4c28"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 180328, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "2a438f4155001cfdea8e5520c1e01d4a011571605adbf5db8e98bf9a1f1a7552"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214128, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "8578a159ca4b87c487631e2646a3bcaa0816e3aec8611318adae954163d14ea3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 186040, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "55c2a4b28b38d84801a80a3a88bba56637ed10212430b6b4e36bd38c7ff1256e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 205752, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "b60dd16414f6e805699382ef645905e5f4ce777b0dab812d827481e55c851469"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173168, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "5d170c970e07398c85ed3af96220683c769f4f1ec351617e472c72139bf971fd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 176184, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "747259285019b321974fe59629c773989c5f646e98b5ef5cd7c05323e92140b6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "aa56ab79aa909bad517e9d4800797ff9fdc90bb9347e6a6f7fb839dafa2b363c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "39244ed4f0811d3b6cd95d049ab5062bba92f8e7b13303c9ad171c73bdce9869"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "53e8cd720ae365077a18f04d0145d2858b3a3c84eaa6a89724cff9d18508c658"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "40a86dbc5b8adb04c17300e960aa877702a75a81f88a7592cac52944954ec733"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "300b3beb04e17a9ee2f7decdec2bdf6e664a0578abae69edf9a76545f88ce78f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214112, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "99456da4b1a6f7a0947445de9f0c4992b18f585bd5c6d303167772ced415c771"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "87553f02713872aec0b4edb69b1646aed7c92656c234e58a4d11d18550ed1b9e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "9e2d3c3fda5042d77d94f4db998c5e28efb03d18e3ea858359a5a91ecad56795"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173152, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "f611736109690f6097d3929cfda31b53a5e3c4d2f2e03dbe0578a2b795fa6483"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "19d663e68e2653756fe534ace632d760a271aa77ce2b4f74f3bd9042bafd35d8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214256, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "6e181072fb674ecf6dba734b5fc165cbdcda8b73341ea1416ff2ad8a3ddaf169"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214080, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "aaf767b81c8b77ca4c5806f290ceadaa1fc010e8d96887ff5a87f0e3c55040c5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166160, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "281b89a092dbe272c35232f47e3bb743007e611ec3f296369959eaac1b7a5dfa"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161888, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "f8d48fe99563f805539eea9f5549ffe35069c6b5c03fb2880ba48a7d6d5ab8a5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 199952, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "beded1fbebfa43ab75036377de0250852a101edeb74579dd2663d20cd3a0cc1f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 191584, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "f9c6a24b048fc7fcb54316979dfa57c1d868320ea187ccfa3075fd64f552f1c8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 173296, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "6db5218bde7fcd3def2a5419575c1ed3353707fdfbfd311d03b88660bb5d54d5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 173120, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "47bb1158c761f44615b58ddc7a0d11d22154700089376d63f53979f56da22efd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 149264, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "c688a756900cbed01709f849c26d2408b460c8bde6bb3f07697703591a6dbb23"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 147040, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "84ed779bee13cfa9c0faa5e8f8db3c96f702789d608454c3dc58ed9007a5c7f3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214272, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "f44b0b78dc756889c9bf1fad849f92e1c01043d260255a2c2a4517d4db3b1dac"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214096, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "0d52c1a6984a7e49373686fdf3ed827351cb56e6a961587fb4ce3fba8393be14"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 157024, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "d4a3935bbb4d952d5f0493e1f25decbcb549d76215bcded0a0e59331a9c26cdf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 152752, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "d227a4320eb96f1cf9cbd028ef6231f81b0afc0b036b739a7500ac9816104a1b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180832, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "f9020d11ffa4f072f450261e1c377a30bbe9fbc5c62b60169f221d52fdc3c88e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172464, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "009aea2aeec777d08c26f3f193fa9212b55651bfa150f6ad39f68a12b9a6c0c8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 173312, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "4be16e91a86a2ac0c5b12900d30085184699e32d148c013d5c1ed872bb3be931"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 173136, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "460c0007d00ab598b1049f411ae0524439893469f2b388ef1db91b47c6d9ce05"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 145120, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "5d560a7a261a646359328832201938d6e0cd9d637581d4eefdd34da5841fed45"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 142896, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "72e6fab9fb6d7945a2c3f0e6897e315f580163f6f1d236ea59bf3f8026c95ea3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 212072, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "1245bca8ea47491284470db4fba2e14a1979456992d33b70a5d9493084633d1e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 224440, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "050978fc39e7c540d575229c6fdc0350a76c7eb654c33853c57a3b5728ed2edd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 189032, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "3898b05ac05abea574dc5c8795b42981b50d12c78ed2ff170035e274774325d4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 203448, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "eddce71d2eec57c1b857f1a234bf3f17047b292b665e5275b7624ce964715445"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 194744, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "5f142d52c96453cce904b14f7d11292f17962b5566bcb03a917a927219b35122"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 207112, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "3e4dfbfd24dad820533c5037f5ff3255ba0f8c1f753376972bdc8c8a017ab8c0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 180792, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "99a3f08a4760b628207fd5dc9e782c41045078590d4e43d6df0f1cbc80f6b7b9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 195208, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "fe48c2750fd728169cccddf7854320e8e1b7800593e513b00b7a0266d483e524"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "017d98456cf3b6b1c5a82d99458c31c1e06c4498695334120f4b6348c053a90c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205920, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "c262ac6cca073eb163afde873ecadc68fc92bce4dc3396ee358725557ce561ae"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "e2f539a26e9936753ca9153218ab63616eb4370ceaf7014e1d350519496392b1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "6f6fec253d4385c1df7a505b8e488594f68bac0c64feecac0e5e5014d3b44a86"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "0655d01827bc022244691ccae9d3dd307518c5d9bc141eb47920a0ffeca5f1e7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "b05661036fc7f81480bf704cb044aedb27067c9e64fe51056c85e23a009923b7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "349a423851759281659ea237e959f788cd1dac6f449910c2886fef7515eaba5c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "d3b6d705d009b2e0709f92fe4d226d1fbb6b5261a3cfcb495fcc80c811ec72e7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "d0ea4ed8a59ded07938448930ceaa40625d61a0359c71b21f0e608e36f612bfb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "32512639a91938d0876fae0bc81a2cdbbeafe303d873f2570c35595f57886a3f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "ab594d1eab77dea00821d523313f634c29b8969a28ca059a8e3d26833a886dc6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "5373501c561145044097b3a2fd2b63689ed43e970da0918d4dd16658af77d248"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 194912, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "f96c0699d7b0f16f63f29b6902e7bf78c857a18d0da55235644dad042d799e44"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "fda97128c748ddecedd7b8e1e17fb6a3a3385b9b5a9abfd24b35644f762cffac"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 206064, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "260a5bd4250742b7c9dde8029163a621af20cd08491fb84621a369507e521d13"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 205888, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "03f4408fe6bc320c978afa1e39f929710ed8d018790149dba33fe335710c48af"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a31e2fa22368b1b28735ffccbbd06d08dacf0899bcfca49edfbcd4ca55f7fe27"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "8e714024143f22d3c707ba6c9423e1f9b9179c8b05eb68a70d0fcee99ed44c6a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 171872, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "9d9f282b2de96f5cfb51cec5bdc9ce729942fff8770d99322259db785b3b834f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "e56e8bd4f71af23119abcd86dc9442d8f33df22dc369f85af15230f635a9580c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "c86bb106aa627c15bb31ef5ff3cc98494dbe06a8b6cf2f1e1c95276717187e02"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "7ddbcfd5b9008f62a77bc07c2781ab7a8e19cac6143354a2af130a1cfc81c6df"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "65b09b09ca47def98b8502f68d7ab9d9fe207fb9c61daf0799391c5743999099"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "5a83b0bcc60b1e70161fb4616c97adcaf1da26e8a71db994adf7e8b644e6c4af"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 206080, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "4c2e9f9629f9e6eb927f0396f6b5828726fc85242988a0bca7927feae7141d1c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "f4828204857a2fb6ee92dd4135e470d921e72a6b4b4935c35bafa10b5d64c7d3"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 149216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "67870b652b6fe1a151f2f74ca5adaaf1957782ad29acec485829ae33c834a7ec"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "13ae3cb8444e84a6a0c0a0c0756fbd8c5ef0f148bc2a181580e5e24a147154e0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163632, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "ebf288f9dc93b45697a0ef187aedbe8dbd1cc8b5cc1a9d0fee4d7e7406962207"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "1c2a10d0e30ec1c722da1b95a8a3f33053686d36022da0befd43913a78aa8a46"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 198728, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "3bd5b60a34b5c2b3305b4fb25c6d372377c38c4d02ab0a4bfbfe9936eba8db75"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 185032, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "854b25c7e8968d3277f4dedf75c13f9542056409175cdb34baf14833bb367810"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "26c515d5a9e29de704bb8635326c3758a94f885f63220f9b3f77a94805fdc81e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "881e18839d18a3955b2169b91bc6d92d033e06403512c2b9f0a40f778de11a5f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 169200, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "47e566cd7ffef1e72d8639f6aa242157389d2a7fdfbf5dd077ac4caa0c639701"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "052e6d73deab1a7a1cadd61e6dd1fcd827ca898acffc34a4b74e2bcba43a4943"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 153456, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "2d382dc3cd001e8baf3de9d8855ddab77d72ad125fbf63b6a8e24b3f21edb2b9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "f8fab4dc17de2579f205aa832709f821c053d5a8d5cf6299f5cc7c03ddff62c6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 211560, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "5ebcc0b62b672782811563c38b32925564420c087da9e89f51afe4952d9b1756"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 223928, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "c7802a50254196a4c9e80817cdc681087cb47bff1b5abcbdd0f578b4f01f50d4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188520, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "bd8eb71e2c522fd33ee31038754c32f09554c4ed49ce8a324b971df9b950462a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 202936, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "34e3dd2ccace82787f85046cffb59407a2f3c1bdf6e30b8e251e15768525d287"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 194232, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "8a5cd865f63a16c9d0e815c4db01edc3431f3b7433393c0a3376fdc25e646e5a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 206600, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "8cf1795725909a8ded5486d83a47ccfb54d5e5070c383c306e1e859d4325d243"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 180280, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "0312dfddf8e1296f27ece2afde4607d46f07a54b3a612e4ea62f958f8af36f90"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 194696, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "e6590e71118ecd6eba574b2b6fe699f9c49fcc97f368ca763647a8b99248f6d6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 223880, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, false, false, false, "42a5e42a3dbff24ed810be03f8aebd4a6142ef7b782814499ad2d3d247d27059"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "7c41bac1cf7ff0c3323d5ca150ca07557a3e7280a26444109c7ab602a086567d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 223896, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, true, false, false, "61cb4d6cae75a1a97e3e3e234128de37e862d870fbb5258809891225df5db0ab"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205920, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "ddd559a9959cc6794695b5496d2e68b7e49b39da3c75e13d842c02e19ecb5a8d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "0e7c7af2dd635b4c7937664b31b1edd3d44f516eef93816ba307e77a6ea31f17"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "a587181b3ea399aeee522b13451d8f0fab2d78d3fe9cbca639b9f82629c95751"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "708df94474e9a2216a20a2f5bb6e4f9f08b34668abeb2fd06ae52b61344f555a"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "a960dd5e1d774ead7a975b3ef47010c06f45663443f3c1929bf82a0d74eb9573"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "1ca4bab07c8ef23993d2785e741be15dcc5f20abdca02cb8407361f98b513173"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "c18fb1e8531d17e11cc76cad8fb02052f587202746f9e6cc70a8cce2b25ef83b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "704479cd859b5b3a42bc583c6c72a7113cce03a185d490add9e4124d96e2dfb6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "26e4b2415352db2d862b12c8067f542c0091005640166f926781622e3a891179"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "cb59142182efb84403bccf2a2154eb8247e9c6e4111a3e9cd51fa5f86c96cdc6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "953eb2c15697a32b8d5e7ecfd2f41c20f7078ed7fe7e7155e2fd293e77e01163"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 194912, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "9953fcdcd648874b52858f56a4de16be762c46f8e0bdcdea4d211562970f5116"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "6037fab4fd3df79119649a46f0b35d7b715d2831767dd118e717fe82327356c4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 224040, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, false, false, false, "8813fd9080a8befa53a847fc7f54fd0bca66f1678342fc3d8b242a6d654d6051"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 206064, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "b0e1bc2f839eca21a999e2b704017bbeb6ebbc682580ba331b5e648d6b1dae5c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen", 223864, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, false, false, false, "be21747c9d02a01555ca6ce79687c5a225a035fa3179133cd6714abf7fe5732d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 205888, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "0f3609be1b1e8c6f27f86336c942fb02cf270273a3bdf2a62ada6b5c62cd0159"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a85cb04093434e6d5cd6863f96a872369c285a791fc9a5af762e46a05fd4488f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "f555cd291e501cd7c1d1dd35eff25df1a0d2b93bffb67171f5cf53fd87924ac2"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 171872, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "9c15d49d94593698780474022ecad603554b5df4e9f57b68591d9653e86c3d61"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "36dc747570fe5938ded2a5bc37ca1a3808aeb69b470cf9a7f08609e47855d638"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "f166f279d48113c5d7bd1cb6fb255d076e8c91222e27456459ae80cdf8cf6f44"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "28db9d62fdb63feb91978246ff0c646c0385bbbf885bb7a3bf66760af1f8fd2d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "fc7049f908cc06bd1005fbc072539810415c0f0daa814edd9d11c05134f70e2c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "16592ee57a19a84ad74363572427a7dc3b5a5719442218d2f4bcb529ef43d0a7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen", 224056, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, true, false, false, "fd1f3a135362300c15bebda8422943f840dd6b4f6de0ac6c033817b83943171d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 206080, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "6e24018a330a3e291102d20a72847a97103c5a237669e24fbee4900f9d774053"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 223880, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, true, false, false, "d5ff8b53512784b3a1613cd5509c07a3191ea6759b8aa21a6b1d92dbbe0af3ae"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "71f7b33429db885f3ddf0a5cf58a86eec5f11e7767bbedbc47a701d6b56a2c86"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 149216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "8518929a78e18e74a4d8ecea93fc2dde7d5c481c20f4907c3bdad5ab3fe6597e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "4c5f699bd7ea1eceb41ca9e1d77db0383fbd9ba89e57eeb2ef0bd840e654010e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163632, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "7621cf16e66931f686b49363c481fc8fcca08b37626f22f8054560e20ac197c9"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "72637ce3f300d6eacb93b2505efb07c1b25931efb6eb38c1d7f29abd0fa1962e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 198216, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "0bf7c5c58f50bc74014f6027d557d62659eef93ece19496020300b14700d00c0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 184520, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "4217437d041a7d277cbcc39ada3dcbda2d5ba0cac2d6e6ee0c9a5e9111be97bd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 229256, 512, 2, 1, 1, 3, 0, 2, true, false, false, true, true, false, false, false, "c0f7d69fb4cfe208e8f604cef1f61b6be4f12b57ca1ba8cf419b5126071e3aaf"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "7b66a0a8affc96410210a10c44a7b5476f9720b342d60f9d62385dfd430efc80"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "29f19870cf12862e4ef22b7d881a5cc23be205367bf858a16dd69b728acfeef7"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 169200, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "741231b52a5a2f6fbceedd9c48a699ca8ee7ff06af74e3798dd7351802054f55"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "58a2cd04f8ac4a762511d8547ddf39699b9a6aa2a9b21ea26ca33fc220dc68ba"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 229416, 512, 2, 1, 1, 3, 1, 0, true, false, false, true, true, false, false, false, "34321bd5dbcc949e9697a17d0d7efc40c67707e40481def289d0395582689f44"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen", 229240, 512, 2, 1, 1, 3, 0, 0, true, false, false, true, true, false, false, false, "ab6e1b6f8548d00f52e622a860455eeeedef88de32d9d2235e503e39df4679e8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 153456, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "7f14274d2802e2d33a87732638093f86f4175eb0756ec621597e5b9886925dca"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "ad650acf0fde6ec176ec5e57cf7cfd3a5b447404e23e3563456c66613980d937"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 211304, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "465271b979e89a2ab2a71de3bd6159b77f367247e25240f690ee4ed030883ed5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 223672, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "247ca15344ba910446befa8065fae4353c4746048e338ab282aeeaf518f5fbe6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188264, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "d15d5586193df0d067298312f280bf9ffc8c42a755aeadf8ff7a794f3a79940e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 202680, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "3af30345678bbcba71566dbd05113176b6c33411a557b0b54854cbdea073d5da"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "54d440642707d81b5b1d8fe133ddb8aeee99bdf3e4174fd9cb304cb6e6528f2c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 206344, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "04a29b43b710b1308896c486df74f0faad35579e9ec7778d52f81e9c5bb85ae1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 180024, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "47dc755929db07c040450051dd710a6b6b398188a0c6d9802c4c1c2606970a8e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 194440, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "ae64d7ab9d7f309803fd7cf745f9c667fcaa27d1b4181474423375738b5cc44d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "cdde5575cbbbf1d7dc543ca7fe623e7c89881ec363f52824cdbee9c19e463abc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205920, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "4cd4ccc262deda37dba105f3c4474ce6db0ab78d543ccfb9b4ba980835078c3c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "e00dfcc12964222cd6fefb0ffdf82d6bd0b2d1f6a7a0eeb8ae6ceecfce976d5f"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "9e330e052d129f9b13a56b7b6b64c0e6e5925dec62ed6fa4a2d85e6be99f4cdb"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "21042332beb916ece049dea198328155ae2c4b9a1ea4269af2dff3bd5120d5dc"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "5c5eb694b1519b95fbf20ea3f12d65d68736f2c642f54f0be6cfa55e2388b8d6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "b2dcbc1730ff2f35afb34f2ab4e5f3bb0515e5ac3c6ab63801eb0582351d7749"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "48c7e4fb80d88ec8bb1c6f2e721f15b81a91380df8072daf825be88fd480c060"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "4261c146809796eb41f222871f8ce3e50a16f9beae7b43fb2fdf2fd1fb4720d5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "5bfd0ba7576bd99200d14857b702a1fd4d6aa3419f7947cccbb134108f61e96b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 182544, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a1881ad2ebc21c60ab14da9ed1bd23e79a35a454d72a711418fe1e9987ca3a1c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 178272, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "4d478433dc6fde0fbcdc4d4204e3920798c236291e8eabc6876a36131c82804d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 194912, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "4884158d38f994170d9b4ace3d901cd924cc356b416d0f172042d282784fc1b6"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 190640, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "1117d912a57b934667ff24e4c34defe67707eb851072d7a2e11a365a6589f84d"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 206064, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "7f302c1709165fd56febda3a0eec9dd64dce4631eb62512c26319e2dd81598b2"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 205888, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "f425c1eef87bb862531abd23c31a31d4c08354b972b25152c3c6ca17368609fa"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "2c5292e40457f37088f7082128e535db9c6d80f6d820f6c8d3a4e430ca16d0ed"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 155232, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "e5177de9a0946b78ae6dc685c8c0202965da0eb76d7750ea84425753c0801ab8"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 171872, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "95db91ff326073101aa9b310940f0d86740db133198c65d0a17732892e93cab0"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 169648, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "3fc70e15afa1b621327305505276ddd0cd93f9e6b3feee0ce05cfe644100421c"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "07d826796ebd19077f86bf468753dfc301d633be5231a32576571deb9431f4c5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 160944, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "73989800b0d6d6febd7689b3fc988893fd0650e6d26783eb51991d5edfee78be"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "26ed509bf8b456c0bb7d4a26c1672ed6c23caa781b6808a597a80fe1922de5dd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 173312, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "82d402d0e9ae8903298f591528391c5895f0171b56394bb8ff42e0e14976f4fd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 206080, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "827aa37ad832e058e5a8171a3f3fe32bceec320c70444698befc5d1edef7c578"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 205904, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "acdfeb935716353202fe6f66e9069ff947d976f00972dbf5f4d4141aedeedf57"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 149216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "d463244845e90c7f244e804c4cdb70a0ef1afbc944c27f86c7888c10f1117560"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 146992, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "a1817c80b341d50a374383eaa38d1e3920563fa910a613b4c9a1b2009a5161df"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163632, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "0ccd7a575143098fa5984c2f4803e5ea41aa36c0c64c35d5b06b636cf13b4f7b"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 161408, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "e6cbc4b47fc124907537fe0af4fc863d7e26f06d3c4d39afe71c5aa9da0ba7a4"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 197960, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "8ed1537fd46580cda7c15fc4b8292b733eb548d79507fb64cc76d0abf1b1d097"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 184264, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "4492e45df5af9ce75b7953496471f8f2e912474a6dfac2dc915287342f919bc5"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "9a234bda3c1524555779b22b81cc85774f1da436a4b0c287ae5c850c10214dc1"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "c4cbb9e58e6928b27fc78dd2a2d709f2812e981e318c0b4e95196f43df232d5e"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 169200, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "dc5bc9927a5edfda1f29ffcd30aca6deb55ca460168ba9236778ca529c719697"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 164928, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "e0bcff729b64c45672b1adaa4480e03bbcb1ad363b6832b41aff367a264837cd"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 153456, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "9274eadf9e9e2e53672430ddfe6d6262befe428cb6bcae7bbb5d1dc31742ed44"}, +{ DATA_TYPE_BF16, DATA_TYPE_BF16, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvBfloat16OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 151232, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "9decbda24b6233972c70b7e6872c4c093aad123567b7b846a58b2a15236190c5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "57084494e18bbd40ceb45c50763df2bebce8f5ba8a909364af5a93291ebb3a5f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "e92d7962c5a34c102231d844af0cdf64396c41bfc18572a2ff63656213fe0657"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e754968b389bae8db8481e7b83f1d1aa18403c6619dcb7398b34ca18ca2a32dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b680d6575319923689eed3a995b5a8e47d2fcd00330d83c2dee3c985da43771c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "5d12b43e13869ebc9358303f1fbeaf98dbb78095b1a4f7fd9293c828083424cc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "ad16bf5ec1d1eb06ecf79a931da85d67e070c28c7bf606d5497f8050fdffa524"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "e24b8d97a963adc91c6cfb568164606bdb709bd7a2ac4b0a1c8de2555002301f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "beaa23aeb49a211c29644e2fe81acc2829b9936f2f0dd2b36936a983c2f61666"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "5ef54ac1f6c2dcc1c5a52cc7bc4ba5dc2baf6e9d0a5c0aece199cc6d60150440"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "6f0d32b5b1a0c35c75364bd47f78e4db087f9fdb245e91d013e971404f76a268"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "6a6d1e7bdb5ef64f462acfc74e62279a566253fe358f29d62649a4f821838daf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c3b01ba73be646d20d25c10747144c04cd7d3e01358bd540bcd42ce993631317"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "f04b2b82390f88126691f4a5bfc34bf7c30afaa53ee33dc156e8f807de5520d3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "de344e522e41c7def28ad8e3b996a1a4648fac7c3840e978cb9792eb7e1cc294"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "1c59cee5ac277140060c48189b49126ee5ea120f0b7ffb276b8d0cab95a4cbc1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "700a07d73350c1c3be6cf090f141f64eab6f53b1e411aec3d654f62bcd981d22"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "cc4bd3a2589d941eb714af76bb7b79aec31037e5ea25b58ac5d41f39ac24b221"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "fdccf415c6766f38255bf46ca42f41b901deacc3758befd555a492be553a4e01"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "30a5db93bacc127d65ac85004bf100763e69c75f1974dd989cf6a0ebafae0735"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "4d6416ee750a6b2d22cfaf7f29378a26109784b01a05bdc7c4fe8dc837515f4a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "3fefb8b3fb140aef457cdec8d4f32d0022e70c4073414c52652408c248577cc1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "f8d83b9760d43cdfb21151b32caaa02359970ead069874b2aa5599d1459c98f5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "a1b12f456391328348cc1c77807897d6dc6fe699352cc1eb3be6ce6acd123a4a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "294b5832dfc6500800ed42d274fcbfa5cff83a0429ba38911a9586bb8fab3414"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "f44062c1e565b8521a2a952fde5ffb8376ecf6fdb043c23e2bf4051b4304c208"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "117ea9b27501912c938cc8fe6a182344a5f6a4714b31d5aa84388be41b893d62"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "fd4747837e00f6900e3cd591905fc4a48dc8a0839020984ae33f3c882e3395f2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "999076747dc18e301d42836e2ef6871fd976a76a9b8ca7d9150413f247c8beee"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "9ab5dfe7f06b4f1b8844d3ecfee8075086fa40b556bdc872ac4ee06aba0e6370"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "eeaf4baa23f85c32ae18b5d2e9f5f9ad3aab417e8f90e417cb025710c7d8edaa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "132a40c898e6bcfcbd513cf22ba22637ec33930809d6088689103c6050c74623"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "e57d6a192d628cbae928f9bf967f465f8fbfab909e5dc06b7a4454376b01b6f4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a0b5fe736dc07ea85501cd43cf93c6a727912265567c8eb3c4d82176d35297fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "b4d10e090dc6cc1eedf0776f7325605877da11c89420850db10e6d9202f34838"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "563f967ed6c9facace61e2008f0a05bd792a5ce69536240ec96bc444dbafef46"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "0d68dd8cb42b888b0dac90b6c3ec2471b36189f0cc54363363f87fbfc3ba4b09"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "3f0266c4f9a8cf68a06135550eccd5dae7cf48d78f29587ac180de6a478246ab"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "c11d5642f86265647100ecf7ed616510e31d337041f753e2e2f8eb5e7648df33"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "4ed93206ced27f92ff6c24b32631d4df7467e835cb9613be2de85f7dc4bdf0d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "ab504620daaa9188d3ac339fdbc97803819cf36f3d1aa9d7d5173ab75945862e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "8781b59ca2e94a135ce66c1924d5022994b95e172445614e5fc0714127056bec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "ee7f52234c7aa69533b5fcbd0d8c068c9d1c38f2234dd042fe2042a95d39fd72"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "917d2b14b896ee618ebc4aa550d8191ff5afd061c64e17d72cf0d518502f9cc5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "9716d432daa01e2fe4136fede7d3f2c10b1dfa27959ec31249ced7b8a1d64a55"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "117acddb68d2262c31cdba1674854457219cd88112e0fa960ea32474109e6efa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "2e1fa418042a599b64d75111ae8efacdf666aa98d45e3c783162a4651acafe79"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a119174bfe557e8aca7de8bac8877f1c07f752a54c783ec06a520241dc44c18a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "102997bc272eda05cf6ca3eea6291c1c1f7a7c153d2de38e82bc002864d0aeca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "cb2f8178b5a71d24b381b38fc9a8edc3a401c3a68a5f235cba88980859df76c6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "b1b9b85bc24e7c0f84f5b4a7cd55d8c35f698f4f9c16a897c0437aec3025f0a8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "85f2eac20b51d3c0303d71b25c8d289afa46985b2da00afb1b1f6273dfb12835"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "db8e11ef3e3aba2e91af7c216ff55e27d987268e2075803a7ef5b27b7e82313a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "19874aa88786051a36df0df16021a42a1f68deba52fe825fada9af1e17ce919e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "85808dbb367c996d9b45aba4aa68656b21f4c791b68f071dfb434602fb8de21c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "9b62715d0b9b05960166022345246507116acf53a7706c592002ea30177fb2f4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "84af4823598b563066ac27ebde1c4590dcd67e60f1911f8ab281ec84a10badeb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "4dbd0e99824a2db947660702ed164495da3dac41693cd72b49451854e07a47f4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "2f5e166a376692ffc2b5caf0ebef578a825452b30da514de06f3f246761bd569"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "9c9b808e0dab5724b3664d940a65b83188cb8511904176a92f0c5728163dcee5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "99229e012d2d7a9fae6a632b4a83a8b5c071f9f0679a037503aa6951972d6ed9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "d2df039841e39b609c6d4b2e7fbe28814f0574c6e796b927f529b494d6663a61"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "600454a707aee048a93628cc5a7c86bdf35ad099cde4c418f643b40de22637a5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "d75bf9708075fc64bb31e4d27eba9c57198343635df02c671cc46da5c58d230e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "76fdd77498c6c635a10ee74dbe305f0a97b0e4735e5a077e2ff0dafa2051d3ae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "8afaab220628dda76b644820994ad8405a70eb3baa45faef6b88a97ed3aab47e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "cd08d76c02f8ef9fbe689046334e3ac82b03361569a9068594de6c0cca3c6406"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ceb94be3e23d059f92d6ffbc81826a341a1d5ffe9bd4086475688c72a68ae240"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "852275fd68f3c832c0a4f27ade6ef4b8ff2bd6771f876b02ce5454b0c64e3f01"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "33a2e01e5047f03a9d276981a0886efef7ebd78898799493cc1ff7d870f8a554"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "992aa0e6b2f806a2a0bb5441721781186ed89bec40743b9df5477a3d75c8d796"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "22b8df730be058f12d61cd388d29a556956ed3d1238c3ddb0133ad7547577ac8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "e094020ee671dc46c0be9d7988e4ec8a34bd8c5654a638d7c33d4b920f664015"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "5be015a90324b5add56f107d78619d6a96c91c512b11ac7fc5f0b9118f9b6105"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "6f944f4a69a08dd7927192a271ba179b0964de98e3495d60635f9bee963333ed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "3feca8c8e90dd7aa8143f033bbcaf0d1335813024212c4dd7c4ebf31533f9c1c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "967fb2a7fdb6888fc4c9cc77150db363b97dceaf18ae376d493d70ce7b4a607a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "4e93ff7eee147e3fa4abecdb957c707924f5f631474b32cb8d2c1189f4d56e30"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "b42a42718da1b802cc7bca4148fa6b63157ca6e74243c62acc22787f965601d6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "95a20fd3dc2a02005ff36545bd186cee5ddb52bfb035095acb3e70d0ccd5197c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "73ce808788055e9480f286f4ec90831b6d0c72006d9a4e160c46c64ab7a34896"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "34779cb304cff1df44c931b2bf1c9c3e8502070c4903cb8576d026d8b34b6c59"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "4c0296bdb1c740a8eb3dd8675baea5de2a8efc55dfcb3f59ea041af149081b4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "65268de89b052a89124652c7f34cf14268d467572b439f40f65a4ae5146813ac"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "ae0e52a0c8beac9e1a3ab9d28188b52b07cd55793ee7ceca63bedb6bec11d688"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "9bea5383881444bae579382de2524f11181a59724f63d2f3d5e5454b2bc89597"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "e0a2605b342d6827c62202b2070d0b6443383ce78ca01c55b91d78441c16519e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "e0ecc0527bcb2f9533bc945651016012b494fb543ca31080e99565da746c2ff4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "02488703bf7691c10d407c9345ac6bb6be70a27f266010edabc909aede24ec05"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "d5001fc9d985dd328a6a055636704165d0048b23753fc79cfd41dd884c766a19"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "6a97fd53002df8f7ce24d772177d111ae5c449db34c54cb98f5d14d11911f1f0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "ab09635aa3ac506920458b2413c35d7317667747ca7911c28fce7f59729c9e4f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "8c4a124b27bdad382abc7284365f04e8b48dc35c28fa672440ce321db162f5bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "27a92dd400e581af360678b737985af7f2eb8f03a4378b21b3466d98ffc23ab2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "678680db0e8d8fb0884b3a81636349a895d9c29799f7688c4bb173e476df7b5b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1fe1259b346b911e4f769bc18a33e09c6f37f67d3667c3f12c01c078f5f0dc90"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "9cfb2e2ea6577d95f302cd526e2c39f9ad59720fb7d5d168ffe89551d8a052cd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "a150ee65b3d1a1610bfe31edcce1fe40d5bdffb4d9414664847bd4244a3f0155"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "15b8d9c73ff1a2da74f96d9db53ca3467d3c6144d4cb17d567fe18baa6347300"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "6ef6e69bee70e077abee49a2c4ace5696f3bc849d0bf572513e49bcf5e0435a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "877b5d6926c7617b3f2a05205d01c24b826a2ff49cc27eb2f62f366a0afff6a7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "f961958945664af466fa6fc571a11e5633744a554d7145a54332a17bcb7c15f8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "0c2fb495a0a9da86048b7adb516d665eea12d20b0087f5fae659b269e3f7bfed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "a1c4c10bf3f8aec0c164e477f0d633819e07ed5181fe6a2ff47bf1c400132479"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "2a116d691051114f2b1f9255368074d03b43bd116e57a605a894271e05e3ec04"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "ccea8e9342ba20e8f6693bc34fbc448d723439fc53b1fdc875b8acb391dd3efd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "d9b1092ea69ca2e007f0e92952f895915330529fbb9a188b76e63c82f983b803"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "0083f2f5fa5cb1d5dd96f72464d02d0da2946ec8c8554881fb623a8ac7fbee32"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "d9ad74cf616f49c05bc56d6d6ef283520cd23fd02647cc463b85d68c37edb5e8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "46cae47f4f7e3e2037669e1685dca4ccb2f8dd7f4f7b95cc78bb8eb072ff450d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "b0943982ae80780fb22aeda48a57535dde512deb2fe7c028b6c8e0ee926a19f1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "841843e7cf4f0abe4b1fc3e9e9cb6155e3946a93a2f7f5acfe55ad762f2e10d3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "1adf29f88c6081cef2223c0139a654b94d3b012a21d2713ead01e9ae43a922cb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "6c1920e3d647fc0c3bd30e27fe0e2323523d4f96fa0e7db1c00c01b3d11a4904"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "0ef0b117e4bbf1708ad1e81dc7894d006a09a36f941faf8cae427cf5f04e5317"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "482c8581e964e5106db9dc316a06f31a96e170aa9b7fe555d412c5ea2a170350"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b654ce53e85c65307a0b0755a1ac1d86f2da9d5b31565efdd47371e545ac386a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "66b8b7a7eb02c1425f33c0301d9c07c727a840b7cca9078cddafc3d2c3ab1708"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "672c46d5b1ff8b7ef2962a9bab3ae47fc2c20309f308cbbf52168ded92da097a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "b793072ad86ec4a1c5f4907036363741334e4f37e561db76f2bfe1d58e807a5d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "ceb759bb045eb0193977a0a634f9f7c21d614d5d16a29d69a59282a900df7e58"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a70d0198a4367e65719fc006e090bc74bbade2246f1aca540f409d689115c06c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7d1f787c819f9debc114a54bc6504c84b30214cedb4a2b268c0c7e1423a4e7d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6eff77b409827b8d6c45cd8d908386873f60e5ac90d574dca8818772ab33c56a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b11a62d1d85ae05235b52ceb2eb973342261396c3c3ad8375f6860cd476f8ac9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "eb2f0fcea5da8afd13a1f6e24d7fc43007f32afee8ef7457d236dd717f9b35e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "547af4ac19f987f53fe5151d7450ebeac0c6a4cd3702a1e18c7b293c3133998c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "5edb88512c01af0f4df248d8a74a6d58d551f646d2714e81714842c9046d9ed7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d7ae662eab445c9f845809eb8fa7882cd478105ab29444be2952fe2565a7a509"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "46635072d07850bd2712da192d7ca6dd25b559497946fa157a29fbde2e7cbfbd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1141f42ff3019af41a1d9a422db13783135c8cb7379d594db505f9c99551db52"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "a2f66d1c9bf7441a6ac02f0a7c542a6c5cf249ec23e96e020f6b492b1fefd2c3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "65fe793a4ed766adfc15a99e8e177bf900f17579278bf35d39fcd43070ddf0d2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "e2947bda3ab5e0c5e9bc0e2e37864f7b51a3022fb62b061e3c8264099e3543dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "146f700150aa288761e360c7304867441252bc746dece1d9191f54d27ac9645d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "74cbf73c28bcfca8e77de4eb094618c4287d1fa462ef112d69c3da6632fc4fe5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "6e3e6ed8c82b0e7a6c3ec02536c1c81f158dc21a3b099521290ffd270219a051"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "9eee9814918a1283827704440fbe69b378f6c737ae4e00cdb28a2993b7e372fb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "d90fe04c475eedf680b3e340e73c994110598d636530a308c5404f4110cf5db5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "bca8837b923f446def185dba103fffd582f878981021e1dea3ab9f60d42dc877"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "dbd05b94c83d2680cf75f7f24eeda312eebff7e7446d94311f7f8822c1b986f1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "7de9c5fa71f2299114496648fb1b1458afafc62e425a12ec05c5a01efb27106c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "3179bb28f98052bb567ee69b857be3e84e3e88c5dcf08b37e01dc10736a1f276"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "5c1d0180f6d31f1155f949e4ab0c1d2400f21fe95f04bdba69ffca157819ca06"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "794e73b459b90a62b8cb687d14e0d9a4d79eb49fdd70b237f213ccb0e2069e52"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "ced7335a8a56c9a53672249de9599f9f43d55d9ad520485eb34a731e8dfb940e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "7ed4ce0637f584fc8ca094956ab86161e14c138c84c475d4dc75782ab4a5a67e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "b880b08e9384926719dcea80bf7bb4e8f07bf7e19a48d67fcb7f83df913931ef"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "1c0b5a37193761b4f4deadd82bc500326d965d1e4bad7e23369a0ddb867f4055"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ed3f967b589f42c80b066ae39912b89053d2f792aa4d78c14bd0c1ed3e907bd3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "5f230999d6ce21ee8f89b541778f1d8c1203652aac8be84506d26431bfb71164"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "51430dd612c06a9dd9442732f359155a7c44650b8f6db30e047da46d7aeb7bf5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ad88776bd23e419fa53d0ed31ac6958667066aee424d8112fc317aa3cce0e449"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "7b2cc13fdbed83dff927f17fd4fc9e3c2d9131ca1b432668f5d3113eb5a08c0a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "82a3b21b886f7265c6c02a64cadf7b846ae959e45f4b6b50096a627818396cfc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "34d09c17a2b982a45b284997be647ad22aa32d3ab19fa7bd8c2672c5c412b844"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "f29ca13f91167f31f11a44d46d101ec04fabbe468deb62294ce2397b204b885a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "6ac66eb4dc38dfe5756cc02bd2aaf337903337b6c91e439d972e96d36d58f68f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "d86d8267ac1df7111a050cab70fa4cb452ccf54c807f9d2cb001c8a4953d651c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "f55ee95af33bf2a22cbc5ce64105479aa4959b8a0739d86e326edac6d7f3c130"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "e44517675c73f5817fc02dddd46be6a0542e58186046de283da9af9b7ec267c2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "f274f9c2bb03de785cef94797ac844c55320d3eb497a20707e69f2d678761271"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "a84c5736df6047befd9856aa9fb104d74d5c8e756afc2cf96aa19988f7c1a81e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "b4f417cdfa3ca9268f1151cab737d07ebf24a4946920266bc8d2c6154283d70d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "594d34668e71304800614ac227fe7324d6e9b4ec9751aa2d36d4b3fef2296474"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "4209ae455d87a7e778232dbc8627e1fe70cd712eda42c505526e7694d784aed8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "d7ac31a6f36c487c848a66d55708d513f04199e1e56dad0b5f5ace3edc9186d3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "380eddf8387b14df4446581b0e80ebe96ead410ed270b6d3bacf5852d42f13b8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "22ce09644146dfd230e4745e31be5b2cc55c8fcf8fa5eb39967f93d3512d0da1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "99c918c6777ab5cc103e83fefc4817855925075cd6d4701dfb52d0fca83a5ae0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "14e84d0e8f8661b8fb4185a2369f62d0cce1232e9cc7fe37d24bd5579299aa4a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "5dbc1e247c5fd52fc44ee49c03f94a3d28211041e8d417dfdb34f1f936f5402f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "8c6b1131473587a13965c2349eac8d5c87e69d65ee949b4227b5a28658b74874"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "7f7c84a71f64a41190bc00b0aa2c94e5fd753092e56254aa801aac4252635f26"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "87a9d0d3e5cb71363fbd639f249a814885b0eca097056e92d8325672acc091b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "69fb550fdc607b71a8c15d2edd3eaf2754bf575f3b2bf2db339bceb9004bc9e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "35067c73f52c16bb51ed738a4594afdfb5e3e8a757e78bde5aa56d29603cfab4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "07c1754d856756f5c2957032d8cefed1268ba6f0309adc2cacc5f9972a0d23b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "4ceb1cb2bb5857d4ee7e168223a84e99a6a06a81901cb25b233d8714317ea332"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ed24d5d990571e95b83251c41180464afc0f860b965b410ebff3ad806d1d8502"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c506fc416df401c57e335b15c410749828c4fecef5932f60e20febaf3a3b8719"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "b48d39cbb979a6b5c090fa542134db1ee7f84f7e6e188205ee0dc26ea12804f5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "b2e44b334791ca3d5ff55e2d1f1a46df976aedf1dcb3d15470ec5fb27f8cb458"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "f333f4c5650c35744f1b2e5d0f0960af18f07a2c46cd05a8bae5c0be9a5f08e3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "3aa6f680aa3a36921fda23f3e19c4c34dcb4fc93a91d14a4a16186035ed4dab0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "fda49da5d47d8c63af8b74f7dd83cc74dae5872130109b4b9d66320bda373475"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "2976160f3b523515b9e911f6012f257e3935c3139b404a7ef15b09fb57d9ee62"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "6a1c8e607546f7b7379a4113219bc13eb393d1eac4227426967fa842001db9be"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "bc21aabcbf4865de1b7c75985922740607d5ba3b9bb56c99ad440b1e42376ce0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "86054374c97448a4d6a84165eeb17a60bd8f6d9f955b431f5819668c40646f66"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "40af7d116c5f2947846b4b8ba6a9577e02b5129cbb3dd05d2f69a3ba07353eb1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "d4eb463cfc5353b3cfebca901f1a80baa32f1a644f89aca1e926ffe421fabe5d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "046efd21510addf4637a7045edbf4ce4adb399f461a488307e8d5a59063f0ccd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "1c8078d717370401090e44bd07bd78216822723b40e5c351d8bd7dc99be13f3f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "f128713d65a7c38848fb4733ae8cbd02d6c7f19e1e6abd1f6cc4017aa0ee9d37"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "af95ab6ab4795b8a850676cddf6b1a125959b7bb4a526fb3eb39211c513c9af9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "399af31c9840833b42b02b84ed3d31edf2d00ee5f32a0a097af3491175403fb0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "02abaf06348c2f60c56b2c8c2dcbd88b0d4f311ef9253c93b31241a5678d7e00"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "ba47f07e10596057e2589a3a641d54cc5e076e9b5e5067bc91401cb8ad986d73"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "533cf3bfaa1e329c80567235280d070a81829dd4284e220a5e60f185528b8abf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "8da0e935635bb627e92f6cad76ca1f3d87e60bd84936b3fb0cbd9fbe9bb7743b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "8b90c4ae0b310868a24f3eb5cbfdfdd989da5bde13dc320a29506cc98abd7b25"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "7a9563ac5ef14f8c2974cf408e79e69530027535a9d583fcef3735da006fd83f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "26a6918f2545b6f5bcd7ba03c2719050e7cb37f5b6549e5958a8ac79b275c15e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "9fa7eb378ed4fb4c722692a0f45590fcbeb030b5381b67a3f389031d05030662"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "88619c29ff6858e96b1d37dd8e62931be217a5554a4f099506ec49c1d9fccf59"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "b56b99021d9270e479d1bf32f19ee1a5d2ec1f2ce4b3541a7b6927014c920c72"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "daee43078a70233291fa36e98b140b053a9d9f6e985dd4323380ba499157e53b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "57b293422291999bd893642e7d2eb5cb8ca7834dbc2a5f0e6688b23f1f7d6411"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "a31ec16f5c184418e0a29bb524092fdf75c5c4057f0d8e0ad1e77a551fecafe6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "ef8909ea66ee47a664471d3c011d18bbe22a7eaa1a8df7cf1f2a91378f2b7620"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "ee402c8486307754175427013c58903034fe361fed8dc1d6538abbc4f9a8c177"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "e19591b98178c515f3603844f027c19ca24f139064b4f008bdd1e3feb94b9054"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "119505c88c399b5136c981bfecae1bc39b8407cfaeaed86d452d85ea32ac96ff"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "e4c8ec88b52f4f92966f1a5671ee9ad233f079eee0c9caa6fb7282798116fea5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "3d3b381e7b1bcd0d3c902b3dcec6a56f7552f4178c8733ccf20000d3f12ff9e2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "44a16594e58002b2f0a4c37775e1837f6023757954e380eef206fc3fb31aa2c4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "c809bd5ce4a3e6714e8baa222cc40a39ec4cffa08e496728e83c6f3ec804f443"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "e5933f8a5c1bb46db7cd6439a6652e0e1315a8762aef6e8b6adf1fcc6a7bb2bf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "8db8e3c30914ca7f0fee217a2145518e4856470ba153bdffdc9cabb22d4dc7df"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "3ad5c4acb64db4fe02ace417b8f5481d9017a869c6baddddc95066fafd0dabfe"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "9829c536a52b81b4f1e87669c8262ad07541c2f58da8d67c674bb57d17e70afd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "3609f9f4b983031e61a1f05a064500ea5c09b12be183ca44fd44d1e049a9bf03"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "690ee2810939957b26c45370cdab6bd23e455464bded2f1dbc1053573993b845"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "7bcb511aabd61337ecabf45715d73bc0ce24e1cf4f11b423b0d7d69d8f5547ed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "928dbd99598914130925fbce87bd83e9784fd6b3a8794d70af484c647ce50814"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "49db76ab6f3eaadde6a9611f8054b62a0f66b59c76133e8ae89b140234dd3a34"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8c9837872cc76440d069e458e58dfc58cde203ed70bb60d528221df206c8c046"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "9b932f62aec2ae8828f804a17571896be2765a5822e6dd1f94afacef1eebef8c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "edc028fd9e7b3226dc68b09a3701f9aef7eaf34068360f5931c1c571265c0fec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "10ce67463f4c28f0ec631588e771ce4d50bc8f5db47620c00df15949141bc6a5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "cc99f4aec69b56b552cb209f48882bc21f8aa5e81af5dfcebff400e5e5895d73"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H256SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "f65a14f08f9ec602a994ed76640268f589ba5c4fb6001721829b65df312f0f84"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b1adf3fb68d633551d3f8d7eb8a2edc24ad34e7da8f64c477b001999c5718de4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "1c784d647037a89e839d43bcf6892e904511e189576d0e541d06e9d9c99bc81b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "41d2a61cad155ca444bc582302fd128f271d536b50983cb9b47061691f82d049"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "74c4f89e0d6f11a91392637e5683582683db00086b384c299b0edd6599ec9397"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "c74d59757279ed547222952e8a5fdfa78b303cc23add805808965bcb1290e97d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "119c70ef2ff449aa51b8a002fada7cef0d8aa87e2b18b14186ec728f632af5a8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "3ab326ee66ab994364f76eca443e2f19191590b79e3ff7346318882a2d749159"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "8139e2ad692acef2e9edeebddba8d84a0ba3183f57255a175fa51d759b5aeec4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "2aaf4f372d34c1d8e59a7af7a659762cb06bc731b11e2b5669f5250d8ad4f8b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "b58fa03f8c66568ff3f5720948198c9166edbc33d76e6bb2c085956f4f9dddc7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "eb92d9fe132331ebe5f5f00863abec4933a4601d594eba4c7d7d503f310090bf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "19c8376546a807541257107fe7179d9660962761f74ff752c5c8b86f5ea4f114"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "d6ef7cd12a0670a17805147ea2c4335e8174fb53a6d58c00e9f2f02d915df3e1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "66d7e69978edeea0a76bae0365002eafe0b3789a86e1f1a643c2c5793c6b7536"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "efaeda3eba2023aef067b918dfcc41d7d39d6e7a42bc3238b7e0fe7eb11b4074"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "576dd52af21178f735186458ff40a1c9104e82633ef63ea3380492c79c39e41b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "49c583caa599d9ed96cc5411418649e5c9280cba87b66a81b72f87a99acae998"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "c4d759311ec97d39b419a8201cdff5a26daebc0cfdf81deb6efe4b79f06c74e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "9f15341ada94b60e00055b30b7c5984b63d1de18cd660cd99f1e07df0d1380da"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "25b2e2233b6092c18239272242e60045d555390ad2bb4630e39137286a00356e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "c5eba1b4d88e6bfd4d111e610ea2f849bd426a37b7a60d536098f0e411eb9e2e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "841725bb9c151ba64b771b35614930c0fc009368746ef04f90430ae5cfba7735"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "21507edc95d52203da0de4fe73c70f08dbb4ced8812a6699af182a956ce2e697"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c45671f923fd96855f107094d550f7419fea0db62d48430397ff8d0530c3b2be"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "4639d121a43682b9287c627beebbb3e884ded1a40963e42be147745246f63c0d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "c15647e66cf413c5ef94f8583157f24c3d792a4a070391f8b738890d219093e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "a3c605baa3af9ce9d27aa66ab5371aee495495f5260c42f2137cc19be88bca65"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "5090dd696da4502b225f71b5f9410a64db54845f0ef0535f2a3a767eeb4daf69"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "a45eb4ed75b2461e0708d28d32baec4f98a0d9da031bfa9eb6db26d5aa853f51"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "bd53c4734e858a8e57a6a844cfa3266582711dddd44c43f764e14241d588f79b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "b2f1c9fac43765e5af751c3c18f393712f6b9ee29277398a1ed2947581a3278e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "5b64bd5eb5fb6b702bf2aebaeb1842404a870322b241ce74aeecb020a88610a6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e656031ede8a353986c9872657452f182f651ed4fad4cb660992d80eb4b1af3f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "97c16372370774ba055140d07c69476bf1e231be78cdc24967447efda8c2cc51"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "35e2cd4deafe0b4b1b7040dcfa0030ffb73ee47e1a394613aa14269cba6e4187"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "b153a2301eec0c5dcf70fb953a628b0c5d770c31e5542a49aa8c44f2900589cb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "2e41b243c3767d8b4abda37c3efb6011af4128b90f85d96a72f8ada198645064"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "3391aedd5202193d0917cb59441c31030b54994721058b8d57bc25e181135af0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "a49c59e214d7779bdd873c13b38aff88e4d437406a0792f6816764a38f08320f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "23670d59420be1f2842ca3bb6a9d5d945cbb9b3e0f24894718aab6bb71abffee"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "ab05dffe41b1a5d12c6d98a4d008becaa8ab1d9d4c398e3973ee444c327d1b12"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "3d9a550d4df04e076c577c2597b7d83c03a7b7014c3daafaa656292a19ce8dd0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "5c05f526f8e82ae24bb214e38360c699b236046f7a81d9207cf3756148c97445"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "d02e821bc6b190d9243fe2bfbe58d8feb63367a82a9d50e5314fc54e2a076ecc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "a55a80396c1e8fc535d5892b6941f3fca7dbec24468f7abd62ed0c73e6d008c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "e0a4faceb7f67aa299ae3071ab59fa7742af48989020fe8c10da1643af28b574"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "d7c0badda1476b88afc47bb54399fb0cc1dd31752e380a7114c9169fd1b4e662"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "9765c2aacdb00891f97278e4358905c0ab142b92704801e076028aa66461cda0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ed90365f25de20ac759f5eb178a079482c0acc61dc0a55c32ba0812cd9006c79"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "8528bd42d13a694fe8404fe206a4006eb69af1d991315d0469b9df992c765eb5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "68bc8d7f73d5146cb808069093fdea9caf7429c48cccd10f50d2bb6ebafd2b8f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "3934c5233c00e29b88ea95c7f002a0fff832c1c4ee5e4a074ce6340b2f0af9fe"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "ba95ff96f0104968d9cca0f34ca8ebdbcbc71936bfdd2092c0bdb20c33bd97ac"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "1a70b5390cd18dc40a1c1f3de3177c2f6ab11a5184f442a14e5987ac7ca217f4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "90ee15cab73be4991598a8032d3cc3f2e3696e813461e79c26653a52f652f80f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "7ac49c2218169a8c7293127ba7ca8f9827194131bceefa9b1232710a8a761009"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "4c46d57e4d86d96b46d2d3eae9f2caa9da17e18f0a95ea29a3b471d3cbfa70c5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "27bcef3376fb65f828aac4bc89ec350146a6f98258d434e72e81ee911153a8c4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "328038a63058a5d35f2522ed26c912d87875c4505a2df73a5770c5a9f03b1ef6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "d080bcb819219ee43ae956660374daccbf9e1a9e5bbb3d060c2fb7ca807486e5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "6dc7af5292bda5cd73f9df028259fa52c90cf7388796b41fcd5540011b85c42d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "f3758195361f84919158fe7f1a26085cf8d6e60374548dbef6cb4253a4513d30"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "6ab3fefef6f43c40e3f637b3e1fbef64716186a11780bba9c0ad3e9c158a4442"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "60fb07ae69bb35e9da70f641f4cdc9da905d736ea6f76af3b8ca1f7ab1741d15"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "4506b2218ec428f0936418f30972868c1f063d8e790db791acbd6fd34ce7ace9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "427ea1e7034058700a8836fb38f74bc293b1754c869516992ac103066265fe63"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "66f199199565bc7778cc6b96698c14b522f67d318f5b5d83a15a7c7fe6b339e8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "8885a0d6ba4da6d166f8180541d232fdd768d64cc5707fb5bdb60529bce8a2bc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "2d5e6a65fdf7d81ab4beadc7cceaa2d8c143b88c0852e6a6a0ee6bdc635c89d1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "26e842c2d73af8a823473da41014d23ab66da9dd4f9523f45b3568477182ef7e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "5770aae67fcf00d6fd78676a6f0a4f109f32694ca9abc92542183512a34dcdf7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "0ce2066174d4ab59ad4313d3707b6aa533a1214a21929b1b4e5c63b651c54588"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "053b1fa731f4f079ec791a80fb5027516bfafb5e5942f22104e39e27d5ee255e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "fed549394fcbe1701bec61182e735280de6b6059e18c7c2bde37f34bc31abd7e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "8118175d7f33e723dded98eb8ff837df70498696ece49de1de1e275df3f15be9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "a4ed97d6cf59f3ee1f5622b44b0f41a69fc310114e4eaf0d14f648bc37b1d5d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "03def1a02812d1dcce732d163d10d06799e19f812d405668077c4fc44fcdfdaa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "e7e94980d09facdf1c4637c7cc5bbdf02af0a238bbed420435b69ac00c1e1ef7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "8d1edce5f0b0f4caa8a2d1d20f3ad87df23423976b884296dcea9bce4fbb7cf5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "526228e131a5b952f4553238b1123ed7cbda5d17a301f2cc5a1def9189d2acd3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "a7cabca33697d2f97cd7cd45a3d6654dde474fd1f59164130fc1c242de5a81b4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "173d43bfb1d8d6f3e1e58b22798ac568a2bb0db8ec49158af241471929e43845"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "40f2a955d0e1505323c89d1f732f9e3f9cd14f189c894c22d87a39b4fbcf12be"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "6be392a76cec9d6c9aa9583e3f33d27c841e38a7e2d554b137fef07bb7af9159"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "3b6ac5b5d8e922a5a1cf162969f0829ea1daaf14dea618654fd62c29879ec594"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "93cf19959a1ae5462a925ee82d64f7c6f66be04f47088c6059fc48f6deaf75d2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "6616c94013fb5ad25e988ee52b1f22655e98edb78c50f61d992cf5beb77244c0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "f9efec4c2e02aaa2eb43f6a982f5939e8f73ebbd31d6b89cb5f5e416244954d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "110645a902f896098c225cf04e2894b08b30e2c079052b471bdce9b92997a78f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "2a57409dbdbb30ee94b125516ae3dd9b729f9dda4db44ca2914c1403162b9a45"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "e89e41869b63d62d8c024a3d0fc896d3aed1d29dac4e5f08d879540220e8e8d5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "767acb37f928e2bf1aa0dac32fb3cbbbabf6ca96cb85f7cc5ac8c9530e4d7611"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "d30c435b0711ec3f126b268e78514af653b99467df343c2639b8457858b01cf3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "b60636a7710cabb7ca908a4683ec750d3d773637e9a845e482396e3a46ba7b9a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "daa3b844582617c0666de19656950d84724a89d994eb955f42f7692e3ae58f77"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "076859f15f4c41cd871c6e45c3c65b5ed40e22606095faf9e056402f580d01a1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "0778b6a765ff81fc48cbfd1badf75954433ef88fc520bdfc81b1c27653987187"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "def29fd3460534d4e16d2843d5ef4070caa7292060ad6f71f85a9caa3b1cb086"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "ef68191f865c13ba528701522916f62be6d9c7be5d32fdb1341a92e93fd31f69"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "4c315fc9241330432e90c8ac0211e9b466ff0028a77844eb14dbae8fb5b5473b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "ec6152a0b7a9fa6d13ca75252d9797e0434f6b60de489311b3e8e3c25958f268"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "2ea913b9e3768a91e6b1409063678b8bae3f4ce9fdb28f43482cb0327698b12d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "17ae831c3bca2dc42ff42c00b602ee0749604b5be8104a831067a64350ca5430"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "886433def0fc5742ea285736e9b5a44e398d634f16917dcc31897493f401e7d8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "66b10a219b7535c60bb3e4f74cf487592e92505e0688f42b3314d4a764841318"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "817a0a2f7c9054b18ff705381fdaddaba449c2dca9fa8f5a6c341253b440abbb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "c0f39d07b82b8842e3c6cb55425d382eb910f334c8a19fd52906ee41573e4d4e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "866ebee47444e3f5aa1ada9b1cc6633e7e74f095c45aad5acc536d97ac7952e5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "fb2a555ea51d4ff919b5ce6ac7bce29823f4f82d731c72446b4fb4ca71cda247"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "b73aff1884b43c29965c9585432fdfd4acbe419c68171548f045770c854feee1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "9e0a2962526a611022b2b7ce06db79c0b33e3f05c34ae9fbf9cd2aba4193554b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "2b474900698cd02a4aaaa4e58663a4304c2a5cb116a52932614b34e2613ad0d8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "cba54941fe30efb8427124666c2bdb572130508ba5fd9f1c6e347e827682281c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "ff013021930921c4c51179977881f8631bb316fab6d1e833dc7f903ac5a7d7c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "373987d04568c8f48518e9baec3233afe00855dc7315bb15d21cadbe9cc2112c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "7a0500f95e284c952779dc689a84fc73cbfbf328da8228f9257fd907313f3039"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128PersistentContext", 115104, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "6f0a936870af0ac515d08831b87998dddb92301cb5488eedd665001d61f240aa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqQ128Kv128StaticContext", 114928, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "de3af91c1f6152980fcf7c53ce6dcbb7f3ef68524f6e6bc655e3ae64d82ed159"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 115120, 512, 0, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "d6fee5223d5979e2f9ea32f9529a5e2fc482e7cbb822e3a1f5913e9de637b2d1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 256, 128, 128, 192, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk192HV128SeparateQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 114944, 512, 0, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "eec91ea2cf1a63db2e9cf8eabc6194ef62f0e13ec65458941d9f928d91fe8023"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "5a0df640903233a8ab2a9c183e5abb11166a89faf137d12bad692ab80819851e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 199352, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "043ef8deba6e9dd1effb89a142d1cc67984a5e3290234b08e15cd7fb1bc6b5c0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216760, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "a0fdb14fb36b30238b1e4ee119b8cc9acfce1564fc3558eb1e936da2a0d7036f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, false, false, false, "44134214090d524cbf80ad18b069b08fa8f69c024861ad8ddbe61c91bcd17968"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190648, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "0c29719dafb5b6367ea4f692d58b739c36c22a938304ab0ae3bef9fb1b6feec8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "3a06a328fd8d96b79b051cf789db4f34fe6a9321cd0a0857b094710dbc00d41a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 200472, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "afd4a9a01d21a277f7e761e3c24cf170ec10aded79b3d4c3e43cdada5e60f803"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 218136, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "cee76495744611c45e8b6e2b59d6c9a2c4fe103f5594664f8f82e022ba05c6c7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197840, 384, 2, 32, 1, 3, 0, 3, true, false, false, false, false, true, false, false, "52aa5cb492a8ab037ccc27d2ee95b90cd2d17973b74f22d217e58c6e3ecc8a8d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 191640, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "95b023d0cce08c7af0e3b0bf0e09d9d94b73bff52579a584500102f2bf042966"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "7bf448502494b7793cb8f40c206fedf52953f65d6132e2970860ee43a22e5784"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "1eae3e32d3454d7f48f8a57a0bc2216ab8e28182b830e018a921e84bad21d196"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "30813745cd77fb7739da9851fccb1f73f34d9ef38208bd3a957f8e1557aad710"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, false, false, false, "e4fc4fa81e82abd65b6cd8aa7267df1134110e625e0acb30284c0921c781cb14"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "1f22bd18a641f63e093919d4f22daa9d8aa3bf70bc48865bfed3470efc8c5a67"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "04c40c4cce01e16ffe89349178d8be7809f512a4705c520e90b43e5d2772e725"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "378bae98dc8124f25dac8840c5e1ee8936ef7bf9c9fd310613da61b43914cf11"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "d4eb526d5664db9a47a604ca8ffb5ad7a315c842739bdb7eb82a8f6c056e6ba5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 1, 3, 0, 1, true, false, false, false, false, true, false, false, "3ad36ab6b114401e7f351d51b1eb14d17a6f06c7b67c09b505550c2b99db530d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "e2f82d032dfe2a4cc71438e3e3001816119e7a1149d1522270c904d7de036c14"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214320, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "0fb4fa272a404357925f7728df70d134450feb3c5e9483042041765f5283fa92"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ128Kv128StaticKeepsAbForGen", 214144, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "6b7615f4c54c813c8040712600325c816d5d3755d2dd0dc5b07290643e32c999"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 170336, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a3d801b14f68139f331d20e1c992126f40ec89190c57361df46992aeca889659"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "e332d72f37af607838afffef51dbfc1d6d19c4f399398ea51fe18c492aa1ca7f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191840, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "359439fc8fd48a8386c4331b93c4509e96d632316953330363682cfb797954b6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "0743e7b9b55ff306e6d0cd5c98955bbcbe0ed0563cecc311c0b900576545c823"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 197968, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "396b767e5008c246e7e7cc43eae5d7e9e014d7b125a259d99881365c45fcdbb3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 197792, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "e0f52854573b288a32fe391915325d1df5cce7cd7513a633048b65b513a5fc73"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 159584, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "4da3fb8aeb706b6e40155a931ecde011eb1b111fe2ed74d240ee8ebec1aa7862"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "88d692c564aefcc03a96ce024c4b6131fa8b4fe1e423574045fd8b1869608ff4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "43cdbaa870827e153032f1d0f37843ca8df6a28c51e06bf70277c7aee034600c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "03e55684043da8e929b031f840926fe3c01a81480c7361312755cff23bfcb39c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 171456, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "38ae7466332d0532359f09e50c9308a6f21d3420e6a8f653db48b87f6cfc21a0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "00126551c0105a781f39d1d5507eff1f5773f7798ca5e6bb5d9ae51008bcae51"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 193216, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "ec1bd1d456ec0982f130732441ab6b9fa48885cd87bac9382c64fd5c43c33a55"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "fb44a67a259894cc3a20884d6f689d593b0e9b65069fce1df19d43143d9787d3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 197984, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "26e13f502620696ec9c2c8ea0574cf352872d060c4a9adabaf444feea013f52b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "7623d5be3bfcb572024f836c3bf0405d9e8b26d4a794012faf1309db87cf0d56"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 160576, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "1fb0e89b3a33cff8e37af1f915ad5a76cc483ee02daad684b0db128138212b8c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "64ba339808a3d3274eb0009cb0cd6ed4350347fb475bfc7a0e858af683c6f1f6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "a8a66a8fa61cc143e689bc44eedec582520081d50867e8ce58e4d06ed4b94a92"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 199352, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "4b4cf8cdbb9aad689ec1c604d438f5d6188e843c1ab950649547179adb5552f9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216760, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "b161081af77cac4c8948440e0c1c3c62b9e33fb992e9921444cb5ba6825b3599"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, false, false, false, "bddf2709ddd8660fb9cd36dc9681e03503a9edd4a4dc19803c35a6d839ad93b1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190648, 512, 2, 32, 2, 2, 0, 3, true, false, false, false, false, false, false, false, "6283cad0aa3f5878eb4ca1a681ac163c74acbff8ab1ce8f9c860a0bd8dfad791"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "58a83c14167e2d99c981fee879a6742202cd0a672e9b825136929cba1b424a89"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 200472, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "13319460dafc010ad08cdf147d87de6c0fdc585a00800a775a30bcc98625bce2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 218136, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "fb1ae4b1672e4d786e9bbdc9f3477532e46606f0d2a4524f551019ce7a1f6fe2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197840, 384, 2, 32, 2, 3, 0, 3, true, false, false, false, false, true, false, false, "23d0e9d0865a54c9d0a7405170aefebde14496bfe4323518c06654c111a0d691"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 191640, 384, 2, 32, 2, 2, 0, 3, true, false, false, false, false, true, false, false, "658d853df30215645b46137f09e52e20f1ee1d42ffddce6223b887f66818e36b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "29b45e9df78abc825d110a5d3f7bd79f6d4e21a48cb63328400b317770722d83"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "904975d284dd8ed7455396ebf3dad4a4a4ed5ef36a27a89972bfcbcafc986f47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "94ea5bc2219a24d4ed750bb64947d67bffa2daa9799dee20a01fb9bd93352b31"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, false, false, false, "3ba22dab67b54d6f102bab627dbf6294a8fb02bc8752e9f7a708d62cd3b3992b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 2, 2, 0, 1, true, false, false, false, false, false, false, false, "6d7b081a75c7de64c2782b3f435dd6fdb10cf51795731b6088d714329be8de4f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "c88862a4274f676d5d153c548e63cac5bcdbf21be95c5489d4b08db987e55f78"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "8ab3b75baf18781dc54f8e66143a23d78849c5be4604768f8949da7b9bef1551"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "de1a4c7a1d7ff5053db167d38a6cf0ed3d8f72866ad5058fe0fa50f1f32fdd17"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197824, 384, 2, 32, 2, 3, 0, 1, true, false, false, false, false, true, false, false, "bc074ca9fc28d5212b8f1d177a31833304936c2f4ede4fa50bd2dceccec35082"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 2, 2, 0, 1, true, false, false, false, false, true, false, false, "4bb944eff7f1e9dda7eeb2fc39551d14a6934195fb277af37cb0698d3e1b5354"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214320, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "91867a02f1c4c7226008e7deb6c49d4255c83d80edddab3f83ad632526568dd8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214144, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "efaf5934281d7ddbdb9157a49c0b29c885ce490ca91e24ab0f5f6b280cd43240"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 170336, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "57809da34a1a381ef222455799ffb0b4f8b10d8fc045d65ddfd52e8ca8901cf6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 166064, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "1a86a0d1a4df4e537b756ebee32e88253f2eaeb4bb4f499f6221257a009d40e6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191840, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "c925b941c5f641b4156da9fa79899b6ab1c48855120b4e1d4f56b5f02c5b678f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183472, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "a8f03758c94155c83315c2692456c6b6ebc59d113aea1c535ec657330813431a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 197968, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, false, false, false, "f5bb92f1360a1fe13f33a92ccd0a5f822a05183b6605a1d287f682f06865e005"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 197792, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, false, false, false, "2867ca4b646f4d7ad9cb083da7482316313674700f2cfbcccfce00a8b8a0e04b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 159584, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, false, false, false, "959b3e90a38da42ad810bcb9605f842b0e92f545b680b8e8d1251b7c66eddb9e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 157360, 512, 2, 32, 2, 2, 0, 0, true, false, false, false, false, false, false, false, "6ab9d816bf43fb14dd71000984920c536d6eaf45f943d1047ccf31842d30489f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "0a1bc4ea55533551859f455535d219aead2222b767f47ad1773447d188fc1f7a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 128, 128, 128, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "785696357544e876eb8248325ccdff5b2380ab174fd1f22780b64d9d2b60bd5c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 171456, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "61c22af9e7b596cfbbc620e83475ebce1596c5c007a23cae2fd0ff697ccdba5d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 167184, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "0147e75d0ce867ffe25c90077cfa34bcfde4224868d8a562a057c74a753497fa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 193216, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "4dddbea02553969760700184ee5804f6d19f5b9b532542d7708cb857b035f015"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 32, 128, 32, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 184848, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "3219c32b49eb3fc0dbfdd624dd2f8e28d746aaaaf7910618b2fb8dddb3e85f09"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 197984, 384, 2, 32, 2, 3, 1, 0, true, false, false, false, false, true, false, false, "b940893ca4154a61a8066b1e5cebc224059e2c4d7a404595f2419ceca8dd0a8c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 197808, 384, 2, 32, 2, 3, 0, 0, true, false, false, false, false, true, false, false, "b52d2115f5930e2c9bfcf3edde61957a371bc588d62309d627d86637dc4f7e3d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 160576, 512, 2, 32, 2, 2, 1, 0, true, false, false, false, false, true, false, false, "4583776f8e43a0e8d2d3e138f197ed5f9c9b14f5c856df16e7c38c13a5937431"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 320, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk320HV256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 158352, 384, 2, 32, 2, 2, 0, 0, true, false, false, false, false, true, false, false, "64b68782cc1d67837e851dcf1d0b24007fb94f66d5e57df0f6a5825e7023b371"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 208056, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "253d9f81263cc35de0a39116682f4eecbe521294aade82cea8527b55a7f475df"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 208200, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "1b41bea58b4aac37b386c28231f3da97b4c4edde2a3c29d31d5e26f97d335fa8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "685d80e981dc2aefb4a676df04fdad0251ab162c5f1ee4dd58fd0f2a42a19f8b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 195400, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "c17237abd70b41f2f4ce32776b2cc0785d06d6d9ebeb74c3b9d252b022078081"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 209176, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "cecee38ca5a6c8a2f8279f3d8f4f36adadc2d354f9bf7e5c026a40b7af8f95ea"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 209320, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "91dd77658d62faae9301e55f4a83227ae0e1aee4c26c2f34d29e1059ab0d265f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 196248, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "42ef2e99f4966e10b0b7520c3ea727bae1b27c2545273153ba839cf6e46547c8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 196392, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "f0e016076d228b1ff8bcda72867f84c8e07e981776579a66cc19be572a17c5a5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "a9590825366ebb492bd3bab474a266dd4fa8fc976b341a5425aa14b33f73b48f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "808733d5e9f7a9779f5a5a1718b1d47da2e81823010d96821a61a979708aaaf8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "300d2a961927aa209d8bcc5d31bf7be686909cfe49e899b094a0bbf9412bdca1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "f2d8800ad2b5937085639b92f0458b3bc6095d71161fe04b9141a70b4a16b0f4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "695f12b69add29dcfd3ff111f1c2683b2f882372b218a9b27f4394edfb31f697"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "f989461af2abffdc917bcc33583f3ff1cfcc54a1b5bebeaae07d13ed8b68cec0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "0b012b9e26726ad71325c8915ef44bd8caa4b58cd08407f9ee8cb88fc28264ae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "18b5f2a176af8a871d894258b5ab7436037d2e3fc5c17124561d774a2f210a36"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "e469a42d50f1f7eb083df185a98173a4b968b7a6c34c398581ca20c0dfeea03c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "bdd784c2488be512b75699bc1a083595efc3650f083cedcd273c05e2cabcb9d3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 178528, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "93e7051744144eacb55f1d1da46e0fb5ba95ed1d68411ed97ce1f5743379114c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "95447498b03d8cbdebbd79b5de3b6252abecdbb4ad0d9b25121159ff10f70aa4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 176624, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "35e0896c752ad79923712161bc49bd390efee94b3a90417fed6b392d7070448e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "3e377761ef8ee98e37e682e66fb30b2439f8e9ffdc6b02ae5b9bddfc0f902614"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "e7dbb7e605b8294e4d6e5f419da86b323e94414361fa3a60dca510994d5809a1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "76db2e1f12024dfcd4e21f5e38c3751a946e2b4eb3c1162da73c01eabdd81d08"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163680, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "f93cb4d470a209352f4e53b5f6bb607bec3c3d05ba9e53d3fffb0903b66613d4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "7de263701c3704595264302867231a1c99556a4b047b6fa4ca4bb948198edae1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 162800, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "c7286affe18a8980770685a0a8031428d117d09acc16706b1150e2698b359253"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "de045f1e548e60096764a3895f5f498d9aff1c8f62690e893cfc270467005c9e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 179648, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "cc5e22689c35f88f03da0943f3e5181632d35c7695ec47e16fe566d6b3fe28ab"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "01846194d586893c213e2bfeb150520376dc8b3642d8652f3688ca6163b1ccbc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "e937631abb194b6e7847cedea76c038298245abfb3f31b0f9cf32356c01345f5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "87bbae3d7ee89f47ca7d2e236030601e2d10804dd547dfadd4d214c1ee5d6952"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "9efe7980e66a0ecca096e051eaced5043a204fa1f96b486e92f7f67562a2895f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "74223307aa0fee599df5bb8f81ee704dfc5acf55b9983b933e9d668723e5158c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 164672, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "24069ac243616c07526cf0e0d75fbea47bcdc7d70064d6a2f81cb78c35933c5e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "4161d66b7b4944155cbf47b9547ca87b6c882c94b51beda70df021b87a188910"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163792, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "09fa882980cc1a0aef227817d34205ee9f529a1463ae08a781cde29cf302b6b3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "b03eb82a109f7afea6f4377f8b2fa8e9cfd1be04b6179dda8d81796b33997780"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 213160, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "b44bb1c31a3b8c6253e1467329375051eda605c7b63739002eaf7e8a44019066"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 200488, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "a46626095621dfcd50da95e310f6bb056efcafb7fc1163b9a2432e3939040f6e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "72d60f61811efc5d802b0d9a12326fd6c2d73894ecc721b672108dc4163fa436"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "8f6a3a6c064d6dccebeef223e3ec0991bf523d37826e8ba4d34aa2e2238aeb46"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 183632, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "d0ac9b1259300b710d67c4dbe49e753b3c034fa04ba74acef0a11d2d6f697ffc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "61c8e01b585e7d1414855bedca44d346ffe5a0a236e0007a2b35b88dc2489ca4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 168912, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "5da5a48975fec8176c272652ec63541b4d835baca0e24051f182206b44d8f6b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 128, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta128PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "f0c739bc006b357c24bb85be9a7de1ea195c0d99ad492f1586a4a2bf96b0f00a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 207544, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "8b6d8c94727c2cc67e81848fcf1458b5a05a7598106d6bbb715851895dd20600"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 207688, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "d4e07315350e1d8fb3bf937effde85b623fd2f057a9672be424a8fff3d94eb64"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 194744, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "a637e46ebb8422dd913344998fbff3a5b844001e7d520a7c20cf2ed10ec17152"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 194888, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "9412b654e6ea7230641f74df638128c537c9efc06ced997314479751e8e52785"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 208664, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "9469e3b41352c65fc6231c9bd4584e51cac0d4bac67550a0307233b374761bd1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 208808, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "d2b8820f20ff463dbf79a6a924d2b7dbf9ee2600a5da8efb116b03bcc7191e4f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 195736, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "8c84b955a2ccfb946dd9c9099c3f627aa5d65d7599090e7215fdd00f6c0b6566"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 195880, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "d05ca921ed73999c7a65f7a53dd0a6c6ff1402b4a0c5d204b629b1556de47c46"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 207448, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, false, false, false, "dc2e2048b5900b166a44442af788e7d8e9a353d82c351966955fefb778286681"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "f653b011643efd8e1de4dbf59da3c4eb3522d21cd9886e8dc358347e4c0e9576"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 207464, 384, 2, 32, 1, 3, 0, 2, true, false, false, true, false, true, false, false, "4e47867377db160e8df2484f57568282035d2293292d3727859c63ad699051ca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "87576f4afa387cc43009a3efdc383d4b1337fb1ff8219cce45332f8face68f1f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "ad69bd14847963e62ce12b5b6336bf84995fc03355d58f18033b2c96d2f2915e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "ea2c6581d3a004ca0a020c4aa158cd70074ff33e5c66ceabb6baa549b0f5e1ec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "a3a2d00c55877b48dbc78e320d1c4988ef4ba36ac0d171a60ecf49d2d5513637"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "02fe0929bf7f93cc711e580a8fa072f02ea85762e70e6d1fb51c5191d133f801"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "65b6d34386084353497dd8dd2053436164c0e43e907fb7d8dc6385e406a1f50b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "7ff0928a573a36a8cc37f48f6d3586bea59a366624a7d5c95c23ba5dcf2e94b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "364731237330efb5049b57201b97d8b5bfc460baa14629d14c9faa2202b8a467"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "ea31f5b6f635967b1b3c0d166f2a52ba05ae3fafb9682d05ccc86f5b8c8f9c1e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 178528, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "d69b7f419f30f0259421f20f7d76198741461fcfbceef5b24230dc47b3d5dabc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "fdba3f0a026fbbb133f252418e697d6b0ea0b17182eb9f36cd4606b42b81f49c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 176624, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "a58868166799122f061cf76bc6f5a2b1098d1fcbe8234deb25c6679fbcb0d389"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "d67af72adddebf7ed052d2e348875e20c9b7bd8e2bec5ca70409a0e5247e4707"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 207608, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, false, false, false, "0f9a64cda22bded9ae7ecfd7395401876798d7ee26e331c564b1a8512e55c10b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "8842dd7d2bce6d10ded7bf89581958e4bf54eccbe9c8481b01b3ad3ad28488b8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128Static2CtaKeepsAbForGen", 207432, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, false, false, false, "c8ab2923da8640e99e9436b699cea800fb82b2289b9f3e09a16b1d1d77653628"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "387196f86f383819005b69e7fbdc173247ab621ef1a2e878b6d4c3b93db24c97"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163680, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "7213eeacb3bf55ae9fdd34ad8c0bc1671607eca72f7c1a67f4c103d383573f15"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "37a66b07b4377a3e607c687e85ab2dd7080bb221c6e7ad15b29368d1c1c1e2af"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 162800, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "65748edeeb7df2c1587837a4e33bfa03da353d5e2ff1c24728b88e274cae9786"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "94117472950e3eaf75fc955f4ebced80893bace960f1db11ac0c17a861efb2b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 179648, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "85c8afedbbff0faf82986bf4a792969a27a64d0e5b349cae6f810483754a6e7b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "a92ae7d7364a103d48d3d9b2dab7cd789f66da4f27df1e1adb3f5ccc18df9cac"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "d94c18e396180523ad7e450a8c56f3c2dedf347267b3df3cfa9b57c5235e9e5b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "cc33fb706d7688fa9efe475facf8b9069a9f94ebb448f9e2481cbd830de28577"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Persistent2CtaKeepsAbForGen", 207624, 384, 2, 32, 1, 3, 1, 0, true, false, false, true, false, true, false, false, "8c435f2e1077d21139541bcd89f5fc21d0859eaed2d6cd9748625cc2ff33cbcf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "044b3930faccb8ae465267b4f3f376554c480a342c4a840e5a70c4a991de9d99"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128Static2CtaKeepsAbForGen", 207448, 384, 2, 32, 1, 3, 0, 0, true, false, false, true, false, true, false, false, "74eec34b2cfa5fda6b6f61258c08f58b50ab438092eb1e6f3342954d8f2e4929"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "f82a0e91d65ca46161cabb4a2a358f8bbd58245194ff2409b68481a4531b9a0b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 164672, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "61514affd4af5593d66f66250d1afaa9e4541f942fbc4b907b6227f50a9966d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "8ad76878e5a047921b5a6a8e1921bd8c5fe190616ac54cb3a6c434023187cff0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163792, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "7ee3eed8dbdc88162cc43a001986fae9a2dbdd32e0a6b942efa0c9bde9734e21"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "07f6c4fc313bdd6abd78fd9dd41df23586ef3dfbd32b3f578ed90c5e077e998d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 212648, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "d5ca49cf729ff3f7d9927ff43adb981a0574dacf8135f341297103b9a1780c18"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 199976, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "18d3131966c7363a8c82e11543ca3c36a3dc2d456aecb3cdb8289216fdbc664c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvGmemSepVarSeqQ64Kv128Static2CtaKeepsAbForGen", 212824, 512, 2, 1, 1, 3, 0, 2, true, false, false, true, true, false, false, false, "71a22d87d7ff3e54b48a511564c4375690d5dd44a8da82beae1353614d198d37"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "b3618b512d33369d1cf497a71549082b5ce84c2ae16ecb24be701bb56cad242b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "5730163b2fe6f61261e15c037113e96a293a651f6099d81da2105a1bb65f5841"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 183632, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "6718564905010badb21eb3dc9992a896ef42c9392ae998225870e12324d1d5e2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "df85af078a0efd6bc4b9a2c98f0e2d7628c338998880b71368fe6e7a48fa72c6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Persistent2CtaKeepsAbForGen", 212984, 512, 2, 1, 1, 3, 1, 0, true, false, false, true, true, false, false, false, "b0ae60bdeeeff9b27d22435cf11e4f734e53f18e7f6fd0e3a4459595a7de02cb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ64Kv128Static2CtaKeepsAbForGen", 212808, 512, 2, 1, 1, 3, 0, 0, true, false, false, true, true, false, false, false, "fee6e144f186304c89878c315d6e5d5555fa78e0f892448967570a79815e6619"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 168912, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "6c01a40232ffb907cde618a5ca362edce2e65d2b77993cb619a37e50c6fca3f8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 256, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512HVPerCta256PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "e014015c41a6e774d0a227b178c4a376f835a9462cc9089418b6933acf70a644"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 207288, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "87333e7e8b1f2f537efa7cd74a27a0c12953f71412b9822f0228c59b25ed788e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ16Kv64StaticSwapsAbForGen", 207432, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "a55b903f8820f3f46079c0cca5900117b58caa4fce77ed04a6d6590e522320a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 194488, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "7ad59d3d49b50bd5848f50b650a7af6f59e089d8e2149bdeab83b743456d3f41"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqQ8Kv64StaticSwapsAbForGen", 194632, 512, 2, 32, 1, 2, 0, 3, true, false, false, false, false, false, false, false, "c62e9d0f0c968f5c0a4f7b616ef6fe802d5ccd99c9c1e30beb2a830506c6e8b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 208408, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "2b18c388fb6cd94c85a01692872f2478fa001adf01479cac47bbb84871c2df95"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 208552, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "1cdeb4bd386c121118509f11acc654d618ab7de20b33fcd0d2942f78ec459bd8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 195480, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "0396e638700fb1ae24c732fe5711740e25dfc0a52f2d2aff44c7e4f6f0943091"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 195624, 384, 2, 32, 1, 2, 0, 3, true, false, false, false, false, true, false, false, "3a5bcb06f5d85467eeea8e654e87a8140b86f3214fce9404a0550bb417d69d94"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, false, false, false, "3fcf8a94a4e7dbecd52f0c3f213f2a30ad9c022adeda597275deaf363474972b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvGmemSepVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 2, true, false, false, false, false, true, false, false, "2f00a8ee8ba26ab48c005061bad497996db0342d7604f0cbea5f20eb1fe4534b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "0b19c75d432a57671e338079137e3ff3b37e4dca1c0533fda16e8604e399beaa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "df570dbb71a562c3ef56f7b9b5b523532121df09138a988fb9e0821392730f09"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "3bce083074e539c82b257f1596c08d675678552847d69d0d527729b672f89630"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 1, true, false, false, false, false, false, false, false, "96df2541d8406fb3869b49964beaae3c15528e9a6856d7d5adbe522506667bda"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "baf201246a4114bca8f653d5ee8881fb86982fcaca120be47aa897fb5de82fbb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "7f8f7a8a05a418c22b4aa5a00f36c2b92ca8301bfa2c1490539b91629cdc342b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "a03518a25123a6cfdfd3e3f26ef5138b897b766c27874fe5eb7a22a1b4cb3826"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 1, true, false, false, false, false, true, false, false, "1166bde23dd277ca2a2430dd4c6d567a34f0de8615a40a070e79606ca8f137b6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128PersistentSwapsAbForGen", 178528, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "7c85d8eb73c4ee566026025483c6f685c18d90402a2fbd8ea60f660ae47b8c20"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv128StaticSwapsAbForGen", 174256, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "711591079234b474d508a192b68d941a325026297eaa9de1d0689b802abe2abd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64PersistentSwapsAbForGen", 176624, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "03fd666e42413cb5b7532a7fee335dd5dc6d35d8dc66fdb879efd4a522cb8011"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ16Kv64StaticSwapsAbForGen", 174400, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "9a5e203983c533ef34fcc61f9d4b5e7e7a7c60561e46517ab1871a8f513cb6d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128PersistentKeepsAbForGen", 214336, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, false, false, false, "37aa3b8571ba8ff8785976bc61aa08f87b70b24922bf56597722b347d4ab7c94"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ64Kv128StaticKeepsAbForGen", 214160, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, false, false, false, "2bfd694f2809be5737bad097392331289df27ed26c50975f2169be922c17e206"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128PersistentSwapsAbForGen", 163680, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "04aed5a0bdc07178c17b8de3b2dfa91ef2e7affa33cb596bbbbc968795299885"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 256, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv128StaticSwapsAbForGen", 161456, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "35c432a5722f74dff22ab63cfbcf5058ddd91f5b7c468683a08301e303963950"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64PersistentSwapsAbForGen", 162800, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, false, false, false, "dad3c914af39d8c6d168f444dea2ae2bad0f9c2475d3462e80db55c61bcbb473"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqQ8Kv64StaticSwapsAbForGen", 161600, 512, 2, 32, 1, 2, 0, 0, true, false, false, false, false, false, false, false, "449e1f70c84e6bd22e416bc02fbab50587742cf03395eca4e41b0a7ad599e3e6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 179648, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "0d742996bf8ef38b874bedae7babe08debbed75e2934a0b8dd17b6d9c5a7cde5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 175376, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "d6cb07979511935c10cb7a625cc71c4c40691fd4338a1069b5387a9eba03c538"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64PersistentSwapsAbForGen", 177744, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "2806cedc7990c064b10f01c7d797e3e0596ef7f431b18339d6dc4342b787c3f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 64, 16, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ16Kv64StaticSwapsAbForGen", 175520, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "3a396b8696fb56b91d43307080ef9fe70187262c3f032bbca7dfafc35319d107"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, false, false, false, false, true, false, false, "0b69327e1256a4efeabe85bff034a63ac2e062e6d2188073cde7ba1afd854948"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 64, 128, 64, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, false, false, false, false, true, false, false, "7f38159d0ff6749a0f53f22ecf47d6f2d39e560f2d391f9b3d12fbbc33fe6036"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 164672, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "3f25be40a562041e02738b977d25b91812ca692d83f87ddb547aab1f387a947e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 162448, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "64a24296461047af31ea5581d851742417aae42a4badef08c897e3954c2e4110"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64PersistentSwapsAbForGen", 163792, 512, 2, 32, 1, 2, 1, 0, true, false, false, false, false, true, false, false, "c15fd2f9670be2e4a293fe9636e90d20b13d6e27b41c87b8414e80b35d661820"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 64, 8, 64, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvDenseP32VarSeqSkipsSoftmaxQ8Kv64StaticSwapsAbForGen", 162592, 384, 2, 32, 1, 2, 0, 0, true, false, false, false, false, true, false, false, "2b343838dee75f146244d0c818d607fbdbe44f0ced1a5ba87ea03973684932cc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 212392, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "451ef8e5c1297d3d8f383bf7619ed4eed4550dc8c1246e8986234b8e5ea01a64"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 199720, 512, 2, 1, 1, 2, 0, 3, true, false, false, false, true, false, false, false, "fac4557f9e09a3c52c8894aa929e6ac7fb16a3d31a5c2dce2c3e26bb05d67777"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "2950b441d80b39043c4f1b896e3754738b0864f635a3f52f8a438725e40c4f4a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 1, true, false, false, false, true, false, false, false, "b377e38c7bbcbfb65d10d481797e6d02302a4ff13579af7ec5505115f4f8184b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128PersistentSwapsAbForGen", 183632, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "fd8cbc9abb15b15ea9658a65e1fad61b0c45caa5178ddf23f1fe4f3ca175dbcc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 16, 128, 16, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ16Kv128StaticSwapsAbForGen", 179360, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "4125909870d06128e503dcc9c47eb802b05f0d473184e87f2b78319d7bcad82a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128PersistentSwapsAbForGen", 168912, 512, 2, 1, 1, 2, 1, 0, true, false, false, false, true, false, false, false, "f42f8085c3c6d396926100b0ae23ee4fa92a98678bb456c07f88fd157d4ed9d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_BF16, 8, 128, 8, 128, 512, 576, 512, kSM_100f, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OBfloat16HQk576HV512PagedKvSparseP1VarSeqQ8Kv128StaticSwapsAbForGen", 166688, 512, 2, 1, 1, 2, 0, 0, true, false, false, false, true, false, false, false, "c6ba20499e331a681a98375407681b736922fc8331b405064d6078e3525bc2e5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "d420868c05d3fc47f6fb63fbc7c804b0e806116b6e780c8b79762d23bc84e6e0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "3da1760ba41f00358576b53b661e07767bde1b5245c5e5f26fa103beb330cafa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "75b861ad34a5b5b0df9f95bf3a43ed54c79ecca504a75326084dedb57c3b567a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "74bf83ba6e784b0a6832963b51fd4ccadaa5bbaea4fb70095501dd81b411a0fe"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "b347b793a6cd2bfc01e33791068915e9936a5aea2c33f89191b2bb7cf08b63ee"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d8337b628b96032b8e73e83fbf124ed14bac232ee0b58bc2b21032e8b5df6936"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "42ce18f8166c9603b844eb5c73c7c33892502822d0123d94416355d9b0a3bf3d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "71ad6c3fdf7ed4c5d33c906086e0fadc9fbf777b7fc291f0e13254ab42cfcc26"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "0db702df47407074c6216faa72b0f350198b9f4d984d40f2125423c96715fd4a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "96882b51f4e1ea238e59dc0da222f4e61365ab2858a532b82743670906839ce2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "5bd108d48316079234b6eead8c3983c51fc928693ebae13e40ca0dce388a862d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "1146262cd3e3b5f219cbde62ba0fca50a8d29422163a924ba859297c385deb27"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "85fc6043219a53f848ccf2a2ff29d466482b4e3230b4497307f382dd61e16504"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "e6d94ad0646f181b0d3b72617a9ed60948d3cf0b1382f2c7676c9c87f281cc26"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "74ddf75ce3cf1767a382feb8c005c97fc172bbe951172bf3f033958e119147c4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "c4a6c6a2dc2ac1d955ac63dc9dd7b5f6a9a251d28aa6de8547cb863e99b913b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "fdcc31d755a70791c33418a30ae9d10e7a793ca5fc1618212cb2eb1ce80d9aa2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "e6a88bd69f9f872e082dfb708254d37139cb487e1492c83796dd01d5cccf0954"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "61e971bd1940291349d8cdcad8bcaaa6aea8620211fb1f364a1b607fc0f5bad4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e0f2899dab2e5accb81e2b9b69eb7dce56478301d2c94f1f0ffa456564d14e94"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "2854852e6518fafd555406a80e07c803239f8fca6c5346fa70f7163d4c6cf034"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "f060e36701522a048cfba3901dfe60c6c94a6a0f478b9cc706e3ed515a8c06f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "9d1dc4952106032d24d21873bcb8b170830990e24e482fe89b53101bbee6a5fe"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "8f56a2f0aecbf9b7c243fca25ca4b60c880872f188b5b53950efb20795ce1a21"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "fdacf0a2f5a4b9407606e66edefb598ceb95e2600a784f31ac79eaf8233385f0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "5aab758d2f573c4bdd4d64edf40ef332ef36441ca1b68558d0982499efd0b300"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "615fc22cb4690a1f4f6589a64f0b10eafecb3dfadb95e561d6c332135102ea41"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "b9335eb771ad72fe72ba9a85f211097653584b4a19b2bbd5a5368bff0e33ace0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "8b268f352291d68003dc7044f1ca5a411677c3741ebbbe7b97bc0ceadbcea106"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "5746c5968e3bdd1621bdb8cd10c94ba23279c5a9cea0b82c682b833b0beffc1f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "d87073298a58ed1515e592908025fb4e02ed61f9c0e3f3b84a2d3d7b508ef8ec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "493e8f5d5680bb328052e1f0ee17ccfb92703f2852d433e88f1630e9770efd46"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "dcebfc7f580b5a8fbc3cea7ddb1dd3e0d202a2dcd4cfa3bfb2e11e02a47635c8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "8ad79330604eeb424ae786654aca94ec7041334e60b3d204dd5e4cc4ac113665"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c0c4ddfcbe570fc17f252743897543e067a05a74266735e5c67dfb4e7a8e9d9a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "cd0a39fcf800aae8c48cf67c27831f284d3652eb0226c2527f767a077f3cecf3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "92a8896f96d57422b31b52fb4e029c53c2c548d2accc1891d7932f845831f298"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "a773a2edbe50225ecdb6a1fac430d97c3ad9426a04bde1063d7437fb759874e3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "324de7af0fc403b5495ffbedecc01f41479ba6a8008ad693bc58b56b06c36aca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "2343b34a1c413c4308f35844c22da10e2f98376d3341fb1579970388caf4bc90"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "ce0f135154233d7cfc5d5d76ad36a90e160b2efe67e3795a4999633b51dc3f0d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "0a18e051dea90865f61cad41b7e198afc14eac004272d12ffd12fd91a14ebd34"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "2451d05cc885f2a2ca31c00f4700c4d7df469c3dd2a5f0c49e7a61f324cd39d1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "d5c8d8326cc732d4f6cb7445a760e5c5f42f703ed43775c3235e06b81192b112"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "97df21128eff7b3e9625288657060c00e9c101d40acc959e6becf44188e1f7ba"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "6acf21c3a03a5602de1bda4d81601d5482e4b83c50d243b78c0851e60d41c299"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "0d2c4608fadd14b2a7827d6c05f81529cf494c6d7a2c8cfb0302fbb4d892a6c4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "bab275f0d5a6357e610afaea71e8bdc83ce62818e238905ded173eced6579ad9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "68ab765734ea7512687c9b2536805185a25b07f1bf5234ce8a12bdb17848293c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "e1fbbefbcba35612f925e223e13b068c072c807d1b3ebae1384c0a7aa6f411f7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "9613571c55e321a6cfb6a15c308c01ca0a87427dd938a0f827de6cfd84658d12"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "2f93f23336175980526a6ebdb59e48448ab2bf439e428b5f5c23aa91d5e355ce"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "a7deffa269f2310146e1aaa44526f3f049158324016570458f129ee566472d47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "bb357b23d4b5abe94a8d73ef66820127fa3ebc1a87a5e564043bad094937b5b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "85b03d403a7e3d89c99d09693b488c9dcc404b376cfe07d01ea900786e5099ce"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "3ba4c846dd092d4577a88842d01fc8fd941251fb2f60bccd5379545c52da054b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "aa50e0ab4db43da68ff89d7d910c83af3687b747f9c3ebcdd5038a0af26b35ed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "e81b79c7917889272a180ece481871f1b8736d19cfc220507ee23d92385f3d77"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "981c064db64daeaac79704e3d474e9686c96ef7ee7e0f7f658fedf0e8ea6039d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "96cc9b27732daf9e67f61a4f70b3f0c9a778e514c03559a747f4511f0d3c3d4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "4042979aee8ce67a1fd984a23aa1b3148ae6aec25a49209d0887109b4cd3b3d4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "4b956b96e1c697e9e4fdc831550cd3450a7c17c32e5bce224b06950ac026a043"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "f976ec96b0324e1a146896c6340b4e0cc101afa0d35b68a24ec9879cffc931fb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "16ef8c02a49aacfb2764b1081ad0c2963120ef217d71f6943299a5b0212f0913"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "d6fa054d52fb3d9784b348d10e22e64a43d043da665f68104eac09a1f5058e39"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "738fdb17bc5a14fc5d1bca9634cc7ff4ee7e686406d5fea9801e1f3926a0493c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "44ebdd59d15e0fdc19d57473353bcaa5b04dee7ec66aedf8a7ed524124807941"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "d944c0fffcf7aaf3b3731d2db513bc3a891776c5ce42c33016c0dcd3a6c76075"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "073d30baeedff98181a5e21781968a835e4f3b346a72edd8e4b78a8bf4e15a2d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "5fcb9613d872b64e8998cbf33d313cf92ef8e648ac7e71ecfdc366ee99044390"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "fae36079373412b9f790556e9eb7e7cada035a97f7475a2e0e78c0ea555255af"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "75b9c83715abda2c0937a37250b9e35f93162b41e17c753b12332e4df1a9be15"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "d2047e83f9368ba7a517fa993c4b8f8be99500e92b41d404387555d8c9b6ed28"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "42e55d14e11fd28e7272b86c8700a21aae71788bc4e4bf462f514e193775ecc8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "7e247ddbf50f77c0ae7e23e3d71defa563bea13064d2a5175130856b17a14dac"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "5c5d40ef9cfaae96c55e4a70fccf4b82b6c5b49e7a67c75964cb3b80cc9707e2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "db4d0219138d33dc97316f863b5619b3eca79248b67ece67114a51fcc0386677"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "76d380c64f56ea6760550ee74cab9f1bf078d9c8bc08dfa8b8fe08ab80d1e6fc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "df2270840f7c3a8a3c990a80308f4582b0d54042b9ef0dca7a17ca36a709f86c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "f4ad6cf341bdcadac6f19cf274c36a8f9fecf42ede5751f090159028804bac7c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "7d8e25d855ae2791e25b3b5390db0067352568c210f1dcc01e620fa8fb4a7aac"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "3e4034c6f66e18a5e9844887c99920e77b15a6c968e42506876ac705da00c6b8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "9cd2bc24d974011d2e31bb0af8761d7d84352c219f92f6dfdb2558937619a54a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "d63753666ce9f25ea5461a30da4448974f83ecd9c715d5dae9534cd7b59c803e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "d3290c988b06bdd90f4aea6dad8eeacd22f051a3c8ea1dbeeb7e0e8a7213dba5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "e266df8b00f1aaa1d08a5f699a9dd2c7d49e9c9dccef61a974ee1a540fce7431"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "17af0193ac35ca9cf81d76f0a1422822f772aa721cf67482cc00cd306d348686"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "f0f1f8e2f1b09dda5a68d21a8ea34491f38e583e13e5a4a45f2bcb6812112524"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "3a2760c30c34f0788d2e1b3a201b66fc35ab4ce2da4c07d2bd58ea03ed4d2905"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "eeaf88f03fda412a4f086fff5b60123158576e793174480edb7747015bdf8b1f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "41343df458669e14a6b2533ea13989ada4b65c635a908611c75b8a06a37a103e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "8fb8b94110dddc9448bd6c77a09fc2b42767198225db6d4b63f0165c2bcf4207"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "d17e992746923f2a2ebe624d3bd99450bee603b01a88af2b0cef9aa520b09d67"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "3748f8bcdd0f25f196a9fcf537b80c81c23428b16460f4c2bbc8964a67dc8b35"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "5700f2ed07fb7a3f06c055cc51c91f15b959df30508870dd717552320f5296fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "d3eca6508531b03b0316d42b0674b9c8f336549a54dfa9e258baa19fe4e1b592"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "1e656a53d2b1b6b8c462dd1446cb5728c64aa03acaa13792ca742bb570a618c5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "07d0d29f6826dec68d51071fe00e00b83b8eba5372bfcaed629013064b858a5c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "2cb2f731735f7a92aef4a6955af8c4e6f7cc2a6170fad3b637300093501725f7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "13654a9c16c5a8312d12186eebde7178c55eec516387171625435fd0ac893a88"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "a77e62a071b9a0ef1a7802a0e8cee18a064ea462b27c44f394b9b31b38fd31a3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "6ba7fbaaf4acfd5f49b9127b23d3c99f779d8692936dd4c832542bf916e2612a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "12544a1ef07edc1280ab4ae8771340e8c0d4daafda599d17ca1fa2ef7b84a728"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "b08d77dd3ab1349396b56da40bf81a148abd5e5aa116cedd1a716bc3c9927c50"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "dc0e46aadac4deba845dac1d511c90fbf523a6f028504d6076f4228f7c17d165"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "9d09d583e753440ba5e572869e1318b38ba3df800a2190753d6104fd487470f5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "33a51c0e074bdb076b3e8437a800232b45fc44eb8ab85d2a0d82e9ea67042763"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "41c8d151eeb930ea5adb951e645c8cfcc78104bc4a1fd94ac0857bd07e93d949"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "50a03013ff6b030479218764ee1cdb10686c82594a8039a91bcb8d351d977372"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "7ad9db05bb43e833b88ff34a18fce98a498054e3694438c62ecc2745821eb6e1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "8a9703b113e2100ea24107ecac4e9a915ab341ec519815ecdeaa57c1338dab2c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "bc6d3d0d32c48cc78bdb602118965ff9108472ce0e17a1ae98cc35a6514a8b59"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "5c8e864eed6e406af06114bb0cc3049157d250cb02f9838ce22bd56b8cee2ae3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "4789ef8946534d19701cc1d45b47cd301a5a37876fea19d4ee735f10117f037c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "799c52d76c5a4371d58ed0bd0aeea060786d56f3bbc655f03dc1a6217c8e6388"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d4cb6080baa0b7a636636463697f3e5c2ba8e45469c9981511ba45851dddbc33"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "34164a5f9969da69ae638d8f5d1e3e5fbd6e3edceeaf865e5d07c2d858b6d561"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "93fc41b982490a1fcf3067d486d265452e747c873c9113b7b8cdef6494f6e524"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "b04782a5c51a7212060a7383a55e68ef3104a0d1d4d93700ac5d107218cd8c96"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "f5e59d2807d43a134007f25d1b46ec12e61dd340b8bc25c176e456c71ed82e86"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "aa69d60fcbb14e4702750040409d4c6793861700e4d7241eb62eb155e26c358d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "f308302b9ef5577b2effdd062e13dc8955dc2c58e0b07f97251e5cab1a153a0a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "9eaa26f8620d67ea7e5dfba78d30d4e3d4ace895235ea40c117566083339509a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "67b8f735030f2d30d0201b1fb4d878542052ff2299f58ca1abc76e9373400d90"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "518f53d7f12b0bbb86c96c50af7579c8c2bc835b2eb0ec2495356044803c9520"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "60f4727cdce77ff824e6ef1e2227fed3d58f09b76792f15b238a104f788065e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "3eea5351d30ea48d1cd77fbb60bb46bb4f7a6ad095c505e265e3e276589c8a9f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "151d4226505b1b13a49553aee45947cf6ed092bd7d169f7c11f946fe44fc548e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "12c9367128eda93cfb7ae6cf68eb35d9a143d5ade811e42f9e07b07be2366bbf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "eb801d8130113ef30b14d3e93f5e5f005e05d8d9ae679238539ec53541d48735"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "633d05abd3269981817621595f0991919e96af39e06cf65e0d45b4c59e70887f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "21c9a3f40773e585c1f56df291d29e8fa936c19f3072194138594ee71bfd5acc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "6058922558239bbba2d789c5305ac89bc6a4be276cdda103eef7e83d00290e7b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "2f0da7359ff68affcd646e183df2d3d85a57e1d60b21c8b0a3934d676405afd3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "efb77c478f54cf75f59ee19288547594318bf48d1e706291a97c6de7e9fbf4f6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "cc2b42ef3594a3153f26d44dd22ddc42a0c78825ba096a413a516fbdfa19136d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "a1298aac6ec546874c82610922e2eb191eee96021680bdf2bd9f4a44eaf37ed2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "d68e7535966423b25b1ff4c6d1db1eeeb257630f0db455bcd28b18fbb6371371"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c08c33b22659c786db571314244e0512392fd87611520ebb79e30bf54f21653d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "951e67123c3b6eafe3e6f1cd1bcd9b5841c4f9a120617c33d9e1aa52398ec3fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "5fc5de3f7ddd5547b179b80c1fcfee51ffa10c198469339d432d5f5a55022893"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "e59e20f8310cf79ab05f07ccb3db2b558fc1c7fdbfa542a3fae233bf0631b5d2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d6e4d74bdace8d8a2692f5a5445c96414ea05736b94ad507a7c19797b12c3b1b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "f96f8f22a0085c39670d7a0e742928ee673684ee656e43cff1eb784480a58d4d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "4ffcfdb91c212c2dc2dd33cc27d0a79a52ac0bade2da2a1376f4d7b494c2d015"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "9f05f273046eb611dfda29a657d45d9c12a0d2b7868d96b060a56a0445581e78"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "c702702760f3eb28d5fa5cec9fb8f91dbe4035577fb35d6ed6223eb39e56bbc9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "6aa3a2bf06d8604a9ec69c1825bcdef0408beb81def094a1685cea072dbbf82d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "b512c0fb350f79f6ab408d104e37979b7c726e6cb06b6484717ce70a47e97434"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "3ddeb079d054dc9d3d2deb519141acc7c464db7557c2a1eca443f756c132b190"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "b3b7b4e77b68dfc8c5d99921cb7926feb4346c3f9397d05252b3533e1f0ede02"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "6bf52cb59971a533c139061450b1e2a4061e56ba5be354ea732fefd8531feb92"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "7facec4393bcab3f9ffde27964abc567611d8fac91bd38968aa56bc2683101ca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "f5e1cd7aa596f6faa1230fff48679e23f6a8a3f69abd72ae4ac4830e1d002bbb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "0321e9487c3e6ad771cf298d52466b969bd0dba0dbcf651ed58aa6eec5960a31"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "94bace0a783612528e80c859bc900e1dad20248718bb28a3507488e815e9a749"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "aca27ac45d3f440774f7ee8cc2121bf3d4e6eb9c3ebba0d0e28e429f099252dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "024b9e0b90b0e3a74b3b22ba3a9a0962ea21b536b75096c7c45c594f93132f59"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "98fa889c0b970608a8104322d8b6916ce371e563352eba31bf3cebdde5c9bbad"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "48d569aa266b0e4e4567dc38d366188e5ae6771fb367d1d897037b47f8fbab14"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "088d25178dd66227dce538f699fa945f0eb6eab4ad76f23af29b264b5e563cd2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "526e12badc1eea9ff1e249222bd5523f42e4209d7cd118540438ed26f3735b9c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "654f74c65a5fa222df9e25beee3af962c0e97b1a6c8642fa2527d1e47d337c7e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "078070ca2427b6bef1ec28e83818b557592514cd2db845c4f1f2622e790b9e0e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "d36162caa74c247e10116ac44383cbd8619019ca7baebe57a4bb1c71d998756b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "abf24251acb8167e60afc4a93df08a1d461837899d4fde6d56bed72ef219bd88"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "37027e2bb4079417ed46c7aa8f3ca716bb834a33ef523db042fabf4d727d3df9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "c329e5d49417e19358796012898f94f29d5f3218e8d45ca930a49530ec237c05"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "cd5deb114075d665ee810e3a7f07d92823cbecad20380e5b3b70b8a30f262b50"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "de9906aab389ee2c17708f828fac5325d38e8fca586ae0822996c2cbc9026b7b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "4479b9cd714fa3a3b5213ac7beff6edb92103f7c55800cf45d3410ddbe5539d2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "d5d808bcd4ddf78a37eb9a1303eef946a45cfb74a4bf5c128dca8615467395a2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "13a10d9858565bf2fb4fb702e9c481d35f04d31f259e09512bb03cb56f046f3f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "14d40f539b348671c365663ba0c4b33ef09c7bbb13eb8a4737a4dbca0d50437b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "1589bd7563a43366954be0d85db1b0b9dac14671c97f3f9988dfb223b0eb92d2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "ec94f083ee912a55ba8a2e9b097ced203031d658c0ac025a0b6e94360f794045"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "fe8190b6601bee3b652bb4ef88ccc90ae15b250e004c2f22aaeab487b6ff5e9c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "98661fec3189c5b879b53c86ef3db13639d02b2d9b37963b02369149fae6c10c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "985d3737b2eb273cc80f1162e5c778b189b34223c06a0cf034f621ca0ab7b059"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "625fabde906cac29466f7b87fb191e679c33c5d6d9ccb67c07b04205c3a8418d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "787b4d34db21b44ffbb080c3d640d07eb3213eb66e2831edd12aa6f35dd2c234"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "d0be75246935f0ba650b56667762783d138f478e14235b9174956beca8a4a86e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "806ee1d86dc41abe53628be985a1d567a701328a5d539c89d9aedc7e37637658"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "a3e05be48597e14e951604715cac0f683d03dbca52759874211246306d076e33"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "b8dabc710ee6af7c136851791f4cd404eca0a3310936284d20f3f44c8cd9f850"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "416b8cb4a1310dcd0ab2784162da11c2d339080b5c874c60373348d40a702640"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "81541014720c44e316cd499df252d710e7a4eaf988d673bebfd78fe07fecd7dc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "161710b72b9f456265d5c027d19c8252f42738b1c3bdfc89d075ab5ad322521f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "10dc26d3810944cd8993fd31e78d8b4548f267145ea33db3de7ff977e69ae968"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "67ee82a934bd73ec105a82db71aa66d0b8b7daf5ce8a2670866127277e69dd09"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "9b58518cfeae54dacd7421253483911a40f1ef08cf18421d62c250569dbff3a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "8efc06bce44fabb00a916ef6df7a9973a7f749886070841d8f7f96fcbdc7385d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "732e9bb090ab6d7d386309b2e1797eeda895c750c69c62be3f1324ca0c1137a2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "6e7b50d2e4a7c1d5ffcad437d630d64a537a303b0437e539f53ea965af009155"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "664876d0be1f04f906f6bba606ce57daf02539a6848063881a4075efc2f611d6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "fb38936defd7c3dd6c3d4a343c835645533b69a83038b6adc1f4a74811ac724c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "1c2d30b4c5d09e8187b1df20fb5df1d73d3b516a46c049417cbdcab6a7b758a6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "db0a5a4ac0e94bb7e635261260f0b637e2787730102cf0997a8146efcacb2805"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "426a9575075b3113eef7e4621c8410f267ddfb4195c6620a91f6440af9a8acb2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "45fb41b2aac83a249ec888488d910b9d0b6ceadb5ce6b6e2deb5c069d4d13ed2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "023110ac474a1a83ae30c133a41f46bd8fe59ea7bf5428a339066d3f17a36e0b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "023dfd178cc8cfdb8ac3500724f4b22a0a267cc74c36acab4aaee11ab662e690"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "b9123fef66852cc9b55867cb24358d668670def102ba4190c3ddf0bbd0143c7c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "2a37aabd6889d9329de8a3c706df74ed8f535d9355558ad4f7da7a47a44d4b9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "cd81a34f8151ce7b70fda33813661dd8893e963587ea9f0aa5c55027e7cd061e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "be2c1fba7993aa9bdcfe7b5c93dbff663e1a5ed78e3de02b4d673d5ab6408f0f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "b69f9f18b5c372399140d80d4002a108514c3a480b5a0e1cf75f73e9e684f7ba"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "b476601f266e873bf3f38a336cbb40c682eb45ba59a4d57606f1cf0733b790cb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "0ef6f3a6e38e5693cc8d6b88210ef9cc39af91eedd137807321366e35b42838c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "6f0299b8a9b936c5cd9a4df86efe0939ecf5c18e982a3b2aea83ae898e91f538"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f02ce075dc0a633673617510fd4a6976cbfed513bccb5a5b32ec3070ece41148"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "aba66888a19658ffe1221b7f9593b27c09b698c0ba9a2ae3ba61e3286cd0f27d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9c767d128d261c036b592d3e00ad6e416239b8842482e69895a7f0fc51903c72"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "b762f5cd75447ed40188e7b462606d5a87e78ff5ca22e9b69397b2e134654e42"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "09ef4a59ab0081ffb1599f1c3688cd8d2cd045970a8af9ad8a817f6faed6d3d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "6a2854fea3c88cb6e8dd4fe915d702baa2d8365c71d0ab806bb061e4c7dedb66"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "877243b6cfc679a29db8a23ef6d8a43ca2e4710ebe7fe39d6828a585f29b8180"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "43a35c6e669d3443efc5c8733a2897f1eafe3f81f664d84d14b64c5345ab7555"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "6a62c40cb63c840c067263f9e5ce683149c07db0223f7b0fb534f00295903a69"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "7eec7d333bf3d3cdce5ab6420b53ca69eb8f8f36ba930de1e2c4f137b231c773"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "83f9fad765519a43ade1290c4db8bcf220459d8765179f410c4d7f530a97504e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "c07e7d07e6e39a5947b9940bc77f137d12b20aa216de8dfc6aa9273b48d79cec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "6dc89e383dbf3c072428c1295e343a4f402bbe9603ae89eb91d9c9f0a3f62107"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "219c0e555dbe1f7ba49348b4c9d5525b45d8b427cdc395739bc26e7b260cc39b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "8ff19065243b610b8ee19af76693a536f1d853adf4cbf9249e73e2c48d454a66"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "a46490ffe924e5f5e1e57f73777d8086f9fb43ea1337fc3d4feb02d59f6faf20"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "ff4faa08d760317a231fd6655fc51ee9fe0e030782e32104cd6a7d9b571478bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "51d321c059282e5d8af89998d13b23463b29e1142af540b346cafa3d4a9d782f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "7899459fcbb13d441064fb90b177dba5e7acde8fc6d9639543cc95da62dc871f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "af07db03af4513a9f5079157de06c2bdfc8cf623151d1d2b6cb699ddcecd1e84"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "dbfd5887e447b89013d43ce232edc46c50c64b695a4f9a2877b2cfa163a35eae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "0f7a34bafe351512664a655cf03088873fdda03a987fae542384cd419b6b1b53"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "da3f168003d8975370709515fddd2e2ac6f01d0f7032c8d058ea7e2757cf0bb1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "94108dbc2f6be81fd905c9aa621b5eecb4d61edf4cf74e4431fd731f57b4ee5a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "829534316e13bf92a1f2c4f177980804f002a992b218d1a8b2678b10281a464d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "1dd5c692de203d89215fc5acfa81dabfec19111134e862cdcee6ffe947f45a4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "93f9ce2d751d8ccf25afe6900775ac44b81d1c40e11014d17ecc1621a7cb5745"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "1b9552b6fd37ff87fe510e0cf569b84f6ce6ddf46bd92c58dd077cd4c0113ca2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "796b9b71bbe865cbefe3eaa7444b7a1e9b4d201ca1f1e3e199397abf89301ab0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "5a30dd1b6c1a8e6700d34aa1f5eb808f10f77430b552eb6b080f0a8d4b100b9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "c132fe898d522695e7f3f43550c5cdaea9041180e76f310967cb478b2baab0aa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "f432f06c996c6ade47d92991353431c597879462d79ec56ff8c69c7513fbb61a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "1c7affae35502309083f3455e371153a9bbcbc4e3ceb120e304540b05ec5b892"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "cbfa1c85cf44f92992c40741173d03303c695069f5be21235a695b2dc508475c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "1db1490fa6736b94417f72e031e71b8c1aa2cbd3ace2e29964cc80fa7a5a4eaf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "4bec0f16247030a1b4065547207e443edefe300dc46e97e57ffeecf728bae97c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d9f7577a66a1e03219cea9a61214e93a5bc8efd410126f16e9a6c5f9da192e46"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "ea3cde40b7ec466a38f2fee53300c135c75e4965823306bf3b81c72a36c08d6f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "66e13bb6851bd06619657d86f4972cc722cda13e3f230ccee95c65969a511a08"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "205fe6e438e208ae1b36969515784235691f506949366faf3318577274b3628e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "086343347c33fb74253c0e11d310ea5febfa2df8a7e5cb6edf0e3d150948fb51"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "5e7bc84109be14b01993446e0c76edb51dda661e630ea457f687b4e67ecdd6dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "1ab845fdfdc961b4f1c9c90e015408f595209bf1f07ff6826641347642b955b2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "3a587c55c2395625d140a27aeee63cec9b9046c67b56d4bf144ab01bd362a306"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "0633298ecc62246f6c55b449f4460fc281b184ac9893b3b02631fe77d953e447"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "8644f4f12658aed2b3282dbf7e14ece221b4871291e07028d6ce80ef0318de81"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "282dc47623dab6a353e8c2df22f84d64e0e248d3f8556383e3a21f6baa2bec3b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "30231922a1ae8162289cecc2e6a34b3a13d7b9ab1b930a00bf598e453b00560a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "cdeff86b3d306949bd33d5ae79991f562a7e6e1a486f78741521f2d9e50e41fb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "4ea525f611904e5808aed03a4227d3450ffdc76625ef4165037f91e2ab2c27f0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "0fc279a7d84b8b3898f14f8c99e70a34ae46bd13e4488e164d5b07e168526e16"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "ace4222a04ea7776c9c94164f9f0c44867564a24becbfae04b1859f92ba31b1f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "7784847f65e793038fb628c7c170acdf9a2e3e810d1e623838b2c474f4908ae8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "940f9e3d28804813cba161325417e519bc809cb7e6aed306f34e5381c48b0bca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "2d129bf020447d5aa8352dc0d8fe08207a126ea9884c90c841797b07ebc6c1c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "19858bad4c1bd7d2c93bf2e4ad67629efd467e3d37121866edb44540a5ae8b9d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "5aca871cb01a03a476b32f9cae9fd8860d982bf6812bf64da93607704011df8e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "4ffba8e10bc22305dcaf0a3e2ccd75c8b230bfdee4d740cb593c3410b89f9ca9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "f28fecf1f3bc0369c15563027eff4e3b4e6f13126a33c73e36431337fff7d4d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "5d6fd8db043a433bd3478c2c40acef94df217b5d9e717b26d2876a6c125bc370"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "9a6277b20ca88553d603667feafed0d73d8b9abf45e8220896dcaef9d1121a77"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "575a9740ec75b066e797f284430c7219de1900a53e4d45a47c03ba9dfe3f8d79"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "2818d00761cbae0336ce79e917c5024edde695ecbab129bbcdb67d188bcadbd5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "2fe4de143c8ffffe5ac4ef549fa5fb3bd464420d748284dca42bf199a671d1f2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "ac3a1aead36573b85e3acf07f141493f7acea40f177dc4d50a94c3d00d0390c7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "7478d563ac8f47f41e616df2c6be5d5b1384a375f6a286f6b29a7fdeed33582c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "9c2394d558694dab63caa6fb3f7750d0fe0cacaad49f83f6c3772df6e761bf19"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "657211c2cc50f88afcbb0befc1d6fc2647229d0f1910b2163dcad8d2440d42c1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "065975fd30e9659a1d932d3825fbf5a0878b9242842c4dea4b7c6ca78bf68da2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "010614dffdaa074771246e6e3af008c6963673a5cea86546d2e56b47136875f0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "ecc93572cba066b6f230a3710f37d5bda112ef021791d7accaeb09a9b9f37997"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "60bd031cb1ad3b48ab1cea452e7c487d513fd69189f8ca200ca300a7293b60f0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "52feabdecae4dc251b286229d3bef5c826f63b6a614b7366ff40e9e00de1d48f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "840980a6e344d2792f19086e890b3650bb0708fe9d688fd231727d454e2d24e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "57432fa7caba834798f5f107613a7fd8fd22a0f24accc0827cc11f3c9481b179"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "e1f70ff99e2307235bd58c74ed4009b93113d2666182ff380954a231a51b4913"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "a3639f2dea2032674a4252197b6b04446baeae5774e0931e896b2313c567a29f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "c0870c3a0afe1649894b0023ed1f77c8ec401d90474fbf061747159820e87217"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "f32e565d01bfc213930ec77ac4ba6f673e14b32e48d01e7eb6699887c636bfd0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "36aac4bdc6684767828ba6b7c68e16d4e8eb4983ca555edbd02b9c6c5403267d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "5e2e3ffec4eb73924e1a5ff6ed95c42636e7275db38350fab066fe43d88cd100"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "223e1e4f589f4815d1b62fbb1f72ed36548e8a237445839759cd52ca3b63a5fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "b3ac0866cbca39f20b50b59d02651aaeae7a6af3128318f963165c309570a069"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "d915e6cb608e68f31896ba15869a07f33c9160b43fcbc9a58b5d0a24f85b9e7a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "8709c54d063d6cddee9b445383f0e04264f2f2fc0dfc5a68d252289fdca95add"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "4d6d1ffadd15a6d2a8edb7c69156a99271c45b21a749eec3c657039559dc2941"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "f25f5d1c919d7565c301a2037745d7d7b6c14acf03a9013082d08cfe78aac5f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "31f3096efe8bcedbae30634b476f07d11534e82c8e062cbac88cd93a38590504"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "f4f43a406501d34b17f434cc5a46e4acc862395446bdcb1b0fdb1cb10614794d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "9d7227d968c3c9fe7a302a063fae2cfe61298af0db5067bdea82dff7f9d50bfc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "284027e01f5f7b38d5834f1758ba9089bb4863570627f13929ea64ccd0211b3d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "fd6d06a465e81f7e72313a747fb26319ccf704bac85ff10ff677992ff6002319"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "62f91be7b8f53e07f56cac861ec8dba6dc5ca12f074cd802c9f872caa7cabd78"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "d1c96f0eab55dab03bfc53b0210dd0c694e8f921ba43db56566fc4af564cd92f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "f5664709d7e7edce56267ddb6f18ea5390a9ba8e0c4aae8ba978b76f055b42f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "aaf0a81bb1666390851993d03845a90819446fdc35260fea33d8155b3329d15f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "cd5374ec2bb15c91f0c113ec854dfc3f2daba58b3719fcc855c10480addc857a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "528fa246eac152e3822936e3dc48ea3a100004fbed37c1e8332ebfe5d5465f3b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "b1c5e897d892c88a54e5ea173e042483b3ab1c65466ba75fe2b3236ccf62793e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "e238d1b9476938f49a3368b26e6251150e7357bafd07899b5048f6f297431983"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "5066a29af4f6a19a38885adaf7f877159441dce9dbd0467ea60251f7097310ae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E2M1, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE2m1H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "71aaefe79f0e4c34bc0313e226d9ab08fc92f2e6bad167913e5b759f79644106"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "fa9b0d9e97985c6513b34dec56754ebee3c0394e1299483af9d936bab5b96692"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "80ac47fecaf983219b452920fe992806025b236caadc0c84ac36274b13b8aa27"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "04dd982d3fc7e47bb0daaaaa37a168c03a0773f01429475b52569b0bdcc96ab3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "89bd3e0b31d9c76fc2fd9e668169aeec04868370fbffa2fdc48fbdab9ff728ca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9bb8d5e8e04d922742d57fe9e6ed1febbaaf906841e7c7cc1c1b46bdf33844d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "13b18d3e8e778462da08d76d34fa417368bde277a77b54994f082327530d2cfd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "47b476b43e83bc1211209acccaa025b59b8809dad1df07148dee48af2141706f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c74e061192b8ef67e400d2d7e9d84ac7a3f99c309c777ac7853cbfa476b36fae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "872952d9bb56f9a34e1734a7d7e74f0c570bd8fb62e1f503fa84ec58e0df5b0c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1e59edb9d00ec35354eb8d62870e5cf68c443694c33848123070362ad023b188"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "d3b54360c0b1f3ea50f3b11db16e3ddb77e036bccb383e8c2ee1bc50781d36f4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "b34b6a33f83a61104cd2a546242906a14e24453be1e5db1559e8771e4a9f2631"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "f086c3e75790568ebfaaac5a356b2d0655e42f5e49d43d64b08e4d55024450ce"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "820cc55804a6a1d1e354d10f7d1724cae4f17ff2b24f5fa3876947cb8d971418"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "aeb4a5d85ba576f9c9485340486010c9e375a8704951eaa80d33a1151f73ac87"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "08a76034e78daaeca5d97467c159011c782c826800069a0e7014133fdb4d5587"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "eb41a73207ef99745fe344b5f0873050febea4547c04ebb677aa331b2cdb4bc9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "4dbcbcb46af1b069f0bbaf132c3885983f52d629844ff1a49f40d757baecef73"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "51cd0cba8081fcf9240a5c2247c9f407fe7dab0412894e56344388d952e20287"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "fe6dd5c7431daa6f10e2c82fd764e6760f1236de9baf0e2b5e468d9c11fb5c06"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "9f01dba29ca98b108a4227a150ae06da95324485f792a04ad31191df5e80bdb5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "79330d1a2c632a2a5b747420299fbd176d67133d2d395862b0501cdcf8e48970"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "af7f87f5c45cb39e560a97f9fc974e0f8610cc1e0d887c9a37b228d9ff527e05"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "746c61da798ec7e47fa05f9d03117566f3ed7b2f4e85bb74d312105fcf6d4227"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "8f5977462ef067e6567cb1153b39847969ba247caa9dc156abfaf727c8933eba"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "ba19a179b228bd41836cd7eebc268947a8606281f3ae64613f2bee3b28255fa9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "be0e4cda6de22c8bc94feee74a5b5cbb36a132719d99d77ae09cf38c0183e7a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "61e31401abaee06b6c3e2f8ed647efb9819dd378d9dc979dcc744ed4512e0726"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "19041558b05acf4770f083857a1259e12c60eed0c32a298b360eb33b593b6ea7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "c1c6a8ca6eba2831566f589c3f30edd05a615d87e7ef80ac41d5751333146d4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "fa96e22dd40673a4c5a421c4917fe21fef213bb17ccdeae2aaa1089714966596"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "72f579eb3046bc09fc51d27912e1671a8c307022bde2d47c79838f2e22d02612"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "3353c3f482ac16081466291c8c3cb2e4793a364c7888dc439688029b805c9eb9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "7b03927f5f476fcac29c3a23a8daa107450c3ac91214dc53e4c4bc9e4f4d12bb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "411cca9aa2e98297cce02172b24c393385990e63ec6012c79b7cc21da694b3ad"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "8ac8c0792881f6b596b0ea227eaa7f9460f8b2cb8c28d5ad8ca180c7f318c07a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 160096, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "258be95cca8045d95a7546cc23c15758ad909ed16144bae5e8374443bad70876"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "82232ddaf32ca434796b2a934843341f194c1d909b0a5363b4b570b896f2ee09"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 171360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "10483f01519dd1fc16e25639b861bcc5f3b48c8a130c4fba193cc42f480ad320"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "43d1d8b404aedb17d1391d178c761e01cbc949cc29a9dcc3257cf76757cdd01e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "cf29fbec291861647b94185c98a6694e97e030a966bfb68c0cb9133b943b58c2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "57666a7a71a6c045f323e6d849091ed0f7df8a4af9b83fd4b9b2328397d54ac3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 154464, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "748b230c0504405ebba7dfec9c3fc95c5d09afb48b2b88e3481260871cd550a5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "9af386c2c99d5206b53c47a457aa4aedd919c420f61c9076839905dd945ba9d9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "b9015bcb3e4154cdedd41753c6caef1e228303926214180573cb0dd48bd2b9aa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "7e7b7be5c5271d0a62b16995eae5d4b095ea7b5a86ad523d68f6ce7bf0fcca2b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "2e61635203d9793a2c39174fd50d5681901972fb23371bf730099b2a728fa997"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "5a58667f197b82ac12672eeb48096293a73c911f53d7192bd8f5da32e697c56f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 161216, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "d51945abe743c672a6ad0234123fb6d18f4e75bdad7c139cbf8a0487794e7737"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "5fd29b58bdeab959a9aee2d0d74684b3ed4d225db122f54108158154c5dedef7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 172736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "cf72e845275c752a72e18189ff249e6b795a3f1022471b31103651cda2c585a8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "2a55775aa88acd3cd9236d9442a6819e0247ddef7410c051107174f5568f3579"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "f87efcda32dee452b710b282d5824f0c5828b0975306d8894879743517ba63a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "ddef2bba9b2093f8573dfb81ad46cfbd5924b37c8bbc464d1c2b404bcf0b3729"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 155456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "3a0f4755d837d92db984226448ef769a229f89282d67a04c576c93d9aad0f073"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "a44ce6df984a10efb33fb3d3a955b9740e617c35c92eb82ff06c97dc8c139c54"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "6cd901699a3a4d98dfcc801b86f5743d898b248605a52f7089f54fdee85cf03e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "1c7b2ec8785042532418c2e44124a0ba2872de66fdb07703b46658e3d6cf47df"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "51ef441f2ebec52f7e78cb2779730accaa7334bd940a70119b6c27596f13fb1c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "bc61a66e3eb02131cd4283628d260bd093c7398468b40650579328597c9e6573"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "fbf765acb52805662a096b698f85eda5bbb72da0b2b5f433d22fbe86bc5d4902"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "608929044f5910188fbe7e30f704a571cf008116ab8168537d5e4aab350508d6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "79a30d8223cdef277b4dd0fdff4237e11652bb76002b6c426bdfba61674648be"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "d594b5c3f9ea9346fb224314857615507c0e8deb5cf5e33dc4da8bb46e8a3612"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9e9c89fc5c94b5e8b27cc13f9b910766e0214faeb8231c232323bce1b50075d8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "6f7338423c08f5afc7211286df2a5b12aa45b8bfcaecca73a743c16bd9f5757b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "adce5009155e916fc60a39a5aadf6d79185d860f9128c29d2a7f98c5552970fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "231386ef51738f89623bcff3219570139d25f967ac1a07ef82e984668ec0e3c3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "2ef9993da6b53ceac1113540ea5b6157580db09524f3e0553fb259d55c65f525"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "435d22792ff91df6cf5463487096da2fa53bd30bf8e999a19fe185603de690dc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "3984f243f1becf05fb7a1191425add01a6530d94d0a8cf40895540e9cf1a12c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "93659989a32b5f8808fbdbf7e8b0321dc1f5326ec701355941d28e6af79f069d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "19c9a47a9c01e62508e2fb29443f62164627353f696e053107ab636ad2962ac7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "b210fa7834818ab4099fd48b3df58cebf89d391f12312c5f70ef79c4ab39cb58"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "9265f63877d159265ff87399d6061cf6adccc236b734845c3e06a500d5152d48"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "936f8481dfae5ddc55c47114b3146246c47cba137b55e2e967cd6d56f334f9ff"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "7182e587fd29f2dea184468b6f1c417302616d0444fb46c8c2d20974fe5c366e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "115c1fca51da103667622fb6fcda139544c4cf37f0f462f1d3a7b3e3f81f3ff4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "f40103479bc2169697bdf0dcf14d469a45275451b00d77d9c4487d258a43f4d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "86251657d53cc9156644ff70c4c375f807c52d2b5aaf4b0da2679253614f7382"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "8ca8181b34288d0bf21ede27232e6c36a5a557e4b043d89f0da5025d7b819858"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "c9b67f6981891ade8b1f559f688a5c5c6352c57158b25ce67a24f0afd95adfb6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "c7ee147eed387652209c1d6dba6573b4f087863869f1644d9e85c063d0dec638"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "5dcace477f49fa12eabee692d64636ccf1cc2ef7c61a0750888cfa88f6e3abb1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "8a2d10d5aa754415f8f5ebfdd76ef630272166a087d95ae5bd770a55f5e99af3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "db6adfc24873f161264d6967f6489d3494cb24456ee895937e1ca4818364f9f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "3a7b3d49bb5f4f97981ae346420240b183b2346b788ebd836c9a1ffde160acb9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "e4fd7c48767a4b183299dbdd08e1dc0fee669567ddae0c2aeab0bbc81a5a7e9c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "caf01866adc2ce53bba54efe72f3853add0370371723ed946cab91de2509354c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "cd22359ba6ff9f3fb61fa87dd8f1228cf8a81228e6aa621aca380a0a6a2d38de"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "34c3234d88d500d4173341e6e5c31f455ab4767c8bb1a9c7f20fec3ab3332cf6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "99c3f99e2ff20748c0fc6d456e0f8b571f830f0d343c0338b51d174397680692"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 160096, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "7b45d4f795f2481ff46cc0fa0fcf1bd57ea04543043b8597ecfafe41f14b1340"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "d5adc680252230d3fb1df2283526dde10064ebde7c01fc91614c14f9a13c1ebb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 171360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "452f3106a0a213d3d5c9e03be75e751426e864517a81647bfffe47f8b8012b78"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "ccd00cbb2d7c0041970296a9a43695b9e7fc4e55991bec58cf850ab5e6570db1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "2de847f8fa1e820c43b2c29e208b5f24279c30521b4e4f7767e3dc076d61ac24"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "bdfd55cf90492fddbc964fa8c7ed3336b300e683e31797f479cc63c27b9ce810"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 154464, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "c851a298c0182b768a1861c1a5ae77095e34e1e2d8b07f6a2f6aaaec26cae150"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "b2798a09b248a0b0c7d2ef08774fe91dbc3fbd729f33340a446c7191fd5dad07"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "ae21d1b9526789d81cfe9aba4e80d313a3f2b6ce42b1fd54e4e2a9cee8dd9207"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "382140c72325cf2993ecd2c48949599724d02cdc640d1f5726f4c1d66b7f4287"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "4ed554a896d644783697f48813fa1298efc77efbf3bad3d2e85d3ffc6f046b6b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "760c19858c61d3cc1b0adeb8524ce892b3803dc9e8b1eededf44447560c0f137"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 161216, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "ad8ab657cdd18c3f1abd7cb096db2517d050804cdec3f72010a269e233889951"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "3e65bfa3e6bd4f461143d6173475ee97facb679472093152a82feaf5330bdaa9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 172736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "301e4d2b84d92388718569c3de168fde2527a470e141814bf37c3f59120b34e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "c2d9bdfaed0690c30304c509603adb1cf18ccf175900252fc0960047afe296c7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "6d53b3c01cc3656ca496416b5119a0ab808edd38abaa31161ea13f6a5cc75b33"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "6886260c6940930f892c12afb11727ceccf2c3fd59667437143e3158dd290da3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 155456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "21eb44dfb100f14f04dd037ea918a935af5b9cc8a29428638ac95580a4073f2e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "628b4d193dea1d3c415612aa6e46398b8f6fd75129cb2ef42deeebe47f13bf3a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "77038304e61157baae03f3f8069fa9cd59b24a8b98a031142cd57d2302410207"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "866cc51e0194960247010aa98d2bc46ee86cb59880cfbef1ccda31e267ad6a7e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "008a792ac2e38ce4ceeced807e160e44255c6942a27400637835c46285377d6b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a12d11b6d402097723f67eaf3b716531c3b95187006d1e08e49a88d6877f5790"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "33afde69194267e9c2cfbbac73aa6cb7f08129bda7de60ff32bebef7348416d4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "43fa1812802c6d15c10168baa5d816d001ba7ace37364443848d79924500f0e7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "1cc269baf20ef4e7088ee448cf20a63d9b5344dbfb6e6b8f9a6126a1a068b31d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "0ea56eea01cfac34a4775f42998e98f6f7a52fc4ced89e40eabe395e83692502"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "cd0de5894d3f0d6fccf9f74cd749755eef1daeceb3a94c893ece9478ba9bded0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "ee24968931f236454a257a71bf009538a80dbc60dac860671478e20cb4e24336"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "98140d5143476e69d5de8ae07267fbcc3f501a050435061e2aab4f7ea400b78f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "cc06882dfb92ef9142bf1220899b91f4fc775e7e169f9a532dd532668e46f870"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "8447268b7c1ad168186a45d93def8f3562781832d59f47b30326c96ac28a9875"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "303bd24318be6fd171b38fbdbd0d5acf51ee32aeeae5a328105d3e8a24b74e03"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "30b2623b9f68aa7067d772b31390417e882f351e34b190bdc70f9fe0f217c99a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "15437ed2fad9cf7318f320ecac7755a69f66d330e67fbb22e85f3a228cf8aaaa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "4d821e3a83eb7638be2ccbfeeb6aacdaad4459f545dfdf954910ffac4128f8bb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "a72d3b76d38b39aed5c6ffc6980b0282b03edb7aaff8352755165c585442b171"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "c569e9c9db907cbd6410aa4ae4c71fe8728bde21dcbdc37b4ee0d1a988d58a9a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "2eeb7a4b118bf2255878d6d547be51b2d6214522bc6f56b61f35f18b4ea72b89"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "240825788df042ffb56a03ede27835af37aa5844a4a136b4878ffd2384948d15"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "c21ade2dc35101aceeaae296843ee459d1850c1db0269899ed042331691e36f3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "f65c215bf2c898ae919cc58ba04f3ebbd6964c430e36b5d39d58827f27f3c73e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "ef3404262e8e386508d885f582576ea128ccbbd3339022ff1acd7b37211c8577"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "15fa730c1286844068ef14f3f87bfb33b68deb87dce6117cf7604b5fa97f1128"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "cc28f6c216f403aab46166fbab3a54636133aa7acabb2e259302d7ee5761a935"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "bc82c0db87c80e586cfd9775d80e906f096896a63af1fe011bd052219b7f6f64"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "f21e2e86521e92949a379de6673803dabea029c9e0152b951b1a7e5910952ba2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "c51c19f691fb8446f4aaaff163b770cd9caac7057bef0a60fa658f3e7b24b818"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "d7af41cb45830e45f198289870cc707e77458bf0c26d8fa3258fca729601a1ed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "33847af9b83845b4564b295b6f736c4aa960c4c112a6864f2e3b071123e77bb3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "b6a14e97d94492d60acad663d263e7e9e73f450efce2503083b66e79039e5147"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "2e886e0a34756bcaa0570fab66e609d1b4fbdf88399d6a92dc21e7f78d4d4e4d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "8f1431a0f842eda84c2b70f4aa8724a30dbecee439266e33628c0b179625ecfa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c89d38acda4d04f8da1aa1c1dcaa5011a10f78d21557970aead38943e0bf0059"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "e0bb23957ec54854ce88e9586671fd4961f8dcdd9a53d65990c4e2e725b7eff8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "bb8cf962fe7b46a92f438871a99def10ae2090a6840b16e566dd07351a247917"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "1f4eeac2f37551d69dd65009c22e6c6a1e5669072765c21dcdb004674fa76529"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d1e1583aa919cb49b50e5392753049a7dbdade8b8acd7834679045ec1e493b85"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "e3bcd906f71b8cac4780fb113f4ff5b191a917821457b90ab0e80d28daadd3fa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "d440242b104e96813e2be7f6bb4959f680f9c9aa0c03303729ce878d9d0f8446"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "7134ce4c34e6bb8c0b406fa2eb48d3a8a5506bf8d6bcc888c1bdbf7938a55338"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "dd87a3933eb86405430eb5d64c84ff3677ba5d14dffd467da18f576a5855ceef"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "a8208462131eb549cea1c18c67f05e21e1bb3c44a2c0f0c8594d654f3ebb715d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "21e295f9a8d8f550ab3949235f2e2f7c43fca18576445a89d1c0b9aaf0b9ed38"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "b2951d45d76d461474bd67393a09e4abd7ab5df538265dd1a0eb175f98cbd6e5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "8b06e3bacc04d83cd55a80df64e36f7b5c812240e817ed952cf53e6bac83cf82"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "a59d8f5eff31d1de4f7a9132235464dda5af4df4358385df3c73994ffef1e5c0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "4c13f14bcff5f145b8a283529c4778042b3611ff8434dd24cbf7294da333345a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "54579651309991af9f7c46f779b0a114bbb7e416583ce41b17a412699eed7aae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180928, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "b8d03fc6f9f768907ecbc7d6ba15f88aafd19dabbb78915da30f00ed35aac7f8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "92862ade9a7ddbbf73a3b250f18225fb4985de02e7b94c5268dae4f7407087a0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "db2b08a2949a1481d01d6c8cc511b3020443740cf3c715c4104cae4c88362b77"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "003290af8f350e6acbf8d8fce65a8f4f10c3adf43e959b475356735064c41b93"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 157504, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "1ae7d19bfd87892c133f794f93f958f129c2d2459deaa74628db000339975c90"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "471bb943240da31d1fc20d45d4b8e51f6d5e08e589f90e2dacef0c6a89165e92"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "42801b0c57dc485501d0f5cd2c8be7735586c95001fdf71f502e5604a791cfa9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "4bca2883afb8ffaf1a8a3c97f55752b362e5126d6987e021a04987dd3e8e759d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "95f02a54c03ef7b26b80c68d6189e672a2f40bdf2cc89e7048954e87ac049419"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "005475034a47ed681a097713433a9fe265b3c8fcb61a67eae5b225489fd6a375"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "88f7b5e9b2095f240dba819ee8dbcf3e3cdf1dfe6239223bc77f338de9158f34"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "d7d9f5645b0a67b497c06476f8a7f34e3256c86cefa474688e80b4961030f404"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "5142b65670ae3b71f2eb715307ec4378740853ec9b07233a49ef8fe65b153056"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "2d8c6e8d91af608e44ca2ddfc89fc0311573b35b4138f0d0e80406c51fbf745d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "4703aa0ab2fa4bb7891a1d65bbe892a287368c9d6c937a6dc489c683c59c73b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "a7cc20d130277725d7139baf461345317d2ab5c0c5536108869e8a5b3d1c3197"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "125f8a1e604a5d1c8c9032676522a22768bfb48ab0cf06009d5043a90b782f11"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "5d595a6ea2722f1a4a43f0b65f41097c640a0c0ba7051e4a6b0859138eca0aff"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "79833a21b90214951548819591e72376603d8039986f38464d34510f1708462a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "132a130e27de88c5b1122a17d40119e4b9c4c01f61dddac6a7cb6ab6f2722c47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "de4a2712192fb38e2fb484ed2cd2d49de843bb370f9cb264358e48d7bbb2ac3b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "affa41a6e79aadbe49c1d2f081e07d3ecf026cb65b74589973758e32dff8753a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "e7239e21563e16616c4ea9e8b3141b9e2f2a49727707984f58c4a4a43507bc96"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "5227466c2cfbfed852f8d7476a18d71b81da5ed79702032b534c6f37f7658e7e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "3fc1bbdbf6aada22122660a682b6c9d2caa8140ff2202b5dc500e80550b2f6aa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "44f99192abadc104f3693791f59e102ff72d02c0a3c328173295560605c3ecb2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "7cb8e142fc770ed853bab4541450797aeb9c5f8e5180495e8b2508e673815c19"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "81b98084f172c68f5ba0322cb8354c4da646942038a9e96db22bf01fe7904136"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "e8bfb83f766f4cbcc9dcb7cb7b3e5e827d8c16c9c50cb09a41a2745df8c4aa74"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "4c22739aaaf1c9483468a6f0ab82513ce6e8e973379fc350afa0be6db1399ebd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "5f5380f56623a9bdc57ab11437390a5e454a5267611aaba6c50360eacad2eeca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "e65d216c9e62ad6dd14b755bbc89baf538b62c2ca7c322942d50f6b110cdd5e3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "feee40da1d14350c86e867a343e7245e6d0313847e6d6fbf2b09b8eb8d78ee63"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "4eca8713d98adcf84ad3634a1c7adbd74f11ee4f570b18d135d5b854421c6932"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1c940c4110e5466ea595755ab52ff62897cbe4d5d9a8078ec4f36ee644777899"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "e008daee7fb0e6c34841cd24e19df64566be6e1624e963e7bb12c9f4b6fa3d95"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "1db8840cc4233fc899a24f6a55170b773c143169be7ab426b997d6c94e407e47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "b96a4ed8a294106d88981b7dae4afa2d6f17ae419a9f55819ede00ed29678007"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "9b14cf94b4e0d2d708c0cb57ff7271af03f7a720f4597e8db270b10a83cb0cf1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "af918824080e998951fd226b1926192526dcf0304cb45147195e324a7562d164"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "56e0497b9e54f8301fdda6379ae5cf1758f1a1e64fde25917dd58b8f77a814e8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "a95c15754e24cac11f55be578200d7fff9b47b9bb1326b3775056041c1ecf795"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "22d93b435044c4f52c0ebba469ece6539736997a307ee3b5b97fa860094fc26d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "bd21aa89e300b6ec1c79ec63a94e638749ba1b9052c670f870a9b722d77292b6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "9c99bf60f08493936212b8f8a900912f4351b06bba456c93ad6bd2662f79a5a1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "37ec247223aff42ebcac2ba4e2954bffbb4f62155f078e86bd58944484f9fff9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 165312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "7726eb671aa21bc7775da72e13979f3b0b360acb84c19361c7c19d7bde582ef3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "2ffd08e57f4832aec1cf106d1cd1c841efe61daadf5430ae68e5152a99e96842"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 180928, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "2f0457f6667da07a51881e90970eb9d4a2f169a839d52ba3ee202cb2e24e39bb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "13cca8e46f8807ca02bb651773390f6bbc0bf9cdf68b07acbbb37c4ce788d704"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "a66f87b9454ae1e5646d28759d46784e1b7fb099b501653cfa7744ed99a59911"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "736973822b80e1a088b526d7ca4f84779c6e97b0f40c429ed7de6d97c49a2b6e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 157504, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "c2ee2688513ec1aa651d6e801da23e8d35e6bd6ffceafda1f25d9eb956b6a201"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "cd0f4e0d791f289fe1a2808802594c3bc2b422ba3f67dabe9e4df33daff410ca"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "8dda2a58d3b41d6c8482a6f00a98e8d928e86682215b64136ecbb9e9529a4263"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7ffe41129139cf1f2c664d2fc913c2fab1150f68d1d12cc09d08f822eaeffacd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "6782fe20bc8d5b4a0b43e002531cd72ff28680ffc1fa99caa291736f45453d53"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "44d2e504db374988dc9d069052b0ec3084dfc58e033b187e92fdf3f6e26d00e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "d842bbfab73e7b271a43f23e7aa65be7a594a95fd33541b00c2d748434f889a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "83b6711efaed992a9cfc390f9b9340f902bacf15a8f3316dfd30464f48c388cc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "c255f28475272c15020304203a075c38b52d3eb3ae6a76dbf17c8a032bc226e7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c463cfa00c4a1b5269653b64b5b636397cb43302695f4bebe3974dcbd086e425"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "6d2d9cf22a9ea1a1ad262dafeb4887a68e269d29c4f3b3f2ed5fa386c507b617"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "35a892807390500440aebf0803534c35d13659a76defefc33e2d9ef0dfa6f45d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "6f8d82dad6b90baa56a861b55673bc6d1f7e7b9599d76043a54252cb62b0a942"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "0a59ede759278dd4d8ba11c9b1644407b09f75d0ea17a8c9e54eb9dc3e566d98"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "3ab7d2d5b3ab98d5914ce4c00bfb665c91d7538249d9a294d6fd608e805760bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "ca93b44b9f5aa2fc5e69ab27d16a42dc5f24cf592762591c2584f8fbc31fd240"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "b6f6743eeffdbd8879063f33b776f701b81076f615422539ce0306ac571aa61a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "18d0dfe2acf5227a7e9c057b5d40c49dc1c509c177249d5195d4be35c5c0babd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "641da762d1bda149266b06847e8e7d9bfc1fc2f0e4abcca958012cbb2212f8bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "1eca1465a705f7d45e41c990e6752004623df1b587b249c4f02302154e059c05"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "080bccfe81d82f007aba44e068ee466cc7a392380fb32aa62203b23f21f39e6a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "dd8d7ac2c9b51569fc713d1a1f02600c7e668c29b0035575fdf199a898719222"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "584948dedd3cae71ad7ae1d8a77fd235bea90ce6aa2b008a28ac2b7ed3ed7d94"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "f0f774d718bf4425b03984b16f59ddf97360ac31c2b8eed066ade636eea1b59d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "8b5e8a42b90ded1a680b596856b01f1a09d4cfea79a5727b23dca1bac1ea3d1e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "d64c3474510dba5d4ce02e3256ccd204a25832481d694f4587d8be443fe8f318"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "9a15f33aab6f03735849fa117a891306735e5d9b3b4bb9d86b57c6c1a9155dd8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "ebb3a3ec1d917b6a01bdb266f4452c335392704efd00e3f7ee271cc326c34818"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "2b1f7ff7366f5ffa24b0ba4a0970c6fdb06116a0de30e4b2050b5feed566ea66"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "4e524091ad606f555f556897032a07736fcb7089d8856153214913cc02a5665c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "692ad0e125f509a1d9b00c1a430d5e8de1b776eb941c1732d3830b409e3c3ab1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "2923c484885117bf77a69a9bb846b9aa0b65afa7a8bc5af2febef78eb4df4113"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "88322c8ff74937c78691a399b95c4805cb6daa24dd1eed15c1269982f684e432"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ff714b1d7d8fd279efa06035ddd5c32335722ac5cf7825314c6ead88974a1023"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "5f130780987f0935261307ee00bec1ae4713c1dd32df3f99901bac7aba43bf8e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "835bef1afe5e14787ef46ed8a3d711ccab2c5b34396808f6a4dd560c84385451"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "06d711fd01f8d870f950aa9aa3faa148ae87632a76ea3f7c21c8239263437b60"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "f07454eca2d26b2a7e86d7def7fbd4e837d129f7c6800a8d05ea40b5fed26bf9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 157168, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "0b320b1d92d40c330b4a529ba491e906322844089169c8c595cb3b58e96a9410"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "19ba5263ed60bfcaf5bfd6171e8616a82dbaa229acc8a02d1aa3122e42585b27"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 165360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "83601db38696a04fa5bb3cc86102b901b421377b3b02c97d7466b58017ab25ce"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "e8449a4f497c55de6d0a87009ab8250453ca41785a9a733457c684089a543b7d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "4ed631fbd9afce5b9f9b5602cf9b8bffd8bbd37a17143007f9ae23745bb859e7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "8991866f1c6cd839f6292917ff604f19de9620d537ff8eecd8728da164e6bd7d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153072, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "2c2d3dd403ecce45895b01356514418d3e355e00da56ef6ba9870c386f471604"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "af4b21dfc75b99a5f1a876ef437991d279d13c8152bac3dd26000da525fd11b3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "96e53dcce123d69c1941ee6a29df439bf4e7dff9702ee5e1ab7ebed63acf3df0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "36945c9ce56bed6204f18c7e5b8771b80b8a249c97b6175eeb4f5fa1af222545"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "951903b1e3f384c8bbbb837529246ff8ebd5643669710e67565c059cf0172124"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "03ac8966b3f0e6d5b777e762b760e339d688fe07fa006bc8c6b6dc64dce2ba80"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 158288, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "00d4848b948464e33740d6b520b922cfa4d89eb9c513a5a38e5b0f549ea95964"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "63fcb7c47607414ba37b03c5219deab4e1e90fc7ac01488553c11b014d533677"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 166736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "406a254875e15b04881956956cef9569deea06b34e5f4b7de3c9f651bc3f3a1e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "17f548630d0e63a606f4198cb3ef5204b2f80a23e62a63cf8b596d808eabc988"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "f8cf46bc3f30b8895d9c15ac6c2049c31bbb2ae6fe95d4887fbcf665765b3bf5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "5a9c700e2276770144cb7a3dad9810b3b9a7e2fa5467322b4a84c5aa2f4367d4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154064, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ee1e97f6afe63a6280276d4045271900cb70fff427f73c8fdf89075168328a82"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "91e0bac66cebb39658916767a184002f793993d9eeeb13958ff0e273e40e43e2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "e0f3b5253a5c61956d4637c4511216a2eac98378d4c8e1bd70c33af0c08ba7e2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "35e207c271826bab70c53bca49b8a5138e593420b658cf05dc2aad22037f1eb3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "a4ca565475e775dbc3e9ebf50bbedc675172c8ca54e7168102a0d28275ead1c6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "4ca7f6353240c1a68bbe6f3b967b84377447a3d6a965730d0c70f048847ba4c0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "b79785232b89eacc17c5dbeced718998fe76ac95191e79ff85286e8034d7a0e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "04e388858d16d80bef3c40a33fd17d8ac9e87f62ce1ce0b2e1c64251dcf676dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "5287a60830bebd2e8cd309a4074ec4fb39ae62779cd9d4429859d5537d45ddc5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "f8d24fa25216a169437de07f0cba1539cc245cc8c03bb9eaced805ab74e1385c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "9feb6fc98b4c047ebf7e50d62f50f41ee59c004f9223f500bc3e44224f1ff8ad"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "af36eccaf08259fc5b980f3077e1e566fa63e2da1037f8511ed16a26197de415"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "744035f82b8df27a72396589bd1245f6759d815d966a7cb1fe29e3823291f5fe"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "7e651b59dd696c2eca21709b1c677f3e160c9180637344444050aa770525e783"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "bfb6740eddd7744eb01a49ff8178d64d1c47c04ac1c5da59ceb47bbc75bf1fb3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "5194bed9ef3a9ad6811e154a300795033eb17c1c61db4c491c1f99f3514907c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "28bc44e8e8dce306974d7649fe01dc0b872516bcc95e660fa10def9a8dfa0291"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "3056b19ec954840d2577b32c07cb71624834bd14edaeb56f5bb4ee25b8ba9412"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "e43919cd1d89c2f6b782cdc780d3e864d9bdb6621af95a6e70a526c00669c905"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "bd9eb75b2be5c46d6220788a383e2bc6ec1eb5e03527e07780d7889ec0c6ce9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "32724af9f2491bd50889a6f486ba7662b9f1d9bb71211e2b93fb9c23bdd0179d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "daddd9e0c873e0747314ab39ac17da9d1315e59acfb06209257323818bef696f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "5fec3ebb28d3526f32beca683889772dcbe9422e8037c6c23f39ff5d33253326"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "497a55491957390015829373bb21964ad1e9d94f1bc90c5fb1dfd36f0ffd9f5c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "2448737a6ca879d8467fc92d0aa1f35ea649d5dcbf688c5f2daeff6d1258f99c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "ae700fc43a0282c1f8ca841834f7ec0ea0e17227834c9ba71acaaf903810ad7f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "787d365a869cd244c1defa4c4108eb6a5da703e969c164f6353f601b4e4b9fce"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "902a3d598b14cb0bef2712066d10d3643793bd4fd054ad309404adf10179e83b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "d891b78e0446eb38fc8453b02cc995acd9be868dc202c5a2096b74fbb78d0940"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "b7dc193e7c614c2d591bdd8ea933020640c72575110062cf7f29415bfa387202"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "123d8c78410e55140b1edb74cf6d118d2e6ae33b756c74d56a7a1171ec4d3739"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "fb37bc288ae02e40b2ee3b80120c79d456e0dfbe97ff792ae47d60d4091c6403"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "5c8ef13af34db140ad11d0b879c9572dcdf59f67940b8d16f9097466175d13c3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "9973481bd949bf035c052ea1136aca0ce4a404562f13de0b118fb8f19bcefe9e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "323e4191bc3c95e2b6319f98acbe80d89f41096dc26729abdf2e1ac7f2b200c9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "9793bee82d9c5221ff3c8ca576c9cb6e5a69e56ca74e2a277f4ec37107489f4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "b5781ea37361110cccacbcc12941beca5e11fbf155e17000032b219f4a56f172"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "4f6eedc595a7a0db8459a9a23c3247c8b77f8623ad515136c47c1485fec1fdd6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 157168, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "b12147a79b0d65169f19e0341c80786836c0a994d1d37083fe0c7ea6b104e19c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "2f2e64d6646a7c5340bb27dfba1c7a5e7b446753f1b10c32348440ff905e88ed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 165360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "2c46f8d5ee62bc619aee87461573b87ee4af813d14d349623c102cbe2ff35286"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "d87fed17bafd1dd7c0782b47017d06cbff23a91ee13af7330b6322a27c48d740"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "ec2ea65f724e26fc660956bd75043b49bb5db5654ddda825878d5382e8606d71"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "1dcff44cfcf183e5bcd1d9ce250ff7bbb98dd8073e29d797aec6ef2e0cc888dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153072, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "5898f6d999b6b29f689f71d7da34a03b2ef827108d2cca65b7c10d780fc2e836"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "a8fe0832d3fe1b0b08ba99d6bb3dd1d127599c95f3d46b06d4af24201be26741"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "9186e747da70808f19a1556ec85cf14ace51d92b1d8f2fc821b5c78134cfc72d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "fde3fbac8ff68314684f55c28573f6a16825cbd0dadbafc5c915470fd5003294"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "ed3af0f1607bfc601d46fc4f2d5e2e98f3f21ad96fa5f7b72a36066e5c6e695f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "752841c47f5f7ca5af7b00903617144a749dea2bf1082f1205b0fc4a0f9dd5a7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 158288, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "15766faa7ab787781eddf50b448891f8a51a4e912e78606208880530989387bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "e55c16091c355ec5cf1d5c7dad96abf1e934dc06d060858708e5fd4c0d231016"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 166736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "a91a5295e94a807e45fd4efd36f8d685df925a905dd5dd27c9280177e924066a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "ea3570bf450b081d6118d0c85ef4c8f6cce7cd7d459b398f980c500dadb8e7ae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "83ad6ca9134587e5feeabd35f7e7ed840d572cf1c30b4a66e90dc9fb1f131b98"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "7a4aac6a97cb72661a3a3825150517976c262dec136b6fdad1259c4b9b6a4e35"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154064, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "2f4cda6da37ce9b7eb72e249a4500b804070d6293fbc421cb00113f93aabd396"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_E4M3, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OE4m3H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "a24efc502f4f50d9c11573ca88a63509c4fe38a6b6931acbce377ed690c24ad9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e5d9534f18183e45d8c86ec3deb266e21c7e6b21ef0818f3c2febdf5b3035244"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7e06d4af15581fe7c5081e1f6849758811a0d43279fbf8eeff2358fe0ff1863a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f2af809bfab70dbc21d7a9b39ef239e1d03d803c8b38fc5075fa90a72cd97aa1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "e13520e2e866aea30717824b3f884994a6ab46a4027e0346d9d42e4c9e39711a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "372e8baede6f6dd377eeed6c830ceef64ee1ef9cce078408212261a45b8fec07"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "0a81f057c474db198b58f27fabe0d9e77290d0f0f8e12e5c3e18a05fb17f32b0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "1e66f1985e29afa6e294084a9e23073ad8e14bba756e67f8ba268c08c6d1282c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "fd5520c77d95a0f1e3846563a2b68fe59cf719650df0e14fbd255ec614a511e0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "985f21f8a5d79a3d0b74a4e52cabe26b88cdd04ae13eeab23eb8f9c0017c2b0a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "94e03785cb012c32a2a9918395e7e6153431c79d66ced048d1abdc683c5352c2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "255abf305c5834e963980a3b01fffd131ace8f2a2814edfd6bcca408c53b700a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c96ce9d9ad49e52953a09c18a85f3388e8a133b287aa226ef4a5e8691f13d508"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "71e91ab3199c6086bb059f1c4b38568bd9aea2b7db9ecb077369c8650d5c0589"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "f5c4fbda922309854e3e092736d933646a2d492376a14f7dc26a8645a45bf155"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "f173a8cccbb1a6b08b5ea38d4104dd92ba77fd5c9aaaff5a973a25e32695dac6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "5781d5683ed958db73be7fa5c8077aa1868bd39af9d716ab7e4b14d8e5d04114"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "dcf298717a2d55b55930e6540afe7049261edba1aba87120206ba86e501f433e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "d3138bf30c6b082c90b922acaf7f1988e6e1b21ac8922ea57dd672fdd0353340"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e9c8a06f627790231bceba08359661159007894ec2d504b0ef6d29daee2af09a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "4e86f45c33ed8fe0411377fc8c8c1c1a371c566fe647f0aca903327eb6c779a3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "b2a129fa262c7f81a60c3ebe55ac0fc944e4c5a8705be4e51f8b82e0c65de5e4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "8ec1ae7a48226fdcf2b1313f0244ec2bbfe7c158649af4e3088d031c3d44fbc3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "5d4bf4f45a98d49de41339899627b8bd260099ded90936c6fbf01bc8c520ea0b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c73b7f299cfcf755ce23cd869c74b03f4cfabde4fad633581b0703be25c592d5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "912ef0cdaebead7bfd73f49f27caa0ebce7de617dcd10d49848b08a3e78f4bdc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "c9e7e88678c3a8b8d82d79aa0544e67fc7603622ba4752c81ca374c25924152d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "74044ec9e1fbec5fda13cfa1340b46db441282d117d6936b19947cf22e5edbe4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "af8decf2c56bae0c6425ae8d533c7a89aa58199c3859dda1fd689a1e2044af47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "189a43df4c754077f1eb3fd67b1710aea9499e2bb70d2c8b51c25198daeeaace"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "a1a93b96b1733be403b37b8292271e661e40f697756316f9598f5f5d98233cf9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "bbcfabab93c25333d0ecb1c93bef333a879e004143140dd8025ed0d0f2139c5d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "c34d9031351f32f6b40235c0b72f23876c8561fc896adec0d53d8c312691326b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "3f665c75941d7d1f75c20cb9f2bcbbf2cce30b502bfcc4500de0d82efd2738b9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "211cbac68e5849508cdcee6ed887f728e4956e8c2ebe21f2ae0774468599ef6f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "7b6239180aa17356b1deb3ff1a2f7f2588925b59bc9bc66d9cfe8ab8f1fb485e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "23603e98beadd20ed633fbfa9464c18ad474f4951b89e0e7957ec3a8bcfa0c4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "6c479b83645d25e54a410ca3b28b107d5a4720a54f4f6cde0b55461a7389d2a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "863aaffaeb9861c9ec695435c6f9dc50fe33bfcb3fe5ad9c67c3d6b4e3905969"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "8280b7b48dff59daf63cc729f34ef666ca550c91ed7479d6ad03b3e5a15ebcc4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "519403a8fd2243b6af5c4856e1097ecbff7b89fe0e4e2a7e766cffa2d68aa664"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "3d54b140c47479c0a51475ef6c184b093148e03fde941a5fa51f617566cd8717"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "32ad1ec87d0c08e4abe0e0c846b66be0aa1d08c6929e0a3134174e6929049f72"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "c57c82b9d254b4a6b4748dc0521dcb9ae352ad1c41b403a723a5420d0eb19c38"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "00c82d8a0418769dddfe492a00725eb492547b2a6ef5e88f2f750b816ad9264f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "1823396d8813a78c683473e8fe863dcaec6f6c213f39fdee5afc79254759f238"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "606b6f0c70975c4a9e9e7710d4d7c773bf24eb8b7a6adcdda4c248745bb972c7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "27690f2cfbe499f335d02eb99de6879f9ac252a80176ce5012b84dd4b97e27d6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "d18707bac222d49dbd843cb37cc87ab693d7b0f60b0d2d89f9c75a357f3d2181"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "a2b1c1ae3afd72ec6ea76a6f1f7877ff0afdf521f16c2a085115b899a27b691a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "6a8d3bf648215c12c60bc2c4adfba6336f0eeee9a45449bdde7db59d3f78cdc1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "e21e50a1e47f6e568e813a884c2c59753834d914f4d66ee8524881b589a950e8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "736ac085ab7debb651220fa901287bf44693f921208544ff97de043f8e77d97f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "c2437e14bb9770f3df75069d602f9ba26f91fd61b0d9d4cc9ba2626f31158fb4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "519237d9575a696904c5952dc6bc108418916746f1d8702dc9b3af89762b8230"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "fc0b781cbbb169ff8b698001d97c3e9deaebc840164a0d1acf622a743a19a165"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "7e0a77eeb18ed1fc3e0c6b15cdd7bbff994ff6b1aff13dfb213a1997440c0e9a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "719faec0cf4978c96e0afedbb318a3269e1291157c836d1bfe2384a8aa445d8d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "94ab7da292563ee9a57282b6ac44c49bf071e79e37153d45ae7dc13c97c175a7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "337e1b3de6684f4e7b710a6ad8d75e08e7d858e95ea671c67e2687dfca65d723"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "ddbd10ed7e643ebb07afcde332bbc03b34c17d9b2319c45019dbee034b6fc1ad"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "2155d25cc2c85acf068771b48fa25e032f04a8e055c6dbbe64cd86f9dcf401d0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "b2d069d062a29b0ff60431bea7bb694d7d1b355f4b60b6cac1662ba29fde63b6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "56f2dd47f9d3d8d1f562ba44c4756a060d25b84cf86a28061eebe4854e22edef"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "4c5b60aef1b18949e5e772dbe9ee32a0b82c5499afaf048f7028c5a39d7f1598"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "37684832511a3db9c0071c72abc4bf7ec97d02e3821c6c6f4584875997dae71b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "50bbdf597d5556612ad2dd23cfb67dbfd906de8de2047ceaa1ff7acf5476abd4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "431d54b62f54211eed9169c39bad356ca50fa73f8f97e04f737b97f5c51d8394"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "af6dc5003bda0be69feff856895d51882fd891024ea785870807439952b390ad"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "5eae4eb182b8fd4a7cceb1867586da0c4deebb6654c889fb352850a945084e08"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191672, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "d27391f78920777f176b9f099bc83fa88c9eba0168c1e14339067a648dbc55af"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200888, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "0e386c0922d0d38b2699866db837d02382476fe674a69cca8b24f029597ea735"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "ab103cc74f573b3ccb7604815c99413d5da6a35c571e9a40b0f79972351ec692"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187064, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "c1bec9a9212bf984971577ed5c0559931b56eb6f358816967cc50dc5f1eb0f31"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "b0e0e547860dc56eb67275b6f380e67b1fbbe213c1c441c4a4b3364b61d8819c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 192792, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "8a1797c145b6bcd78b7ff1ecf2d4f9146fb9acad2a3c6e24cdd1d3c40e428687"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 202264, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "d9dcec3dc8b139614bf736787142c164b034ea0168f74ed8413804dc7e125a5c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "4475be1aaea3fb3feccdc00ab9e5e55e27ca7eaf06e466fdff75bc12490125a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188056, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "bc775c0f412609947bf5b8704f0e9040d608a90699afbc843a815eeed68692fa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "2c4d380f23281e3430b98d1a7a76d24ba0cabcd425e5f4114e405e08b8250cab"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "d6e47a0544789cdc7a6629e652969d42f064365b98a263ef5941eddb402c38ea"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "e63de3c1f27f45a89a84656fc53336cca1990265eda489d6fb0d1c9a13ba07ec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "4585f91fdcdeac6215364dfeff5f916922c8532be51f897b5293fe46b85e97b8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "b62ecb1c9a3459a5bae986f5714bbea3598ea4805374d9a2904f24716e96f8b4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "21bcc51c88724cef85ca86d7f2e3db96d15038e4e3cef3d9e576089f69b82861"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "b7ee2e1fb837f8d10d53c94160dcfda8fd3f2364feda7bca047f677c20e40010"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "e335155986c7a747ceb50a0d075e7af836aa0556ef28c69caf778a4a4b6055b7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "50020c1d23c61b817c9cbee827477efca6852dcbd52b037a5ade4cb7a50dfd62"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "9fca30b605e63fd5b30ca2fef8502ef02f1f6123796cbf42d9847d1a9c363d7f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "471453a99d7b567964a31f8c12e65fbd456bc6de13953a03aca943a0c10b1288"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "93c2bafaa1bba3e99ab70fa2f18033400ac2f3805f557b2f024d43ea9af9c0bb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "920dbca4b57e45ce408168093629fa963f3bd1049be4654825c1d895bfba2921"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "9eeae6788e1631b036ab9552a4b0f950573f6d4b5abd058d1b163820b7446268"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162144, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "36c50509780be1beaf12f97f781a3914a65010b8b98e299e6b12cb24be8a7d5a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157872, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "d21844eb0e287a466c3b4a7ee2391babd89a8f999585c999354085547480bcae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175456, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "3a7a8723fa036042c87aabd8f5bccf82c0204c9012edb36bbcf75f6f7f5610a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167088, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "f065bd3b8e30d3cdf3cb3e9d7b32dc1d836b2defe84adc2651baf08e48e04b94"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "eb7a3002bd9c9523e4c3349dd7029004c5f9c3cb1a084c22d7fa617492fda0b1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "52ad05a89ec3ae40bea806e6220b9e19ea785472ad453a8ae060159e1202cec6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 155488, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "5674c66577751d1e9b68d6a7f5f4f8af09d0b60b30b9f4947d6bd9d49d0698a8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 153264, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "a212ef7d519fd010f3d87ebe8ef0cd9cac64eb89df5186fe13f84aa3522d2c73"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "af8b57c3b6509a38b543e375fcbcdb176e921475e7f5a041800d019ed589c4a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "c1dc553eff5482d9d4e5d094b1d082924a409c9f3b0e47fc4385c03aaa58a8a2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "42b817666285fbdee64224c6f4fe2687cb7f1954248966f82a53064615f6f3a6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "476ce6f8d2ed77b24a72350fdc7f95007b42dc808dd69f544ea1caa1da29bcc1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163264, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "156a483cdd20a6c6cef51b66436bbd68c03b16dd5cd5d9e5fa5890cd3aa8e7a2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 158992, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "27d1dcb79bd457f522689a7378d285c205cdb252c3145aaf46e946b1c9e497c0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176832, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "2437f502cb56c67ecc55d1fb3c856e1e29745088ec20ab91978e643b61450b6e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168464, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "bdcf13b885c7abf6882c33d1fabcdf1a30e8af31c2b2a88dd0a6b86acc03eb0b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "edc1198c0f0255b61085326627b1d89e08f5e81cf66e67910be77d91c985a508"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "68557f01a7831a03d47ef84f37d9f8d04e7b0748ab04f25764c1dece3fb8e39e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156480, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "9edc6171987804a71f2dd794757df833fd19d1791a9c645a3e06ec8cd05c6282"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 154256, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "e6b97ef2fecfce8c8d22ce731f26e14ab83aaf315ee71a70f512f7c472047c05"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "89d45eda48dc99f1adcbf91b4a7dd3190150d5b1cf4cede8fbf6293bd6e07ac8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "5a434c55df68c248c91522f20eefb46c70dd908d688884fc011670c47a9b208c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "05aba0d7ae667211e39925c1c8bbd0f7839c6d0111f5da320c6413e9fde15a75"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "077c95d69d4d01aa51162c2b1496715b38ac013a5436a9bfe116caa73212e484"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "b40a3e8af629317ffffc078a577f588ce73533ca1cd7cf738f058e5b31c69140"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "902e173e679a98e1298a88be41d890ab8aeba1c4fc7bcdbd17c6dd6b82bcaeef"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "e60106d277b997ff945d5e96d45804a0cfcbd3c31215714e75d703e6573bf540"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "9cd8c5e50d2f2bbeeae0faa26a2f320d01a6f0545d5fb2ae09ba91e87e48672d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 213488, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "4a51c47b5ebc4c8dfa4f6dcf6e18a9ecb0ceb0168745f4b26e051558ffc3e561"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 213312, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "ed6a4b469f26e84aa9180376d1d15d484d5325a3280c4476cfdad11c956feebb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 213504, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "57a89d40f24e7fce8a3d78dee428627dbaa9f2e813ffe66fae0c336f098f348a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 213328, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "e25031dd716de3b4fd4e83ca7deb2dcde168d8abe6ac3750a23aa68289d12efc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "632e49cd4fb7d16ded65b53067252516b8140e9c21753913275260e4463e83cf"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "823bcab85fb25a4b48f0fac213e391571971f01d0d0ddda72dc04cb76c70479b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "6a72d297a9e958cc95360ac6d1b35fcdf5286b6085b5a191f642a34803c809a0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "8fbc51aeee9cc2a5606307b9a7457f6f7d897262c40e059946c512476f860670"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "4e19860e014a3e1ea86959ac7564532442e54cc01501bb5b27d7b7f9d50618b4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "a5b65146e7c177d17cc1e2c96c1fc626478c1f486c66c5f2c8f356ffe1f7e976"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "ebf6708d26099014ea42d3ebd6f71f1e42445af216b9fefa37bcf951e737ef6d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "32a4697d9e3492ed1b538bf9ba0d0e847391d94e0fdd4e1342995c2ec2a76d4f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "ee6add0d80e6d974d0bc85d34a08b20065a82748753ccc84d159366b6286429d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "caf3409ce254d0a1dfbbb9743bbab0cf52aaf68be9fecf01c84bb870b2107c24"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "e4fcd11014193992c2fa4ee4dbd6eb3eaefa6f6f9639b5e6e38e7f42ce833819"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "9c68e2070120069d2351e1ebc6cca32e4a6d5e13faabdb7a1fcdee53bed1f4a4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "b9f838e119b838c116b847238b7221de2a89b24c8bc6647c809f0198aacbf3d5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "00d631a3fd3e0619f341aa39b1539061d4c460a83512467494170dd1554bf5ce"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "5019a22df4265913f0fb3d716beacd51c397fa02e3a5faea32c77412e7a0b5a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "e2cafdd3968fdf01f5f51041f206fddf773dbaa96f66d9c36cc92d92f53cbe75"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "8bdebd61182e0cecbcf9a7fc12afd141919eea41a5b593d660d4a33b28f9110a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "310d37eb64526335c804f0205dbea9bb7db83d522c50180b4c22be99abf7d5dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "fcffd0c110c30c416a9c66d381d815dadf8686f12d2570ee9750fc6a5ad77ddb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "9773a453630d1754fe19d0e773c789e0f4e0b7c0bc3858615db6c5ac39638781"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "4fb965256cb0ed8766f39138abfca7a85f4da0a00b6db58c4d85ccdadda87e97"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "80ed8ad9b3d562052049bd2d2670257008f4a8ac905218920ea1a008565e341e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "a8bfaaca4a8c36cfbb46564f149ad466606160a1ffc7a816f58635e4c0f12f7b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "68097ef87f891e0b3e9d4d0a47ce783f3cd07caf58e5b4d77ae0e734ebfaab95"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "04ab2d1b40a5f6c5a3a644328e3dd1dc7b0dd480e9ec121d7af739bbd3c74aed"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "64c5107d8b775c148b3ef8073b1fc5b3b425e388dbf820530dc6b62b19ee252d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "b8c4bc928a36ee1c24e117d480b59add5096811ac3f105064538b2c38e6f96ec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "2dfca2f9677068f8b855f7d7ad13673cb1dcfe8a119c5b76859f5574e8b13340"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "6ed4c0bdb69bd8021716d70af1cbb8c92ccd0dae478ce3bc5f6d19194d285d9e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "b8e7a56790b8e35c189a480e41d73b567e3c579387ddd474ec803051cbd659bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "d3ee52743a61fd8532ae8105e49079359d81a4d0ba02ed46d0f5c6933a498fe0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "be64d6fd41e022546dab78e28c466bcb78a66404fc262f97040bed88b6a16ee5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "87094d342756a98c0e499f76c2cc75a705bacc605f2a5a157c66fdad15f2e123"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "1967da5c1b4d486533baa49d5b5558bc4d5f6a41a5a780b1efed88c34bb50c9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a19140047086729b9acc578e63a349081827c1f489195adeb94e8bf7dcd7558c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "5e6866fffe29289f3145c1deb2fd1c9211299f7f30f8ffcb6893fab43e603b47"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "8187ab91d66f446b82f033ec4969ed34b30e54267f7c33ec3c74509162a26d6f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "8d73cc4b31fab2c656e0e7537b2b1cdeb68711c07f74cd3a655102c76d336d30"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "e3358d22db929c9b1dbbc1ae60a7a21c5bdae44c92d9b2fde562df3ba1e2131e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "d9fe83b7e75ca3c294e735c49de53792e9d96bd4f2b0921ed3ab7c8271783f83"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "a55b3215a308731055246fa8ea70c9b0660b5d8041f322c1a3b97257acafbd53"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "7d101623a96e0ece4f2adf427d88260a47a6b5cec50431e97b6dc0927cc3e313"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "c579cd7743c4cb9ac379878b7544a3f8397d5a3fef510cc405deafd52ba9c28d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "504d8a3853ee8a49c2632ceb1fe2d2608837914dd1a77a3628789cc5944e3744"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "42270cfb5f445f81bea57de7bd99a4378e08597fcab14dfab185545ffd71328f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "dbd1574a2d83ab9cbc43c59ac19a1f792ed86b35271b26b9dbb70b91f75b1dea"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "05b2ad078fca8423e5f9162e43e4b67f8186b70a2db8ea00af7a1c4205572ae8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "b015abe28919e167b24d2c933e414f65c0a551a1048fb8aa1b159bcbd10ee6cd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "24ee6e09d183c08493f92fcefdcfdb961979635a978a30a0f975ab2583962be9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 195256, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "4d695869b459332be4a6cb59a5c909aece7bcb34476408a10be4771efb8d0bf1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 208568, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "4596e3d098cf2096650eb21c96e2b5554ad9ed64b5c6caaedbcd221a339445a2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "835828d7ccc181f0651340ad21d968d3b4c6162de2a8aa48eb1117539b8b379c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 188600, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "1929875711455bc044e8d3e7ef4fb394ce76c654e9599680dfee9217460b60f7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214224, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "860de3437607dfbe7518d1b58b9390a59dda216330a66ab03217b9383f05e4e9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 196376, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "bf85fba4ca2ca6ba3ccf9b757d252278e6bd9cb2524950f74ea73419924c7fd0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 209944, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "b076c28be48ca9631df5177bf586b957a71c565118b5eb1da1cea2d0fab6f11c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181456, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "74405e89e35b6a11e8ec5f04179d605abc455e1402e6ae9187c07be1d2c9dc8c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 189592, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "03328cfc285ad07cd5fd58d56c53cb2f91e404dea39de18519b8deb942f6de2a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "6750f809d7d038591312c03d34e4b9b03a84dce3e939891d2a42efde1bcb6b92"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "1a90097b633d31df10ec8e2d465789c3ec94e44ad20f70a322d07b143050fb8d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "97db3c51a8b41b81061b427d5d2cfe27b3f708f9c86627ef8295fc0d8a0ba78e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "eee562d65e2d4a4ec68615e7071cd6791993c8830edd21a29ca08d23c92841f4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "3d46ebd82de459d825a955329b0bc0171cc83192996a6e28e75c518504cce8fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214208, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "5cc440f5c5cc66a29ab8155066f4195da98891f86ef785f952a1204cf5f6c259"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "dbac258fcbb9ef18e1f608296e9509eaded463df7620d0116eabc05b21de7041"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "1546a68f72a942900515dbb9705fb5a576256335cb55629071bb561f44a958a9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181440, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "5cf09fb7cf5552ac287bf1dd82f7162d0f4548433ae42da8bb7efd76b3162941"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "8f77976e741575017704b25a38175a9449df40bd9876e6d4929772f9a5cf7d28"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 214352, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "b5e6a7b226079e17d8246f3f8082236e92e404c6ead60d8435dd7144826d21e0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 214352, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "bf4ab950ac49fbccc98de33fbed46cecb6ab0129e73f13d4cf615ba28af47ae9"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 214176, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "42946d94f2e4a3d1545b2d7e3f39000f4886e50e9077618b4c5aeb9b2252a22c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 214176, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "dee37ef31367d101327822d766a1eaeb64749fe41e529574d9484a2248af86bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 166240, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "c59ca42408eaddc349c5c3db329c189e60a5a527c45593ae9f21fdbe67badc33"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "22fed9e79d5035a85ecc945ec6c9ff5afddc39cd6a66e556f5c9c4d21af31712"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 183648, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "72d9d8769728fef01383564887166c1d8b23021d02f959d12f5f9725e1c76dfa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "91f2892380302ce88f3d26462f62e5b94f198b9cff703c401801f439bfe25496"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 181584, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "5723adab21f0cc9eaced3020a4d71b481f0cd6c71faa69b54f3476ee62667241"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 181408, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "e32e0f47a34d582496dc0cb7d96a5de66dca1fa664942455e0d1064610659bc4"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 157536, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "694074df4ff22ce0fe5265e8c98d0768bd8e0f1c8fd51f109d008c91f68ec14d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "e6a7a6703e3850eeafccea1408be70d8f30c43133b726d8e2339a02f2258254d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 214368, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c1d2353519a47d5fb3b7fd003745d52aaec72685949526bacdf53ec790f59044"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 214368, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "cc5a55c345e85109759926ea469d3e3cf5a6afdb9cb57ceb3392605aef441dea"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 214192, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "f05e852d4be28652f8977016361e77495157f64a5a70b3e46ac762256bb140e2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 214192, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "2a1ecb6c562dfbef94cfecb3f1b54787fb41cc1439b6736cb4a6d6d7560ad604"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 167360, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "fd96299000da8227ccd59e8c1d3ef8856e8c1f2bc0f9a8318fef4b5acdfa7e48"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 163088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "0cc620cc019ad8e7580b751912d28860bc94d9af39beac4d143b57b16f9bde60"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 185024, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "424238e3060a0f18758ec834d60bc2910ab9cda4620de9c902643882bcedcb3d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 176656, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "ef58506b239b383a01fe6bbd7ddb4e19c13668332e2feae1900190cec61fc92a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 181600, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "55eef3976b2e72c3130d7f47f300ad27a927586635df8d06853a75846f6e7255"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 181424, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "740a29a0c53448c661ae0d4e3b6751db82a046f32da30e7843c13a7482100479"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 158528, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "8b2375cd3e71a36530b2ae4ee989e77a32015659940b6dbb372c77bf964590dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 156304, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "2ba6c7614d93fcee38ef87f6d79f6d66d4a0090f9ce3703caf5ac1aa6c906454"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "6d39049f64352c0efd4907e4aacc4a8f7ef2da1f6a51e347e636c949ca2bf3fd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "9cfe3c57b5b49c346f46c0a907d8a1f36f9817f578bd593387f29d00d5bf6b83"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "0d7d04f548072c8796b490c3659025a82c044d4207e9229ff7bb5983d40236f6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "0aa31bcc9230783b2d32f67a4ea980577b97cc8cbb8a136973f0121c0e3a1d41"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "5859934e2164c4e31e921a112748bf816dca4044e45be19bb29fbbf0cb08847f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "50fbf6131b46ca679ab06d35264e8d37e6aab0a59d80bc517394feb1be9a691d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "fb492e0ddebfe210216ed3a31e981afbd73201036bccd0a1ebb25c60d89c6ac8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "a31d479035d2a3f27924e33514d96028b851407f0d3bc8d3f3358336b241e2ce"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 41376, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "645658954612d11b1ab76dce95470f4e88602895ab8bab3d3a6527b48e84a3c5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 41200, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "70cb1846b07eb3426feb366cfd06b12cb59f4b3f86994428a1ace3076cc91a28"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 41392, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "a9017d3373cdf288077bb799f951b676beb66baa5905cf6e116c9738d343facb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 41216, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "30f5208d1f85e461281a8f3daba7c8626c5fab2366b6299ae0012becda29004c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "10fd807da3074aaf21730b8694282da8a1e202abba8f2dd03de47630aedc815c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "3b2c88925af540fad45312698c09ce6aa464d71c19a2b6316b07a96dae6499c2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "f6334195de522a3375ae979592d329b179284b62166b9804f619be8851439df7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "5390f0755e69d7ca278ea5c344bcea13d91d398ec391389b5bc29345e38bde80"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "908eef73f279ba719d8b5d29c4d40c153939b50ce0ca15e56c967cb39b96ef4b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "ca86918a3b9a0529b636a99c7ae086c269d4e1202163f3e58e5b1dce89f04813"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "eca5af9b69b5dd40280186b3e7f24a5064814579209d2190e222e124996b8ca0"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "7fd8f3a21e40bcf0b99af5a0b15eb0501ce39a6fdd1b1bb61e6908c94775145d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "bebc74e215f6dbf984b97d16c4a83885b31ee07df0687fe5f1beec96f1c98bc6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "b7608831f2a16768ac26673ec0942033fc87de45c98ca481bca1d7e11c14ab9f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "3d97db12d08bf2d7b43643db1a75dc5ebbb8439e40576933cf1ea6194392ef88"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "5d73a808fb5605429ba9777c7bea5dba7c2978e59be9ef16f3330fbe3e71fd29"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "b8b8e80702ec1862cf5ab1f34ca8a152c3f027bf53093cb9e69ffd3fa29b539f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "86990e7b6d7341b72535245f828421c567889b924e03058467c4e32c56202c33"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "eda319554693f80b93e5a826338f2b9278a1985579b3b0d3bad942822c90d812"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "66cc4541b8038b67896ad2bdbf676dc69d56488a921e90cab0fad3e80b7f7e3f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "9ac377500a29f68397c4686ac64f29792304b9c1f5c06ef93500463ff7723688"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "a23806a8e7686daf66eeafabf3bff07576e57b03ab377b2997e39adfa5b5ab5a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "6abba1a8577628830d11d1d46c30b7b7cde72ea1b4b9894f3276b4fed3387296"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "c284dbb6aca9ba4a79af62b8888a697a4dd8dd79e17ed3d873d21a2a77aeec08"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "b37b6709c68d706ddf856a248b7b7923f287945e837a8bbc5c31367443477a7c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "78d2f6cd9e0494d629a2353ce76be354b151d96d1b48cbd742f32034573e4f31"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "78642bbb66c16fa6ccb5bdedeac321bd699e1dc36f84c0db44381b6908dfc5d7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "106cb46241d902ed3d2ac9e46c91eb7588352bc5a0fe3d8ed314a2f35c0a6ea8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "790567f552fad5b6e3e27e2cfc531d26d4315942228879527cd0979a45cbbfec"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "9c3bc95d8bfed873bf2add7ffa100574ff0d2797640f691a9d2bb951335ef8fc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "82250ebf28c6c7f4de9358de3a4eec24dcc15f77d40f183925ed4572c86c572a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "f6bc396c839ab2a20bbca6afeaf63d681a97aecaf2792d0fff09898dc2fe0892"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "2c12c6115c9efe2a94ea8568476aa185e560c4859b18f60e5c18db0e921ef741"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "90acc7cf826e171dc75ab6eb677f76b725ffb7ef24ed3b84f9d7c89f7e607e78"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "ed0cc9040c40cce893ea2ef65cbec6bd5cd188a9f09e5888fef105330453bbe3"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "9ce18937a91706da25facd259b29e55355032ea99710cb0e5cd8e2ffc30a0037"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "0a123876a4bbb85616d003e95d9f6a16f2b48f987d7d8dadab8adb4292ce1779"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "db568cf6361136961251835ec21fb38956f81d9edddf87ecc1dfe785b7abb799"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "45fc5d42b85de17818f6de8b2500bed2bcfd40246004adec393e8f38005a7677"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "8f0f3f90e3c5b5bbb0385dada04d52ca0c4c1c338c36ac82acb04ddb31061938"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "961b43b826878eec60a12914dfe4c2f5c61e1ed6ffb11ae81dc23f87eb473b90"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "627b91d5794d489efd8910b8b4475a8798a8248841c9e7cbed5bd13a5b57d4ee"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "52480a2d53213007537adb11d0996a7b371cfb3caf7657977740fbe802eb2b8a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "b87dd37827226f08155883495da6cf97773c766701b20b5ec7e1f8dfdf255b8d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "e0e3cc4c11532b2d423ccc18c6e6ffe9536bb52221ad419f6ecea517b3e83b3c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "448e079d8036739862698d8f6ba0fbe705a2613ecc521ba4a405553dffd8595c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "f99a15f8e2af39ac543adf6689c5a90c0f129e44302b17a5a9842228ec66b64b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "9f65649857c416b14ed61022fd29e884ff30ae76acff9c3bbf5557b65f62ed78"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "89a566386dbd77dfa3a4edf411c830ceff0aa8a617cb27b0a6252b4d16c284dd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "52c8d4b022bccda218a09d92d5635d8375285328d9363a8017ecae5dee0ea12e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "5d562340011f350becc16cca89ff1f673536f30c9a64f83913a4f15db12c6882"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "baeed1bc718f3071656585be2df706e9a1e0a3ccf3d038cb5414ca25039cf349"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "d9700a1cdb25c4d842ae4154d0d294d4b8aedd2823672e0b1f609b7956313f35"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "0a251597f1a70a12566ae15b365304ca6bc0880dc9068cd743a67ec8e8696214"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "730f7091479246f0ebd5fc17b64d3d77aa6745db65102ad9976cd6c3fdf8a874"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "892c46eedf080d99d54ba0cb44c5b59eca0e5e56e7dabb8a8d3f02b48afb551c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "498bbcf4971a32f3ed2247f3ee674ab60f420e1fd313ba6c973329c7df5e79e7"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f410d990fe92bbb94bf028e45e828be82c4b7a8f490e1f51f7977dcd8a7ce942"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "af4ebd83cb5fdb90e4ddede978e2326da32ba243aeae901f3e1d4b272c6caf5c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "c11beeb281154733a8fe9a28886a7e4eb1fceef9706c2472201cfb7fa9bd2b0b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "16d0f3b009796ebdc5ec9dfe2bb0a1e77cee0a1db76f16f39934475250dce6db"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 190792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "7101b98cfca023f4abdb9c039e1089b09fc11fc571277e3c1e68534cd20d00a2"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 197960, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "093ab04169b2b7f021b508d6418e2c69cea20016e75b19120c638080d55b2a4f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "af9e892b83b6538a3bec5a54c31cf351335003c92e47396a6830467b11cc196d"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 187208, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "a3c96dec9acd6e008c80f6db6aca32f7fa7f8f8a2cb1dc6a56ddc233d2deb894"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157024, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "c9346c60e982a22338947bd23167382622c6992e4f0898a4ac8775f51d4145d1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 191912, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "5a70b36de036f21782ae24d0a286d234ea7683202577a342ed4f49ad91c6fbdc"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 199336, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "57815ded2b292cbff4085d354b5aa245fc53755d8edb02f81f66decc9bccb9b5"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152928, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "cd1cee435ceceac9f8244aec328b3df64a3722345e4f6449d590e792e050d681"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 188200, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "a192f43ea8ea502824780766b0bee6d0e960d30b00f2d490f3390abfcd77c54a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "da1e13dcc753b6c1723f190994ef45ef5df94bebcadd1a42b29a0609c2499a9b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "9fd0c7cd728f153609eebdf06255e77e9df6919c41a6343e9629b2962fd8cc98"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "223851df7ff808d861bc7d5fca6707afcb83356972d78b4ba365445e7c20fc02"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "029456a298b8e23d5ed1172ffd66806f9f8d577fb37b4f7de053a8b010610520"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "8dc85b2cbe76fdd24b5cbb1e1a5c6022a97f9e486a42511ab4079bc2bca0458b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 157008, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "8453edca0de658d470bddec52d445d0e93f8f82d472fb1a16402c1c8ccf0e9f1"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "92281a481e89180835b98a6a3a2dd2b049d85ffb05b43a9abd92096172ae77fb"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "12cf43ffea002a4c2403daf1604e6004b994e28ca3d767ad2fb31857092464bd"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152912, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "9c16a916e8c09a6df1c0ce6046d2ee4225a2ed7df6c8c77ff9b5e520e236a864"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "8398d8b7e1f42c9236e4769e68f0bada30f4a9bada87c5557f3f4c4c2d092952"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 42240, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "e9891e246ca4bfdcb2795d7473ebe530749e0a2e2d01acdc09f97c7f838bdf8b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 165360, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "0ea51b3ecd056b58619c0d1e19554b118a2d88fc4276c2df66890ef581dfb06f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 42064, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "763b7f10a71c7c0604db68248860f7ec402a740ad81f950e365f0cda80f9a488"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 156976, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "4906af6de54e56daee28f08e3f12efe1c23131bee0c98dbc263448f73bc5e127"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 158192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "c58c472e334e49d4a0b26a84a81814d12501f8f9a82db2978ba1ceff43f7e146"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 155968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "e2060393c080074f04916050eeb76184ca04f0f59c8a57183bfeb4a4479e7d0c"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 167408, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "6c5886636f64926ecc9db040d4339263d15eae56fb404b4a6654162c1ea46b2a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 163136, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "e6e009c80466b900c31130bd9b5ed089db17b972d56838b8c39adc9142295a40"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 157168, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "1a95efdcdebd0d4b780c886bdd756cde5c52800e197971a8c8ee109f03350016"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 152880, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "134336b1627eeb21187cb024854bd3cd2a5fb78c437b20b2b68527c78f70ce80"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 153584, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "90489228d1c5b8975c33a31bc02dcbc59d2a05397066133f8af236c4412fc19f"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 152384, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "997963191c264e4ee8385f375a801c404f1046d85756683af37f03170268b97e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 42256, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "70bb9722d1c480135ef0cff8f92d3c91f89cd18f8b820ed08476b3601336e680"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 165376, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "4269e36e1d0170c25ee0ac1aa6dd580425fee4e2d6d28b96cffbf829a5da875a"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 42080, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "189209b939588d5c3fd7c2fa849120f6a0f42d61577dc3ef1f0a0705d56624b6"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 156992, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "7dfc36a9702bdb354def24ed194c8ad783805b29f5227af326e58dd8620ecd13"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 159312, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "cda0da28b6b110e716a1578268da0af2c51acd12a84fdcbf7c0bc6f126ae9a20"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 157088, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "2904da9643405368e532ee92c93e3bfe1f4fb66160cce5d18a8634b1c9b4ffc8"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168784, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "ed570ab9a99ccdae406b80714d0e1bfa2d6853da9528656a7ade1ef243f7d18e"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 164512, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "d38707ebc9cc90fda746c1e5230545bb83dc1d2dda64fbc6066b9caf6bc37d34"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 157184, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "cbc0a5e5b88f423f30e6be5361785671aa8d35fbcf804bf1fe0209f9457232ae"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 152896, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "a9cd84f5066bde5f63cb1f30cf56e9a42a41ed189856ebaaf4e99d643beef16b"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 154576, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "a0ba9de164a98740fecfc4219cf8d186e3f5eddf25a05cc7ef21a290e374b7fa"}, +{ DATA_TYPE_E4M3, DATA_TYPE_E4M3, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvE4m3OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 153376, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "72419ea374d1ec6c403290899f073388a7c0bafc6da040fe4b206d1ee716d1da"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "ab428208e9b148b340525957023f94b18860ae6746815e0b50b8535033c1f744"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "4c64bb960aafdd07445bef4051021e23a84135a3baf73e5a7c7785281ebd14d4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "8e4567805b400ccdbc3a3a89179bd971e890a8734c0ca3302f4b2dbf479128fd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "073e22840ef8c41ff09c03df05ffae801ee684fb6322211ae862774b6b519fb1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "87884a0c73c2ba7b351fbe27f1dd1aa223a778779aaa6c802e33f37f8ef37a66"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "58a195030eb52e4fe174f913ba2555234375e3dc060ba1aa2fcb3c7e97d0f628"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "9e06d2eaec9f1ec0ecb62399dd793c1c12eb4e4ac26e55270b7cd0c1f199faec"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "d0eaaebff676a47b90d5c32c62a1f6a467a79ff7eeedf2a5667127ab4b91bc6f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 164288, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "50240da19fe6daae9389bf95d05a482e15aa650ec6acf92e99a46aa14ed68b63"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 164112, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "f2a8bcecf18751ebb7f5e39fafad8c43b79656f0a52b79bea028cf8116ca5eda"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 164304, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7cb3568bb1f645d2b49b63cd8f3e58dc326dc3e7cfa8a724bddcc24396930394"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 164128, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "d9238048b6957df0380ec3b7dac169778d3d65df27ce8a2b298d4f218500f4fd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "73aad2d86d54d360f7e528cebbba081eae7ad37c8fb39dc42d45b65cf8bb0554"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "6832c8908a6937671b6dc3b0524cd494ce74f3f0006709865384aa0fdc4321c9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "7d960c5bfcaccc440d2b0c74a3185edc8018c087a41104b89fc1f17d5fc3b6de"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "8f72afc44afb61e618e9e5d8ca3aa8698c1cbe46cf60755917ce3664c19f8699"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "7bc39b4aa49783715ae1da601abce59123ee0f55a11af76ab1eab0c847338a0c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "685565ccbc474deeb3e50f4ce0d96a5f94713c95445937616b0c5bd0a6cd4a77"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "b67a061fafa893923677f1361b0b40056b52ba8ecbb9e1fbc5f586543fdc6a4c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "e4d819a42dca877fb03f20ede592477c83952796b4b53a71a2a03ce576f85f3d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "eebaa575d5789fb9c192623e665241baf22a51e1c1310bdcdceea1f1f3063093"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "b4c1fe4f83e4475d18889d640b0e8ada2b4a2cb48a6076e023fa8a3809ee602f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "d71c878bf2d8bb5dc417cb173dcea09f1dd24fedf3ab6aa16d97855b4957707e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "08f07d793f349d498dd88231615b4f70df0823cd87453fd9b0e903d941ddf75d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "996ec8dce22f633d86d9173b21a30aad1107a55ad0799777a3b305b634b7fbf5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "2243d9b4cd75b2a59b2075700ff466e90df3a1e1c2b813018f200dcc40034814"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "7c83c414f01678c4cccabd1bea94389f226734ad1b1d58ad0df948e94a909a42"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "8c02d6d9c4edf38126ff0ad3fc293014e2a4176af68af905c6210905ef90ebf2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "c0c68736f020d384c4434e3e7ef3033481753608c157d3604b8d9830f936a342"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "99cbc85ca2b7d6eef910d9789cdf0b3eaa2f354672ddaca195b021c940b77bcc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "16bee39a57292f6f48ea00cfd2ae9c9019c5917135f036cb3578e01f809938a4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "b927e42b1a3e28bda76f763e234fe4634e90717bc73c8534c5618323a4c8c057"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "9324b5bc54ade9abf5b1e87d401e017a8f8154b6b4f1f8b30c79a363f6d2fb42"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "8cf7255c8d73b8eb080c4692c1807da0656ace4b2b875e5990850b354a5e0e80"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "94d20d35c424b2f3cf93207aee9fb482c6d94d6e0a3e3eed7f119b2f8728d7f7"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "e5779dc621bfd659c4a11a5599c885c0c8245afcc52c287271e35ffb909cdf1d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "90100dc9b3d55149df19f9969d5ebd7d8c98b89af9fd5e7a98ca367a34b07954"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "d7fc0deba2e3af2394d38593b4bfbf91e32b0170551af8275473419f4354f8e3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "2540eb0801db6be4bd61580a8df0ac46e79b01507e4dbd124198fddf1a25fb03"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "82c4bf7782d4d7160a96e2dea97cd19b2b609306d218fc5efcd0cd08b044fc79"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "83414d9e9ca0b7d288b52e1ffc09bfa7cbd70f945816df49ed4a48bf107c9f6b"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "891b4076007e38e6df92e7ec74aef6beed3722bfc356da15d5a70faf77d1f3d5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "dec485c517e83b13da2ce66d4fe465dc7c0d4cee436c0a40779d93bfe7e0955c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "ab4e2521e688bc9595eb62ae5707ef20fde79aed214a4a52c3d227796628e1a3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "aba95c9d5540c1d0215629e1a689f2ff38b174a45fee44c872b57786210dac63"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "eaddd69e0288466659bdb20fbd142f55e63db7bb848c44b86ce898c8d838c540"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "6e18896babc9b1b1ac0243b0fa9ae9763d76ab7e9727973afa251329e89377d1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "27cb305124b7acb6d175ebca9715a865fc0089323952f70d0bee4a8cc62c4309"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "c2cebecb2bd2bddfa8aba319bc3972accb0a852155f424a6d49c3b03ab89d0d2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "56cc30f6f35c6521686236611d4f31ce930d40895428ce526199a5f5e8041a07"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "f2e9efb31e546a60e94d8595bdcdd074d40256570a569af07d2693775cf0bb50"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "427a39338c295c64fd270cccb4ec8e6d580b715d8db9040deb85a8235859fdce"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "65318fc2c2f4716fa93a531ffe1ea3b870ad50cb76df8d1ffceba3aec8a858f5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "51afe5567e49b9c4d89369ecf23d3bd1644dd174f8b68c5b2a373f6080270f01"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "919e1f2a2da6a595cba0cd64b2cf94a46128f3e79a6efe85de1ec8a36bcdb133"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "02eb951afb9d0caa86ff4e44e92b82803109a1a4effe6d7a3c5aa436155abd0e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "5ba1eac5ac7e650990f17f2a1f6e8ca5122f5aad9fce4eae7cdb6f5e0d067630"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "2adf1a348e1e8520d5c08a4b5d4d1fd85a6b4e5e696536ca034eb79a826007b0"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "1d6ace6a7a1013fbeb5a7909fc4aa417988708643e4bfc73d8abeedf0da931c3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "94b09a6cafdfdbec96be0496f4f3b7115199251d977dc1ab3fcf6348c27a58ad"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "f29e5e432fb3dab9d1e0b72648da534e12b78032be3da8bae6d9e6147fd1f1fb"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "d0ab763a1715e0b85769ffab1c6d4c808f38765890b94ff906b5871f6dbfc65e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "d08c963111466ebf012214432c423b7c58b11b60ca55a131146576834fc8cccc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "01a823b537d7e9901a44f3bac33a350e714c6a9b631f7c00f0aa08391ac5ba98"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "d952277ed590c2514eaadbe8afa0995cc89fee90a528b90e25ed733bd35460f4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "cc08750aa2f06f2b9baf153bcac111fae547bdaf40979b6cae543a37c0237dc3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "b1b34080be47673dea9d04a060dbe2682cfbc6e21dfe2246c490272822064ee2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "130df275ec67cd7e27e004b2467cefcb500eeead62c5dc7787da58bcafa11189"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "aa198f367d49c33a222e21787d51a9e1c7a75ee125f055a58468f9760c1f6ea6"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 183400, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "363f5ae398e317f3eef6794e68c344d1db24302f8a37eeef4c0f712765fa41dd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 200808, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "d9fa5e6aa3391638d9eb665db9134123178b97b212d2364c56fe3236cf56d068"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "d1d4201ba1b0dda86c8f5c151518e0325b12f7390a62fbcd564b8ab7fd824443"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 174696, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "d2a18f8bed81d95ae7a9537261331cb44faa4d7975b91bd7876e1fae5e105b24"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164992, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "28f62232a7f1a85192246ad5223d3716f7cdf1274a225ef242164c0146893286"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 180408, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "8787516e15b5b72dc0b4751a38e29bb584e9aa08c4f2ea4904128c685aad8527"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 193976, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "cc9c69bfca128a08c47a52cfc63c73ab9183357ccd4371a228d690aa20947ff8"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148608, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "abe7c209b386bab4fb15db1a11eaf42b669b61f3e45c2796a9c5c1e946994416"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 173624, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "9e1c5fd5247701ba44cce22125f55306f8fc2224d699f1105385b0b77677db34"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "f7f5049893ee0272df9584708a758f5543b8919e9bfe7aeefc13563913efc9ac"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "6416465b839cbdce13cad59ea6fa51b046f5a3ff397a78c7c562d0b05ac06033"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "5567ea524fd73941cb6dc9c59e933a5ad6a2620380d083fa809d5111037aff83"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "e2c5a8563f67ce8e3be5e084b5823a7546ac1b7abdb5e17f5b776441beac8b6a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "89b877eee9b4eff51d489fb90a1a48ee8845e7ffa77a9acc8fd5e53a67562a24"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164976, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "6b9f1a0f1794c5cafee1d91579113463dcad79bc16dfbb06633dfa57dcfb2a68"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "d251eb538c78e03c08862e0306b14c0aeacf619077c6976fbaf0f0b412973df9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "d3755ce4985f7d36cd56d3b4d3aba6ccc1ba7530a93bc91df918a3efb4db3b7f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148592, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "431545422e9e4f9d5e59cdaf86d5d56c6cf52f6d179cd7e1334ba4708bd7a366"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "6ea981776924ac482672b86756ec31672fb31f464035685e0412e29cfa998c28"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 165152, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "892ddef84387c28c0d9b8338e6792c0ef03bc5e501551efc66f66458774e57c9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197904, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "e9b9981267e4d88aab098a03f874e348968939840a9daa8290c2057070c773a4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 164976, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "253c86bb62e31011a27bd8ed8d99d62842bdaa4a9b3015c2886cad9a43287bb9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 164944, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "0c17382999c97ae5994f4a011b9a026492bf2569302de48b8e8919336da09757"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 153872, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "ff452cfed559dc2c533717c9825259071e67d609ed631dc0a03883b192f44c7e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 149600, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "93e29915c6e86525acef6aa7c9eb835a10025b475985b5b767797fb02a2f3216"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 175376, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "06903b08d6495c01832fc38c8af5a6d23cd9ab6dadaa5e9667752c2edd14f4ff"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 167008, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "76e78f2630ece278586c5ff861a9c3f5be6b80f39022cceb8cb6b77be7b7fc4f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165136, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "253020f141d06fe5760e89b42fb83985c3ec295c21fd281ee0802e28a472bca6"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 148560, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "d53a1554a10054a81e968e28915577c75ade8dbfb3c4a3af4919cbf85be073d5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 143120, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "b13079648c1e546e4e62165b26f3016010b311d62bf41d69f2421170d56c87e0"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 140896, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "ce26432227028378b72192a4d1fe5066ec238feabbb33ebb66756fd221b89a64"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 165168, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "43c62ce209690d17127b4a1be6c4e9cce9d8da4e9a937b7e06ac3df9e5f868bb"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197920, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "d6e842eea5fdf2799dfae77278a01f35e341b8454f7a8339b9a2e1b94bf45e6b"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 164992, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "4fc54108687292b9a3d500c9b23f10b436fa26d0a468b972c98596cf0c3b0913"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 164960, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "c05dc273ef7314b007f7171673975d402ce1037dc0314a48d02de2725f88384f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 150880, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "9d1ed6f12fbc6be1111e348b513349e0bc1151929fc1b017c3d3ef3ba68d0d31"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 146608, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "d6350a06ba0cd3ea4ee19047564a28a038f8f39fef821e7986ba0d6d87569dc9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 168544, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "556604d7d1e26f9d7746b1b1fbd16573f249033cfcf18060555649b7f6edfbaa"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 160176, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "7c54ca184a8d6b5c7d160e03613b9e3609ad70aaecaf6cef27a8bb8c4c038af6"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165152, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "56e2091cdcc9640976073f41cfd792c7c3f49e773b8bd64e999c7313506a57bb"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 148576, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "40d7d74c71b4baeff8af066575df6bc9ea07ede99f50f2428e60df922743cb27"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 142048, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "39a97fc9857cb4bf1bd9e7d3fc212b051edab9827146988a774c4ce0bc6d196d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 128, 128, 128, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H128PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 139824, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "f0b47899041420a2572488d0b175df67b74f63b29706f9f102ef022360ff2ccf"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "e2ede27ff81870ca5fe94df193b8aa8f78d3b24b39c1cc1daaf206d784dc47df"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "c73d4f181296fdae2823f2089f9626b7049786d1d8e927a0d3a3a33c92be9a7f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "e67a600d7291247fae8697debdbd024b776412cbaa0674bfbd42cc773af5518d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "7692e4fbcd8b54c67e5bc0af16f00637926f43355ba6b28d1b71c6542f37fffc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "1a76fd96796ea4daf0ab9b51013260f3c02840cae74d2872b969ca1254b4a957"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "f4746c690708d6684ac49053d938a809e5dfddabbb353ad6ddcbace2e3605269"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "95ff45e69fff32c9cb64716daec483e78fd1122f0eb4faabb8eeaf26352118f9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "fb0245f31e4c993488714802023e46cc8898eb0c10adbc3038b0461ac503cc87"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 197008, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "c0b22266a0336c52d8d45acec237f2955679c15f2781d37f519bfa7e9b562526"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 196832, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "e37fc98d6a7f6181234ce23a8a2b613fcfca0e42676f23eadca4f5d2838955b7"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197024, 384, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "7a980b559308dad2c4318627180a6e6e36ed4d23cd4be12071fd4cc830c03256"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 196848, 384, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "66892460d3c28df764ef1f47642317e9f2a76c40c4b5064be7cb2789bdcc252f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "6736eedb1eb47495336b1ce57e4fd01fd7ece46b8dd080373692154012adfa34"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "1d4af0880e99ebda56c05551f585b8968c3f80115c4a7c90f20e890fdb95aab0"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "bd73efed5de0531ebb2b092c08841664df062c3f3c1a4ae7e83ec9944f2b6e5a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "4f53c1a3fd85baa142f7a49557058ccdf65009e708a54a9864a8efc397e1918a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "f0b1f84e2231747d51a212717c2eec353704895afbcb7dc2202c3beed53657b6"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "7bf50393a703807633bff5b4218e0df8560041da74a6147f0d2752d4d9a85e96"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "5f763dcd2d61dcf39fe8b8d452addba501a91fb6316befbaec51e8c555109c3e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "af918a29abb1f88ef372543c11659c558ec086eeca4ab8d3ef35bb4baa57ab08"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "8d292660516cd1e520fec947ee4a3ae320cc11d94c3611187039185860998a93"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "f5dfef5c2f7ff9adbf715acc1c53ecfe7e5a420725f2d6eb45a85bb1e147a5b5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "c94905720299a18b81506ff2d16f80af3f74fcb8505195b72a43adef27762b15"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "f5754e073c8dc8c694674fe546159129655b5d70d3316304ecaf5f32497a1f23"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "adc49b35fd5721836bfab7a05fdac8cba4a943fe87367d5965a5b1a5611cd6d1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "f75b7a647ac941451985ec94248113142bf41ae6e7309e4bd1313d435e41b810"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "407e552c2b3cf025ae6182655f727fee236fd588329f6734cfcb272132afe111"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "644f0141bbe705dc9db3cf21c333924eddc47947470e7f0e23db8a55aa7f970c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "ad8a3566369dd52e41a0f2eb9b04bb3792069899e45856d3b4108fc7eeeac313"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "e42f4ee5d59fbe2e27689f15b9b4c4b4407920d53722ba6fb1273d009395340d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "d0a68ddc595d26f9f721f550ea5777d96c9477b8be239ffbe4371bceb60cca78"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "72bc5a447df980da293ae92d1b67bc79cd7a77fbd3189a27f66a74611aacfda2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "1b14e99dfe7313179b726ce7c5a9c96807002f4683b3ab1de5ba036c43e334e5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "de99157aa8ac56fe1488eedbc9e17461ba102444decfbcfde258d3d0aceca12e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "917d12b4ef478da7b7450a3240363d21d194a43bd8a4e0ccdede5899eff0d775"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "61d3907fa98016c3177f13079c5820ebc717af2a776166d55daa2fd0bc287086"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "b092736907c4249932d44e19a7396f6aef22f2b4c70216f8d737136a355f8a3a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "0ca26023772daf03ac4bcc83381bd21e0f348f5cce80dd9aa7725a63a5623719"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "9dda15ba2d2e4318cabfa528eeae7ee012bb39bb6d2e0bb6a25d38e534c00f2f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "f670b1747e95c295e9d75461a392c37b090e075e16da3e3b7ec38b2da4d24e99"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "502823d772ae16a99338231fd7ff23ba9f89fdd9bf9a05631e35bae8559bbe57"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "08e64ea000620ff7ea7b4f41a93e0f72bd087b903b8026faa95463a303c2b6c5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "1064ad0b727cbd94e7ce894fc366ad81d9b5e894a3e3c25c0eb074433735ec33"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "7be3668094671b0820207760b784cb1b5b4dd9f487eef65712d2b37e0885f7bc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "d88bdd19c0a23f78658bfa19e841c5c1561a8e649dc9efe670de7a501c294942"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "92e8c9eb7723a161f47f01948fc41fef366aa79e60720a87a16c111693230293"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "9c846bc7d014389bd1d34403cf087336a1e1baf91d9adaa665e7a9d7771ebf7d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "144362d5ca23c5e0054d057180a4a746edd06dacf4327fd6d5a757501e55afde"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "3e2371eb188e8e00e15684b209b24293ab071f331898957085a46244f5885a15"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "3441019f274bbacf853d18b23e9c68968f25ab83762b870e0a2e08713e33d4d7"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "6048da4d4370c5a0066b63cbcd1fbc1db6245d1ddfd214963613fce930396ae8"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "0947aef97ab0a7ed12213cf1a136f1dd9e9922cb06df809b0529f08498728134"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "2d3c01bb62e997f656978ed837e7c079950100907e6e0fa5ae422c0607129f6c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "ca69fb3df849e102e364f0516808c05c994027f4c718d968c775609927d4d7a5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "ca352c7163b8a40a902778daa0bdda11141aa9dfd4517ee4fc42dd9d5a0cb995"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "f796eaae7c2f5914210c1c54831bee459af58f7b99244b8b4ea61496b27d32c0"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "8cf0a4947aa2962b24ce284cab610154bb4196485c4c51eecb2ca83af957df38"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "d1e6c57e6fb4bf916fad4e8bf1c757ce0909a0ddf26888ff03851b8d3e0372f2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "ba61e587ad106048131ee9d0e9878df2aad0005d13d16819a595f3dcb650d58e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1691959836523a606073f41f402dc25d44519c0d6cc7b89ab081019f77ebe7d4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "7f1a46816885e5eefa5e903ba1d3278b49e9728efa46e31d0ef504fe0ccac4ce"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 191080, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "4964c06d9407041a633ee7cd1bda390ce660515ce8db180d8dae3ad4627ddf04"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 216680, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "4e1995adb2c53b39e752f070cae529c6009b0810aa711e93b7ab6b115d16998d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "283183575a45ac54d954816fb47618b517b7e1e8fb29bf8c8dba74c1576c1dce"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 178280, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "20470aa9402a082f87b0e5f52f4731ed642509de920811d9e2a23aa847fc56a4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197744, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "1d5a4f770f6d199614ccfb751249bef39c5d2a58124d4e42d0618f0832496678"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 183992, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "180acb4c5f86319c65c7008da0067453abc7566f9d9fb93fdfa01f38f4180f15"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 201656, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "1f1ea2427fe54003ab09df6c1126b59b20c611da2b5e1fa72fc86e84e75baf1a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164976, 384, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "3e0172da702ea1c87a8951cc8c4768337378ef18d292ca3dcbf547b00848457f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 175160, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "e2717b0cb8ee88c551230cc43ebcb7c07604fa4801281ed51491cd5ae929c788"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "198e1f27d4959ac17327ddbcdd47300385fac9f60f23b221fa864cff8b3deb69"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "765379654e9342552c4ab7fe18fce3b75c7aa08e63bc01be79a668277f1928d2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "87b16b11d87bc91e13e05865c8636026508136a0b8a0dd5a00a6ad34381cdb74"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "f80067d8b505e91b3f100fdc47012ff72bf2b60161fe8a9bfd4ed691920133fc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "e6c704b8b92a49c8b4771e7e27f30dde015cc49a8d9997d92e7e3831d467913c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197728, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "a67ac8da4d6b507b30b2a541843465584cd7599e8a0dd9af63dfb21b6d578ce6"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "f723eaae70081b918882533071b806960044f26a8fdbf9c00cd8cd1d45cfdcc5"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "80f2098f8117f1e3c8d0bd3a2acbbf68077475634ffbabda4d2debda1a1dc7a2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164960, 384, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "d91fa213a4f1562ef0c1f21c04d57c968684df3a3dade8f6b2ae6a3c25191f73"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "b91442f5414294c3667ef60c2271f602d6f05b65da009321a2650854d77799fa"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 197872, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "b3fe5e3b0e22a2952ba85a135064910dfabf2d9c8200ad57d8b8be20f4964ff3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 197872, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "02219c7f9506596d1bbe3b00487cd815979a4b434dc1c2f82c3952e52dc0bf60"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 197696, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "1ee615d3f80141237d1582bba02329944f63f6329853f41d016bb8997b0d6a91"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 197696, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "a1e176ab1811c0b347a36b71d27036d7370098ee6f30d00ec5e1cdd98db4ebba"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 162064, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "5f7818785544401ff132aa158e2091c00367a6cea6f70dd32cb14f9d07666c5d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 157792, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "be86f12865ba1b18636a4a71e2feb08e4b15cf03f5421d09f08be3dbbd509993"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 191760, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "399de07a9d6d8bd7022e3393d217b36ae2e7852820feb302980a2aa96a8c9887"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 183392, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "99f5100d9baef1a0bdc3121b207b9acd0d92978dc157e4d55d2f93610599382b"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165104, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "efb98a4bc6f10247ac255e47eafc18747203ce614a9baa569f7e2bff7411ac54"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 164928, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "13e5557c1e1f609823159c75397b014fca614fafdbade4970950c69ffdf5e149"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 147216, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "51495d95c18ae1ad1352e3f5d682443771d14bec1b633de8bc415c6b7641ce40"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 144992, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "02ee88f04b317ac93640cf397044aa718d2d2942fca60111165a335c04e387ae"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 197888, 384, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "d77761e66f7f06fe440a4d73e6495110a0a4362237e6700b04cae1d3f637f9c2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 197888, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "c3ab9ecbb5fa79a5e781f070d88ffa1992afc923c5127a16a897224b0e187df2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 197712, 384, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "be71b1c943458a61cf623ef7be548d95a022f05c601b2a6bbb89d79b19e1efc8"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 197712, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "b0c9ecbc63b3751c3c050ba5ceae01ea7ab9851d9aa3d94815b99ee486667f6a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 154976, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "d907898529e0cfd21a70712512e8783e351266bea29cc1e703306e8374e5e2c0"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 150704, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "92676b1f64dfe671e57b6025a2ccfad1d3d9711f0fcca4532b750208a593970e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176736, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "13340451d2c9559200f195f9a466d7945f4e5bb6d850491b638c65849aabf793"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 168368, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "7fa284fd92ed52dd6da342ee7512c764b0ffc577861b47ecf0339caf10ee4324"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165120, 384, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "e9b5fb20acd6e8ad3e862cc562b629f0ba319001f02743d3c1ad325dee78b587"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 164944, 384, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "62363f8ec1b44741237b72e94dcf957ee597738ce56af46811ed8d0c323ab0e3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 144096, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "c5abd7adbdb2f533ceb039fefa2681c35f80bf01eb6690ca7566eb3f90bef5c7"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 256, 256, 256, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H256PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 141872, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "24447bdce3d237ad9244dbb46f869ceae95297dd0a4fae0a25e0ffe828392b8a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "fb25d8de9da5c855be7bc659a410c4548e3d7639c26325e7fb7f503caf7b0849"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "74c4f32d4006b77a0439c152a0b162417a3facea7efa58ab47e207ffc4bbaed2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "ad9b23b0f846850dc71a764383b779216b86c4e3941d7513d28e092f4bf62786"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "f6a62484900a0ef938acbe35c49517b65a4cad02938c538c92152d2a811c7fb2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "d5dd0e03ca6885cc7e1a7c8b7d93b3892ad1f59aec898e4660cc6a5efa39eb97"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "910ae3b53d076f8b9ea26994dc8386a341c1b7bab9cd46956b78ef468d1a55b3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "1dad6b1591ed520d23a79eacf5fb6e511c7630bc77769807689b53c3c67b7ca2"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvDenseVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "1e89c1fe43fa60215a94b7389c506b7f712f44ab2aedbca349cecd1df60c92b0"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128PersistentContext", 82336, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "e70c83a2a37e6b0630e741bca8c0c918bab173b816a2d9d2bc32174a560828e1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqQ128Kv128StaticContext", 82160, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "92142c6aef8ab8607c0c0c9d65063288caa23646f9318a25c737bf91da798260"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128PersistentContext", 82352, 512, 1, 0, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "34f01d54392b05f0017d97b81ecba91a8bf2a0ae72e2c2ac7f7d6a3f7ec8a08d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PackedQkvSlidingOrChunkedCausalVarSeqSkipsSoftmaxQ128Kv128StaticContext", 82176, 512, 1, 0, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "3ac6bef39a367e35c70ce1f7cecf7ab50cd043af851049b194bfc09920f11478"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "0cbb894dc1fa7173a3e7019a15d4f5febaa7121acfe0828c0376788909d9a5e9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "e2049f6a31130d40f5d94a606441af6739b3387bf72e13b6292c5c91ed0dc3e6"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "56363c9aaa889f3e5c624b4175c3961e7b01f0c475c3389b27bcbc05deed70d8"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, false, false, false, "0ad581e86983c6b6290c4b64627571e3f2d826f3b4485cf4cd7f28d1f5283cb1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 1, 2, 0, 3, true, true, false, false, false, false, false, false, "fc1cafc2296944e0d320535432f3746ecc6e165de6a7948d8015da28ed3b8ae3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "cdfd00a5cc4783e6287e8b2ff3526bb674d75db4bf00bedc9664c741cdad6b8a"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "32384270b110d4b54f4dc417d0802bc5d82e1600dcf78903e9ded5ae43fde1ed"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "8534de48e1b2da596299220edd707326062e641af35c1d7627d9d76416335a92"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 1, 3, 0, 3, true, true, false, false, false, true, false, false, "1041e84e2c6e2e37540343ab6264cb2ba7804e015bba8094612f73c79536ba10"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 1, 2, 0, 3, true, true, false, false, false, true, false, false, "ca87598060050b722aba8b7af0001c7e101a09671cbef30504e479799e5d6881"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "4b37d57570aeebf63961b99045cb87b4056cb7ae76c70bf0584471701af4e9e1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "de9506fbafb9b1012ab6c6dd0d7c97b463316166cc40ce5877e16887ff892c8c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "c09e6308d2fcf259e0f9bb7f0f79884197b596c5081d495499de5d11689c675c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, false, false, false, "67cede7203acf4817f806ca20169b04503915a839e71783d27c8f66a0989102e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 1, true, true, false, false, false, false, false, false, "294e9e9752b0c89ed79dcb30f65f6e53351ad87a52f05702875d3da4bdcd879c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "025bb6447e1b1f4c468e37ad1f65200db5ff5ae6e1031d47e2cf0b3795c34cc3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "455444754b445ab1933295a9511e10312dbd0cad8f0f18b017d32df73200afab"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "d31e1fbc602cb64a260eac381e278e858e32e1aee533f417093d058ea95ae109"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 1, 3, 0, 1, true, true, false, false, false, true, false, false, "b45ee1b91ea70e0609d4a7ab2ff771c2c6de40ae8500a7656395ed91827f868f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 1, true, true, false, false, false, true, false, false, "3e7a42f251f8bc768cf6f4631a9599f85c557a0aff71c57c2a359b6b19b86959"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, false, false, false, "1c93af31a257691a0af6e05519215db8b1f2a8da396692bc8771965936603466"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "eea59f1984a6ca6cbc4936668976361804135b3765adb0346b0815a81048f4fc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, false, false, false, "9ad0d94937192ad0fed19f86bbc73dad17bf3d44bc924b4df2b20a5b9bb8ab08"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "e04b61c1dee07cdf215f00b27979b90590eb0a85f2e5f13d4432ac2ce6568a5f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "a7bb4449070c38a310d4652e3ab7c8c5272d0eeaadb4a856503f72e2c6a4b979"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "a4f217f1426102e06eaef1ca48385bbc11a033081ec3b43025128c19b630b9db"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "9ce0d39df916bd6ac6b5a0e54ca13f78e8acb184f2158ccb4b64cdb7d642e8bd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "dee4c79561e8934fb22c0ce22fa4b7c5bdb777d61977288fb85e81932b2b593c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, false, false, false, "c7109fa7c720e0e8315fc758735b755780b74e0e504790084a698a35a1652e05"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, false, false, false, "4d88ebd9b6eed8e37e91ebdec951a11592ac3b721aba56e7ac1718a72fb7c54d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, false, false, false, "635582f3ffe7195d92bb34338a9f35fa9ca1c7ac8c2a4cb56e78a1c40a6ed16d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 1, 2, 0, 0, true, true, false, false, false, false, false, false, "11eb4ace517891eb78bc8fad24627a29a87ba241ce1e9ec4453979c97b7271be"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 1, 0, 1, 0, false, false, false, false, false, true, false, false, "f1e3834047f67ab5415798a2a797032be2105504a16ec725dbc1a827d7343145"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "71ee2c0020112d771996c95bba77ec63f85f656d4add3eca8896929b877b3b95"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 1, 0, 0, 0, false, false, false, false, false, true, false, false, "a7aa03168c467e70199ab2477a4b2e65e8394a1729566bcfeb390772ec7104ff"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "5b908161733acef342893fb8eb5c69b6c880aa17e4e9697c1fbb0bfd4e05acc8"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "206154e78ab01c49bf6a958c8c1c195a53916dc9d2d99a3f56fe2a41bbe202c4"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "8932d94550aaf0918c602d3fda89006012c05262662fa160fa37029cf6b199eb"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "9fed089f55bbc7ab82584ec9f6ae7e3d0216573b9545dd5dd27036eadf050885"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "7e4575674ae9bddfa223c993d75d3e216da0879713cd37286cb00528deb6cdc3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 1, 3, 1, 0, true, true, false, false, false, true, false, false, "308af1170c21f344604933cf09974c66c6990e363df340339928c4fc5ae28766"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 1, 3, 0, 0, true, true, false, false, false, true, false, false, "98e6c7c9ef9060298c5e07c449c1e555199147a8eaf9be8f2cc9d8097392ae60"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 1, 2, 1, 0, true, true, false, false, false, true, false, false, "7df59966f096fecde9aea02f360cf67a73618974a605ef61bacc59fd1039e821"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 1, 2, 0, 0, true, true, false, false, false, true, false, false, "005d1365ce7ea3cbb4fd2dbab2e3da5bde854ce67e5b8fac9c47f37746fadc6e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, false, false, false, "01866f21777fd1227955ab2c452b00e62ee6c16496a914005684131b7066acbd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 3, 3, 0, 3, true, false, false, false, false, true, false, false, "d7741bc9329b695d3f30ec42d83dc41a95560f12ce6b0fc86bf669100685846e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, false, false, false, "6c243f52d7a58911c8d9bfedf0dae231a54dc5782e6e8e07123d42792aecea5b"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 3, 3, 0, 1, true, false, false, false, false, true, false, false, "9b10dd378668e8eca0ea55008899a0a5b2ce4729b54b0ee81a59e4f5d0dc6694"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, false, false, false, "f8f0638998ffa86fb1dd9cea5c7ba8465b2613fcb7e55f920aaf6b0fa0d4a094"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, false, false, false, "09fd6ac06ce8b2712b277ed43a0a8b4f778e99415cc7423d564ad191d185972d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 3, 3, 1, 0, true, false, false, false, false, true, false, false, "4323e7f547374f166e4f72205a6b1e239f6f4096592f888e93114bdd4c29e644"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvCustomP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 3, 3, 0, 0, true, false, false, false, false, true, false, false, "abe37ccf14b9986d345f43c7229ce5f57b2ab8557af76db2766ebddc4ebfc444"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, false, false, false, "4fea530ffaad03b9bd72c4e29ebcae992609819e6cc4a6b2662bbbf2c06326f1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, false, false, false, "b6a8002920e98a59b1120e49ed0c6c02ca9be9857e5d2c5dec9a6ab2311f3734"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 0, 0, 1, 0, false, false, false, false, false, true, false, false, "6fc441d12e7224d0893b66c52b800f3245fbc9b8437cc865d61232a3ba7163b9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvDenseP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 0, 0, 0, 0, false, false, false, false, false, true, false, false, "30f58e666a40f5f78013d9fc47539e67836aee64e0dff2ac2873a37816fc8fdb"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "259ea85a1f1fa7f1cca89fb2a29dc1078a16d244e67247d27b8495f73a5ac11c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen", 196792, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "76a3c8566f8731a20cb52504ceea24c30fa60f41ca40969f0c2483f16977df25"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen", 210104, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "6eb2123db4f6488a5c0ccacae3039b58a5677b3d27bac5c8f42d7b94904ccf11"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, false, false, false, "bbfcf5e854732dbb09ada6a5eefd43b23bded1d835ef9807284ef74e6be31a0f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen", 190136, 512, 2, 32, 2, 2, 0, 3, true, true, false, false, false, false, false, false, "5fcedd249b2285c1136340ce040751b5996f6bbc5726ce2ea2b8eb88073b56fc"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165072, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "86f4d4795ac5d0dcdc304f1fb078c0c43e9b6d7102890c81f59c6e89f8b7e78c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 195848, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "dfed017870719bb40539bae490ae833d083e777f5649af9e02dcc9101c1e0c9f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 207368, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "f657534ae1198bfa0f7509c14eb932abb030afa60e19419ed25334e733f33928"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156880, 512, 2, 32, 2, 3, 0, 3, true, true, false, false, false, true, false, false, "19d21caab87d166079d69efcd8d158e688327129ae3fdb96e294c70c614a3cba"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvCgaVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 190088, 384, 2, 32, 2, 2, 0, 3, true, true, false, false, false, true, false, false, "863d94c826d9e9751e945e4c0f22dcb9521d7d6f990a91f596b8bed493949a7e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "909be8aa3b7f5499041b69281e327dbdd62c73978f315ca6278b8883087df823"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "26ccd38c4cf8a199c3bf5276cf873038496c05135fc89cb20b4b9d3d1e0b345f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "fdbf8e76b0c2e1c315e87cc557bef72f881fcb53f410a393e267b032b6753e1d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, false, false, false, "0989d912f97574dbfdfff5615b42ae3b931f445a9f00d6be8b303ebe6a0c4d01"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 1, true, true, false, false, false, false, false, false, "fbfc69d706ec6fe0a90955e89103de18a388f7432762340936e60eca4b7c743f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165056, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "62932b2fb31ec4451d26fa729e10074dc80b3f9704faaa256dad796916b3654c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "60fbe0e46b1f55c3534d741f33c585400f980d5de48a1144cc90105f17e48fb3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "d9d85d7670fa888573a09ba3e99ea0a175829dffae9f81e73c41f33ac9a12d90"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156864, 512, 2, 32, 2, 3, 0, 1, true, true, false, false, false, true, false, false, "da815ff158d535b599d0ea9e6dac6742814a272b7d5f8dc93304b013322a052c"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32MultiCtasKvVarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 1, true, true, false, false, false, true, false, false, "2f9d7cd63cfabae0bdc9b63c3dd92a1c3c4a9ae839ba94ea2a7a10f830441af3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentContext", 83200, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, false, false, false, "ead451248819ecf516e85d116951f163973fc44857a53ba4f8297d3e2a7ed5db"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128PersistentKeepsAbForGen", 181600, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "f4eac6c5fad2e355a7c211030979291adcf19a0e9758d293f9604346b650282e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticContext", 83024, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, false, false, false, "b40bdbc3d0bfef60c845136c26813c670e7130f64103ac4a421ae2826f02cdaa"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ128Kv128StaticKeepsAbForGen", 165024, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "a062e05810d813950101315c32565d0ea4c565ad7e973cbf700a3671887f00a1"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128PersistentSwapsAbForGen", 164192, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "bef390244e615114918ca3598cde20a5abdcb5c83d30f665b391b27b1a913be9"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ16Kv128StaticSwapsAbForGen", 161968, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "deb8e138d3f7b853968cdbab4c7a9d374ef63a7263194f2a6222584ec7bd01fe"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128PersistentSwapsAbForGen", 179552, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "3b7b331f430d2e1ed0aaf5abc67afae75e4745ee64500824e14b38b4873aca9e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ32Kv128StaticSwapsAbForGen", 175280, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "0912dba69660aaa6942d7aef177d4b17ae7e0d42e2c966e131816b8add9ffd88"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128PersistentKeepsAbForGen", 165216, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, false, false, false, "779fe7db239e468cf84166cbf89c2ccbf699c6f1edf703bdc585f3a4670a146f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ64Kv128StaticKeepsAbForGen", 156832, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, false, false, false, "8c17f39e23bd642abd953d3b007275d2f0051bf113d5fbcae9beffb527689e7f"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128PersistentSwapsAbForGen", 156512, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, false, false, false, "9b04780e4dd106fda9afe2d42f2c4f09827acb0be668cc19d4eebd4e4f56ab92"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqQ8Kv128StaticSwapsAbForGen", 155312, 512, 2, 32, 2, 2, 0, 0, true, true, false, false, false, false, false, false, "736b941c28e64355449f82d498873caed16aedd31a7c5277d39c7600fce86898"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentContext", 83216, 512, 2, 32, 2, 0, 1, 0, false, false, false, false, false, true, false, false, "c0806737d9e3270b173388c73dac9db2cd8b5e6cecefe3ac67d237d31344721e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128PersistentKeepsAbForGen", 181616, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "a0f1ba1e668b395c61788500a1cb436557dd040c07760d78f966e51843ca320d"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 256, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticContext", 83040, 512, 2, 32, 2, 0, 0, 0, false, false, false, false, false, true, false, false, "c20023c89ec93136d1332379a9bc8c48b0e820397bb7c9607bf1b1b806aad2d0"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 128, 128, 128, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ128Kv128StaticKeepsAbForGen", 165040, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "6f8a93ff824e0eb7de3e76a3f5292fff29723d47eb64fafd1599932d9d815355"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128PersistentSwapsAbForGen", 163248, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "f3952cf2400916f65c00a50c6ab7e9a20e6f27197128b3d3af1c9597e450f94e"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 16, 128, 16, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ16Kv128StaticSwapsAbForGen", 161024, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "76227592fa450890ab495dbe0f896ffa57fc5acdb44006d3eee7a341ded109a3"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128PersistentSwapsAbForGen", 176816, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "47be865958261e660f1bab87350f842d3b2698288eeb1e6efa8a48b393604727"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 32, 128, 32, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ32Kv128StaticSwapsAbForGen", 172544, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "db32470a8dbd648f48458cd3452ffc04737d65c1607bb461aed9563b0a4fa408"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128PersistentKeepsAbForGen", 165232, 512, 2, 32, 2, 3, 1, 0, true, true, false, false, false, true, false, false, "bbf0d730fcf0bc7a2e47914e2c5d71e360a8c27bad2bf1c8aca4788bee2ca5cd"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 64, 128, 64, 256, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ64Kv128StaticKeepsAbForGen", 156848, 512, 2, 32, 2, 3, 0, 0, true, true, false, false, false, true, false, false, "5f68d044b3c028814728b64e2ba0bcd49c027550208650caee398121aa394020"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128PersistentSwapsAbForGen", 156464, 512, 2, 32, 2, 2, 1, 0, true, true, false, false, false, true, false, false, "21a18c767b418950e3dd5463f169c6a3129ad2fa4b42a134f495bda3cb330dfe"}, +{ DATA_TYPE_FP16, DATA_TYPE_FP16, DATA_TYPE_FP16, 8, 128, 8, 128, 64, 64, 64, kSM_100f, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin, FmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen_cubin_len, "fmhaSm100fKernel_QkvFp16OFp16H64PagedKvSlidingOrChunkedCausalP32VarSeqSkipsSoftmaxQ8Kv128StaticSwapsAbForGen", 155264, 384, 2, 32, 2, 2, 0, 0, true, true, false, false, false, true, false, false, "8b5e23d6897a15a31bd1ff25698ebfc4ad39ddfda23d605363c934d64a4c7a9b"}, #endif // EXCLUDE_SM_100F }; // clang-format on diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cuda_ptx/cuda_ptx.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cuda_ptx/cuda_ptx.h new file mode 100644 index 000000000000..b150b749e023 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cuda_ptx/cuda_ptx.h @@ -0,0 +1,58881 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// -*- cuda -*- + +#ifndef LIBCUDA_PTX_H + +// Start prologue +// XXX: Ensure this prologue stays in sync with ../test/test_ptx_prologue.h +#define LIBCUDA_PTX_H + +#include + +// Forward-declare __half and __nv_bfloat16. The cuda_fp16.h and cuda_bf16.h are +// expensive to include. This is the user's responsibility (if they need the +// types). +struct __half; +struct __nv_bfloat16; + +// Start of ./ptx_isa_target_macros.h +// -*- cuda -*- +#ifndef PTX_ISA_TARGET_MACROS_H +#define PTX_ISA_TARGET_MACROS_H + +/* + * Targeting macros + * + * Information from: + * https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#release-notes + */ + +#if (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ > 13)) +// Handle CTK 14 +# define __libcuda_ptx_isa 920ULL +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 13 && __CUDACC_VER_MINOR__ >= 2)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 920ULL +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 13 && __CUDACC_VER_MINOR__ >= 1)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 910ULL +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 13 && __CUDACC_VER_MINOR__ >= 0)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 900ULL +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 9)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 880ULL +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 8)) || (!defined(__CUDACC_VER_MAJOR__)) +// PTX ISA 8.7 - CUDA 12.8, driver r570 +# define __libcuda_ptx_isa 870ULL +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 5)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 850ULL +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 4)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 840ULL +// PTX ISA 8.3 is available from CUDA 12.3, driver r545 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 3)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 830ULL +// PTX ISA 8.2 is available from CUDA 12.2, driver r535 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 2)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 820ULL +// PTX ISA 8.1 is available from CUDA 12.1, driver r530 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 1)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 810ULL +// PTX ISA 8.0 is available from CUDA 12.0, driver r525 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 12 && __CUDACC_VER_MINOR__ >= 0)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 800ULL +// PTX ISA 7.8 is available from CUDA 11.8, driver r520 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 8)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 780ULL +// PTX ISA 7.7 is available from CUDA 11.7, driver r515 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 7)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 770ULL +// PTX ISA 7.6 is available from CUDA 11.6, driver r510 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 6)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 760ULL +// PTX ISA 7.5 is available from CUDA 11.5, driver r495 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 5)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 750ULL +// PTX ISA 7.4 is available from CUDA 11.4, driver r470 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 4)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 740ULL +// PTX ISA 7.3 is available from CUDA 11.3, driver r465 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 3)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 730ULL +// PTX ISA 7.2 is available from CUDA 11.2, driver r460 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 2)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 720ULL +// PTX ISA 7.1 is available from CUDA 11.1, driver r455 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 1)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 710ULL +// PTX ISA 7.0 is available from CUDA 11.0, driver r445 +#elif (defined(__CUDACC_VER_MAJOR__) && (__CUDACC_VER_MAJOR__ >= 11 && __CUDACC_VER_MINOR__ >= 0)) || (!defined(__CUDACC_VER_MAJOR__)) +# define __libcuda_ptx_isa 700ULL +// Fallback case. Define the ISA version to be zero. This ensures that the macro is always defined. +#else +# define __libcuda_ptx_isa 0ULL +#endif + +#endif // PTX_ISA_TARGET_MACROS_H + +// End of ./ptx_isa_target_macros.h +// Start of ./ptx_dot_variants.h +// -*- C++ -*- +#ifndef _LIBCUDA_PTX_DOT_VARIANTS_H_ +#define _LIBCUDA_PTX_DOT_VARIANTS_H_ + +/* + * Public integral constant types and values for ".variant"s: + * + * - .sem: acquire, release, .. + * - .space: global, shared, constant, .. + * - .scope: cta, cluster, gpu, .. + * - .op: add, min, cas, .. + * + * For each .variant, the code below defines: + * - An enum `dot_variant` with each possible value + * - A type template `variant_t` + * - Types `variant_A_t`, ..., `variant_Z_t` + * - Constexpr values `variant_A` of type `variant_A_t` + * + * These types enable specifying fine-grained overloads of a PTX binding. If a + * binding can handle multiple variants, then it is defined as: + * + * template + * [...] void ptx_binding(variant_t __v) { ... } + * + * If it only handles a single variant, then it is defined as: + * + * [...] void ptx_binding(variant_A __v) { ... } + * + * If two variants have different behaviors or return types (see .space + * overloads of mbarrier.arrive.expect_tx for an example), then these can be + * provided as separate overloads of the same function: + * + * [...] void ptx_binding(variant_A __v) { ... } + * [...] int ptx_binding(variant_B __v) { ... } + * + */ + +namespace cuda_ptx { + +template +struct __integral_constant +{ + static constexpr T value = v; + using value_type = T; + using type = __integral_constant; // using injected-class-name + constexpr __host__ __device__ operator value_type() const noexcept { return value; } + constexpr __host__ __device__ value_type operator()() const noexcept { return value; } // since c++14 +}; + +// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#operation-types +enum class dot_sem +{ + acq_rel, + acquire, + relaxed, + release, + sc, + weak +}; + +// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#state-spaces +enum class dot_space +{ + global, + cluster, // The PTX spelling is shared::cluster + shared, // The PTX spelling is shared::cta + + // The following state spaces are unlikely to be used in cuda::ptx in the near + // future, so they are not exposed: + + // reg, + // sreg, + // const_mem, // Using const_mem as `const` is reserved in C++. + // local, + // param, + // tex // deprecated +}; + +// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#scope +enum class dot_scope +{ + cta, + cluster, + gpu, + sys +}; + +enum class dot_op +{ + add, + dec, + inc, + max, + min, + and_op, // Using and_op, as `and, or, xor` are reserved in C++. + or_op, + xor_op, + cas, + exch +}; + +enum class dot_cta_group +{ + cta_group_1, + cta_group_2 +}; + +enum class dot_kind +{ + f16, + f8f6f4, + i8, + mxf4, + mxf4nvf4, + mxf8f6f4, + tf32 +}; + + +template +using sem_t = __integral_constant; +using sem_acq_rel_t = sem_t; +using sem_acquire_t = sem_t; +using sem_relaxed_t = sem_t; +using sem_release_t = sem_t; +using sem_sc_t = sem_t; +using sem_weak_t = sem_t; + +[[maybe_unused]] static constexpr sem_acq_rel_t sem_acq_rel{}; +[[maybe_unused]] static constexpr sem_acquire_t sem_acquire{}; +[[maybe_unused]] static constexpr sem_relaxed_t sem_relaxed{}; +[[maybe_unused]] static constexpr sem_release_t sem_release{}; +[[maybe_unused]] static constexpr sem_sc_t sem_sc{}; +[[maybe_unused]] static constexpr sem_weak_t sem_weak{}; + +template +using space_t = __integral_constant; +using space_global_t = space_t; +using space_shared_t = space_t; +using space_cluster_t = space_t; + +[[maybe_unused]] static constexpr space_global_t space_global{}; +[[maybe_unused]] static constexpr space_shared_t space_shared{}; +[[maybe_unused]] static constexpr space_cluster_t space_cluster{}; + +template +using scope_t = __integral_constant; +using scope_cluster_t = scope_t; +using scope_cta_t = scope_t; +using scope_gpu_t = scope_t; +using scope_sys_t = scope_t; + +[[maybe_unused]] static constexpr scope_cluster_t scope_cluster{}; +[[maybe_unused]] static constexpr scope_cta_t scope_cta{}; +[[maybe_unused]] static constexpr scope_gpu_t scope_gpu{}; +[[maybe_unused]] static constexpr scope_sys_t scope_sys{}; + +template +using op_t = __integral_constant; +using op_add_t = op_t; +using op_dec_t = op_t; +using op_inc_t = op_t; +using op_max_t = op_t; +using op_min_t = op_t; +using op_and_op_t = op_t; +using op_or_op_t = op_t; +using op_xor_op_t = op_t; +using op_cas_t = op_t; +using op_exch_t = op_t; + +[[maybe_unused]] static constexpr op_add_t op_add{}; +[[maybe_unused]] static constexpr op_dec_t op_dec{}; +[[maybe_unused]] static constexpr op_inc_t op_inc{}; +[[maybe_unused]] static constexpr op_max_t op_max{}; +[[maybe_unused]] static constexpr op_min_t op_min{}; +[[maybe_unused]] static constexpr op_and_op_t op_and_op{}; +[[maybe_unused]] static constexpr op_or_op_t op_or_op{}; +[[maybe_unused]] static constexpr op_xor_op_t op_xor_op{}; +[[maybe_unused]] static constexpr op_cas_t op_cas{}; +[[maybe_unused]] static constexpr op_exch_t op_exch{}; + +template +using cta_group_t = __integral_constant; +using cta_group_1_t = cta_group_t; +using cta_group_2_t = cta_group_t; + +[[maybe_unused]] static constexpr cta_group_1_t cta_group_1{}; +[[maybe_unused]] static constexpr cta_group_2_t cta_group_2{}; + +template +using kind_t = __integral_constant; +using kind_f16_t = kind_t; +using kind_f8f6f4_t = kind_t; +using kind_i8_t = kind_t; +using kind_mxf4_t = kind_t; +using kind_mxf4nvf4_t = kind_t; +using kind_mxf8f6f4_t = kind_t; +using kind_tf32_t = kind_t; + +[[maybe_unused]] static constexpr kind_f16_t kind_f16{}; +[[maybe_unused]] static constexpr kind_f8f6f4_t kind_f8f6f4{}; +[[maybe_unused]] static constexpr kind_i8_t kind_i8{}; +[[maybe_unused]] static constexpr kind_mxf4_t kind_mxf4{}; +[[maybe_unused]] static constexpr kind_mxf4nvf4_t kind_mxf4nvf4{}; +[[maybe_unused]] static constexpr kind_mxf8f6f4_t kind_mxf8f6f4{}; +[[maybe_unused]] static constexpr kind_tf32_t kind_tf32{}; + + +template +using n32_t = __integral_constant; + + + +} // namespace cuda_ptx + +#endif // _LIBCUDA_PTX_DOT_VARIANTS_H_ + +// End of ./ptx_dot_variants.h +// Start of ./ptx_helper_functions.h +// -*- cuda -*- +#ifndef _LIBCUDA_PTX_HELPER_FUNCTIONS_H_ +#define _LIBCUDA_PTX_HELPER_FUNCTIONS_H_ + +#include + +#if defined(__CUDACC__) || defined(_NVHPC_CUDA) || defined(__CUDACC_RTC__) +#define _LIBCUDA_PTX_CUDACC_MAJOR() __CUDACC_VER_MAJOR__ +#elif defined(__CUDA__) && defined(__clang__) +#define _LIBCUDA_PTX_CUDACC_MAJOR() (CUDA_VERSION / 1000) +#endif // ^^^ has cuda compiler ^^^ + +#if !defined(_LIBCUDA_PTX_ARCH_SPECIFIC) +# if defined(__CUDA_ARCH_SPECIFIC__) +# define _LIBCUDA_PTX_ARCH_SPECIFIC() __CUDA_ARCH_SPECIFIC__ +# else +# if defined(__CUDA_ARCH_FEAT_SM90_ALL) +# define _LIBCUDA_PTX_ARCH_SPECIFIC() 900 +# elif defined(__CUDA_ARCH_FEAT_SM100_ALL) +# define _LIBCUDA_PTX_ARCH_SPECIFIC() 1000 +# elif defined(__CUDA_ARCH_FEAT_SM103_ALL) +# define _LIBCUDA_PTX_ARCH_SPECIFIC() 1030 +# elif defined(__CUDA_ARCH_FEAT_SM120_ALL) +# define _LIBCUDA_PTX_ARCH_SPECIFIC() 1200 +# else +# define _LIBCUDA_PTX_ARCH_SPECIFIC() 0 +# endif +# endif // ^^^ !defined(__CUDA_ARCH_SPECIFIC__) +#endif // ^^^ !defined(_LIBCUDA_PTX_ARCH_SPECIFIC) + +#if !defined(__CUDA_HAS_ARCH_FAMILY_SPECIFIC) + +#define __CUDA_HAS_ARCH_FAMILY_SPECIFIC(N) false + +#endif // !defined(__CUDA_HAS_ARCH_FAMILY_SPECIFIC) + +namespace cuda_ptx { + +#if _LIBCUDA_PTX_CUDACC_MAJOR() < 13 +struct alignas(32) longlong4_32a +{ + long long x, y, z, w; +}; +struct alignas(32) ulonglong4_32a +{ + unsigned long long x, y, z, w; +}; +struct alignas(32) double4_32a +{ + double x, y, z, w; +}; +#else +using ::double4_32a; +using ::longlong4_32a; +using ::ulonglong4_32a; +#endif // _LIBCUDA_PTX_CUDACC_MAJOR() < 13 + +/************************************************************* + * + * Conversion from generic pointer -> state space "pointer" + * + **************************************************************/ +static inline __device__ std::uint32_t __as_ptr_smem(const void* __ptr) +{ + // Consider adding debug asserts here. + return static_cast(__cvta_generic_to_shared(__ptr)); +} + +static inline __device__ std::uint32_t __as_ptr_remote_dsmem(const void* __ptr) +{ + // No difference in implementation to __as_ptr_smem. + // Consider adding debug asserts here. + return __as_ptr_smem(__ptr); +} + +static inline __device__ std::uint32_t __as_ptr_dsmem(const void* __ptr) +{ + // No difference in implementation to __as_ptr_smem. + return __as_ptr_smem(__ptr); +} + +static inline __device__ std::uint64_t __as_ptr_gmem(const void* __ptr) +{ + // Consider adding debug asserts here. + return static_cast(__cvta_generic_to_global(__ptr)); +} + +/************************************************************* + * + * Conversion from state space "pointer" -> generic pointer + * + **************************************************************/ +template +static inline __device__ _Tp* __from_ptr_smem(size_t __ptr) +{ + // Consider adding debug asserts here. + return reinterpret_cast<_Tp*>(__cvta_shared_to_generic(__ptr)); +} + +template +static inline __device__ _Tp* __from_ptr_dsmem(size_t __ptr) +{ + // Consider adding debug asserts here. + return __from_ptr_smem<_Tp>(__ptr); +} + +template +static inline __device__ _Tp* __from_ptr_remote_dsmem(size_t __ptr) +{ + // Consider adding debug asserts here. + return __from_ptr_smem<_Tp>(__ptr); +} + +template +static inline __device__ _Tp* __from_ptr_gmem(size_t __ptr) +{ + // Consider adding debug asserts here. + return reinterpret_cast<_Tp*>(__cvta_global_to_generic(__ptr)); +} + +/************************************************************* + * + * Conversion to and from b8 type + * + **************************************************************/ + +template +__device__ static inline uint32_t __b8_as_u32(_B8 __val) { + static_assert(sizeof(_B8) == 1, ""); + uint32_t __u32 = 0; + memcpy(&__u32, &__val, 1); + return __u32; +} + +template +__device__ static inline _B8 __u32_as_b8(uint32_t __u32) { + static_assert(sizeof(_B8) == 1, ""); + _B8 b8; + memcpy(&b8, &__u32, 1); + return b8; +} + +} // namespace cuda_ptx + +#endif // _LIBCUDA_PTX_HELPER_FUNCTIONS_H_ + +// End of ./ptx_helper_functions.h +// End prologue + +// Start of ./instructions/barrier_cluster.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_BARRIER_CLUSTER_H +#define INSTRUCTIONS_BARRIER_CLUSTER_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/barrier_cluster.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + + +/* +// barrier.cluster.arrive; // PTX ISA 78, SM_90 +// Marked volatile and as clobbering memory +template +__device__ static inline void barrier_cluster_arrive(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline void barrier_cluster_arrive() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "barrier.cluster.arrive;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + + +/* +// barrier.cluster.wait; // PTX ISA 78, SM_90 +// Marked volatile and as clobbering memory +template +__device__ static inline void barrier_cluster_wait(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline void barrier_cluster_wait() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "barrier.cluster.wait;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + + +/* +// barrier.cluster.arrive.sem; // PTX ISA 80, SM_90 +// .sem = { .release } +// Marked volatile and as clobbering memory +template +__device__ static inline void barrier_cluster_arrive( + cuda_ptx::sem_release_t); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline void barrier_cluster_arrive( + cuda_ptx::sem_release_t) +{ + // sem == sem_release (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "barrier.cluster.arrive.release;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + + +/* +// barrier.cluster.arrive.sem; // PTX ISA 80, SM_90 +// .sem = { .relaxed } +// Marked volatile +template +__device__ static inline void barrier_cluster_arrive( + cuda_ptx::sem_relaxed_t); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline void barrier_cluster_arrive( + cuda_ptx::sem_relaxed_t) +{ + // sem == sem_relaxed (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "barrier.cluster.arrive.relaxed;" + : + : + : + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_barrier_cluster_arrive_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + + +/* +// barrier.cluster.wait.sem; // PTX ISA 80, SM_90 +// .sem = { .acquire } +// Marked volatile and as clobbering memory +template +__device__ static inline void barrier_cluster_wait( + cuda_ptx::sem_acquire_t); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline void barrier_cluster_wait( + cuda_ptx::sem_acquire_t) +{ + // sem == sem_acquire (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "barrier.cluster.wait.acquire;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_barrier_cluster_wait_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_BARRIER_CLUSTER_H + +// End of ./instructions/barrier_cluster.h +// Start of ./instructions/bfind.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_BFIND_H +#define INSTRUCTIONS_BFIND_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/bfind.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// bfind.u32 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind( + std::uint32_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind( + std::uint32_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.u32 %0, %1;" + : "=r"(dest) + : "r"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// bfind.shiftamt.u32 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::uint32_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::uint32_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.shiftamt.u32 %0, %1;" + : "=r"(dest) + : "r"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// bfind.u64 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind( + std::uint64_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind( + std::uint64_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.u64 %0, %1;" + : "=r"(dest) + : "l"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// bfind.shiftamt.u64 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::uint64_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::uint64_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.shiftamt.u64 %0, %1;" + : "=r"(dest) + : "l"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// bfind.s32 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind( + std::int32_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind( + std::int32_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.s32 %0, %1;" + : "=r"(dest) + : "r"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// bfind.shiftamt.s32 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::int32_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::int32_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.shiftamt.s32 %0, %1;" + : "=r"(dest) + : "r"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// bfind.s64 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind( + std::int64_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind( + std::int64_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.s64 %0, %1;" + : "=r"(dest) + : "l"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// bfind.shiftamt.s64 dest, a_reg; // PTX ISA 20, SM_50 +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::int64_t a_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint32_t bfind_shiftamt( + std::int64_t a_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "bfind.shiftamt.s64 %0, %1;" + : "=r"(dest) + : "l"(a_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bfind_shiftamt_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_BFIND_H + +// End of ./instructions/bfind.h +// Start of ./instructions/bmsk.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_BMSK_H +#define INSTRUCTIONS_BMSK_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/bmsk.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// bmsk.clamp.b32 dest, a_reg, b_reg; // PTX ISA 76, SM_70 +template +__device__ static inline std::uint32_t bmsk_clamp( + std::uint32_t a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 760 +extern "C" __device__ void __cuda_ptx_bmsk_clamp_is_not_supported_before_SM_70__(); +template +__device__ static inline std::uint32_t bmsk_clamp( + std::uint32_t a_reg, + std::uint32_t b_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "bmsk.clamp.b32 %0, %1, %2;" + : "=r"(dest) + : "r"(a_reg), + "r"(b_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bmsk_clamp_is_not_supported_before_SM_70__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 760 + +/* +// bmsk.wrap.b32 dest, a_reg, b_reg; // PTX ISA 76, SM_70 +template +__device__ static inline std::uint32_t bmsk_wrap( + std::uint32_t a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 760 +extern "C" __device__ void __cuda_ptx_bmsk_wrap_is_not_supported_before_SM_70__(); +template +__device__ static inline std::uint32_t bmsk_wrap( + std::uint32_t a_reg, + std::uint32_t b_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "bmsk.wrap.b32 %0, %1, %2;" + : "=r"(dest) + : "r"(a_reg), + "r"(b_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_bmsk_wrap_is_not_supported_before_SM_70__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 760 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_BMSK_H + +// End of ./instructions/bmsk.h +// Start of ./instructions/clusterlaunchcontrol.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CLUSTERLAUNCHCONTROL_H +#define INSTRUCTIONS_CLUSTERLAUNCHCONTROL_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/clusterlaunchcontrol.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [addr], [smem_bar]; // PTX ISA 86, SM_100 +template +__device__ static inline void clusterlaunchcontrol_try_cancel( + void* addr, + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_clusterlaunchcontrol_try_cancel_is_not_supported_before_SM_100__(); +template +__device__ static inline void clusterlaunchcontrol_try_cancel( + void* addr, + std::uint64_t* smem_bar) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [%0], [%1];" + : + : "r"(__as_ptr_smem(addr)), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_clusterlaunchcontrol_try_cancel_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [addr], [smem_bar]; // PTX ISA 86, SM_100a, SM_110a +template +__device__ static inline void clusterlaunchcontrol_try_cancel_multicast( + void* addr, + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_clusterlaunchcontrol_try_cancel_multicast_is_only_supported_on_SM_100a_110a__(); +template +__device__ static inline void clusterlaunchcontrol_try_cancel_multicast( + void* addr, + std::uint64_t* smem_bar) +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + asm ( + "clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [%0], [%1];" + : + : "r"(__as_ptr_smem(addr)), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_clusterlaunchcontrol_try_cancel_multicast_is_only_supported_on_SM_100a_110a__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 pred_is_canceled, try_cancel_response; // PTX ISA 86, SM_100 +template = true> +__device__ static inline bool clusterlaunchcontrol_query_cancel_is_canceled( + B128 try_cancel_response); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_clusterlaunchcontrol_query_cancel_is_canceled_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline bool clusterlaunchcontrol_query_cancel_is_canceled( + B128 try_cancel_response) +{ + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + std::uint32_t pred_is_canceled; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + ".reg .b128 B128_try_cancel_response; \n\t" + "mov.b128 B128_try_cancel_response, {%1, %2}; \n\t" + "clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 P_OUT, B128_try_cancel_response; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(pred_is_canceled) + : "l"((*reinterpret_cast(&try_cancel_response)).x), + "l"((*reinterpret_cast(&try_cancel_response)).y) + : + ); + return static_cast(pred_is_canceled); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_clusterlaunchcontrol_query_cancel_is_canceled_is_not_supported_before_SM_100__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100 +template = true, typename B128, std::enable_if_t = true> +__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_x( + B128 try_cancel_response); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_x_is_not_supported_before_SM_100__(); +template = true, typename B128, std::enable_if_t = true> +__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_x( + B128 try_cancel_response) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + std::uint32_t ret_dim; + asm ( + "{\n\t" + ".reg .b128 B128_try_cancel_response; \n\t" + "mov.b128 B128_try_cancel_response, {%1, %2}; \n\t" + "clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 %0, B128_try_cancel_response; \n" + "}" + : "=r"(ret_dim) + : "l"((*reinterpret_cast(&try_cancel_response)).x), + "l"((*reinterpret_cast(&try_cancel_response)).y) + : + ); + return *reinterpret_cast(&ret_dim); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_x_is_not_supported_before_SM_100__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100 +template = true, typename B128, std::enable_if_t = true> +__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_y( + B128 try_cancel_response); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_y_is_not_supported_before_SM_100__(); +template = true, typename B128, std::enable_if_t = true> +__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_y( + B128 try_cancel_response) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + std::uint32_t ret_dim; + asm ( + "{\n\t" + ".reg .b128 B128_try_cancel_response; \n\t" + "mov.b128 B128_try_cancel_response, {%1, %2}; \n\t" + "clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 %0, B128_try_cancel_response; \n" + "}" + : "=r"(ret_dim) + : "l"((*reinterpret_cast(&try_cancel_response)).x), + "l"((*reinterpret_cast(&try_cancel_response)).y) + : + ); + return *reinterpret_cast(&ret_dim); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_y_is_not_supported_before_SM_100__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100 +template = true, typename B128, std::enable_if_t = true> +__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_z( + B128 try_cancel_response); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_z_is_not_supported_before_SM_100__(); +template = true, typename B128, std::enable_if_t = true> +__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_z( + B128 try_cancel_response) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + std::uint32_t ret_dim; + asm ( + "{\n\t" + ".reg .b128 B128_try_cancel_response; \n\t" + "mov.b128 B128_try_cancel_response, {%1, %2}; \n\t" + "clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 %0, B128_try_cancel_response; \n" + "}" + : "=r"(ret_dim) + : "l"((*reinterpret_cast(&try_cancel_response)).x), + "l"((*reinterpret_cast(&try_cancel_response)).y) + : + ); + return *reinterpret_cast(&ret_dim); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_z_is_not_supported_before_SM_100__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 block_dim, try_cancel_response; // PTX ISA 86, SM_100 +template = true, typename B128, std::enable_if_t = true> +__device__ static inline void clusterlaunchcontrol_query_cancel_get_first_ctaid( + B32 (&block_dim)[4], + B128 try_cancel_response); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_is_not_supported_before_SM_100__(); +template = true, typename B128, std::enable_if_t = true> +__device__ static inline void clusterlaunchcontrol_query_cancel_get_first_ctaid( + B32 (&block_dim)[4], + B128 try_cancel_response) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "{\n\t" + ".reg .b128 B128_try_cancel_response; \n\t" + "mov.b128 B128_try_cancel_response, {%4, %5}; \n\t" + "clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {%0, %1, %2, %3}, B128_try_cancel_response; \n" + "}" + : "=r"(block_dim[0]), + "=r"(block_dim[1]), + "=r"(block_dim[2]), + "=r"(block_dim[3]) + : "l"((*reinterpret_cast(&try_cancel_response)).x), + "l"((*reinterpret_cast(&try_cancel_response)).y) + : + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_clusterlaunchcontrol_query_cancel_get_first_ctaid_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CLUSTERLAUNCHCONTROL_H + +// End of ./instructions/clusterlaunchcontrol.h +// Start of ./instructions/cp_async_bulk.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CP_ASYNC_BULK_H +#define INSTRUCTIONS_CP_ASYNC_BULK_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/cp_async_bulk.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + + + +/* +// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* smem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(__as_ptr_gmem(srcMem)), + "r"(size), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 86, SM_90 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(__as_ptr_gmem(srcMem)), + "r"(size), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [rdsmem_bar]; // PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes [%0], [%1], %2, [%3];" + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes.ignore_oob [dstMem], [srcMem], size, ignoreBytesLeft, ignoreBytesRight, [smem_bar]; // PTX ISA 92, SM_90 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_ignore_oob( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + const std::uint32_t& ignoreBytesLeft, + const std::uint32_t& ignoreBytesRight, + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 920 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_ignore_oob_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_ignore_oob( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + const std::uint32_t& ignoreBytesLeft, + const std::uint32_t& ignoreBytesRight, + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.ignore_oob [%0], [%1], %2, %3, %4, [%5];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(__as_ptr_gmem(srcMem)), + "r"(size), + "r"(ignoreBytesLeft), + "r"(ignoreBytesRight), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_ignore_oob_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 920 + +/* +// cp.async.bulk.dst.src.bulk_group [dstMem], [srcMem], size; // PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.global.shared::cta.bulk_group [%0], [%1], %2;" + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.dst.src.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask; // PTX ISA 86, SM_100 +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk_cp_mask( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + const std::uint16_t& byteMask); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_cp_mask_is_not_supported_before_SM_100__(); +template +__device__ static inline void cp_async_bulk_cp_mask( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + const std::uint16_t& byteMask) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "cp.async.bulk.global.shared::cta.bulk_group.cp_mask [%0], [%1], %2, %3;" + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "h"(byteMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_cp_mask_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + + +/* +// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem], size, [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* srcMem, + const std::uint32_t& size, + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1], %2, [%3], %4;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(__as_ptr_gmem(srcMem)), + "r"(size), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CP_ASYNC_BULK_H + +// End of ./instructions/cp_async_bulk.h +// Start of ./instructions/cp_async_bulk_commit_group.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CP_ASYNC_BULK_COMMIT_GROUP_H +#define INSTRUCTIONS_CP_ASYNC_BULK_COMMIT_GROUP_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/cp_async_bulk_commit_group.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// cp.async.bulk.commit_group; // PTX ISA 80, SM_90 +template +__device__ static inline void cp_async_bulk_commit_group(); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_commit_group_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_commit_group() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "cp.async.bulk.commit_group;" + : + : + : + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_commit_group_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CP_ASYNC_BULK_COMMIT_GROUP_H + +// End of ./instructions/cp_async_bulk_commit_group.h +// Start of ./instructions/cp_async_bulk_tensor.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CP_ASYNC_BULK_TENSOR_H +#define INSTRUCTIONS_CP_ASYNC_BULK_TENSOR_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/cp_async_bulk_tensor.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2}], [%3];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2}], [%3];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cta } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2}], [%3];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2}], [%3];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.1d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group [%0, {%1}], [%2];" + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3}], [%4];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3}], [%4];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cta } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3}], [%4];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3}], [%4];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group [%0, {%1, %2}], [%3];" + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4}], [%5];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4}], [%5];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cta } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3, %4}], [%5];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3, %4}], [%5];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.3d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3}], [%4];" + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5}], [%6];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5}], [%6];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cta } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3, %4, %5}], [%6];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3, %4, %5}], [%6];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.4d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5];" + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5, %6}], [%7];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5, %6}], [%7];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cta } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3, %4, %5, %6}], [%7];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3, %4, %5, %6}], [%7];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.5d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6];" + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + + + + + +/* +// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, {%2}], [%3], %4;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%0], [%1, {%2}], [%3], %4;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%0], [%1, {%2}], [%3], %4;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, {%2, %3}], [%4], %5;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%0], [%1, {%2, %3}], [%4], %5;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%0], [%1, {%2, %3}], [%4], %5;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, {%2, %3, %4}], [%5], %6;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%0], [%1, {%2, %3, %4}], [%5], %6;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%0], [%1, {%2, %3, %4}], [%5], %6;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, {%2, %3, %4, %5}], [%6], %7;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%0], [%1, {%2, %3, %4, %5}], [%6], %7;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%0], [%1, {%2, %3, %4, %5}], [%6], %7;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + + + + + +/* +// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100 +// .dst = { .shared::cta } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100__(); +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3, %4, %5, %6}], [%7];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cta } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_shared_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar) +{ + // space == space_shared (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::1 [%0], [%1, {%2, %3, %4, %5, %6}], [%7];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::2 [%0], [%1, {%2, %3, %4, %5, %6}], [%7];" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .shared::cluster } +// .src = { .global } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void cp_async_bulk_tensor_tile_gather4( + cuda_ptx::space_cluster_t, + cuda_ptx::space_global_t, + cuda_ptx::cta_group_t cta_group, + void* dstMem, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + std::uint64_t* smem_bar, + const std::uint16_t& ctaMask) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_global (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%0], [%1, {%2, %3, %4, %5, %6}], [%7], %8;" + : + : "r"(__as_ptr_smem(dstMem)), + "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_tile_gather4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// cp.async.bulk.tensor.2d.dst.src.tile::scatter4.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .dst = { .global } +// .src = { .shared::cta } +template +__device__ static inline void cp_async_bulk_tensor_tile_scatter4( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_tensor_tile_scatter4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void cp_async_bulk_tensor_tile_scatter4( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6];" + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_tensor_tile_scatter4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + + + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CP_ASYNC_BULK_TENSOR_H + +// End of ./instructions/cp_async_bulk_tensor.h +// Start of ./instructions/cp_async_bulk_wait_group.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CP_ASYNC_BULK_WAIT_GROUP_H +#define INSTRUCTIONS_CP_ASYNC_BULK_WAIT_GROUP_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/cp_async_bulk_wait_group.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// cp.async.bulk.wait_group N; // PTX ISA 80, SM_90 +template +__device__ static inline void cp_async_bulk_wait_group( + cuda_ptx::n32_t N); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_wait_group_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_wait_group( + cuda_ptx::n32_t N) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "cp.async.bulk.wait_group %0;" + : + : "n"(N.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_wait_group_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.async.bulk.wait_group.read N; // PTX ISA 80, SM_90 +template +__device__ static inline void cp_async_bulk_wait_group_read( + cuda_ptx::n32_t N); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_async_bulk_wait_group_read_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_async_bulk_wait_group_read( + cuda_ptx::n32_t N) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "cp.async.bulk.wait_group.read %0;" + : + : "n"(N.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_bulk_wait_group_read_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CP_ASYNC_BULK_WAIT_GROUP_H + +// End of ./instructions/cp_async_bulk_wait_group.h +// Start of ./instructions/cp_async_mbarrier_arrive.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CP_ASYNC_MBARRIER_ARRIVE_H +#define INSTRUCTIONS_CP_ASYNC_MBARRIER_ARRIVE_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/cp_async_mbarrier_arrive.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// cp.async.mbarrier.arrive.b64 [addr]; // PTX ISA 70, SM_80 +template +__device__ static inline void cp_async_mbarrier_arrive( + std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 700 +extern "C" __device__ void __cuda_ptx_cp_async_mbarrier_arrive_is_not_supported_before_SM_80__(); +template +__device__ static inline void cp_async_mbarrier_arrive( + std::uint64_t* addr) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "cp.async.mbarrier.arrive.b64 [%0];" + : + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_async_mbarrier_arrive_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 700 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CP_ASYNC_MBARRIER_ARRIVE_H + +// End of ./instructions/cp_async_mbarrier_arrive.h +// Start of ./instructions/cp_reduce_async_bulk.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CP_REDUCE_ASYNC_BULK_H +#define INSTRUCTIONS_CP_REDUCE_ASYNC_BULK_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/cp_reduce_async_bulk.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .b32 } +// .op = { .and } +template = true> +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_and_op_t, + B32* dstMem, + const B32* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_and_op_t, + B32* dstMem, + const B32* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_b32 (due to parameter type constraint) + // op == op_and_op (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.and.b32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .b32 } +// .op = { .or } +template = true> +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_or_op_t, + B32* dstMem, + const B32* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_or_op_t, + B32* dstMem, + const B32* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_b32 (due to parameter type constraint) + // op == op_or_op (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.or.b32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .b32 } +// .op = { .xor } +template = true> +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_xor_op_t, + B32* dstMem, + const B32* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_xor_op_t, + B32* dstMem, + const B32* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_b32 (due to parameter type constraint) + // op == op_xor_op (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.xor.b32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.u32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.u32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .inc } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_inc_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_inc_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_inc (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.inc.u32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .dec } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_dec_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_dec_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_dec (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.dec.u32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .s32 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s32 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.s32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .s32 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s32 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.s32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .s32 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s32 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.s32 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .u64 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u64 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64 [%0], [%1], %2, [%3]; // 1." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.u64 [dstMem], [srcMem], size, [rdsmem_bar]; // 2. PTX ISA 80, SM_90 +// .dst = { .shared::cluster } +// .src = { .shared::cta } +// .type = { .s64 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_cluster_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size, + std::uint64_t* rdsmem_bar) +{ + // space == space_cluster (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s64 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64 [%0], [%1], %2, [%3]; // 2." + : + : "r"(__as_ptr_remote_dsmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size), + "r"(__as_ptr_remote_dsmem(rdsmem_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .b32, .b64 } +// .op = { .and } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_and_op_t, + Type* dstMem, + const Type* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_and_op_t, + Type* dstMem, + const Type* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(Type) == 4 || sizeof(Type) == 8, ""); + // op == op_and_op (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sizeof(Type) == 4) { + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b32 [%0], [%1], %2; // 3." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + } else if constexpr (sizeof(Type) == 8) { + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b64 [%0], [%1], %2; // 3." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .b32, .b64 } +// .op = { .or } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_or_op_t, + Type* dstMem, + const Type* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_or_op_t, + Type* dstMem, + const Type* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(Type) == 4 || sizeof(Type) == 8, ""); + // op == op_or_op (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sizeof(Type) == 4) { + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b32 [%0], [%1], %2; // 3." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + } else if constexpr (sizeof(Type) == 8) { + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b64 [%0], [%1], %2; // 3." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .b32, .b64 } +// .op = { .xor } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_xor_op_t, + Type* dstMem, + const Type* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_xor_op_t, + Type* dstMem, + const Type* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(Type) == 4 || sizeof(Type) == 8, ""); + // op == op_xor_op (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sizeof(Type) == 4) { + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b32 [%0], [%1], %2; // 3." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + } else if constexpr (sizeof(Type) == 8) { + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b64 [%0], [%1], %2; // 3." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .inc } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_inc_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_inc_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_inc (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.inc.u32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u32 } +// .op = { .dec } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_dec_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_dec_t, + std::uint32_t* dstMem, + const std::uint32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u32 (due to parameter type constraint) + // op == op_dec (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.dec.u32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .s32 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s32 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .s32 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s32 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .s32 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int32_t* dstMem, + const std::int32_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s32 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.s32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u64 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u64 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u64 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u64 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u64 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u64 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .u64 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::uint64_t* dstMem, + const std::uint64_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_u64 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .s64 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s64 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s64 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .s64 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s64 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s64 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .f32 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + float* dstMem, + const float* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + float* dstMem, + const float* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_f32 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f32 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .f64 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + double* dstMem, + const double* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + double* dstMem, + const double* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_f64 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f64 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.u64 [dstMem], [srcMem], size; // 6. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .s64 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + std::int64_t* dstMem, + const std::int64_t* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_s64 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64 [%0], [%1], %2; // 6." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .f16 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + __half* dstMem, + const __half* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + __half* dstMem, + const __half* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_f16 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.min.f16 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .f16 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + __half* dstMem, + const __half* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + __half* dstMem, + const __half* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_f16 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.max.f16 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.noftz.type [dstMem], [srcMem], size; // 5. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .f16 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + __half* dstMem, + const __half* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + __half* dstMem, + const __half* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_f16 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f16 [%0], [%1], %2; // 5." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .bf16 } +// .op = { .min } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + __nv_bfloat16* dstMem, + const __nv_bfloat16* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_min_t, + __nv_bfloat16* dstMem, + const __nv_bfloat16* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_bf16 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.min.bf16 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .bf16 } +// .op = { .max } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + __nv_bfloat16* dstMem, + const __nv_bfloat16* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_max_t, + __nv_bfloat16* dstMem, + const __nv_bfloat16* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_bf16 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.max.bf16 [%0], [%1], %2; // 4." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.dst.src.bulk_group.op.noftz.type [dstMem], [srcMem], size; // 5. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .type = { .bf16 } +// .op = { .add } +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + __nv_bfloat16* dstMem, + const __nv_bfloat16* srcMem, + std::uint32_t size); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_add_t, + __nv_bfloat16* dstMem, + const __nv_bfloat16* srcMem, + std::uint32_t size) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // type == type_bf16 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16 [%0], [%1], %2; // 5." + : + : "l"(__as_ptr_gmem(dstMem)), + "r"(__as_ptr_smem(srcMem)), + "r"(size) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CP_REDUCE_ASYNC_BULK_H + +// End of ./instructions/cp_reduce_async_bulk.h +// Start of ./instructions/cp_reduce_async_bulk_tensor.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_CP_REDUCE_ASYNC_BULK_TENSOR_H +#define INSTRUCTIONS_CP_REDUCE_ASYNC_BULK_TENSOR_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/cp_reduce_async_bulk_tensor.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor } +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[1], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(op == op_add || op == op_min || op == op_max || op == op_inc || op == op_dec || op == op_and_op || op == op_or_op || op == op_xor_op, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (op == op_add) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.add.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_min) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.min.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.max.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_inc) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.inc.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_dec) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.dec.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_and_op) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.and.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_or_op) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.or.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_xor_op) { + asm ( + "cp.reduce.async.bulk.tensor.1d.global.shared::cta.xor.tile.bulk_group [%0, {%1}], [%2]; // 1a." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor } +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[2], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(op == op_add || op == op_min || op == op_max || op == op_inc || op == op_dec || op == op_and_op || op == op_or_op || op == op_xor_op, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (op == op_add) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_min) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_inc) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_dec) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_and_op) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_or_op) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_xor_op) { + asm ( + "cp.reduce.async.bulk.tensor.2d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2}], [%3]; // 1b." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor } +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[3], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(op == op_add || op == op_min || op == op_max || op == op_inc || op == op_dec || op == op_and_op || op == op_or_op || op == op_xor_op, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (op == op_add) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_min) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_inc) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_dec) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_and_op) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_or_op) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_xor_op) { + asm ( + "cp.reduce.async.bulk.tensor.3d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3}], [%4]; // 1c." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor } +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[4], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(op == op_add || op == op_min || op == op_max || op == op_inc || op == op_dec || op == op_and_op || op == op_or_op || op == op_xor_op, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (op == op_add) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_min) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_inc) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_dec) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_and_op) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_or_op) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_xor_op) { + asm ( + "cp.reduce.async.bulk.tensor.4d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3, %4}], [%5]; // 1d." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90 +// .dst = { .global } +// .src = { .shared::cta } +// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor } +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + const void* srcMem); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); +template +__device__ static inline void cp_reduce_async_bulk_tensor( + cuda_ptx::space_global_t, + cuda_ptx::space_shared_t, + cuda_ptx::op_t op, + const void* tensorMap, + const std::int32_t (&tensorCoords)[5], + const void* srcMem) +{ + // space == space_global (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + static_assert(op == op_add || op == op_min || op == op_max || op == op_inc || op == op_dec || op == op_and_op || op == op_or_op || op == op_xor_op, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (op == op_add) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.add.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_min) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.min.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.max.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_inc) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.inc.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_dec) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.dec.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_and_op) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.and.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_or_op) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.or.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } else if constexpr (op == op_xor_op) { + asm ( + "cp.reduce.async.bulk.tensor.5d.global.shared::cta.xor.tile.bulk_group [%0, {%1, %2, %3, %4, %5}], [%6]; // 1e." + : + : "l"(tensorMap), + "r"(tensorCoords[0]), + "r"(tensorCoords[1]), + "r"(tensorCoords[2]), + "r"(tensorCoords[3]), + "r"(tensorCoords[4]), + "r"(__as_ptr_smem(srcMem)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_cp_reduce_async_bulk_tensor_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_CP_REDUCE_ASYNC_BULK_TENSOR_H + +// End of ./instructions/cp_reduce_async_bulk_tensor.h +// Start of ./instructions/elect_sync.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_ELECT_SYNC_H +#define INSTRUCTIONS_ELECT_SYNC_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/elect_sync.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// elect.sync _|is_elected, membermask; // PTX ISA 80, SM_90 +template +__device__ static inline bool elect_sync( + const std::uint32_t& membermask); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_elect_sync_is_not_supported_before_SM_90__(); +template +__device__ static inline bool elect_sync( + const std::uint32_t& membermask) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t is_elected; + asm volatile ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "elect.sync _|P_OUT, %1; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(is_elected) + : "r"(membermask) + : + ); + return static_cast(is_elected); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_elect_sync_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_ELECT_SYNC_H + +// End of ./instructions/elect_sync.h +// Start of ./instructions/exit.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_EXIT_H +#define INSTRUCTIONS_EXIT_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/exit.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// exit; // PTX ISA 10, SM_50 +template +__device__ static inline void exit(); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_exit_is_not_supported_before_SM_50__(); +template +__device__ static inline void exit() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + asm volatile ( + "exit;" + : + : + : + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_exit_is_not_supported_before_SM_50__(); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_EXIT_H + +// End of ./instructions/exit.h +// Start of ./instructions/fence.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_FENCE_H +#define INSTRUCTIONS_FENCE_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/fence.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// fence.sem.scope; // 1. PTX ISA 60, SM_70 +// .sem = { .sc } +// .scope = { .cta, .gpu, .sys } +template +__device__ static inline void fence( + cuda_ptx::sem_sc_t, + cuda_ptx::scope_t scope); +*/ +#if __libcuda_ptx_isa >= 600 +extern "C" __device__ void __cuda_ptx_fence_is_not_supported_before_SM_70__(); +template +__device__ static inline void fence( + cuda_ptx::sem_sc_t, + cuda_ptx::scope_t scope) +{ + // sem == sem_sc (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_gpu || scope == scope_sys, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + if constexpr (scope == scope_cta) { + asm volatile ( + "fence.sc.cta; // 1." + : + : + : "memory" + ); + } else if constexpr (scope == scope_gpu) { + asm volatile ( + "fence.sc.gpu; // 1." + : + : + : "memory" + ); + } else if constexpr (scope == scope_sys) { + asm volatile ( + "fence.sc.sys; // 1." + : + : + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 600 + +/* +// fence.sem.scope; // 2. PTX ISA 78, SM_90 +// .sem = { .sc } +// .scope = { .cluster } +template +__device__ static inline void fence( + cuda_ptx::sem_sc_t, + cuda_ptx::scope_cluster_t); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_fence_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence( + cuda_ptx::sem_sc_t, + cuda_ptx::scope_cluster_t) +{ + // sem == sem_sc (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.sc.cluster; // 2." + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// fence.sem.scope; // 1. PTX ISA 60, SM_70 +// .sem = { .acq_rel } +// .scope = { .cta, .gpu, .sys } +template +__device__ static inline void fence( + cuda_ptx::sem_acq_rel_t, + cuda_ptx::scope_t scope); +*/ +#if __libcuda_ptx_isa >= 600 +extern "C" __device__ void __cuda_ptx_fence_is_not_supported_before_SM_70__(); +template +__device__ static inline void fence( + cuda_ptx::sem_acq_rel_t, + cuda_ptx::scope_t scope) +{ + // sem == sem_acq_rel (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_gpu || scope == scope_sys, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + if constexpr (scope == scope_cta) { + asm volatile ( + "fence.acq_rel.cta; // 1." + : + : + : "memory" + ); + } else if constexpr (scope == scope_gpu) { + asm volatile ( + "fence.acq_rel.gpu; // 1." + : + : + : "memory" + ); + } else if constexpr (scope == scope_sys) { + asm volatile ( + "fence.acq_rel.sys; // 1." + : + : + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 600 + +/* +// fence.sem.scope; // 2. PTX ISA 78, SM_90 +// .sem = { .acq_rel } +// .scope = { .cluster } +template +__device__ static inline void fence( + cuda_ptx::sem_acq_rel_t, + cuda_ptx::scope_cluster_t); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_fence_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence( + cuda_ptx::sem_acq_rel_t, + cuda_ptx::scope_cluster_t) +{ + // sem == sem_acq_rel (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.acq_rel.cluster; // 2." + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// fence.sem.scope; // PTX ISA 86, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +template +__device__ static inline void fence( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_fence_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (scope == scope_cta) { + asm volatile ( + "fence.acquire.cta;" + : + : + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm volatile ( + "fence.acquire.cluster;" + : + : + : "memory" + ); + } else if constexpr (scope == scope_gpu) { + asm volatile ( + "fence.acquire.gpu;" + : + : + : "memory" + ); + } else if constexpr (scope == scope_sys) { + asm volatile ( + "fence.acquire.sys;" + : + : + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// fence.sem.scope; // PTX ISA 86, SM_90 +// .sem = { .release } +// .scope = { .cta, .cluster, .gpu, .sys } +template +__device__ static inline void fence( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_fence_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope) +{ + // sem == sem_release (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (scope == scope_cta) { + asm volatile ( + "fence.release.cta;" + : + : + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm volatile ( + "fence.release.cluster;" + : + : + : "memory" + ); + } else if constexpr (scope == scope_gpu) { + asm volatile ( + "fence.release.gpu;" + : + : + : "memory" + ); + } else if constexpr (scope == scope_sys) { + asm volatile ( + "fence.release.sys;" + : + : + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 +/* +// fence.mbarrier_init.sem.scope; // 3. PTX ISA 80, SM_90 +// .sem = { .release } +// .scope = { .cluster } +template +__device__ static inline void fence_mbarrier_init( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_fence_mbarrier_init_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_mbarrier_init( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t) +{ + // sem == sem_release (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.mbarrier_init.release.cluster; // 3." + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_mbarrier_init_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 +/* +// fence.proxy.alias; // 4. PTX ISA 75, SM_70 +template +__device__ static inline void fence_proxy_alias(); +*/ +#if __libcuda_ptx_isa >= 750 +extern "C" __device__ void __cuda_ptx_fence_proxy_alias_is_not_supported_before_SM_70__(); +template +__device__ static inline void fence_proxy_alias() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm volatile ( + "fence.proxy.alias; // 4." + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_proxy_alias_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 750 +/* +// fence.proxy.async; // 5. PTX ISA 80, SM_90 +template +__device__ static inline void fence_proxy_async(); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_proxy_async() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.proxy.async; // 5." + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// fence.proxy.async.space; // 6. PTX ISA 80, SM_90 +// .space = { .global, .shared::cluster, .shared::cta } +template +__device__ static inline void fence_proxy_async( + cuda_ptx::space_t space); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_proxy_async( + cuda_ptx::space_t space) +{ + static_assert(space == space_global || space == space_cluster || space == space_shared, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (space == space_global) { + asm volatile ( + "fence.proxy.async.global; // 6." + : + : + : "memory" + ); + } else if constexpr (space == space_cluster) { + asm volatile ( + "fence.proxy.async.shared::cluster; // 6." + : + : + : "memory" + ); + } else if constexpr (space == space_shared) { + asm volatile ( + "fence.proxy.async.shared::cta; // 6." + : + : + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_proxy_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 +/* +// fence.proxy.tensormap::generic.release.scope; // 7. PTX ISA 83, SM_90 +// .sem = { .release } +// .scope = { .cta, .cluster, .gpu, .sys } +template +__device__ static inline void fence_proxy_tensormap_generic( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_proxy_tensormap_generic( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope) +{ + // sem == sem_release (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (scope == scope_cta) { + asm volatile ( + "fence.proxy.tensormap::generic.release.cta; // 7." + : + : + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm volatile ( + "fence.proxy.tensormap::generic.release.cluster; // 7." + : + : + : "memory" + ); + } else if constexpr (scope == scope_gpu) { + asm volatile ( + "fence.proxy.tensormap::generic.release.gpu; // 7." + : + : + : "memory" + ); + } else if constexpr (scope == scope_sys) { + asm volatile ( + "fence.proxy.tensormap::generic.release.sys; // 7." + : + : + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// fence.proxy.tensormap::generic.sem.scope [addr], size; // 8. PTX ISA 83, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +template +__device__ static inline void fence_proxy_tensormap_generic( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + const void* addr, + cuda_ptx::n32_t size); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_proxy_tensormap_generic( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + const void* addr, + cuda_ptx::n32_t size) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (scope == scope_cta) { + asm volatile ( + "fence.proxy.tensormap::generic.acquire.cta [%0], %1; // 8." + : + : "l"(addr), + "n"(size.value) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm volatile ( + "fence.proxy.tensormap::generic.acquire.cluster [%0], %1; // 8." + : + : "l"(addr), + "n"(size.value) + : "memory" + ); + } else if constexpr (scope == scope_gpu) { + asm volatile ( + "fence.proxy.tensormap::generic.acquire.gpu [%0], %1; // 8." + : + : "l"(addr), + "n"(size.value) + : "memory" + ); + } else if constexpr (scope == scope_sys) { + asm volatile ( + "fence.proxy.tensormap::generic.acquire.sys [%0], %1; // 8." + : + : "l"(addr), + "n"(size.value) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_proxy_tensormap_generic_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 +/* +// fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90 +// .sem = { .acquire } +// .space = { .shared::cluster } +// .scope = { .cluster } +template +__device__ static inline void fence_proxy_async_generic_sync_restrict( + cuda_ptx::sem_acquire_t, + cuda_ptx::space_cluster_t, + cuda_ptx::scope_cluster_t); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_proxy_async_generic_sync_restrict( + cuda_ptx::sem_acquire_t, + cuda_ptx::space_cluster_t, + cuda_ptx::scope_cluster_t) +{ + // sem == sem_acquire (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90 +// .sem = { .release } +// .space = { .shared::cta } +// .scope = { .cluster } +template +__device__ static inline void fence_proxy_async_generic_sync_restrict( + cuda_ptx::sem_release_t, + cuda_ptx::space_shared_t, + cuda_ptx::scope_cluster_t); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_proxy_async_generic_sync_restrict( + cuda_ptx::sem_release_t, + cuda_ptx::space_shared_t, + cuda_ptx::scope_cluster_t) +{ + // sem == sem_release (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_proxy_async_generic_sync_restrict_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 +/* +// fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90 +// .sem = { .acquire } +// .space = { .shared::cluster } +// .scope = { .cluster } +template +__device__ static inline void fence_sync_restrict( + cuda_ptx::sem_acquire_t, + cuda_ptx::space_cluster_t, + cuda_ptx::scope_cluster_t); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_sync_restrict( + cuda_ptx::sem_acquire_t, + cuda_ptx::space_cluster_t, + cuda_ptx::scope_cluster_t) +{ + // sem == sem_acquire (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.acquire.sync_restrict::shared::cluster.cluster;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90 +// .sem = { .release } +// .space = { .shared::cta } +// .scope = { .cluster } +template +__device__ static inline void fence_sync_restrict( + cuda_ptx::sem_release_t, + cuda_ptx::space_shared_t, + cuda_ptx::scope_cluster_t); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__(); +template +__device__ static inline void fence_sync_restrict( + cuda_ptx::sem_release_t, + cuda_ptx::space_shared_t, + cuda_ptx::scope_cluster_t) +{ + // sem == sem_release (due to parameter type constraint) + // space == space_shared (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "fence.release.sync_restrict::shared::cta.cluster;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_fence_sync_restrict_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_FENCE_H + +// End of ./instructions/fence.h +// Start of ./instructions/get_sreg.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_GET_SREG_H +#define INSTRUCTIONS_GET_SREG_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/get_sreg.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// mov.u32 sreg_value, %%tid.x; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_tid_x(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_tid_x() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%tid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%tid.y; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_tid_y(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_tid_y() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%tid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%tid.z; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_tid_z(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_tid_z() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%tid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%ntid.x; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_ntid_x(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_ntid_x() +{ + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%ntid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%ntid.y; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_ntid_y(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_ntid_y() +{ + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%ntid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%ntid.z; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_ntid_z(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_ntid_z() +{ + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%ntid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%laneid; // PTX ISA 13 +template +__device__ static inline std::uint32_t get_sreg_laneid(); +*/ +#if __libcuda_ptx_isa >= 130 +template +__device__ static inline std::uint32_t get_sreg_laneid() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%laneid;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 130 + +/* +// mov.u32 sreg_value, %%warpid; // PTX ISA 13 +template +__device__ static inline std::uint32_t get_sreg_warpid(); +*/ +#if __libcuda_ptx_isa >= 130 +template +__device__ static inline std::uint32_t get_sreg_warpid() +{ + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%warpid;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 130 + +/* +// mov.u32 sreg_value, %%nwarpid; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint32_t get_sreg_nwarpid(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_nwarpid_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_nwarpid() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%nwarpid;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_nwarpid_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%ctaid.x; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_ctaid_x(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_ctaid_x() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%ctaid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%ctaid.y; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_ctaid_y(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_ctaid_y() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%ctaid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%ctaid.z; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_ctaid_z(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_ctaid_z() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%ctaid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%nctaid.x; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_nctaid_x(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_nctaid_x() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%nctaid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%nctaid.y; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_nctaid_y(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_nctaid_y() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%nctaid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%nctaid.z; // PTX ISA 20 +template +__device__ static inline std::uint32_t get_sreg_nctaid_z(); +*/ +#if __libcuda_ptx_isa >= 200 +template +__device__ static inline std::uint32_t get_sreg_nctaid_z() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%nctaid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%smid; // PTX ISA 13 +template +__device__ static inline std::uint32_t get_sreg_smid(); +*/ +#if __libcuda_ptx_isa >= 130 +template +__device__ static inline std::uint32_t get_sreg_smid() +{ + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%smid;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 130 + +/* +// mov.u32 sreg_value, %%nsmid; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint32_t get_sreg_nsmid(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_nsmid_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_nsmid() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%nsmid;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_nsmid_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u64 sreg_value, %%gridid; // PTX ISA 30 +template +__device__ static inline std::uint64_t get_sreg_gridid(); +*/ +#if __libcuda_ptx_isa >= 300 +template +__device__ static inline std::uint64_t get_sreg_gridid() +{ + std::uint64_t sreg_value; + asm ( + "mov.u64 %0, %%gridid;" + : "=l"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 300 + +/* +// mov.pred sreg_value, %%is_explicit_cluster; // PTX ISA 78, SM_90 +template +__device__ static inline bool get_sreg_is_explicit_cluster(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_is_explicit_cluster_is_not_supported_before_SM_90__(); +template +__device__ static inline bool get_sreg_is_explicit_cluster() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mov.pred P_OUT, %%is_explicit_cluster; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(sreg_value) + : + : + ); + return static_cast(sreg_value); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_is_explicit_cluster_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%clusterid.x; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_clusterid_x(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_clusterid_x_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_clusterid_x() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%clusterid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_clusterid_x_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%clusterid.y; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_clusterid_y(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_clusterid_y_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_clusterid_y() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%clusterid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_clusterid_y_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%clusterid.z; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_clusterid_z(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_clusterid_z_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_clusterid_z() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%clusterid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_clusterid_z_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%nclusterid.x; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_nclusterid_x(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_nclusterid_x_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_nclusterid_x() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%nclusterid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_nclusterid_x_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%nclusterid.y; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_nclusterid_y(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_nclusterid_y_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_nclusterid_y() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%nclusterid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_nclusterid_y_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%nclusterid.z; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_nclusterid_z(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_nclusterid_z_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_nclusterid_z() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%nclusterid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_nclusterid_z_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_ctaid.x; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_ctaid_x(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_ctaid_x_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_ctaid_x() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_ctaid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_ctaid_x_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_ctaid.y; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_ctaid_y(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_ctaid_y_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_ctaid_y() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_ctaid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_ctaid_y_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_ctaid.z; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_ctaid_z(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_ctaid_z_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_ctaid_z() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_ctaid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_ctaid_z_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_nctaid.x; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_nctaid_x(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_nctaid_x_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_nctaid_x() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_nctaid.x;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_nctaid_x_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_nctaid.y; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_nctaid_y(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_nctaid_y_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_nctaid_y() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_nctaid.y;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_nctaid_y_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_nctaid.z; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_nctaid_z(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_nctaid_z_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_nctaid_z() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_nctaid.z;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_nctaid_z_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_ctarank; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_ctarank(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_ctarank_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_ctarank() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_ctarank;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_ctarank_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%cluster_nctarank; // PTX ISA 78, SM_90 +template +__device__ static inline std::uint32_t get_sreg_cluster_nctarank(); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_get_sreg_cluster_nctarank_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_cluster_nctarank() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%cluster_nctarank;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_cluster_nctarank_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mov.u32 sreg_value, %%lanemask_eq; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint32_t get_sreg_lanemask_eq(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_lanemask_eq_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_lanemask_eq() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%lanemask_eq;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_lanemask_eq_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%lanemask_le; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint32_t get_sreg_lanemask_le(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_lanemask_le_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_lanemask_le() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%lanemask_le;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_lanemask_le_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%lanemask_lt; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint32_t get_sreg_lanemask_lt(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_lanemask_lt_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_lanemask_lt() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%lanemask_lt;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_lanemask_lt_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%lanemask_ge; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint32_t get_sreg_lanemask_ge(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_lanemask_ge_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_lanemask_ge() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%lanemask_ge;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_lanemask_ge_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%lanemask_gt; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint32_t get_sreg_lanemask_gt(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_lanemask_gt_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_lanemask_gt() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%lanemask_gt;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_lanemask_gt_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u32 sreg_value, %%clock; // PTX ISA 10 +template +__device__ static inline std::uint32_t get_sreg_clock(); +*/ +#if __libcuda_ptx_isa >= 100 +template +__device__ static inline std::uint32_t get_sreg_clock() +{ + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%clock;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// mov.u32 sreg_value, %%clock_hi; // PTX ISA 50, SM_35 +template +__device__ static inline std::uint32_t get_sreg_clock_hi(); +*/ +#if __libcuda_ptx_isa >= 500 +extern "C" __device__ void __cuda_ptx_get_sreg_clock_hi_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_clock_hi() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%clock_hi;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_clock_hi_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 500 + +/* +// mov.u64 sreg_value, %%clock64; // PTX ISA 20, SM_35 +template +__device__ static inline std::uint64_t get_sreg_clock64(); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_get_sreg_clock64_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint64_t get_sreg_clock64() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint64_t sreg_value; + asm volatile ( + "mov.u64 %0, %%clock64;" + : "=l"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_clock64_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// mov.u64 sreg_value, %%globaltimer; // PTX ISA 31, SM_35 +template +__device__ static inline std::uint64_t get_sreg_globaltimer(); +*/ +#if __libcuda_ptx_isa >= 310 +extern "C" __device__ void __cuda_ptx_get_sreg_globaltimer_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint64_t get_sreg_globaltimer() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint64_t sreg_value; + asm volatile ( + "mov.u64 %0, %%globaltimer;" + : "=l"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_globaltimer_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 310 + +/* +// mov.u32 sreg_value, %%globaltimer_lo; // PTX ISA 31, SM_35 +template +__device__ static inline std::uint32_t get_sreg_globaltimer_lo(); +*/ +#if __libcuda_ptx_isa >= 310 +extern "C" __device__ void __cuda_ptx_get_sreg_globaltimer_lo_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_globaltimer_lo() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%globaltimer_lo;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_globaltimer_lo_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 310 + +/* +// mov.u32 sreg_value, %%globaltimer_hi; // PTX ISA 31, SM_35 +template +__device__ static inline std::uint32_t get_sreg_globaltimer_hi(); +*/ +#if __libcuda_ptx_isa >= 310 +extern "C" __device__ void __cuda_ptx_get_sreg_globaltimer_hi_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_globaltimer_hi() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm volatile ( + "mov.u32 %0, %%globaltimer_hi;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_globaltimer_hi_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 310 + +/* +// mov.u32 sreg_value, %%total_smem_size; // PTX ISA 41, SM_35 +template +__device__ static inline std::uint32_t get_sreg_total_smem_size(); +*/ +#if __libcuda_ptx_isa >= 410 +extern "C" __device__ void __cuda_ptx_get_sreg_total_smem_size_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_total_smem_size() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%total_smem_size;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_total_smem_size_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 410 + +/* +// mov.u32 sreg_value, %%aggr_smem_size; // PTX ISA 81, SM_90 +template +__device__ static inline std::uint32_t get_sreg_aggr_smem_size(); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_get_sreg_aggr_smem_size_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t get_sreg_aggr_smem_size() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%aggr_smem_size;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_aggr_smem_size_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// mov.u32 sreg_value, %%dynamic_smem_size; // PTX ISA 41, SM_35 +template +__device__ static inline std::uint32_t get_sreg_dynamic_smem_size(); +*/ +#if __libcuda_ptx_isa >= 410 +extern "C" __device__ void __cuda_ptx_get_sreg_dynamic_smem_size_is_not_supported_before_SM_35__(); +template +__device__ static inline std::uint32_t get_sreg_dynamic_smem_size() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 350 + std::uint32_t sreg_value; + asm ( + "mov.u32 %0, %%dynamic_smem_size;" + : "=r"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_dynamic_smem_size_is_not_supported_before_SM_35__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 410 + +/* +// mov.u64 sreg_value, %%current_graph_exec; // PTX ISA 80, SM_50 +template +__device__ static inline std::uint64_t get_sreg_current_graph_exec(); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_get_sreg_current_graph_exec_is_not_supported_before_SM_50__(); +template +__device__ static inline std::uint64_t get_sreg_current_graph_exec() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint64_t sreg_value; + asm ( + "mov.u64 %0, %%current_graph_exec;" + : "=l"(sreg_value) + : + : + ); + return sreg_value; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_get_sreg_current_graph_exec_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_GET_SREG_H + +// End of ./instructions/get_sreg.h +// Start of ./instructions/getctarank.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_GETCTARANK_H +#define INSTRUCTIONS_GETCTARANK_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/getctarank.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// getctarank.space.u32 dest, addr; // PTX ISA 78, SM_90 +// .space = { .shared::cluster } +template +__device__ static inline std::uint32_t getctarank( + cuda_ptx::space_cluster_t, + const void* addr); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_getctarank_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t getctarank( + cuda_ptx::space_cluster_t, + const void* addr) +{ + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + asm ( + "getctarank.shared::cluster.u32 %0, %1;" + : "=r"(dest) + : "r"(__as_ptr_smem(addr)) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_getctarank_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_GETCTARANK_H + +// End of ./instructions/getctarank.h +// Start of ./instructions/ld.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_LD_H +#define INSTRUCTIONS_LD_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/ld.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// ld.space.b8 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B8 ld( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B8 ld( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "ld.global.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_is_not_supported_before_SM_50__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.b16 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B16 ld( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B16 ld( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint16_t dest; + asm ( + "ld.global.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_is_not_supported_before_SM_50__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.b32 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B32 ld( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B32 ld( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "ld.global.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_is_not_supported_before_SM_50__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.b64 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B64 ld( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B64 ld( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint64_t dest; + asm ( + "ld.global.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_is_not_supported_before_SM_50__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.L1::evict_first.b8 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B8 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.b16 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B16 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_first.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_first.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.b32 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B32 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.b64 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B64 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_first.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_first.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_first.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_first.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_first.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_first.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_L1_evict_first( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.L1::evict_first.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.L1::evict_first.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_first.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_first.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_first.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_first.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_first.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.L1::evict_first.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.L1::evict_last.b8 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B8 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.b16 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B16 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_last.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_last.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.b32 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B32 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.b64 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B64 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_last.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_last.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_last.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_last.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_last.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_last.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_L1_evict_last( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.L1::evict_last.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.L1::evict_last.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::evict_last.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_last.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_last.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::evict_last.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::evict_last.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.L1::evict_last.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.L1::no_allocate.b8 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B8 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.b16 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B16 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint16_t dest; + asm ( + "ld.global.L1::no_allocate.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::no_allocate.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.b32 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B32 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.b64 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B64 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint64_t dest; + asm ( + "ld.global.L1::no_allocate.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::no_allocate.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::no_allocate.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::no_allocate.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::no_allocate.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::no_allocate.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_L1_no_allocate( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.L1::no_allocate.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::no_allocate.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.L1::no_allocate.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.L1::no_allocate.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.L1::no_allocate.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.b8 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B8 ld_nc( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "ld.global.nc.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.nc.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.b16 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B16 ld_nc( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint16_t dest; + asm ( + "ld.global.nc.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.nc.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.b32 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B32 ld_nc( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "ld.global.nc.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.nc.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.b64 dest, [addr]; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B64 ld_nc( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint64_t dest; + asm ( + "ld.global.nc.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_is_not_supported_before_SM_50__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// ld.space.nc.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld_nc( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.L1::evict_first.b8 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.b16 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_first.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.b32 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.b64 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_first.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_first.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_first.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_first_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_first.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_first.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc_L1_evict_first( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.L1::evict_first.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_first.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_first_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_first.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_first.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.L1::evict_first.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.L1::evict_last.b8 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.b16 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_last.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.b32 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.b64 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_last.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_last.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_last.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_last_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_last.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_last.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc_L1_evict_last( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.L1::evict_last.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_last.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_evict_last_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::evict_last.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::evict_last.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.L1::evict_last.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.L1::no_allocate.b8 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::256B.b8 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B8* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B8* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::256B.b8 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.b16 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::no_allocate.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::256B.b16 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B16* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B16* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::256B.b16 %0, [%1];" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.b32 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::256B.b32 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B32* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::256B.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.b64 dest, [addr]; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::no_allocate.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::256B.b64 dest, [addr]; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B64* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::256B.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.b128 dest, [addr]; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::no_allocate.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_70__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::no_allocate.L2::256B.b128 dest, [addr]; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B128* addr); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate_L2_256B( + cuda_ptx::space_global_t, + const B128* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::no_allocate.L2::256B.b128 B128_dest, [%2]; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::no_allocate.v4.b64 dest, [addr]; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B256* addr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc_L1_no_allocate( + cuda_ptx::space_global_t, + const B256* addr) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.L1::no_allocate.v4.b64 {%0, %1, %2, %3}, [%4];" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.L2::256B.b8 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B8 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B8* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.L2::256B.b8 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return __u32_as_b8(dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.L2::256B.b16 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B16 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B16* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint16_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.L2::256B.b16 %0, [%1], %2;" + : "=h"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.L2::256B.b32 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B32 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B32* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.L2::256B.b32 %0, [%1], %2;" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.L2::256B.b64 dest, [addr], cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B64 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B64* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.L2::256B.b64 %0, [%1], %2;" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::no_allocate.L2::cache_hint.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.L2::256B.b128 dest, [addr], cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline B128 ld_nc_L1_no_allocate_L2_cache_hint_L2_256B( + cuda_ptx::space_global_t, + const B128* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + longlong2 dest; + asm ( + "{\n\t" + ".reg .b128 B128_dest; \n\t" + "ld.global.nc.L1::no_allocate.L2::cache_hint.L2::256B.b128 B128_dest, [%2], %3; \n\t" + "mov.b128 {%0, %1}, B128_dest; \n" + "}" + : "=l"(dest.x), + "=l"(dest.y) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_L2_256B_is_not_supported_before_SM_80__(); + longlong2 err_out_var{0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// ld.space.nc.L1::no_allocate.L2::cache_hint.v4.b64 dest, [addr], cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline B256 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline B256 ld_nc_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + const B256* addr, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + cuda_ptx::longlong4_32a dest; + asm ( + "ld.global.nc.L1::no_allocate.L2::cache_hint.v4.b64 {%0, %1, %2, %3}, [%4], %5;" + : "=l"(dest.x), + "=l"(dest.y), + "=l"(dest.z), + "=l"(dest.w) + : "l"(__as_ptr_gmem(addr)), + "l"(cache_policy) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ld_nc_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_100__(); + cuda_ptx::longlong4_32a err_out_var{0, 0, 0, 0}; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_LD_H + +// End of ./instructions/ld.h +// Start of ./instructions/ldmatrix.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_LDMATRIX_H +#define INSTRUCTIONS_LDMATRIX_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/ldmatrix.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// ldmatrix.sync.aligned.m8n8.x1.space.b16 out, [smem_ptr]; // PTX ISA 65, SM_75 +// .space = { .shared } +template = true> +__device__ static inline void ldmatrix_m8n8( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const B16* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 650 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n8_is_not_supported_before_SM_75__(); +template = true> +__device__ static inline void ldmatrix_m8n8( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const B16* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 750 + asm ( + "ldmatrix.sync.aligned.m8n8.x1.shared.b16 {%0}, [%1];" + : "=r"(out[0]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n8_is_not_supported_before_SM_75__(); + #endif +} +#endif // __libcuda_ptx_isa >= 650 + +/* +// ldmatrix.sync.aligned.m8n8.x2.space.b16 out, [smem_ptr]; // PTX ISA 65, SM_75 +// .space = { .shared } +template = true> +__device__ static inline void ldmatrix_m8n8( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const B16* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 650 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n8_is_not_supported_before_SM_75__(); +template = true> +__device__ static inline void ldmatrix_m8n8( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const B16* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 750 + asm ( + "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n8_is_not_supported_before_SM_75__(); + #endif +} +#endif // __libcuda_ptx_isa >= 650 + +/* +// ldmatrix.sync.aligned.m8n8.x4.space.b16 out, [smem_ptr]; // PTX ISA 65, SM_75 +// .space = { .shared } +template = true> +__device__ static inline void ldmatrix_m8n8( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const B16* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 650 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n8_is_not_supported_before_SM_75__(); +template = true> +__device__ static inline void ldmatrix_m8n8( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const B16* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 750 + asm ( + "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n8_is_not_supported_before_SM_75__(); + #endif +} +#endif // __libcuda_ptx_isa >= 650 + +/* +// ldmatrix.sync.aligned.m8n8.x1.trans.space.b16 out, [smem_ptr]; // PTX ISA 65, SM_75 +// .space = { .shared } +template = true> +__device__ static inline void ldmatrix_m8n8_trans( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const B16* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 650 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n8_trans_is_not_supported_before_SM_75__(); +template = true> +__device__ static inline void ldmatrix_m8n8_trans( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const B16* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 750 + asm ( + "ldmatrix.sync.aligned.m8n8.x1.trans.shared.b16 {%0}, [%1];" + : "=r"(out[0]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n8_trans_is_not_supported_before_SM_75__(); + #endif +} +#endif // __libcuda_ptx_isa >= 650 + +/* +// ldmatrix.sync.aligned.m8n8.x2.trans.space.b16 out, [smem_ptr]; // PTX ISA 65, SM_75 +// .space = { .shared } +template = true> +__device__ static inline void ldmatrix_m8n8_trans( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const B16* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 650 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n8_trans_is_not_supported_before_SM_75__(); +template = true> +__device__ static inline void ldmatrix_m8n8_trans( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const B16* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 750 + asm ( + "ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n8_trans_is_not_supported_before_SM_75__(); + #endif +} +#endif // __libcuda_ptx_isa >= 650 + +/* +// ldmatrix.sync.aligned.m8n8.x4.trans.space.b16 out, [smem_ptr]; // PTX ISA 65, SM_75 +// .space = { .shared } +template = true> +__device__ static inline void ldmatrix_m8n8_trans( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const B16* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 650 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n8_trans_is_not_supported_before_SM_75__(); +template = true> +__device__ static inline void ldmatrix_m8n8_trans( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const B16* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 750 + asm ( + "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n8_trans_is_not_supported_before_SM_75__(); + #endif +} +#endif // __libcuda_ptx_isa >= 650 + +/* +// ldmatrix.sync.aligned.m8n16.x1.space.b8x16.b6x16_p32 out, [smem_ptr]; // PTX ISA 86, SM_100a, SM_110a +// .space = { .shared } +template +__device__ static inline void ldmatrix_m8n16_b8x16_b6x16_p32( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const void* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n16_b8x16_b6x16_p32_is_only_supported_on_SM_100a_110a__(); +template +__device__ static inline void ldmatrix_m8n16_b8x16_b6x16_p32( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const void* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + asm ( + "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {%0}, [%1];" + : "=r"(out[0]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n16_b8x16_b6x16_p32_is_only_supported_on_SM_100a_110a__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// ldmatrix.sync.aligned.m8n16.x1.space.b8x16.b4x16_p64 out, [smem_ptr]; // PTX ISA 86, SM_100a, SM_110a +// .space = { .shared } +template +__device__ static inline void ldmatrix_m8n16_b8x16_b4x16_p64( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const void* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n16_b8x16_b4x16_p64_is_only_supported_on_SM_100a_110a__(); +template +__device__ static inline void ldmatrix_m8n16_b8x16_b4x16_p64( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[1], + const void* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + asm ( + "ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {%0}, [%1];" + : "=r"(out[0]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n16_b8x16_b4x16_p64_is_only_supported_on_SM_100a_110a__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// ldmatrix.sync.aligned.m8n16.x2.space.b8x16.b6x16_p32 out, [smem_ptr]; // PTX ISA 86, SM_100a, SM_110a +// .space = { .shared } +template +__device__ static inline void ldmatrix_m8n16_b8x16_b6x16_p32( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const void* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n16_b8x16_b6x16_p32_is_only_supported_on_SM_100a_110a__(); +template +__device__ static inline void ldmatrix_m8n16_b8x16_b6x16_p32( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const void* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + asm ( + "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n16_b8x16_b6x16_p32_is_only_supported_on_SM_100a_110a__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// ldmatrix.sync.aligned.m8n16.x2.space.b8x16.b4x16_p64 out, [smem_ptr]; // PTX ISA 86, SM_100a, SM_110a +// .space = { .shared } +template +__device__ static inline void ldmatrix_m8n16_b8x16_b4x16_p64( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const void* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n16_b8x16_b4x16_p64_is_only_supported_on_SM_100a_110a__(); +template +__device__ static inline void ldmatrix_m8n16_b8x16_b4x16_p64( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[2], + const void* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + asm ( + "ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n16_b8x16_b4x16_p64_is_only_supported_on_SM_100a_110a__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// ldmatrix.sync.aligned.m8n16.x4.space.b8x16.b6x16_p32 out, [smem_ptr]; // PTX ISA 86, SM_100a, SM_110a +// .space = { .shared } +template +__device__ static inline void ldmatrix_m8n16_b8x16_b6x16_p32( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const void* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n16_b8x16_b6x16_p32_is_only_supported_on_SM_100a_110a__(); +template +__device__ static inline void ldmatrix_m8n16_b8x16_b6x16_p32( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const void* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + asm ( + "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n16_b8x16_b6x16_p32_is_only_supported_on_SM_100a_110a__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// ldmatrix.sync.aligned.m8n16.x4.space.b8x16.b4x16_p64 out, [smem_ptr]; // PTX ISA 86, SM_100a, SM_110a +// .space = { .shared } +template +__device__ static inline void ldmatrix_m8n16_b8x16_b4x16_p64( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const void* smem_ptr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_ldmatrix_m8n16_b8x16_b4x16_p64_is_only_supported_on_SM_100a_110a__(); +template +__device__ static inline void ldmatrix_m8n16_b8x16_b4x16_p64( + cuda_ptx::space_shared_t, + std::uint32_t (&out)[4], + const void* smem_ptr) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + asm ( + "ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(__as_ptr_smem(smem_ptr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_ldmatrix_m8n16_b8x16_b4x16_p64_is_only_supported_on_SM_100a_110a__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_LDMATRIX_H + +// End of ./instructions/ldmatrix.h +// Start of ./instructions/mapa.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_MAPA_H +#define INSTRUCTIONS_MAPA_H + +#include // NV_IF_TARGET below. + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/mapa.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// mapa{.space}.u32 dest, addr, target_cta; // PTX ISA 78, SM_90 +// .space = { .shared::cluster } +template +__device__ static inline Tp* mapa( + cuda_ptx::space_cluster_t, + const Tp* addr, + std::uint32_t target_cta); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_mapa_is_not_supported_before_SM_90__(); +template +__device__ static inline Tp* mapa( + cuda_ptx::space_cluster_t, + const Tp* addr, + std::uint32_t target_cta) +{ + // space == space_cluster (due to parameter type constraint) + NV_IF_ELSE_TARGET(NV_PROVIDES_SM_90, ( + return static_cast(__cluster_map_shared_rank(addr, target_cta)); + ),( + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mapa_is_not_supported_before_SM_90__(); + return __from_ptr_dsmem(0); + )); +} +#endif // __libcuda_ptx_isa >= 780 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_MAPA_H + +// End of ./instructions/mapa.h +// Start of ./instructions/mbarrier_arrive.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_MBARRIER_ARRIVE_H +#define INSTRUCTIONS_MBARRIER_ARRIVE_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/mbarrier_arrive.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// mbarrier.arrive.shared.b64 state, [addr]; // 1. PTX ISA 70, SM_80 +template +__device__ static inline std::uint64_t mbarrier_arrive( + std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 700 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_80__(); +template +__device__ static inline std::uint64_t mbarrier_arrive( + std::uint64_t* addr) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t state; + asm ( + "mbarrier.arrive.shared.b64 %0, [%1]; // 1. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_80__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 700 + +/* +// mbarrier.arrive.shared::cta.b64 state, [addr], count; // 2. PTX ISA 78, SM_90 +template +__device__ static inline std::uint64_t mbarrier_arrive( + std::uint64_t* addr, + const std::uint32_t& count); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t mbarrier_arrive( + std::uint64_t* addr, + const std::uint32_t& count) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t state; + asm ( + "mbarrier.arrive.shared::cta.b64 %0, [%1], %2; // 2. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mbarrier.arrive.sem.scope.space.b64 state, [addr]; // 3a. PTX ISA 80, SM_90 +// .sem = { .release } +// .scope = { .cta, .cluster } +// .space = { .shared::cta } +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr) +{ + // sem == sem_release (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t state; + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.arrive.release.cta.shared::cta.b64 %0, [%1]; // 3a. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.arrive.release.cluster.shared::cta.b64 %0, [%1]; // 3a. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + } + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // 3b. PTX ISA 80, SM_90 +// .sem = { .release } +// .scope = { .cta, .cluster } +// .space = { .shared::cta } +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& count); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& count) +{ + // sem == sem_release (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t state; + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.arrive.release.cta.shared::cta.b64 %0, [%1], %2; // 3b. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.arrive.release.cluster.shared::cta.b64 %0, [%1], %2; // 3b. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + } + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.arrive.sem.scope.space.b64 _, [addr]; // 4a. PTX ISA 80, SM_90 +// .sem = { .release } +// .scope = { .cluster } +// .space = { .shared::cluster } +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr) +{ + // sem == sem_release (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [%0]; // 4a. " + : + : "r"(__as_ptr_remote_dsmem(addr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.arrive.sem.scope.space.b64 _, [addr], count; // 4b. PTX ISA 80, SM_90 +// .sem = { .release } +// .scope = { .cluster } +// .space = { .shared::cluster } +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& count); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& count) +{ + // sem == sem_release (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "mbarrier.arrive.release.cluster.shared::cluster.b64 _, [%0], %1; // 4b. " + : + : "r"(__as_ptr_remote_dsmem(addr)), + "r"(count) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +// .space = { .shared::cta } +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& count); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& count) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t state; + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.arrive.relaxed.cta.shared::cta.b64 %0, [%1], %2;" + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.arrive.relaxed.cluster.shared::cta.b64 %0, [%1], %2;" + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + } + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// mbarrier.arrive.sem.scope.space.b64 state, [addr]; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +// .space = { .shared::cta } +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t state; + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.arrive.relaxed.cta.shared::cta.b64 %0, [%1];" + : "=l"(state) + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.arrive.relaxed.cluster.shared::cta.b64 %0, [%1];" + : "=l"(state) + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + } + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// mbarrier.arrive.sem.scope.space.b64 _, [addr], count; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cluster } +// .space = { .shared::cluster } +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& count); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& count) +{ + // sem == sem_relaxed (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [%0], %1;" + : + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// mbarrier.arrive.sem.scope.space.b64 _, [addr]; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cluster } +// .space = { .shared::cluster } +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_arrive( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr) +{ + // sem == sem_relaxed (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [%0];" + : + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 +/* +// mbarrier.arrive.noComplete.shared.b64 state, [addr], count; // 5. PTX ISA 70, SM_80 +template +__device__ static inline std::uint64_t mbarrier_arrive_no_complete( + std::uint64_t* addr, + const std::uint32_t& count); +*/ +#if __libcuda_ptx_isa >= 700 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_no_complete_is_not_supported_before_SM_80__(); +template +__device__ static inline std::uint64_t mbarrier_arrive_no_complete( + std::uint64_t* addr, + const std::uint32_t& count) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint64_t state; + asm ( + "mbarrier.arrive.noComplete.shared.b64 %0, [%1], %2; // 5. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_no_complete_is_not_supported_before_SM_80__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 700 +/* +// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], tx_count; // 8. PTX ISA 80, SM_90 +// .sem = { .release } +// .scope = { .cta, .cluster } +// .space = { .shared::cta } +template +__device__ static inline std::uint64_t mbarrier_arrive_expect_tx( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& tx_count); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t mbarrier_arrive_expect_tx( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& tx_count) +{ + // sem == sem_release (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t state; + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 %0, [%1], %2; // 8. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(tx_count) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.arrive.expect_tx.release.cluster.shared::cta.b64 %0, [%1], %2; // 8. " + : "=l"(state) + : "r"(__as_ptr_smem(addr)), + "r"(tx_count) + : "memory" + ); + } + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.arrive.expect_tx.sem.scope.space.b64 _, [addr], tx_count; // 9. PTX ISA 80, SM_90 +// .sem = { .release } +// .scope = { .cluster } +// .space = { .shared::cluster } +template +__device__ static inline void mbarrier_arrive_expect_tx( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& tx_count); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_arrive_expect_tx( + cuda_ptx::sem_release_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& tx_count) +{ + // sem == sem_release (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64 _, [%0], %1; // 9. " + : + : "r"(__as_ptr_remote_dsmem(addr)), + "r"(tx_count) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], txCount; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +// .space = { .shared::cta } +template +__device__ static inline std::uint64_t mbarrier_arrive_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& txCount); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t mbarrier_arrive_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + const std::uint32_t& txCount) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t state; + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.arrive.expect_tx.relaxed.cta.shared::cta.b64 %0, [%1], %2;" + : "=l"(state) + : "r"(__as_ptr_dsmem(addr)), + "r"(txCount) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64 %0, [%1], %2;" + : "=l"(state) + : "r"(__as_ptr_dsmem(addr)), + "r"(txCount) + : "memory" + ); + } + return state; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// mbarrier.arrive.expect_tx.sem.scope.space.b64 _, [addr], txCount; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cluster } +// .space = { .shared::cluster } +template +__device__ static inline void mbarrier_arrive_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& txCount); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_arrive_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_cluster_t, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + const std::uint32_t& txCount) +{ + // sem == sem_relaxed (due to parameter type constraint) + // scope == scope_cluster (due to parameter type constraint) + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "mbarrier.arrive.expect_tx.relaxed.cluster.shared::cluster.b64 _, [%0], %1;" + : + : "r"(__as_ptr_dsmem(addr)), + "r"(txCount) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_arrive_expect_tx_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_MBARRIER_ARRIVE_H + +// End of ./instructions/mbarrier_arrive.h +// Start of ./instructions/mbarrier_expect_tx.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_MBARRIER_EXPECT_TX_H +#define INSTRUCTIONS_MBARRIER_EXPECT_TX_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/mbarrier_expect_tx.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 1. PTX ISA 80, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +// .space = { .shared::cta } +template +__device__ static inline void mbarrier_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + std::uint32_t txCount); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_shared_t, + std::uint64_t* addr, + std::uint32_t txCount) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.expect_tx.relaxed.cta.shared::cta.b64 [%0], %1; // 1." + : + : "r"(__as_ptr_smem(addr)), + "r"(txCount) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.expect_tx.relaxed.cluster.shared::cta.b64 [%0], %1; // 1." + : + : "r"(__as_ptr_smem(addr)), + "r"(txCount) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 2. PTX ISA 80, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +// .space = { .shared::cluster } +template +__device__ static inline void mbarrier_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + std::uint32_t txCount); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__(); +template +__device__ static inline void mbarrier_expect_tx( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + cuda_ptx::space_cluster_t, + std::uint64_t* addr, + std::uint32_t txCount) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + // space == space_cluster (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (scope == scope_cta) { + asm ( + "mbarrier.expect_tx.relaxed.cta.shared::cluster.b64 [%0], %1; // 2." + : + : "r"(__as_ptr_dsmem(addr)), + "r"(txCount) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "mbarrier.expect_tx.relaxed.cluster.shared::cluster.b64 [%0], %1; // 2." + : + : "r"(__as_ptr_dsmem(addr)), + "r"(txCount) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_expect_tx_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_MBARRIER_EXPECT_TX_H + +// End of ./instructions/mbarrier_expect_tx.h +// Start of ./instructions/mbarrier_init.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_MBARRIER_INIT_H +#define INSTRUCTIONS_MBARRIER_INIT_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/mbarrier_init.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// mbarrier.init.shared.b64 [addr], count; // PTX ISA 70, SM_80 +template +__device__ static inline void mbarrier_init( + std::uint64_t* addr, + const std::uint32_t& count); +*/ +#if __libcuda_ptx_isa >= 700 +extern "C" __device__ void __cuda_ptx_mbarrier_init_is_not_supported_before_SM_80__(); +template +__device__ static inline void mbarrier_init( + std::uint64_t* addr, + const std::uint32_t& count) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "mbarrier.init.shared.b64 [%0], %1;" + : + : "r"(__as_ptr_smem(addr)), + "r"(count) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_init_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 700 + + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_MBARRIER_INIT_H + +// End of ./instructions/mbarrier_init.h +// Start of ./instructions/mbarrier_inval.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_MBARRIER_INVAL_H +#define INSTRUCTIONS_MBARRIER_INVAL_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/mbarrier_inval.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// mbarrier.inval.shared.b64 [addr]; // PTX ISA 70, SM_80 +template +__device__ static inline void mbarrier_inval( + std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 700 +extern "C" __device__ void __cuda_ptx_mbarrier_inval_is_not_supported_before_SM_80__(); +template +__device__ static inline void mbarrier_inval( + std::uint64_t* addr) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "mbarrier.inval.shared.b64 [%0];" + : + : "r"(__as_ptr_smem(addr)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_inval_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 700 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_MBARRIER_INVAL_H + +// End of ./instructions/mbarrier_inval.h +// Start of ./instructions/mbarrier_wait.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_MBARRIER_WAIT_H +#define INSTRUCTIONS_MBARRIER_WAIT_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/mbarrier_wait.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +#if defined(__NVCC__) +#pragma nv_diag_suppress 549 // "parameter is never used" +#endif + +namespace cuda_ptx { + +/* +// mbarrier.test_wait.shared.b64 waitComplete, [addr], state; // PTX ISA 70, SM_80 +template +__device__ static inline bool mbarrier_test_wait( + std::uint64_t* addr, + const std::uint64_t& state); +*/ +#if __libcuda_ptx_isa >= 700 +extern "C" __device__ void __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_80__(); +template +__device__ static inline bool mbarrier_test_wait( + std::uint64_t* addr, + const std::uint64_t& state) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t waitComplete; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.shared.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_80__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 700 + +/* +// mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 80, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_test_wait( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_test_wait( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.acquire.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_test_wait( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_test_wait( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.relaxed.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.relaxed.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_test_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// mbarrier.test_wait.parity.shared.b64 waitComplete, [addr], phaseParity; // PTX ISA 71, SM_80 +template +__device__ static inline bool mbarrier_test_wait_parity( + std::uint64_t* addr, + const std::uint32_t& phaseParity); +*/ +#if __libcuda_ptx_isa >= 710 +extern "C" __device__ void __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_80__(); +template +__device__ static inline bool mbarrier_test_wait_parity( + std::uint64_t* addr, + const std::uint32_t& phaseParity) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + std::uint32_t waitComplete; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.parity.shared.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_80__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 710 + +/* +// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 80, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_test_wait_parity( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_test_wait_parity( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.parity.acquire.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_test_wait_parity( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_test_wait_parity( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.parity.relaxed.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.test_wait.parity.relaxed.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_test_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + + + +/* +// mbarrier.try_wait.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 78, SM_90 +template +__device__ static inline bool mbarrier_try_wait( + std::uint64_t* addr, + const std::uint64_t& state); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait( + std::uint64_t* addr, + const std::uint64_t& state) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mbarrier.try_wait.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 78, SM_90 +template +__device__ static inline bool mbarrier_try_wait( + std::uint64_t* addr, + const std::uint64_t& state, + const std::uint32_t& suspendTimeHint); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait( + std::uint64_t* addr, + const std::uint64_t& state, + const std::uint32_t& suspendTimeHint) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state), + "r"(suspendTimeHint) + : "memory" + ); + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 80, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.acquire.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 80, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state, + const std::uint32_t& suspendTimeHint); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state, + const std::uint32_t& suspendTimeHint) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.acquire.cta.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state), + "r"(suspendTimeHint) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state), + "r"(suspendTimeHint) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.relaxed.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.relaxed.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state, + const std::uint32_t& suspendTimeHint); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint64_t& state, + const std::uint32_t& suspendTimeHint) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.relaxed.cta.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state), + "r"(suspendTimeHint) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.relaxed.cluster.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "l"(state), + "r"(suspendTimeHint) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + + +/* +// mbarrier.try_wait.parity.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 78, SM_90 +template +__device__ static inline bool mbarrier_try_wait_parity( + std::uint64_t* addr, + const std::uint32_t& phaseParity); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait_parity( + std::uint64_t* addr, + const std::uint32_t& phaseParity) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mbarrier.try_wait.parity.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 78, SM_90 +template +__device__ static inline bool mbarrier_try_wait_parity( + std::uint64_t* addr, + const std::uint32_t& phaseParity, + const std::uint32_t& suspendTimeHint); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait_parity( + std::uint64_t* addr, + const std::uint32_t& phaseParity, + const std::uint32_t& suspendTimeHint) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity), + "r"(suspendTimeHint) + : "memory" + ); + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 80, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 80, SM_90 +// .sem = { .acquire } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity, + const std::uint32_t& suspendTimeHint); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_acquire_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity, + const std::uint32_t& suspendTimeHint) +{ + // sem == sem_acquire (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity), + "r"(suspendTimeHint) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity), + "r"(suspendTimeHint) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64 P_OUT, [%1], %2; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 86, SM_90 +// .sem = { .relaxed } +// .scope = { .cta, .cluster } +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity, + const std::uint32_t& suspendTimeHint); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); +template +__device__ static inline bool mbarrier_try_wait_parity( + cuda_ptx::sem_relaxed_t, + cuda_ptx::scope_t scope, + std::uint64_t* addr, + const std::uint32_t& phaseParity, + const std::uint32_t& suspendTimeHint) +{ + // sem == sem_relaxed (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t waitComplete; + if constexpr (scope == scope_cta) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity), + "r"(suspendTimeHint) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm ( + "{\n\t" + ".reg .pred P_OUT; \n\t" + "mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64 P_OUT, [%1], %2, %3; \n\t" + "selp.b32 %0, 1, 0, P_OUT; \n" + "}" + : "=r"(waitComplete) + : "r"(__as_ptr_smem(addr)), + "r"(phaseParity), + "r"(suspendTimeHint) + : "memory" + ); + } + return static_cast(waitComplete); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_mbarrier_try_wait_parity_is_not_supported_before_SM_90__(); + return false; + #endif +} +#endif // __libcuda_ptx_isa >= 860 + + + + + +} // namespace cuda_ptx + +#if defined(__NVCC__) +#pragma nv_diag_default 549 +#endif + +#endif // INSTRUCTIONS_MBARRIER_WAIT_H + +// End of ./instructions/mbarrier_wait.h +// Start of ./instructions/multimem.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_MULTIMEM_H +#define INSTRUCTIONS_MULTIMEM_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/multimem.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .min } +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::uint32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::uint32_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + asm ( + "multimem.ld_reduce.weak.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::uint32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::uint32_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.min.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .min } +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::uint64_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + asm ( + "multimem.ld_reduce.weak.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::uint64_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.min.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .min } +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::int32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::int32_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int32_t dest; + asm ( + "multimem.ld_reduce.weak.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::int32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::int32_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.min.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .min } +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::int64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_min_t, + const std::int64_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int64_t dest; + asm ( + "multimem.ld_reduce.weak.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::int64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + const std::int64_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.min.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .max } +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::uint32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::uint32_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + asm ( + "multimem.ld_reduce.weak.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::uint32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::uint32_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.max.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .max } +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::uint64_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + asm ( + "multimem.ld_reduce.weak.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::uint64_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.max.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .max } +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::int32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::int32_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int32_t dest; + asm ( + "multimem.ld_reduce.weak.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::int32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::int32_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.max.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .max } +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::int64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_max_t, + const std::int64_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int64_t dest; + asm ( + "multimem.ld_reduce.weak.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.s64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::int64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + const std::int64_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.max.s64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .add } +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::uint32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::uint32_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + asm ( + "multimem.ld_reduce.weak.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.u32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::uint32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::uint32_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.add.u32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .add } +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::uint64_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + asm ( + "multimem.ld_reduce.weak.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::uint64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::uint64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::uint64_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .add } +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::int32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::int32_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int32_t dest; + asm ( + "multimem.ld_reduce.weak.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.s32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::int32_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int32_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::int32_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.add.s32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .add } +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::int64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_add_t, + const std::int64_t* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int64_t dest; + asm ( + "multimem.ld_reduce.weak.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.u64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::int64_t* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template +__device__ static inline std::int64_t multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + const std::int64_t* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::int64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.add.u64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .and } +template = true> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_and_op_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_and_op_t, + const B32* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_and_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + asm ( + "multimem.ld_reduce.weak.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .and } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + const B32* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_and_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.and.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .or } +template = true> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_or_op_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_or_op_t, + const B32* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_or_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + asm ( + "multimem.ld_reduce.weak.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .or } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + const B32* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_or_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.or.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .xor } +template = true> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_xor_op_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_xor_op_t, + const B32* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_xor_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + asm ( + "multimem.ld_reduce.weak.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.b32 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .xor } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + const B32* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B32 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + const B32* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_xor_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint32_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.xor.b32 %0, [%1];" + : "=r"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .and } +template = true> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_and_op_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_and_op_t, + const B64* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_and_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + asm ( + "multimem.ld_reduce.weak.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .and } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + const B64* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_and_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.and.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .or } +template = true> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_or_op_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_or_op_t, + const B64* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_or_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + asm ( + "multimem.ld_reduce.weak.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .or } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + const B64* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_or_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.or.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .weak } +// .op = { .xor } +template = true> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_xor_op_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_weak_t, + cuda_ptx::op_xor_op_t, + const B64* addr) +{ + // sem == sem_weak (due to parameter type constraint) + // op == op_xor_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + asm ( + "multimem.ld_reduce.weak.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.ld_reduce.sem.scope.global.op.b64 dest, [addr]; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .acquire } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .xor } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + const B64* addr); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline B64 multimem_ld_reduce( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + const B64* addr) +{ + static_assert(sem == sem_relaxed || sem == sem_acquire, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_xor_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + std::uint64_t dest; + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.ld_reduce.relaxed.cta.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.relaxed.cluster.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.relaxed.gpu.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.ld_reduce.relaxed.sys.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cta) { + asm ( + "multimem.ld_reduce.acquire.cta.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_cluster) { + asm ( + "multimem.ld_reduce.acquire.cluster.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_gpu) { + asm ( + "multimem.ld_reduce.acquire.gpu.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } else if constexpr (sem == sem_acquire && scope == scope_sys) { + asm ( + "multimem.ld_reduce.acquire.sys.global.xor.b64 %0, [%1];" + : "=l"(dest) + : "l"(__as_ptr_gmem(addr)) + : "memory" + ); + } + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_ld_reduce_is_not_supported_before_SM_90__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 810 +/* +// multimem.st.sem.global.b32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .weak } +template = true> +__device__ static inline void multimem_st( + cuda_ptx::sem_weak_t, + B32* addr, + B32 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void multimem_st( + cuda_ptx::sem_weak_t, + B32* addr, + B32 val) +{ + // sem == sem_weak (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "multimem.st.weak.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_st( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + B32* addr, + B32 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_st( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + B32* addr, + B32 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.st.relaxed.cta.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.st.relaxed.cluster.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.st.relaxed.gpu.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.st.relaxed.sys.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.st.release.cta.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.st.release.cluster.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.st.release.gpu.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.st.release.sys.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.st.sem.global.b64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .weak } +template = true> +__device__ static inline void multimem_st( + cuda_ptx::sem_weak_t, + B64* addr, + B64 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void multimem_st( + cuda_ptx::sem_weak_t, + B64* addr, + B64 val) +{ + // sem == sem_weak (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "multimem.st.weak.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_st( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + B64* addr, + B64 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_st( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + B64* addr, + B64 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.st.relaxed.cta.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.st.relaxed.cluster.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.st.relaxed.gpu.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.st.relaxed.sys.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.st.release.cta.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.st.release.cluster.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.st.release.gpu.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.st.release.sys.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_st_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 +/* +// multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::uint32_t* addr, + std::uint32_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::uint32_t* addr, + std::uint32_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.min.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::uint64_t* addr, + std::uint64_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::uint64_t* addr, + std::uint64_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.min.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::int32_t* addr, + std::int32_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::int32_t* addr, + std::int32_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.min.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .min } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::int64_t* addr, + std::int64_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_min_t, + std::int64_t* addr, + std::int64_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.min.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::uint32_t* addr, + std::uint32_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::uint32_t* addr, + std::uint32_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.max.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::uint64_t* addr, + std::uint64_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::uint64_t* addr, + std::uint64_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.max.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::int32_t* addr, + std::int32_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::int32_t* addr, + std::int32_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.max.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.s64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .max } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::int64_t* addr, + std::int64_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_max_t, + std::int64_t* addr, + std::int64_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.max.s64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.u32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::uint32_t* addr, + std::uint32_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::uint32_t* addr, + std::uint32_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.add.u32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::uint64_t* addr, + std::uint64_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::uint64_t* addr, + std::uint64_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.s32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::int32_t* addr, + std::int32_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::int32_t* addr, + std::int32_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.add.s32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.u64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .add } +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::int64_t* addr, + std::int64_t val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_add_t, + std::int64_t* addr, + std::int64_t val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.add.u64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(val) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .and } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + B32* addr, + B32 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + B32* addr, + B32 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_and_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.and.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .or } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + B32* addr, + B32 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + B32* addr, + B32 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_or_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.or.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.b32 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .xor } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + B32* addr, + B32 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + B32* addr, + B32 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_xor_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.xor.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .and } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + B64* addr, + B64 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_and_op_t, + B64* addr, + B64 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_and_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.and.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .or } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + B64* addr, + B64 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_or_op_t, + B64* addr, + B64 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_or_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.or.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// multimem.red.sem.scope.global.op.b64 [addr], val; // PTX ISA 81, SM_90 +// .sem = { .relaxed, .release } +// .scope = { .cta, .cluster, .gpu, .sys } +// .op = { .xor } +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + B64* addr, + B64 val); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); +template = true, cuda_ptx::dot_sem Sem, cuda_ptx::dot_scope Scope> +__device__ static inline void multimem_red( + cuda_ptx::sem_t sem, + cuda_ptx::scope_t scope, + cuda_ptx::op_xor_op_t, + B64* addr, + B64 val) +{ + static_assert(sem == sem_relaxed || sem == sem_release, ""); + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + // op == op_xor_op (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sem == sem_relaxed && scope == scope_cta) { + asm ( + "multimem.red.relaxed.cta.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_cluster) { + asm ( + "multimem.red.relaxed.cluster.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_gpu) { + asm ( + "multimem.red.relaxed.gpu.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_relaxed && scope == scope_sys) { + asm ( + "multimem.red.relaxed.sys.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cta) { + asm ( + "multimem.red.release.cta.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_cluster) { + asm ( + "multimem.red.release.cluster.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_gpu) { + asm ( + "multimem.red.release.gpu.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } else if constexpr (sem == sem_release && scope == scope_sys) { + asm ( + "multimem.red.release.sys.global.xor.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&val)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_multimem_red_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_MULTIMEM_H + +// End of ./instructions/multimem.h +// Start of ./instructions/prmt.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_PRMT_H +#define INSTRUCTIONS_PRMT_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/prmt.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// prmt.b32 dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50 +template = true> +__device__ static inline std::uint32_t prmt( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_prmt_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline std::uint32_t prmt( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "prmt.b32 %0, %1, %2, %3;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(/*as_b32*/ *reinterpret_cast(&b_reg)), + "r"(c_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_prmt_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// prmt.b32.f4e dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50 +template = true> +__device__ static inline std::uint32_t prmt_f4e( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_prmt_f4e_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline std::uint32_t prmt_f4e( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "prmt.b32.f4e %0, %1, %2, %3;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(/*as_b32*/ *reinterpret_cast(&b_reg)), + "r"(c_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_prmt_f4e_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// prmt.b32.b4e dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50 +template = true> +__device__ static inline std::uint32_t prmt_b4e( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_prmt_b4e_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline std::uint32_t prmt_b4e( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "prmt.b32.b4e %0, %1, %2, %3;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(/*as_b32*/ *reinterpret_cast(&b_reg)), + "r"(c_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_prmt_b4e_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// prmt.b32.rc8 dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50 +template = true> +__device__ static inline std::uint32_t prmt_rc8( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_prmt_rc8_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline std::uint32_t prmt_rc8( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "prmt.b32.rc8 %0, %1, %2, %3;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(/*as_b32*/ *reinterpret_cast(&b_reg)), + "r"(c_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_prmt_rc8_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// prmt.b32.ecl dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50 +template = true> +__device__ static inline std::uint32_t prmt_ecl( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_prmt_ecl_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline std::uint32_t prmt_ecl( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "prmt.b32.ecl %0, %1, %2, %3;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(/*as_b32*/ *reinterpret_cast(&b_reg)), + "r"(c_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_prmt_ecl_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// prmt.b32.ecr dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50 +template = true> +__device__ static inline std::uint32_t prmt_ecr( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_prmt_ecr_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline std::uint32_t prmt_ecr( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "prmt.b32.ecr %0, %1, %2, %3;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(/*as_b32*/ *reinterpret_cast(&b_reg)), + "r"(c_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_prmt_ecr_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +/* +// prmt.b32.rc16 dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50 +template = true> +__device__ static inline std::uint32_t prmt_rc16( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg); +*/ +#if __libcuda_ptx_isa >= 200 +extern "C" __device__ void __cuda_ptx_prmt_rc16_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline std::uint32_t prmt_rc16( + B32 a_reg, + B32 b_reg, + std::uint32_t c_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "prmt.b32.rc16 %0, %1, %2, %3;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(/*as_b32*/ *reinterpret_cast(&b_reg)), + "r"(c_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_prmt_rc16_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 200 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_PRMT_H + +// End of ./instructions/prmt.h +// Start of ./instructions/red_async.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_RED_ASYNC_H +#define INSTRUCTIONS_RED_ASYNC_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/red_async.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .u32 } +// .op = { .inc } +template +__device__ static inline void red_async( + cuda_ptx::op_inc_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_inc_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_u32 (due to parameter type constraint) + // op == op_inc (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.inc.u32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .u32 } +// .op = { .dec } +template +__device__ static inline void red_async( + cuda_ptx::op_dec_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_dec_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_u32 (due to parameter type constraint) + // op == op_dec (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.dec.u32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .u32 } +// .op = { .min } +template +__device__ static inline void red_async( + cuda_ptx::op_min_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_min_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_u32 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.u32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .u32 } +// .op = { .max } +template +__device__ static inline void red_async( + cuda_ptx::op_max_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_max_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_u32 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.u32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .u32 } +// .op = { .add } +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::uint32_t* dest, + const std::uint32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_u32 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .s32 } +// .op = { .min } +template +__device__ static inline void red_async( + cuda_ptx::op_min_t, + std::int32_t* dest, + const std::int32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_min_t, + std::int32_t* dest, + const std::int32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_s32 (due to parameter type constraint) + // op == op_min (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.s32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .s32 } +// .op = { .max } +template +__device__ static inline void red_async( + cuda_ptx::op_max_t, + std::int32_t* dest, + const std::int32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_max_t, + std::int32_t* dest, + const std::int32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_s32 (due to parameter type constraint) + // op == op_max (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.s32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .s32 } +// .op = { .add } +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::int32_t* dest, + const std::int32_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::int32_t* dest, + const std::int32_t& value, + std::uint64_t* remote_bar) +{ + // type == type_s32 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.s32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .b32 } +// .op = { .and } +template = true> +__device__ static inline void red_async( + cuda_ptx::op_and_op_t, + B32* dest, + const B32& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void red_async( + cuda_ptx::op_and_op_t, + B32* dest, + const B32& value, + std::uint64_t* remote_bar) +{ + // type == type_b32 (due to parameter type constraint) + // op == op_and_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.and.b32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(/*as_b32*/ *reinterpret_cast(&value)), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .b32 } +// .op = { .or } +template = true> +__device__ static inline void red_async( + cuda_ptx::op_or_op_t, + B32* dest, + const B32& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void red_async( + cuda_ptx::op_or_op_t, + B32* dest, + const B32& value, + std::uint64_t* remote_bar) +{ + // type == type_b32 (due to parameter type constraint) + // op == op_or_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.or.b32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(/*as_b32*/ *reinterpret_cast(&value)), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .b32 } +// .op = { .xor } +template = true> +__device__ static inline void red_async( + cuda_ptx::op_xor_op_t, + B32* dest, + const B32& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void red_async( + cuda_ptx::op_xor_op_t, + B32* dest, + const B32& value, + std::uint64_t* remote_bar) +{ + // type == type_b32 (due to parameter type constraint) + // op == op_xor_op (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.xor.b32 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "r"(/*as_b32*/ *reinterpret_cast(&value)), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90 +// .type = { .u64 } +// .op = { .add } +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::uint64_t* dest, + const std::uint64_t& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::uint64_t* dest, + const std::uint64_t& value, + std::uint64_t* remote_bar) +{ + // type == type_u64 (due to parameter type constraint) + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64 [%0], %1, [%2]; " + : + : "r"(__as_ptr_remote_dsmem(dest)), + "l"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.u64 [dest], value, [remote_bar]; // .u64 intentional PTX ISA 81, SM_90 +// .op = { .add } +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::int64_t* dest, + const std::int64_t& value, + std::int64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_red_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void red_async( + cuda_ptx::op_add_t, + std::int64_t* dest, + const std::int64_t& value, + std::int64_t* remote_bar) +{ + // op == op_add (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64 [%0], %1, [%2]; // .u64 intentional" + : + : "r"(__as_ptr_remote_dsmem(dest)), + "l"(value), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_red_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_RED_ASYNC_H + +// End of ./instructions/red_async.h +// Start of ./instructions/setmaxnreg.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_SETMAXNREG_H +#define INSTRUCTIONS_SETMAXNREG_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/setmaxnreg.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// setmaxnreg.inc.sync.aligned.u32 imm_reg_count; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +template +__device__ static inline void setmaxnreg_inc( + cuda_ptx::n32_t imm_reg_count); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_setmaxnreg_inc_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void setmaxnreg_inc( + cuda_ptx::n32_t imm_reg_count) +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm volatile ( + "setmaxnreg.inc.sync.aligned.u32 %0;" + : + : "n"(imm_reg_count.value) + : + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_setmaxnreg_inc_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +/* +// setmaxnreg.dec.sync.aligned.u32 imm_reg_count; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +template +__device__ static inline void setmaxnreg_dec( + cuda_ptx::n32_t imm_reg_count); +*/ +#if __libcuda_ptx_isa >= 800 +extern "C" __device__ void __cuda_ptx_setmaxnreg_dec_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void setmaxnreg_dec( + cuda_ptx::n32_t imm_reg_count) +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm volatile ( + "setmaxnreg.dec.sync.aligned.u32 %0;" + : + : "n"(imm_reg_count.value) + : + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_setmaxnreg_dec_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 800 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_SETMAXNREG_H + +// End of ./instructions/setmaxnreg.h +// Start of ./instructions/shl.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_SHL_H +#define INSTRUCTIONS_SHL_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/shl.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// shl.b16 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template = true> +__device__ static inline B16 shl( + B16 a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shl_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B16 shl( + B16 a_reg, + std::uint32_t b_reg) +{ + static_assert(sizeof(B16) == 2, ""); + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint16_t dest; + asm ( + "shl.b16 %0, %1, %2;" + : "=h"(dest) + : "h"(/*as_b16*/ *reinterpret_cast(&a_reg)), + "r"(b_reg) + : + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shl_is_not_supported_before_SM_50__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// shl.b32 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template = true> +__device__ static inline B32 shl( + B32 a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shl_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B32 shl( + B32 a_reg, + std::uint32_t b_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "shl.b32 %0, %1, %2;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(b_reg) + : + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shl_is_not_supported_before_SM_50__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// shl.b64 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template = true> +__device__ static inline B64 shl( + B64 a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shl_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B64 shl( + B64 a_reg, + std::uint32_t b_reg) +{ + static_assert(sizeof(B64) == 8, ""); + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint64_t dest; + asm ( + "shl.b64 %0, %1, %2;" + : "=l"(dest) + : "l"(/*as_b64*/ *reinterpret_cast(&a_reg)), + "r"(b_reg) + : + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shl_is_not_supported_before_SM_50__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_SHL_H + +// End of ./instructions/shl.h +// Start of ./instructions/shr.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_SHR_H +#define INSTRUCTIONS_SHR_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/shr.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// shr.b16 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template = true> +__device__ static inline B16 shr( + B16 a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shr_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B16 shr( + B16 a_reg, + std::uint32_t b_reg) +{ + static_assert(sizeof(B16) == 2, ""); + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint16_t dest; + asm ( + "shr.b16 %0, %1, %2;" + : "=h"(dest) + : "h"(/*as_b16*/ *reinterpret_cast(&a_reg)), + "r"(b_reg) + : + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shr_is_not_supported_before_SM_50__(); + std::uint16_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// shr.b32 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template = true> +__device__ static inline B32 shr( + B32 a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shr_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B32 shr( + B32 a_reg, + std::uint32_t b_reg) +{ + static_assert(sizeof(B32) == 4, ""); + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint32_t dest; + asm ( + "shr.b32 %0, %1, %2;" + : "=r"(dest) + : "r"(/*as_b32*/ *reinterpret_cast(&a_reg)), + "r"(b_reg) + : + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shr_is_not_supported_before_SM_50__(); + std::uint32_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// shr.b64 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template = true> +__device__ static inline B64 shr( + B64 a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shr_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline B64 shr( + B64 a_reg, + std::uint32_t b_reg) +{ + static_assert(sizeof(B64) == 8, ""); + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::uint64_t dest; + asm ( + "shr.b64 %0, %1, %2;" + : "=l"(dest) + : "l"(/*as_b64*/ *reinterpret_cast(&a_reg)), + "r"(b_reg) + : + ); + return *reinterpret_cast(&dest); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shr_is_not_supported_before_SM_50__(); + std::uint64_t err_out_var = 0; + return *reinterpret_cast(&err_out_var); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// shr.s16 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template +__device__ static inline std::int16_t shr( + std::int16_t a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shr_is_not_supported_before_SM_50__(); +template +__device__ static inline std::int16_t shr( + std::int16_t a_reg, + std::uint32_t b_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::int16_t dest; + asm ( + "shr.s16 %0, %1, %2;" + : "=h"(dest) + : "h"(a_reg), + "r"(b_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shr_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// shr.s32 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template +__device__ static inline std::int32_t shr( + std::int32_t a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shr_is_not_supported_before_SM_50__(); +template +__device__ static inline std::int32_t shr( + std::int32_t a_reg, + std::uint32_t b_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::int32_t dest; + asm ( + "shr.s32 %0, %1, %2;" + : "=r"(dest) + : "r"(a_reg), + "r"(b_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shr_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// shr.s64 dest, a_reg, b_reg; // PTX ISA 10, SM_50 +template +__device__ static inline std::int64_t shr( + std::int64_t a_reg, + std::uint32_t b_reg); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_shr_is_not_supported_before_SM_50__(); +template +__device__ static inline std::int64_t shr( + std::int64_t a_reg, + std::uint32_t b_reg) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + std::int64_t dest; + asm ( + "shr.s64 %0, %1, %2;" + : "=l"(dest) + : "l"(a_reg), + "r"(b_reg) + : + ); + return dest; + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_shr_is_not_supported_before_SM_50__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_SHR_H + +// End of ./instructions/shr.h +// Start of ./instructions/st.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_ST_H +#define INSTRUCTIONS_ST_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/st.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// st.space.b8 [addr], src; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B8* addr, + B8 src); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_st_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B8* addr, + B8 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + asm ( + "st.global.b8 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_is_not_supported_before_SM_50__(); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// st.space.b16 [addr], src; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B16* addr, + B16 src); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_st_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B16* addr, + B16 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + asm ( + "st.global.b16 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_is_not_supported_before_SM_50__(); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// st.space.b32 [addr], src; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B32* addr, + B32 src); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_st_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B32* addr, + B32 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + asm ( + "st.global.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_is_not_supported_before_SM_50__(); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// st.space.b64 [addr], src; // PTX ISA 10, SM_50 +// .space = { .global } +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B64* addr, + B64 src); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_st_is_not_supported_before_SM_50__(); +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B64* addr, + B64 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + asm ( + "st.global.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_is_not_supported_before_SM_50__(); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +/* +// st.space.b128 [addr], src; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B128* addr, + B128 src); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B128* addr, + B128 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.b128 [%0], B128_src; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.v4.b64 [addr], src; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B256* addr, + B256 src); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st( + cuda_ptx::space_global_t, + B256* addr, + B256 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.v4.b64 [%0], {%1, %2, %3, %4};" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// st.space.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L2::cache_hint.b8 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L2::cache_hint.b16 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L2::cache_hint.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L2::cache_hint.b64 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.L2::cache_hint.b128 [%0], B128_src, %3; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.L2::cache_hint.v4.b64 [%0], {%1, %2, %3, %4}, %5;" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L2_cache_hint_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// st.space.L1::evict_first.b8 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B8* addr, + B8 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B8* addr, + B8 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_first.b8 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.b16 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B16* addr, + B16 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B16* addr, + B16 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_first.b16 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.b32 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B32* addr, + B32 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B32* addr, + B32 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_first.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.b64 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B64* addr, + B64 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B64* addr, + B64 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_first.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.b128 [addr], src; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B128* addr, + B128 src); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B128* addr, + B128 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.L1::evict_first.b128 [%0], B128_src; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.L1::evict_first.v4.b64 [addr], src; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B256* addr, + B256 src); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st_L1_evict_first( + cuda_ptx::space_global_t, + B256* addr, + B256 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.L1::evict_first.v4.b64 [%0], {%1, %2, %3, %4};" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// st.space.L1::evict_first.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_first.L2::cache_hint.b8 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_first.L2::cache_hint.b16 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_first.L2::cache_hint.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_first.L2::cache_hint.b64 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_first.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.L1::evict_first.L2::cache_hint.b128 [%0], B128_src, %3; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.L1::evict_first.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st_L1_evict_first_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.L1::evict_first.L2::cache_hint.v4.b64 [%0], {%1, %2, %3, %4}, %5;" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_first_L2_cache_hint_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// st.space.L1::evict_last.b8 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B8* addr, + B8 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B8* addr, + B8 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_last.b8 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.b16 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B16* addr, + B16 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B16* addr, + B16 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_last.b16 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.b32 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B32* addr, + B32 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B32* addr, + B32 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_last.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.b64 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B64* addr, + B64 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B64* addr, + B64 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::evict_last.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.b128 [addr], src; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B128* addr, + B128 src); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B128* addr, + B128 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.L1::evict_last.b128 [%0], B128_src; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.L1::evict_last.v4.b64 [addr], src; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B256* addr, + B256 src); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st_L1_evict_last( + cuda_ptx::space_global_t, + B256* addr, + B256 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.L1::evict_last.v4.b64 [%0], {%1, %2, %3, %4};" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// st.space.L1::evict_last.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_last.L2::cache_hint.b8 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_last.L2::cache_hint.b16 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_last.L2::cache_hint.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::evict_last.L2::cache_hint.b64 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::evict_last.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.L1::evict_last.L2::cache_hint.b128 [%0], B128_src, %3; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.L1::evict_last.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st_L1_evict_last_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.L1::evict_last.L2::cache_hint.v4.b64 [%0], {%1, %2, %3, %4}, %5;" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_evict_last_L2_cache_hint_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// st.space.L1::no_allocate.b8 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B8* addr, + B8 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B8* addr, + B8 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::no_allocate.b8 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.b16 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B16* addr, + B16 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B16* addr, + B16 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::no_allocate.b16 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.b32 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B32* addr, + B32 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B32* addr, + B32 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::no_allocate.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.b64 [addr], src; // PTX ISA 74, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B64* addr, + B64 src); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B64* addr, + B64 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "st.global.L1::no_allocate.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.b128 [addr], src; // PTX ISA 83, SM_70 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B128* addr, + B128 src); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B128* addr, + B128 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 700 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.L1::no_allocate.b128 [%0], B128_src; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_70__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.L1::no_allocate.v4.b64 [addr], src; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B256* addr, + B256 src); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st_L1_no_allocate( + cuda_ptx::space_global_t, + B256* addr, + B256 src) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.L1::no_allocate.v4.b64 [%0], {%1, %2, %3, %4};" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// st.space.L1::no_allocate.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B8* addr, + B8 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B8) == 1, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::no_allocate.L2::cache_hint.b8 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(__b8_as_u32(src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B16* addr, + B16 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B16) == 2, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::no_allocate.L2::cache_hint.b16 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "h"(/*as_b16*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B32* addr, + B32 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::no_allocate.L2::cache_hint.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 740 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B64* addr, + B64 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "st.global.L1::no_allocate.L2::cache_hint.b64 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&src)), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 740 + +/* +// st.space.L1::no_allocate.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B128* addr, + B128 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B128) == 16, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 800 + asm ( + "{\n\t" + ".reg .b128 B128_src; \n\t" + "mov.b128 B128_src, {%1, %2}; \n\t" + "st.global.L1::no_allocate.L2::cache_hint.b128 [%0], B128_src, %3; \n" + "}" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_80__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// st.space.L1::no_allocate.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100 +// .space = { .global } +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_100__(); +template = true> +__device__ static inline void st_L1_no_allocate_L2_cache_hint( + cuda_ptx::space_global_t, + B256* addr, + B256 src, + std::uint64_t cache_policy) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B256) == 32, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.global.L1::no_allocate.L2::cache_hint.v4.b64 [%0], {%1, %2, %3, %4}, %5;" + : + : "l"(__as_ptr_gmem(addr)), + "l"((*reinterpret_cast(&src)).x), + "l"((*reinterpret_cast(&src)).y), + "l"((*reinterpret_cast(&src)).z), + "l"((*reinterpret_cast(&src)).w), + "l"(cache_policy) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_L1_no_allocate_L2_cache_hint_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_ST_H + +// End of ./instructions/st.h +// Start of ./instructions/st_async.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_ST_ASYNC_H +#define INSTRUCTIONS_ST_ASYNC_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/st_async.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.type [addr], value, [remote_bar]; // 1. PTX ISA 81, SM_90 +// .type = { .b32, .b64 } +template +__device__ static inline void st_async( + Type* addr, + const Type& value, + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_st_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void st_async( + Type* addr, + const Type& value, + std::uint64_t* remote_bar) +{ + static_assert(sizeof(Type) == 4 || sizeof(Type) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sizeof(Type) == 4) { + asm ( + "st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32 [%0], %1, [%2]; // 1. " + : + : "r"(__as_ptr_remote_dsmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&value)), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + } else if constexpr (sizeof(Type) == 8) { + asm ( + "st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64 [%0], %1, [%2]; // 1. " + : + : "r"(__as_ptr_remote_dsmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&value)), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.type [addr], value, [remote_bar]; // 2. PTX ISA 81, SM_90 +// .type = { .b32, .b64 } +template +__device__ static inline void st_async( + Type* addr, + const Type (&value)[2], + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_st_async_is_not_supported_before_SM_90__(); +template +__device__ static inline void st_async( + Type* addr, + const Type (&value)[2], + std::uint64_t* remote_bar) +{ + static_assert(sizeof(Type) == 4 || sizeof(Type) == 8, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (sizeof(Type) == 4) { + asm ( + "st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32 [%0], {%1, %2}, [%3]; // 2. " + : + : "r"(__as_ptr_remote_dsmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&value[0])), + "r"(/*as_b32*/ *reinterpret_cast(&value[1])), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + } else if constexpr (sizeof(Type) == 8) { + asm ( + "st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b64 [%0], {%1, %2}, [%3]; // 2. " + : + : "r"(__as_ptr_remote_dsmem(addr)), + "l"(/*as_b64*/ *reinterpret_cast(&value[0])), + "l"(/*as_b64*/ *reinterpret_cast(&value[1])), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +/* +// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [addr], value, [remote_bar]; // 3. PTX ISA 81, SM_90 +template = true> +__device__ static inline void st_async( + B32* addr, + const B32 (&value)[4], + std::uint64_t* remote_bar); +*/ +#if __libcuda_ptx_isa >= 810 +extern "C" __device__ void __cuda_ptx_st_async_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void st_async( + B32* addr, + const B32 (&value)[4], + std::uint64_t* remote_bar) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm ( + "st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [%0], {%1, %2, %3, %4}, [%5]; // 3. " + : + : "r"(__as_ptr_remote_dsmem(addr)), + "r"(/*as_b32*/ *reinterpret_cast(&value[0])), + "r"(/*as_b32*/ *reinterpret_cast(&value[1])), + "r"(/*as_b32*/ *reinterpret_cast(&value[2])), + "r"(/*as_b32*/ *reinterpret_cast(&value[3])), + "r"(__as_ptr_remote_dsmem(remote_bar)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_async_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 810 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_ST_ASYNC_H + +// End of ./instructions/st_async.h +// Start of ./instructions/st_bulk.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_ST_BULK_H +#define INSTRUCTIONS_ST_BULK_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/st_bulk.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// st.bulk.weak.shared::cta [addr], size, initval; // PTX ISA 86, SM_100 +template +__device__ static inline void st_bulk( + void* addr, + std::uint64_t size, + cuda_ptx::n32_t initval); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_st_bulk_is_not_supported_before_SM_100__(); +template +__device__ static inline void st_bulk( + void* addr, + std::uint64_t size, + cuda_ptx::n32_t initval) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 1000 + asm ( + "st.bulk.weak.shared::cta [%0], %1, %2;" + : + : "r"(__as_ptr_smem(addr)), + "l"(size), + "n"(initval.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_st_bulk_is_not_supported_before_SM_100__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_ST_BULK_H + +// End of ./instructions/st_bulk.h +// Start of ./instructions/stmatrix.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_STMATRIX_H +#define INSTRUCTIONS_STMATRIX_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/stmatrix.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// stmatrix.sync.aligned.m8n8.x1.shared.b16 [gmem_ptr], input; // PTX ISA 78, SM_90 +template = true> +__device__ static inline void stmatrix_m8n8( + B16* gmem_ptr, + const std::uint32_t (&input)[1]); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_stmatrix_m8n8_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void stmatrix_m8n8( + B16* gmem_ptr, + const std::uint32_t (&input)[1]) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "stmatrix.sync.aligned.m8n8.x1.shared.b16 [%0], {%1};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m8n8_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// stmatrix.sync.aligned.m8n8.x2.shared.b16 [gmem_ptr], input; // PTX ISA 78, SM_90 +template = true> +__device__ static inline void stmatrix_m8n8( + B16* gmem_ptr, + const std::uint32_t (&input)[2]); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_stmatrix_m8n8_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void stmatrix_m8n8( + B16* gmem_ptr, + const std::uint32_t (&input)[2]) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "stmatrix.sync.aligned.m8n8.x2.shared.b16 [%0], {%1, %2};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]), + "r"(input[1]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m8n8_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// stmatrix.sync.aligned.m8n8.x4.shared.b16 [gmem_ptr], input; // PTX ISA 78, SM_90 +template = true> +__device__ static inline void stmatrix_m8n8( + B16* gmem_ptr, + const std::uint32_t (&input)[4]); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_stmatrix_m8n8_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void stmatrix_m8n8( + B16* gmem_ptr, + const std::uint32_t (&input)[4]) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "stmatrix.sync.aligned.m8n8.x4.shared.b16 [%0], {%1, %2, %3, %4};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]), + "r"(input[1]), + "r"(input[2]), + "r"(input[3]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m8n8_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// stmatrix.sync.aligned.m8n8.x1.trans.shared.b16 [gmem_ptr], input; // PTX ISA 78, SM_90 +template = true> +__device__ static inline void stmatrix_m8n8_trans( + B16* gmem_ptr, + const std::uint32_t (&input)[1]); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_stmatrix_m8n8_trans_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void stmatrix_m8n8_trans( + B16* gmem_ptr, + const std::uint32_t (&input)[1]) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "stmatrix.sync.aligned.m8n8.x1.trans.shared.b16 [%0], {%1};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m8n8_trans_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// stmatrix.sync.aligned.m8n8.x2.trans.shared.b16 [gmem_ptr], input; // PTX ISA 78, SM_90 +template = true> +__device__ static inline void stmatrix_m8n8_trans( + B16* gmem_ptr, + const std::uint32_t (&input)[2]); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_stmatrix_m8n8_trans_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void stmatrix_m8n8_trans( + B16* gmem_ptr, + const std::uint32_t (&input)[2]) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "stmatrix.sync.aligned.m8n8.x2.trans.shared.b16 [%0], {%1, %2};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]), + "r"(input[1]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m8n8_trans_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// stmatrix.sync.aligned.m8n8.x4.trans.shared.b16 [gmem_ptr], input; // PTX ISA 78, SM_90 +template = true> +__device__ static inline void stmatrix_m8n8_trans( + B16* gmem_ptr, + const std::uint32_t (&input)[4]); +*/ +#if __libcuda_ptx_isa >= 780 +extern "C" __device__ void __cuda_ptx_stmatrix_m8n8_trans_is_not_supported_before_SM_90__(); +template = true> +__device__ static inline void stmatrix_m8n8_trans( + B16* gmem_ptr, + const std::uint32_t (&input)[4]) +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + asm volatile ( + "stmatrix.sync.aligned.m8n8.x4.trans.shared.b16 [%0], {%1, %2, %3, %4};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]), + "r"(input[1]), + "r"(input[2]), + "r"(input[3]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m8n8_trans_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 780 + +/* +// stmatrix.sync.aligned.m16n8.x1.trans.shared.b8 [gmem_ptr], input; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +template = true> +__device__ static inline void stmatrix_m16n8_trans( + B8* gmem_ptr, + const std::uint32_t (&input)[1]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_stmatrix_m16n8_trans_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void stmatrix_m16n8_trans( + B8* gmem_ptr, + const std::uint32_t (&input)[1]) +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm volatile ( + "stmatrix.sync.aligned.m16n8.x1.trans.shared.b8 [%0], {%1};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m16n8_trans_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// stmatrix.sync.aligned.m16n8.x2.trans.shared.b8 [gmem_ptr], input; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +template = true> +__device__ static inline void stmatrix_m16n8_trans( + B8* gmem_ptr, + const std::uint32_t (&input)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_stmatrix_m16n8_trans_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void stmatrix_m16n8_trans( + B8* gmem_ptr, + const std::uint32_t (&input)[2]) +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm volatile ( + "stmatrix.sync.aligned.m16n8.x2.trans.shared.b8 [%0], {%1, %2};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]), + "r"(input[1]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m16n8_trans_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// stmatrix.sync.aligned.m16n8.x4.trans.shared.b8 [gmem_ptr], input; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +template = true> +__device__ static inline void stmatrix_m16n8_trans( + B8* gmem_ptr, + const std::uint32_t (&input)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_stmatrix_m16n8_trans_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void stmatrix_m16n8_trans( + B8* gmem_ptr, + const std::uint32_t (&input)[4]) +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm volatile ( + "stmatrix.sync.aligned.m16n8.x4.trans.shared.b8 [%0], {%1, %2, %3, %4};" + : + : "r"(__as_ptr_smem(gmem_ptr)), + "r"(input[0]), + "r"(input[1]), + "r"(input[2]), + "r"(input[3]) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_stmatrix_m16n8_trans_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_STMATRIX_H + +// End of ./instructions/stmatrix.h +// Start of ./instructions/tcgen05_alloc.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_ALLOC_H +#define INSTRUCTIONS_TCGEN05_ALLOC_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_alloc.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.alloc.cta_group.sync.aligned.shared::cta.b32 [dst], nCols; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_alloc( + cuda_ptx::cta_group_t cta_group, + std::uint32_t* dst, + const std::uint32_t& nCols); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_alloc_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_alloc( + cuda_ptx::cta_group_t cta_group, + std::uint32_t* dst, + const std::uint32_t& nCols) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(dst)), + "r"(nCols) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(dst)), + "r"(nCols) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_alloc_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_dealloc( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + const std::uint32_t& nCols); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_dealloc_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_dealloc( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + const std::uint32_t& nCols) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" + : + : "r"(taddr), + "r"(nCols) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "tcgen05.dealloc.cta_group::2.sync.aligned.b32 %0, %1;" + : + : "r"(taddr), + "r"(nCols) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_dealloc_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + + + +/* +// tcgen05.relinquish_alloc_permit.cta_group.sync.aligned; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_relinquish_alloc_permit( + cuda_ptx::cta_group_t cta_group); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_relinquish_alloc_permit_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_relinquish_alloc_permit( + cuda_ptx::cta_group_t cta_group) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;" + : + : + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;" + : + : + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_relinquish_alloc_permit_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_ALLOC_H + +// End of ./instructions/tcgen05_alloc.h +// Start of ./instructions/tcgen05_commit.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_COMMIT_H +#define INSTRUCTIONS_TCGEN05_COMMIT_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_commit.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.b64 [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_commit( + cuda_ptx::cta_group_t cta_group, + std::uint64_t* smem_bar); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_commit_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_commit( + cuda_ptx::cta_group_t cta_group, + std::uint64_t* smem_bar) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];" + : + : "r"(__as_ptr_dsmem(smem_bar)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [%0];" + : + : "r"(__as_ptr_dsmem(smem_bar)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_commit_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_commit_multicast( + cuda_ptx::cta_group_t cta_group, + std::uint64_t* smem_bar, + std::uint16_t ctaMask); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_commit_multicast_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_commit_multicast( + cuda_ptx::cta_group_t cta_group, + std::uint64_t* smem_bar, + std::uint16_t ctaMask) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%0], %1;" + : + : "r"(__as_ptr_dsmem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%0], %1;" + : + : "r"(__as_ptr_dsmem(smem_bar)), + "h"(ctaMask) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_commit_multicast_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_COMMIT_H + +// End of ./instructions/tcgen05_commit.h +// Start of ./instructions/tcgen05_cp.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_CP_H +#define INSTRUCTIONS_TCGEN05_CP_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_cp.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.cp.cta_group.128x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_128x256b( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_128x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_128x256b( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.128x256b [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.128x256b [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_128x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.4x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_4x256b( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_4x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_4x256b( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.4x256b [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.4x256b [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_4x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.128x128b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_128x128b( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_128x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_128x128b( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.128x128b [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.128x128b [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_128x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.64x128b.warpx2::02_13 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.64x128b.warpx2::01_23 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.32x128b.warpx4 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_32x128b_warpx4( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_32x128b_warpx4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_32x128b_warpx4( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.32x128b.warpx4 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_32x128b_warpx4_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.128x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_128x256b_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_128x256b_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.4x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_4x256b_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_4x256b_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.128x128b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_128x128b_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_128x128b_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.128x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_128x256b_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_128x256b_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.4x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_4x256b_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_4x256b_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.128x128b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_128x128b_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_128x128b_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr, + std::uint64_t s_desc) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm ( + "tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm ( + "tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 [%0], %1;" + : + : "r"(taddr), + "l"(s_desc) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_CP_H + +// End of ./instructions/tcgen05_cp.h +// Start of ./instructions/tcgen05_fence.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_FENCE_H +#define INSTRUCTIONS_TCGEN05_FENCE_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_fence.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.fence::before_thread_sync; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template +__device__ static inline void tcgen05_fence_before_thread_sync(); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_fence_before_thread_sync_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void tcgen05_fence_before_thread_sync() +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm volatile ( + "tcgen05.fence::before_thread_sync;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_fence_before_thread_sync_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.fence::after_thread_sync; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template +__device__ static inline void tcgen05_fence_after_thread_sync(); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_fence_after_thread_sync_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void tcgen05_fence_after_thread_sync() +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm volatile ( + "tcgen05.fence::after_thread_sync;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_fence_after_thread_sync_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_FENCE_H + +// End of ./instructions/tcgen05_fence.h +// Start of ./instructions/tcgen05_ld.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_LD_H +#define INSTRUCTIONS_TCGEN05_LD_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_ld.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.ld.sync.aligned.16x64b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[1], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[1], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x1.b32 {%0}, [%1];" + : "=r"(out[0]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[1], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[1], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 {%0}, [%1];" + : "=r"(out[0]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[2], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x2.b32 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[2], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x4.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x128.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x128.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x64b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x64b.x128.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x64b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[2], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x1.b32 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[2], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x2.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x4.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x128b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x128b.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x128b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x1.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x2.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x4.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_16x256b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x256b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x256b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x1.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[1], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[1], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x1.b32 {%0}, [%1];" + : "=r"(out[0]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[1], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[1], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 {%0}, [%1];" + : "=r"(out[0]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x2.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[2], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x2.b32 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[2], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 {%0, %1}, [%2];" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x4.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x4.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[4], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 {%0, %1, %2, %3}, [%4];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x8.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[8], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x16.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[16], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x32.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[32], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x64.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[64], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x128.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x128.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 out, [taddr]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_ld_32x32b_pack_16b( + B32 (&out)[128], + std::uint32_t taddr) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.32x32b.x128.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_32x32b_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x1.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[1], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[1], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x1.b32 {%0}, [%1], %2;" + : "=r"(out[0]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[1], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[1], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 {%0}, [%1], %2;" + : "=r"(out[0]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x2.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x2.b32 {%0, %1}, [%2], %3;" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 {%0, %1}, [%2], %3;" + : "=r"(out[0]), + "=r"(out[1]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x4.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x4.b32 {%0, %1, %2, %3}, [%4], %5;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 {%0, %1, %2, %3}, [%4], %5;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x8.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x8.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8], %9;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x8.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8], %9;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x16.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x16.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16], %17;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x16.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, [%16], %17;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x32.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x32.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32], %33;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x32.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, [%32], %33;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x64.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x64.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64], %65;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x64.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, [%64], %65;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x128.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2( + B32 (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x128.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128], %129;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 out, [taddr], immHalfSplitoff; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true, int N32> +__device__ static inline void tcgen05_ld_16x32bx2_pack_16b( + B32 (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.ld.sync.aligned.16x32bx2.x128.pack::16b.b32 {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, [%128], %129;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_16x32bx2_pack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x2.u32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[2], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.u32.min {%0, %1}, %2, [%3];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.u32.max {%0, %1}, %2, [%3];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x2.s32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[2], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.s32.min {%0, %1}, %2, [%3];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.s32.max {%0, %1}, %2, [%3];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x2.f32.op.abs out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.f32.min.abs {%0, %1}, %2, [%3];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.f32.max.abs {%0, %1}, %2, [%3];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x2.f32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.f32.min {%0, %1}, %2, [%3];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x2.f32.max {%0, %1}, %2, [%3];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x4.u32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[4], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.u32.min {%0, %1, %2, %3}, %4, [%5];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.u32.max {%0, %1, %2, %3}, %4, [%5];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x4.s32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[4], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.s32.min {%0, %1, %2, %3}, %4, [%5];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.s32.max {%0, %1, %2, %3}, %4, [%5];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x4.f32.op.abs out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.f32.min.abs {%0, %1, %2, %3}, %4, [%5];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.f32.max.abs {%0, %1, %2, %3}, %4, [%5];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x4.f32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.f32.min {%0, %1, %2, %3}, %4, [%5];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x4.f32.max {%0, %1, %2, %3}, %4, [%5];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x8.u32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[8], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.u32.min {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.u32.max {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x8.s32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[8], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.s32.min {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.s32.max {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x8.f32.op.abs out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x8.f32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.f32.min {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x8.f32.max {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x16.u32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[16], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x16.s32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[16], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x16.f32.op.abs out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x16.f32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x16.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x32.u32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[32], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x32.s32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[32], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x32.f32.op.abs out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x32.f32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x32.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x64.u32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[64], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x64.s32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[64], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x64.f32.op.abs out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x64.f32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x64.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x128.u32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::uint32_t (&out)[128], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x128.s32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + std::int32_t (&out)[128], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x128.f32.op.abs out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b_abs( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.32x32b.x128.f32.op out, redval, [taddr]; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_32x32b( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.32x32b.x128.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129];" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_32x32b_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x2.u32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.u32.min {%0, %1}, %2, [%3], %4;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.u32.max {%0, %1}, %2, [%3], %4;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x2.s32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.s32.min {%0, %1}, %2, [%3], %4;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.s32.max {%0, %1}, %2, [%3], %4;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x2.f32.op.abs out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.f32.min.abs {%0, %1}, %2, [%3], %4;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.f32.max.abs {%0, %1}, %2, [%3], %4;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x2.f32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[2], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.f32.min {%0, %1}, %2, [%3], %4;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x2.f32.max {%0, %1}, %2, [%3], %4;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x4.u32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.u32.min {%0, %1, %2, %3}, %4, [%5], %6;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.u32.max {%0, %1, %2, %3}, %4, [%5], %6;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x4.s32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.s32.min {%0, %1, %2, %3}, %4, [%5], %6;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.s32.max {%0, %1, %2, %3}, %4, [%5], %6;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x4.f32.op.abs out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.f32.min.abs {%0, %1, %2, %3}, %4, [%5], %6;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.f32.max.abs {%0, %1, %2, %3}, %4, [%5], %6;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x4.f32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[4], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.f32.min {%0, %1, %2, %3}, %4, [%5], %6;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x4.f32.max {%0, %1, %2, %3}, %4, [%5], %6;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x8.u32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.u32.min {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.u32.max {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x8.s32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.s32.min {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.s32.max {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x8.f32.op.abs out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x8.f32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[8], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.f32.min {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x8.f32.max {%0, %1, %2, %3, %4, %5, %6, %7}, %8, [%9], %10;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x16.u32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x16.s32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x16.f32.op.abs out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x16.f32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[16], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x16.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15}, %16, [%17], %18;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x32.u32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x32.s32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x32.f32.op.abs out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x32.f32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[32], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x32.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31}, %32, [%33], %34;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x64.u32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x64.s32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x64.f32.op.abs out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x64.f32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[64], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x64.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63}, %64, [%65], %66;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x128.u32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::uint32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::uint32_t (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::uint32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.u32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.u32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x128.s32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline std::int32_t tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + std::int32_t (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + std::int32_t redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.s32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.s32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=r"(out[0]), + "=r"(out[1]), + "=r"(out[2]), + "=r"(out[3]), + "=r"(out[4]), + "=r"(out[5]), + "=r"(out[6]), + "=r"(out[7]), + "=r"(out[8]), + "=r"(out[9]), + "=r"(out[10]), + "=r"(out[11]), + "=r"(out[12]), + "=r"(out[13]), + "=r"(out[14]), + "=r"(out[15]), + "=r"(out[16]), + "=r"(out[17]), + "=r"(out[18]), + "=r"(out[19]), + "=r"(out[20]), + "=r"(out[21]), + "=r"(out[22]), + "=r"(out[23]), + "=r"(out[24]), + "=r"(out[25]), + "=r"(out[26]), + "=r"(out[27]), + "=r"(out[28]), + "=r"(out[29]), + "=r"(out[30]), + "=r"(out[31]), + "=r"(out[32]), + "=r"(out[33]), + "=r"(out[34]), + "=r"(out[35]), + "=r"(out[36]), + "=r"(out[37]), + "=r"(out[38]), + "=r"(out[39]), + "=r"(out[40]), + "=r"(out[41]), + "=r"(out[42]), + "=r"(out[43]), + "=r"(out[44]), + "=r"(out[45]), + "=r"(out[46]), + "=r"(out[47]), + "=r"(out[48]), + "=r"(out[49]), + "=r"(out[50]), + "=r"(out[51]), + "=r"(out[52]), + "=r"(out[53]), + "=r"(out[54]), + "=r"(out[55]), + "=r"(out[56]), + "=r"(out[57]), + "=r"(out[58]), + "=r"(out[59]), + "=r"(out[60]), + "=r"(out[61]), + "=r"(out[62]), + "=r"(out[63]), + "=r"(out[64]), + "=r"(out[65]), + "=r"(out[66]), + "=r"(out[67]), + "=r"(out[68]), + "=r"(out[69]), + "=r"(out[70]), + "=r"(out[71]), + "=r"(out[72]), + "=r"(out[73]), + "=r"(out[74]), + "=r"(out[75]), + "=r"(out[76]), + "=r"(out[77]), + "=r"(out[78]), + "=r"(out[79]), + "=r"(out[80]), + "=r"(out[81]), + "=r"(out[82]), + "=r"(out[83]), + "=r"(out[84]), + "=r"(out[85]), + "=r"(out[86]), + "=r"(out[87]), + "=r"(out[88]), + "=r"(out[89]), + "=r"(out[90]), + "=r"(out[91]), + "=r"(out[92]), + "=r"(out[93]), + "=r"(out[94]), + "=r"(out[95]), + "=r"(out[96]), + "=r"(out[97]), + "=r"(out[98]), + "=r"(out[99]), + "=r"(out[100]), + "=r"(out[101]), + "=r"(out[102]), + "=r"(out[103]), + "=r"(out[104]), + "=r"(out[105]), + "=r"(out[106]), + "=r"(out[107]), + "=r"(out[108]), + "=r"(out[109]), + "=r"(out[110]), + "=r"(out[111]), + "=r"(out[112]), + "=r"(out[113]), + "=r"(out[114]), + "=r"(out[115]), + "=r"(out[116]), + "=r"(out[117]), + "=r"(out[118]), + "=r"(out[119]), + "=r"(out[120]), + "=r"(out[121]), + "=r"(out[122]), + "=r"(out[123]), + "=r"(out[124]), + "=r"(out[125]), + "=r"(out[126]), + "=r"(out[127]), + "=r"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x128.f32.op.abs out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2_abs( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.f32.min.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.f32.max.abs {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_abs_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.ld.red.sync.aligned.16x32bx2.x128.f32.op out, redval, [taddr], immHalfSplitoff; // PTX ISA 88, SM_103a, SM_103f, SM_110a, SM_110f +// .op = { .min, .max } +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline float tcgen05_ld_red_16x32bx2( + cuda_ptx::op_t op, + float (&out)[128], + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff) +{ + static_assert(op == op_min || op == op_max, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + float redval; + if constexpr (op == op_min) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.f32.min {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } else if constexpr (op == op_max) { + asm ( + "tcgen05.ld.red.sync.aligned.16x32bx2.x128.f32.max {%0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127}, %128, [%129], %130;" + : "=f"(out[0]), + "=f"(out[1]), + "=f"(out[2]), + "=f"(out[3]), + "=f"(out[4]), + "=f"(out[5]), + "=f"(out[6]), + "=f"(out[7]), + "=f"(out[8]), + "=f"(out[9]), + "=f"(out[10]), + "=f"(out[11]), + "=f"(out[12]), + "=f"(out[13]), + "=f"(out[14]), + "=f"(out[15]), + "=f"(out[16]), + "=f"(out[17]), + "=f"(out[18]), + "=f"(out[19]), + "=f"(out[20]), + "=f"(out[21]), + "=f"(out[22]), + "=f"(out[23]), + "=f"(out[24]), + "=f"(out[25]), + "=f"(out[26]), + "=f"(out[27]), + "=f"(out[28]), + "=f"(out[29]), + "=f"(out[30]), + "=f"(out[31]), + "=f"(out[32]), + "=f"(out[33]), + "=f"(out[34]), + "=f"(out[35]), + "=f"(out[36]), + "=f"(out[37]), + "=f"(out[38]), + "=f"(out[39]), + "=f"(out[40]), + "=f"(out[41]), + "=f"(out[42]), + "=f"(out[43]), + "=f"(out[44]), + "=f"(out[45]), + "=f"(out[46]), + "=f"(out[47]), + "=f"(out[48]), + "=f"(out[49]), + "=f"(out[50]), + "=f"(out[51]), + "=f"(out[52]), + "=f"(out[53]), + "=f"(out[54]), + "=f"(out[55]), + "=f"(out[56]), + "=f"(out[57]), + "=f"(out[58]), + "=f"(out[59]), + "=f"(out[60]), + "=f"(out[61]), + "=f"(out[62]), + "=f"(out[63]), + "=f"(out[64]), + "=f"(out[65]), + "=f"(out[66]), + "=f"(out[67]), + "=f"(out[68]), + "=f"(out[69]), + "=f"(out[70]), + "=f"(out[71]), + "=f"(out[72]), + "=f"(out[73]), + "=f"(out[74]), + "=f"(out[75]), + "=f"(out[76]), + "=f"(out[77]), + "=f"(out[78]), + "=f"(out[79]), + "=f"(out[80]), + "=f"(out[81]), + "=f"(out[82]), + "=f"(out[83]), + "=f"(out[84]), + "=f"(out[85]), + "=f"(out[86]), + "=f"(out[87]), + "=f"(out[88]), + "=f"(out[89]), + "=f"(out[90]), + "=f"(out[91]), + "=f"(out[92]), + "=f"(out[93]), + "=f"(out[94]), + "=f"(out[95]), + "=f"(out[96]), + "=f"(out[97]), + "=f"(out[98]), + "=f"(out[99]), + "=f"(out[100]), + "=f"(out[101]), + "=f"(out[102]), + "=f"(out[103]), + "=f"(out[104]), + "=f"(out[105]), + "=f"(out[106]), + "=f"(out[107]), + "=f"(out[108]), + "=f"(out[109]), + "=f"(out[110]), + "=f"(out[111]), + "=f"(out[112]), + "=f"(out[113]), + "=f"(out[114]), + "=f"(out[115]), + "=f"(out[116]), + "=f"(out[117]), + "=f"(out[118]), + "=f"(out[119]), + "=f"(out[120]), + "=f"(out[121]), + "=f"(out[122]), + "=f"(out[123]), + "=f"(out[124]), + "=f"(out[125]), + "=f"(out[126]), + "=f"(out[127]), + "=f"(redval) + : "r"(taddr), + "n"(immHalfSplitoff.value) + : "memory" + ); + } + return redval; + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_ld_red_16x32bx2_is_only_supported_on_SM_103a_103f_110a_110f_depending_on_the_variant__(); + return 0; + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_LD_H + +// End of ./instructions/tcgen05_ld.h +// Start of ./instructions/tcgen05_mma.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_MMA_H +#define INSTRUCTIONS_TCGEN05_MMA_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_mma.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f +// .kind = { .kind::f16, .kind::tf32 } +// .cta_group = { .cta_group::1 } +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32, ""); + // cta_group == cta_group_1 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(105) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(107) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f +// .kind = { .kind::f16, .kind::tf32 } +// .cta_group = { .cta_group::2 } +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32, ""); + // cta_group == cta_group_2 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(105) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(107) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d, %13; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d, %13; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +// .cta_group = { .cta_group::1 } +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + // cta_group == cta_group_1 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::i8 [%0], %1, %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +// .cta_group = { .cta_group::2 } +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + // cta_group == cta_group_2 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], %1, %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::i8 [%0], %1, %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f +// .kind = { .kind::f16, .kind::tf32 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + cuda_ptx::n32_t scale_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + cuda_ptx::n32_t scale_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(105) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(107) + if constexpr (kind == kind_f16 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_f16 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f16 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::i8 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_i8 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::i8 [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f +// .kind = { .kind::f16, .kind::tf32 } +// .cta_group = { .cta_group::1 } +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32, ""); + // cta_group == cta_group_1 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(105) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(107) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d, %9; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f +// .kind = { .kind::f16, .kind::tf32 } +// .cta_group = { .cta_group::2 } +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d, + cuda_ptx::n32_t scale_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32, ""); + // cta_group == cta_group_2 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(105) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(107) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d, %13; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d, %13; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +// .cta_group = { .cta_group::1 } +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_1_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[4], + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + // cta_group == cta_group_1 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %8, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::i8 [%0], [%1], %2, %3, {%4, %5, %6, %7}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, disable_output_lane, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +// .cta_group = { .cta_group::2 } +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_2_t, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + const std::uint32_t (&disable_output_lane)[8], + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + // cta_group == cta_group_2 (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], [%1], %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %12, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::i8 [%0], [%1], %2, %3, {%4, %5, %6, %7, %8, %9, %10, %11}, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(disable_output_lane[0]), + "r"(disable_output_lane[1]), + "r"(disable_output_lane[2]), + "r"(disable_output_lane[3]), + "r"(disable_output_lane[4]), + "r"(disable_output_lane[5]), + "r"(disable_output_lane[6]), + "r"(disable_output_lane[7]), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, scale_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f +// .kind = { .kind::f16, .kind::tf32 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + cuda_ptx::n32_t scale_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + cuda_ptx::n32_t scale_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(105) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(107) + if constexpr (kind == kind_f16 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_f16 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "n"(scale_input_d.value) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f16 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f16 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::tf32 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::f8f6f4 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::i8 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_i8 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::i8 [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2x_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2x_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16 [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32 [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32 [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16 [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32 [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32 [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_fill( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_fill( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::fill [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::fill [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::fill [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::fill [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::fill [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::fill [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_use( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_use( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::use [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::use [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::use [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::use [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::use [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::use [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_lastuse( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_lastuse( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::lastuse [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::lastuse [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::lastuse [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::lastuse [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::lastuse [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::lastuse [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_discard( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_collector_a_discard( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2x_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2x_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::discard [d_tmem], a_desc, b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], %1, %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::1X.collector::a::discard [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf8f6f4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf8f6f4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.scale_vec::1X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_1x_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::2X.collector::a::discard [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.scale_vec::2X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::2X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_2_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.scale_vec::4X.collector::a::discard [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.scale_vec::4X.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_vec_4x_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block16.collector::a::discard [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block16_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block16_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.cta_group.kind.block_scale.block32.collector::a::discard [d_tmem], [a_tmem], b_desc, idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_block_scale_block32_tmem_a_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %6, 0; \n\t" + "tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], [%1], %2, %3, [%4], [%5], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_block_scale_block32_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_MMA_H + +// End of ./instructions/tcgen05_mma.h +// Start of ./instructions/tcgen05_mma_sp.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_MMA_SP_H +#define INSTRUCTIONS_TCGEN05_MMA_SP_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_mma_sp.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.mma.sp.cta_group.kind [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::f8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_f8f6f4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::f16 [%0], %1, %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f16 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::f16 [%0], %1, %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::f8f6f4 [%0], %1, %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::f8f6f4 [%0], %1, %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.sp.cta_group.kind [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::f16, .kind::f8f6f4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + bool enable_input_d) +{ + static_assert(kind == kind_f16 || kind == kind_f8f6f4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::f16 [%0], [%1], %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f16 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::f16 [%0], [%1], %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::f8f6f4 [%0], [%1], %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %5, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::f8f6f4 [%0], [%1], %2, [%3], %4, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16 [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32 [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32 [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16 [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32 [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32 [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::fill [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::fill [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::fill [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_fill( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::fill [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_fill( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::fill [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::use [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::use [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::use [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_use( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_use_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::use [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_use( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::use [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::lastuse [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::lastuse [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::lastuse [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_lastuse( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::lastuse [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_lastuse( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::discard [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::discard [d_tmem], a_desc, b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], %1, %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block16.collector::a::discard [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_103a, SM_110a +// .kind = { .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_discard( + cuda_ptx::kind_mxf4nvf4_t, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + // kind == kind_mxf4nvf4 (due to parameter type constraint) + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block16_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +/* +// tcgen05.mma.sp.cta_group.kind.block_scale.block32.collector::a::discard [d_tmem], [a_tmem], b_desc, [sp_info_tmem], idesc, [scale_A_tmem], [scale_B_tmem], enable_input_d; // PTX ISA 88, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 880 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_discard( + cuda_ptx::kind_t kind, + cuda_ptx::cta_group_t cta_group, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t sp_info_tmem, + std::uint32_t idesc, + std::uint32_t scale_A_tmem, + std::uint32_t scale_B_tmem, + bool enable_input_d) +{ + static_assert(kind == kind_mxf8f6f4 || kind == kind_mxf4 || kind == kind_mxf4nvf4, ""); + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_mxf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf4nvf4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_1) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_mxf8f6f4 && cta_group == cta_group_2) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %7, 0; \n\t" + "tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%0], [%1], %2, [%3], %4, [%5], [%6], PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(sp_info_tmem), + "r"(idesc), + "r"(scale_A_tmem), + "r"(scale_B_tmem), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_sp_block_scale_block32_tmem_a_collector_a_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 880 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_MMA_SP_H + +// End of ./instructions/tcgen05_mma_sp.h +// Start of ./instructions/tcgen05_mma_ws.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_MMA_WS_H +#define INSTRUCTIONS_TCGEN05_MMA_WS_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_mma_ws.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b0::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b0_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b0_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b1::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b1_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b1::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b1_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b2::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b2_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b2::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b2_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::fill [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_fill( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::fill [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_fill_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::use [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_use( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::use [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_use_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::lastuse [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_lastuse( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::lastuse [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_lastuse_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], a_desc, b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint64_t a_desc, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], %1, %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "l"(a_desc), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d, zero_column_mask_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d, + std::uint64_t zero_column_mask_desc) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d, %5; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)), + "l"(zero_column_mask_desc) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.mma.ws.cta_group.kind.collector::b3::discard [d_tmem], [a_tmem], b_desc, idesc, enable_input_d; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +// .cta_group = { .cta_group::1 } +// .kind = { .kind::f16, .kind::tf32, .kind::f8f6f4, .kind::i8 } +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_mma_ws_tmem_a_collector_b3_discard( + cuda_ptx::cta_group_1_t, + cuda_ptx::kind_t kind, + std::uint32_t d_tmem, + std::uint32_t a_tmem, + std::uint64_t b_desc, + std::uint32_t idesc, + bool enable_input_d) +{ + // cta_group == cta_group_1 (due to parameter type constraint) + static_assert(kind == kind_f16 || kind == kind_tf32 || kind == kind_f8f6f4 || kind == kind_i8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + if constexpr (kind == kind_f16) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f16.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_tf32) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } else if constexpr (kind == kind_f8f6f4) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + #endif + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (kind == kind_i8) { + asm volatile ( + "{\n\t" + ".reg .pred PRED_enable_input_d; \n\t" + "setp.ne.b32 PRED_enable_input_d, %4, 0; \n\t" + "tcgen05.mma.ws.cta_group::1.kind::i8.collector::b3::discard [%0], [%1], %2, %3, PRED_enable_input_d; \n" + "}" + : + : "r"(d_tmem), + "r"(a_tmem), + "l"(b_desc), + "r"(idesc), + "r"(static_cast(enable_input_d)) + : "memory" + ); + } + + #endif + #if !((defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110)) || (defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100))) + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_mma_ws_tmem_a_collector_b3_discard_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_MMA_WS_H + +// End of ./instructions/tcgen05_mma_ws.h +// Start of ./instructions/tcgen05_shift.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_SHIFT_H +#define INSTRUCTIONS_TCGEN05_SHIFT_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_shift.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.shift.cta_group.down [taddr]; // PTX ISA 86, SM_100a, SM_103a, SM_110a +// .cta_group = { .cta_group::1, .cta_group::2 } +template +__device__ static inline void tcgen05_shift_down( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_shift_down_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); +template +__device__ static inline void tcgen05_shift_down( + cuda_ptx::cta_group_t cta_group, + std::uint32_t taddr) +{ + static_assert(cta_group == cta_group_1 || cta_group == cta_group_2, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) + if constexpr (cta_group == cta_group_1) { + asm volatile ( + "tcgen05.shift.cta_group::1.down [%0];" + : + : "r"(taddr) + : "memory" + ); + } else if constexpr (cta_group == cta_group_2) { + asm volatile ( + "tcgen05.shift.cta_group::2.down [%0];" + : + : "r"(taddr) + : "memory" + ); + } + + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_shift_down_is_only_supported_on_SM_100a_103a_110a_depending_on_the_variant__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_SHIFT_H + +// End of ./instructions/tcgen05_shift.h +// Start of ./instructions/tcgen05_st.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_ST_H +#define INSTRUCTIONS_TCGEN05_ST_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_st.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.st.sync.aligned.16x64b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[1]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[1]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x1.b32 [%0], {%1};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[1]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[1]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [%0], {%1};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x2.b32 [%0], {%1, %2};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [%0], {%1, %2};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x4.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x64.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x128.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x64b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x64b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x1.b32 [%0], {%1, %2};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [%0], {%1, %2};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x2.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x4.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x64.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x128b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x128b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x1.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x2.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x4.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x256b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x256b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[1]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[1]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x1.b32 [%0], {%1};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[1]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[1]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [%0], {%1};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x2.b32 [%0], {%1, %2};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [%0], {%1, %2};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x4.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [%0], {%1, %2, %3, %4};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x8.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x16.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x32.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x64.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x128.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_32x32b_unpack_16b( + std::uint32_t taddr, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [%0], {%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128};" + : + : "r"(taddr), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_32x32b_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x1.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[1]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[1]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x1.b32 [%0], %1, {%2};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[1]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[1]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [%0], %1, {%2};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x2.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x2.b32 [%0], %1, {%2, %3};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[2]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[2]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [%0], %1, {%2, %3};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x4.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x4.b32 [%0], %1, {%2, %3, %4, %5};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[4]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[4]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x8.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x8.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[8]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[8]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x16.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x16.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[16]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[16]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x32.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x32.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[32]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[32]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x64.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x64.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[64]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[64]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x128.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x128.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128, %129};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[128]); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template = true> +__device__ static inline void tcgen05_st_16x32bx2_unpack_16b( + std::uint32_t taddr, + cuda_ptx::n32_t immHalfSplitoff, + const B32 (&values)[128]) +{ + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm ( + "tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [%0], %1, {%2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36, %37, %38, %39, %40, %41, %42, %43, %44, %45, %46, %47, %48, %49, %50, %51, %52, %53, %54, %55, %56, %57, %58, %59, %60, %61, %62, %63, %64, %65, %66, %67, %68, %69, %70, %71, %72, %73, %74, %75, %76, %77, %78, %79, %80, %81, %82, %83, %84, %85, %86, %87, %88, %89, %90, %91, %92, %93, %94, %95, %96, %97, %98, %99, %100, %101, %102, %103, %104, %105, %106, %107, %108, %109, %110, %111, %112, %113, %114, %115, %116, %117, %118, %119, %120, %121, %122, %123, %124, %125, %126, %127, %128, %129};" + : + : "r"(taddr), + "n"(immHalfSplitoff.value), + "r"(/*as_b32*/ *reinterpret_cast(&values[0])), + "r"(/*as_b32*/ *reinterpret_cast(&values[1])), + "r"(/*as_b32*/ *reinterpret_cast(&values[2])), + "r"(/*as_b32*/ *reinterpret_cast(&values[3])), + "r"(/*as_b32*/ *reinterpret_cast(&values[4])), + "r"(/*as_b32*/ *reinterpret_cast(&values[5])), + "r"(/*as_b32*/ *reinterpret_cast(&values[6])), + "r"(/*as_b32*/ *reinterpret_cast(&values[7])), + "r"(/*as_b32*/ *reinterpret_cast(&values[8])), + "r"(/*as_b32*/ *reinterpret_cast(&values[9])), + "r"(/*as_b32*/ *reinterpret_cast(&values[10])), + "r"(/*as_b32*/ *reinterpret_cast(&values[11])), + "r"(/*as_b32*/ *reinterpret_cast(&values[12])), + "r"(/*as_b32*/ *reinterpret_cast(&values[13])), + "r"(/*as_b32*/ *reinterpret_cast(&values[14])), + "r"(/*as_b32*/ *reinterpret_cast(&values[15])), + "r"(/*as_b32*/ *reinterpret_cast(&values[16])), + "r"(/*as_b32*/ *reinterpret_cast(&values[17])), + "r"(/*as_b32*/ *reinterpret_cast(&values[18])), + "r"(/*as_b32*/ *reinterpret_cast(&values[19])), + "r"(/*as_b32*/ *reinterpret_cast(&values[20])), + "r"(/*as_b32*/ *reinterpret_cast(&values[21])), + "r"(/*as_b32*/ *reinterpret_cast(&values[22])), + "r"(/*as_b32*/ *reinterpret_cast(&values[23])), + "r"(/*as_b32*/ *reinterpret_cast(&values[24])), + "r"(/*as_b32*/ *reinterpret_cast(&values[25])), + "r"(/*as_b32*/ *reinterpret_cast(&values[26])), + "r"(/*as_b32*/ *reinterpret_cast(&values[27])), + "r"(/*as_b32*/ *reinterpret_cast(&values[28])), + "r"(/*as_b32*/ *reinterpret_cast(&values[29])), + "r"(/*as_b32*/ *reinterpret_cast(&values[30])), + "r"(/*as_b32*/ *reinterpret_cast(&values[31])), + "r"(/*as_b32*/ *reinterpret_cast(&values[32])), + "r"(/*as_b32*/ *reinterpret_cast(&values[33])), + "r"(/*as_b32*/ *reinterpret_cast(&values[34])), + "r"(/*as_b32*/ *reinterpret_cast(&values[35])), + "r"(/*as_b32*/ *reinterpret_cast(&values[36])), + "r"(/*as_b32*/ *reinterpret_cast(&values[37])), + "r"(/*as_b32*/ *reinterpret_cast(&values[38])), + "r"(/*as_b32*/ *reinterpret_cast(&values[39])), + "r"(/*as_b32*/ *reinterpret_cast(&values[40])), + "r"(/*as_b32*/ *reinterpret_cast(&values[41])), + "r"(/*as_b32*/ *reinterpret_cast(&values[42])), + "r"(/*as_b32*/ *reinterpret_cast(&values[43])), + "r"(/*as_b32*/ *reinterpret_cast(&values[44])), + "r"(/*as_b32*/ *reinterpret_cast(&values[45])), + "r"(/*as_b32*/ *reinterpret_cast(&values[46])), + "r"(/*as_b32*/ *reinterpret_cast(&values[47])), + "r"(/*as_b32*/ *reinterpret_cast(&values[48])), + "r"(/*as_b32*/ *reinterpret_cast(&values[49])), + "r"(/*as_b32*/ *reinterpret_cast(&values[50])), + "r"(/*as_b32*/ *reinterpret_cast(&values[51])), + "r"(/*as_b32*/ *reinterpret_cast(&values[52])), + "r"(/*as_b32*/ *reinterpret_cast(&values[53])), + "r"(/*as_b32*/ *reinterpret_cast(&values[54])), + "r"(/*as_b32*/ *reinterpret_cast(&values[55])), + "r"(/*as_b32*/ *reinterpret_cast(&values[56])), + "r"(/*as_b32*/ *reinterpret_cast(&values[57])), + "r"(/*as_b32*/ *reinterpret_cast(&values[58])), + "r"(/*as_b32*/ *reinterpret_cast(&values[59])), + "r"(/*as_b32*/ *reinterpret_cast(&values[60])), + "r"(/*as_b32*/ *reinterpret_cast(&values[61])), + "r"(/*as_b32*/ *reinterpret_cast(&values[62])), + "r"(/*as_b32*/ *reinterpret_cast(&values[63])), + "r"(/*as_b32*/ *reinterpret_cast(&values[64])), + "r"(/*as_b32*/ *reinterpret_cast(&values[65])), + "r"(/*as_b32*/ *reinterpret_cast(&values[66])), + "r"(/*as_b32*/ *reinterpret_cast(&values[67])), + "r"(/*as_b32*/ *reinterpret_cast(&values[68])), + "r"(/*as_b32*/ *reinterpret_cast(&values[69])), + "r"(/*as_b32*/ *reinterpret_cast(&values[70])), + "r"(/*as_b32*/ *reinterpret_cast(&values[71])), + "r"(/*as_b32*/ *reinterpret_cast(&values[72])), + "r"(/*as_b32*/ *reinterpret_cast(&values[73])), + "r"(/*as_b32*/ *reinterpret_cast(&values[74])), + "r"(/*as_b32*/ *reinterpret_cast(&values[75])), + "r"(/*as_b32*/ *reinterpret_cast(&values[76])), + "r"(/*as_b32*/ *reinterpret_cast(&values[77])), + "r"(/*as_b32*/ *reinterpret_cast(&values[78])), + "r"(/*as_b32*/ *reinterpret_cast(&values[79])), + "r"(/*as_b32*/ *reinterpret_cast(&values[80])), + "r"(/*as_b32*/ *reinterpret_cast(&values[81])), + "r"(/*as_b32*/ *reinterpret_cast(&values[82])), + "r"(/*as_b32*/ *reinterpret_cast(&values[83])), + "r"(/*as_b32*/ *reinterpret_cast(&values[84])), + "r"(/*as_b32*/ *reinterpret_cast(&values[85])), + "r"(/*as_b32*/ *reinterpret_cast(&values[86])), + "r"(/*as_b32*/ *reinterpret_cast(&values[87])), + "r"(/*as_b32*/ *reinterpret_cast(&values[88])), + "r"(/*as_b32*/ *reinterpret_cast(&values[89])), + "r"(/*as_b32*/ *reinterpret_cast(&values[90])), + "r"(/*as_b32*/ *reinterpret_cast(&values[91])), + "r"(/*as_b32*/ *reinterpret_cast(&values[92])), + "r"(/*as_b32*/ *reinterpret_cast(&values[93])), + "r"(/*as_b32*/ *reinterpret_cast(&values[94])), + "r"(/*as_b32*/ *reinterpret_cast(&values[95])), + "r"(/*as_b32*/ *reinterpret_cast(&values[96])), + "r"(/*as_b32*/ *reinterpret_cast(&values[97])), + "r"(/*as_b32*/ *reinterpret_cast(&values[98])), + "r"(/*as_b32*/ *reinterpret_cast(&values[99])), + "r"(/*as_b32*/ *reinterpret_cast(&values[100])), + "r"(/*as_b32*/ *reinterpret_cast(&values[101])), + "r"(/*as_b32*/ *reinterpret_cast(&values[102])), + "r"(/*as_b32*/ *reinterpret_cast(&values[103])), + "r"(/*as_b32*/ *reinterpret_cast(&values[104])), + "r"(/*as_b32*/ *reinterpret_cast(&values[105])), + "r"(/*as_b32*/ *reinterpret_cast(&values[106])), + "r"(/*as_b32*/ *reinterpret_cast(&values[107])), + "r"(/*as_b32*/ *reinterpret_cast(&values[108])), + "r"(/*as_b32*/ *reinterpret_cast(&values[109])), + "r"(/*as_b32*/ *reinterpret_cast(&values[110])), + "r"(/*as_b32*/ *reinterpret_cast(&values[111])), + "r"(/*as_b32*/ *reinterpret_cast(&values[112])), + "r"(/*as_b32*/ *reinterpret_cast(&values[113])), + "r"(/*as_b32*/ *reinterpret_cast(&values[114])), + "r"(/*as_b32*/ *reinterpret_cast(&values[115])), + "r"(/*as_b32*/ *reinterpret_cast(&values[116])), + "r"(/*as_b32*/ *reinterpret_cast(&values[117])), + "r"(/*as_b32*/ *reinterpret_cast(&values[118])), + "r"(/*as_b32*/ *reinterpret_cast(&values[119])), + "r"(/*as_b32*/ *reinterpret_cast(&values[120])), + "r"(/*as_b32*/ *reinterpret_cast(&values[121])), + "r"(/*as_b32*/ *reinterpret_cast(&values[122])), + "r"(/*as_b32*/ *reinterpret_cast(&values[123])), + "r"(/*as_b32*/ *reinterpret_cast(&values[124])), + "r"(/*as_b32*/ *reinterpret_cast(&values[125])), + "r"(/*as_b32*/ *reinterpret_cast(&values[126])), + "r"(/*as_b32*/ *reinterpret_cast(&values[127])) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_st_16x32bx2_unpack_16b_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_ST_H + +// End of ./instructions/tcgen05_st.h +// Start of ./instructions/tcgen05_wait.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TCGEN05_WAIT_H +#define INSTRUCTIONS_TCGEN05_WAIT_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tcgen05_wait.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tcgen05.wait::ld.sync.aligned; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template +__device__ static inline void tcgen05_wait_ld(); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_wait_ld_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void tcgen05_wait_ld() +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm volatile ( + "tcgen05.wait::ld.sync.aligned;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_wait_ld_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tcgen05.wait::st.sync.aligned; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f +template +__device__ static inline void tcgen05_wait_st(); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tcgen05_wait_st_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); +template +__device__ static inline void tcgen05_wait_st() +{ + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) + asm volatile ( + "tcgen05.wait::st.sync.aligned;" + : + : + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tcgen05_wait_st_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TCGEN05_WAIT_H + +// End of ./instructions/tcgen05_wait.h +// Start of ./instructions/tensormap_cp_fenceproxy.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TENSORMAP_CP_FENCEPROXY_H +#define INSTRUCTIONS_TENSORMAP_CP_FENCEPROXY_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tensormap_cp_fenceproxy.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.sem.scope.sync.aligned [dst], [src], size; // PTX ISA 83, SM_90 +// .sem = { .release } +// .scope = { .cta, .cluster, .gpu, .sys } +template +__device__ static inline void tensormap_cp_fenceproxy( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + void* dst, + const void* src, + cuda_ptx::n32_t size); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_cp_fenceproxy_is_not_supported_before_SM_90__(); +template +__device__ static inline void tensormap_cp_fenceproxy( + cuda_ptx::sem_release_t, + cuda_ptx::scope_t scope, + void* dst, + const void* src, + cuda_ptx::n32_t size) +{ + // sem == sem_release (due to parameter type constraint) + static_assert(scope == scope_cta || scope == scope_cluster || scope == scope_gpu || scope == scope_sys, ""); + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 900 + if constexpr (scope == scope_cta) { + asm volatile ( + "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cta.sync.aligned [%0], [%1], %2;" + : + : "l"(__as_ptr_gmem(dst)), + "r"(__as_ptr_smem(src)), + "n"(size.value) + : "memory" + ); + } else if constexpr (scope == scope_cluster) { + asm volatile ( + "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cluster.sync.aligned [%0], [%1], %2;" + : + : "l"(__as_ptr_gmem(dst)), + "r"(__as_ptr_smem(src)), + "n"(size.value) + : "memory" + ); + } else if constexpr (scope == scope_gpu) { + asm volatile ( + "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.gpu.sync.aligned [%0], [%1], %2;" + : + : "l"(__as_ptr_gmem(dst)), + "r"(__as_ptr_smem(src)), + "n"(size.value) + : "memory" + ); + } else if constexpr (scope == scope_sys) { + asm volatile ( + "tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.sys.sync.aligned [%0], [%1], %2;" + : + : "l"(__as_ptr_gmem(dst)), + "r"(__as_ptr_smem(src)), + "n"(size.value) + : "memory" + ); + } + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_cp_fenceproxy_is_not_supported_before_SM_90__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TENSORMAP_CP_FENCEPROXY_H + +// End of ./instructions/tensormap_cp_fenceproxy.h +// Start of ./instructions/tensormap_replace.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TENSORMAP_REPLACE_H +#define INSTRUCTIONS_TENSORMAP_REPLACE_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/tensormap_replace.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template = true> +__device__ static inline void tensormap_replace_global_address( + cuda_ptx::space_global_t, + void* tm_addr, + B64 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_global_address_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_global_address( + cuda_ptx::space_global_t, + void* tm_addr, + B64 new_val) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.global_address.global.b1024.b64 [%0], %1;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "l"(/*as_b64*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_global_address_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template = true> +__device__ static inline void tensormap_replace_global_address( + cuda_ptx::space_shared_t, + void* tm_addr, + B64 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_global_address_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_global_address( + cuda_ptx::space_shared_t, + void* tm_addr, + B64 new_val) +{ + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.global_address.shared::cta.b1024.b64 [%0], %1;" + : + : "r"(__as_ptr_smem(tm_addr)), + "l"(/*as_b64*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_global_address_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template = true> +__device__ static inline void tensormap_replace_rank( + cuda_ptx::space_global_t, + void* tm_addr, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_rank_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_rank( + cuda_ptx::space_global_t, + void* tm_addr, + B32 new_val) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.rank.global.b1024.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_rank_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template = true> +__device__ static inline void tensormap_replace_rank( + cuda_ptx::space_shared_t, + void* tm_addr, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_rank_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_rank( + cuda_ptx::space_shared_t, + void* tm_addr, + B32 new_val) +{ + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.rank.shared::cta.b1024.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(tm_addr)), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_rank_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template = true> +__device__ static inline void tensormap_replace_box_dim( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_box_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_box_dim( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.box_dim.global.b1024.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_box_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template = true> +__device__ static inline void tensormap_replace_box_dim( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_box_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_box_dim( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.box_dim.shared::cta.b1024.b32 [%0], %1, %2;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_box_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template = true> +__device__ static inline void tensormap_replace_global_dim( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_global_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_global_dim( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.global_dim.global.b1024.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_global_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template = true> +__device__ static inline void tensormap_replace_global_dim( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_global_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_global_dim( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.global_dim.shared::cta.b1024.b32 [%0], %1, %2;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_global_dim_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template = true> +__device__ static inline void tensormap_replace_global_stride( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B64 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_global_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_global_stride( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B64 new_val) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.global_stride.global.b1024.b64 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(ord.value), + "l"(/*as_b64*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_global_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template = true> +__device__ static inline void tensormap_replace_global_stride( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B64 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_global_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_global_stride( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B64 new_val) +{ + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(B64) == 8, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.global_stride.shared::cta.b1024.b64 [%0], %1, %2;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(ord.value), + "l"(/*as_b64*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_global_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template = true> +__device__ static inline void tensormap_replace_element_stride( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_element_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_element_stride( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.element_stride.global.b1024.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_element_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template = true> +__device__ static inline void tensormap_replace_element_stride( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_element_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_element_stride( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [%0], %1, %2;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_element_stride_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template = true> +__device__ static inline void tensormap_replace_element_size( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_element_size_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_element_size( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_global (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.element_stride.global.b1024.b32 [%0], %1, %2;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_element_size_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template = true> +__device__ static inline void tensormap_replace_element_size( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_element_size_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template = true> +__device__ static inline void tensormap_replace_element_size( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t ord, + B32 new_val) +{ + // space == space_shared (due to parameter type constraint) + static_assert(sizeof(B32) == 4, ""); + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.element_stride.shared::cta.b1024.b32 [%0], %1, %2;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(ord.value), + "r"(/*as_b32*/ *reinterpret_cast(&new_val)) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_element_size_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template +__device__ static inline void tensormap_replace_elemtype( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_elemtype_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_elemtype( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.elemtype.global.b1024.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_elemtype_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template +__device__ static inline void tensormap_replace_elemtype( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_elemtype_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_elemtype( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.elemtype.shared::cta.b1024.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_elemtype_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template +__device__ static inline void tensormap_replace_interleave_layout( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_interleave_layout_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_interleave_layout( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.interleave_layout.global.b1024.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_interleave_layout_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template +__device__ static inline void tensormap_replace_interleave_layout( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_interleave_layout_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_interleave_layout( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.interleave_layout.shared::cta.b1024.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_interleave_layout_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template +__device__ static inline void tensormap_replace_swizzle_mode( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_swizzle_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_swizzle_mode( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.swizzle_mode.global.b1024.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_swizzle_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template +__device__ static inline void tensormap_replace_swizzle_mode( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_swizzle_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_swizzle_mode( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_swizzle_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template +__device__ static inline void tensormap_replace_fill_mode( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_fill_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_fill_mode( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.fill_mode.global.b1024.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_fill_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template +__device__ static inline void tensormap_replace_fill_mode( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 830 +extern "C" __device__ void __cuda_ptx_tensormap_replace_fill_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_fill_mode( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 900) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.fill_mode.shared::cta.b1024.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_fill_mode_is_only_supported_on_SM_90a_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 830 + +/* +// tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .global } +template +__device__ static inline void tensormap_replace_swizzle_atomicity( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tensormap_replace_swizzle_atomicity_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_swizzle_atomicity( + cuda_ptx::space_global_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_global (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.swizzle_atomicity.global.b1024.b32 [%0], %1;" + : + : "l"(__as_ptr_gmem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_swizzle_atomicity_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +/* +// tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f +// .space = { .shared::cta } +template +__device__ static inline void tensormap_replace_swizzle_atomicity( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val); +*/ +#if __libcuda_ptx_isa >= 860 +extern "C" __device__ void __cuda_ptx_tensormap_replace_swizzle_atomicity_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); +template +__device__ static inline void tensormap_replace_swizzle_atomicity( + cuda_ptx::space_shared_t, + void* tm_addr, + cuda_ptx::n32_t new_val) +{ + // space == space_shared (due to parameter type constraint) + #if defined(_NVHPC_CUDA) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1000) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1030) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1100) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1200) || (_LIBCUDA_PTX_ARCH_SPECIFIC() == 1210) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(103) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(110) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(120) || __CUDA_HAS_ARCH_FAMILY_SPECIFIC(121) + asm ( + "tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32 [%0], %1;" + : + : "r"(__as_ptr_smem(tm_addr)), + "n"(new_val.value) + : "memory" + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_tensormap_replace_swizzle_atomicity_is_only_supported_on_SM_100a_100f_103a_103f_110a_110f_120a_120f_121a_121f__(); + #endif +} +#endif // __libcuda_ptx_isa >= 860 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TENSORMAP_REPLACE_H + +// End of ./instructions/tensormap_replace.h +// Start of ./instructions/trap.h +// -*- cuda -*- + +#ifndef INSTRUCTIONS_TRAP_H +#define INSTRUCTIONS_TRAP_H + +// We don't support including this header directly. It must be included through +// ptx.h. +#ifndef LIBCUDA_PTX_H +#error "instructions/trap.h should only be included in from ptx.h" +#endif // LIBCUDA_PTX_H + +namespace cuda_ptx { + +/* +// trap; // PTX ISA 10, SM_50 +template +__device__ static inline void trap(); +*/ +#if __libcuda_ptx_isa >= 100 +extern "C" __device__ void __cuda_ptx_trap_is_not_supported_before_SM_50__(); +template +__device__ static inline void trap() +{ + #if defined(_NVHPC_CUDA) || __CUDA_ARCH__ >= 500 + asm volatile ( + "trap;" + : + : + : + ); + #else + // Unsupported architectures will have a linker error with a semi-decent error message + __cuda_ptx_trap_is_not_supported_before_SM_50__(); + #endif +} +#endif // __libcuda_ptx_isa >= 100 + +} // namespace cuda_ptx + +#endif // INSTRUCTIONS_TRAP_H + +// End of ./instructions/trap.h + +#endif // LIBCUDA_PTX_H diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h index c31b9a9163f8..93e6a2c18e21 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h @@ -18,22 +18,44 @@ #include "cuda_runtime_api.h" #include "tensorrt_llm/common/config.h" +#include +#include +#include #include #include +#include +#include +#include +#include #include #include "tensorrt_llm/common/cudaDriverWrapper.h" +#include "tensorrt_llm/common/cudaUtils.h" #include "tensorrt_llm/common/envUtils.h" #include "tensorrt_llm/common/logger.h" +#include "tensorrt_llm/kernels/multiHeadAttentionCommon.h" #include "cubin/kernelMetaInfo.h" #include "fmhaReduction.h" #include "fmhaRunnerParams.h" -#include "kernelParams.h" #include "prepareCustomMask.h" -#include "tensorrt_llm/kernels/multiHeadAttentionCommon.h" +// Switch to streaming-style TLLM_LOG_* macros for trtllm-gen export headers, +// which use streaming syntax (e.g., TLLM_LOG_INFO("val=", x)) instead of +// TRT-LLM's printf-style (e.g., TLLM_LOG_INFO("val=%d", x)). +#include "trtllmGen_fmha_export/FmhaAutoTuner.h" +#include "trtllmGen_fmha_export/FmhaInterface.h" +#include "trtllmGen_fmha_export/FmhaOptions.h" +#include "trtllmGen_fmha_export/KernelParams.h" +#include "trtllmGen_fmha_export/trtllmGenLogCompat.h" +// Restore original printf-style TLLM_LOG_* macros for the rest of this file. +#include "trtllmGen_fmha_export/trtllmGenLogCompatEnd.h" + +namespace +{ namespace tc = tensorrt_llm::common; +namespace tg = trtllm::gen; +} // namespace TRTLLM_NAMESPACE_BEGIN @@ -94,6 +116,13 @@ class TllmGenFmhaKernel using KernelMeta = TllmGenFmhaKernelMetaInfo; using RunnerParams = TllmGenFmhaRunnerParams; using SelectKernelParams = TllmGenSelectKernelParams; + using FmhaOptions = fmha::FmhaOptions; + using FmhaOptionsFromArgs = fmha::FmhaOptionsFromArgs; + using FmhaAutoTuner = fmha::FmhaAutoTuner; + using FmhaInterface = fmha::FmhaInterface; + using FmhaConfig = fmha::FmhaConfig; + using FmhaData = fmha::FmhaData; + using KernelParams = fmha::KernelParams; // Ctor. TllmGenFmhaKernel(KernelMeta const* pMetaStart, unsigned int nMetaCount, Data_type dtypeQ, Data_type dtypeKv, @@ -161,6 +190,164 @@ class TllmGenFmhaKernel } } + std::pair checkIfKernelExist(RunnerParams const& params) const + { + // Some conditions to check if the kernel is supported. + // This is meant to avoid occupying unnecessary hashId bits. + if (params.mHeadDimQk % 8 != 0 || params.mHeadDimV % 8 != 0) + { + return std::make_pair(false, "HeadDimQk and HeadDimV must be divisible by 8"); + } + + if (params.mMaxSeqLenQ == 0 || params.mBatchSize == 0 + || (!isContextKernel(params.mKernelType) && params.mMaxSeqLenKv == 0)) + { + return std::make_pair(false, "Empty batch or zero sequence length"); + } + + // The selectKernelParams that might be updated. + SelectKernelParams selectKernelParams{params}; + + int32_t ctaDim = 512; + FmhaOptions options; + FmhaOptionsFromArgs optionsFromArgs; + parseOptionsFromRunnerParams(params, options); + options.mCudaArch = intToCudaArch(mSM); + + FmhaAutoTuner autoTuner(options, optionsFromArgs, params.mMultiProcessorCount); + std::tie(options, optionsFromArgs, ctaDim) = autoTuner.selectKernel(); + // Check if the options are valid or not. + checkFmhaOptions(options, optionsFromArgs); + // Update the options if needed. + updateFmhaOptions(options, optionsFromArgs); + // The number of CtasQ and CtasKv per sequence, Ctas in the Y dimension, and Ctas in the Z + // dimension. + computeNumCtas(options, params.mMultiProcessorCount); + + // Check if a precompiled cubin exists for this configuration (same lookup as run()). + // If not, return (false, info) so the dispatcher can fall back to unfused MHA like on main. + algoFilterForCubinPath(options); + auto [hashId, info] = hashFromFmhaOptions(options); + + if (mFunctions.find(hashId) == mFunctions.end()) + { + TLLM_LOG_WARNING("Trtllm-gen kernels not found: " + info); + return std::make_pair(false, info); + } + TLLM_LOG_DEBUG("TRTLLM-Gen kernel traits: %s", info.c_str()); + + return std::make_pair(true, info); + } + + void algoFilterForCubinPath(FmhaOptions& options) const + { + if (!isContextKernel(options.mFmhaKernelType) && options.mMaskType == TrtllmGenAttentionMaskType::Dense) + { + options.mMaskType = TrtllmGenAttentionMaskType::Causal; + } + } + + void run(RunnerParams const& params) + { + if (params.mMaxSeqLenQ == 0 || params.mBatchSize == 0 + || (!isContextKernel(params.mKernelType) && params.mMaxSeqLenKv == 0)) + { + return; + } + + int32_t ctaDim = 512; + FmhaOptions options; + FmhaOptionsFromArgs optionsFromArgs; + parseOptionsFromRunnerParams(params, options); + options.mCudaArch = intToCudaArch(mSM); + + FmhaAutoTuner autoTuner(options, optionsFromArgs, params.mMultiProcessorCount); + std::tie(options, optionsFromArgs, ctaDim) = autoTuner.selectKernel(); + // Check if the options are valid or not. + checkFmhaOptions(options, optionsFromArgs); + // Update the options if needed. + updateFmhaOptions(options, optionsFromArgs); + // The number of CtasQ and CtasKv per sequence, Ctas in the Y dimension, and Ctas in the Z + // dimension. + auto [numCtasX, numCtasY, numCtasZ] = computeNumCtas(options, params.mMultiProcessorCount); + + // Set the launch grid size. + tg::CudaRunner::Grid grid{numCtasX, numCtasY, numCtasZ}; + + // Prepare custom mask for spec-decoding generation kernels if needed. + if (params.mLayerIdx == 0 && params.mIsSpecDecTree) + { + int32_t stepQ = options.mTileSizeQ * options.mNumInstsQ; + int32_t stepKv = options.mTileSizeKv * options.mNumInstsKv; + runPrepareCustomMask( + params, options.mFmhaKernelType, stepQ, stepKv, options.mTileSizeQ, options.mTileSizeKv, params.stream); + } + + FmhaData fmhaData; + setFmhaData(params, options, fmhaData); + bool isLlama70bFp4Tp4 = options.mHeadDimQk == 128 && options.mHeadDimV == 128 + && options.mDtypeKv == tg::Dtype::E4m3 && options.mNumHeadsQ == 16 && options.mNumHeadsQPerKv == 8; + + bool shouldUseNvrtc = options.mFmhaKernelType == FmhaKernelType::SwapsMmaAbForGeneration && !options.mIsMlaGen + && options.mDtypeKv != tg::Dtype::E2m1 && options.mHeadDimQk != 64 && !isLlama70bFp4Tp4; + + if (shouldUseNvrtc) + { + // nvrtc path - uses mFmhaInterface member for kernel caching + FmhaConfig fmhaConfig; + fmhaConfig.mOptions = options; + std::ostringstream sstream; + populateJsonConfig(options, sstream); + fmhaConfig.mGenCfgJsonStr = sstream.str(); + + fmhaConfig.mExecPath = getExecPath().c_str(); + fmhaConfig.mCtaDim = ctaDim; + fmhaConfig.mGrid = grid; + mFmhaInterface.generateAndCompileKernel(fmhaConfig); + mFmhaInterface.run(fmhaConfig, fmhaData, params.stream, params.mMultiProcessorCount, 0); + } + else + { + algoFilterForCubinPath(options); + auto [hashId, info] = hashFromFmhaOptions(options); + + // load from cubin + auto const findIter = mFunctions.find(hashId); + // Add debug info when kernels are not found. + TLLM_CHECK_WITH_INFO(findIter != mFunctions.end(), "Trtllm-gen kernels not found: " + info); + + auto const& kernelMeta = mKernelMeta[findIter->second.mMetaInfoIndex]; + const CUfunction func = findIter->second.mDeviceFunction; + + // mGroupsHeadsQ and mGroupsTokensHeadsQ are not part of the hashID, so they don't + // affect kernel lookup. Use cubin-side values from kernelMeta instead of AutoTuner + // output, since cubins are exported with enableAutotuner=false. + options.mGroupsHeadsQ = kernelMeta.mGroupsHeadsQ; + options.mGroupsTokensHeadsQ = kernelMeta.mGroupsTokensHeadsQ; + + KernelParams kernelParams = fmha::KernelParamsSetup::setKernelParams(options, grid[0], grid[1], grid[2], + fmhaData.mMetaData.cumSeqLensQPtrD, fmhaData.mMetaData.cumSeqLensKvPtrD, fmhaData.mMetaData.seqLensKvD, + fmhaData.mInputBuffers.qBasePtr, fmhaData.mInputBuffers.kBasePtr, fmhaData.mInputBuffers.vBasePtr, + fmhaData.mScales.kSfBasePtr, fmhaData.mScales.vSfBasePtr, fmhaData.mMetaData.kvPageIdxD, + fmhaData.mScales.outputScaleD, fmhaData.mScales.scaleSoftmaxLog2D, fmhaData.mScales.kvSfScaleD, + fmhaData.mScales.oSfScaleD, fmhaData.mInputBuffers.customMaskPtrD, + fmhaData.mInputBuffers.customMaskOffsetsPtrD, fmhaData.mMetaData.firstSparseMaskOffsetsKvPtrD, + fmhaData.mScales.sageAttnSfsQPtrD, fmhaData.mScales.sageAttnSfsKPtrD, fmhaData.mScales.sageAttnSfsPPtrD, + fmhaData.mScales.sageAttnSfsVPtrD, fmhaData.mInputBuffers.attentionSinksPtrD, + fmhaData.mOutputBuffers.oPtrD, fmhaData.mScales.oSfPtrD, fmhaData.mOutputBuffers.multiCtasKvCounterPtrD, + fmhaData.mOutputBuffers.partialOPtrD, fmhaData.mOutputBuffers.partialStatsPtrD, + fmhaData.mOutputBuffers.skipSoftmaxStatsPtrD, fmhaData.mOutputBuffers.softmaxStatsD, + fmhaData.mOutputBuffers.oDebugPtrD, fmhaData.mScales.softmaxScale, fmhaData.mMetaData.inflateMax, + fmhaData.mScales.kvSfScale, fmhaData.mScales.oSfScale, fmhaData.mMetaData.startTokenIdxSfO, + options.mUseBlockSparseAttention, options.mUsesSharedPagedKvIdx); + + launchFmhaKernel(kernelParams, kernelMeta, func, grid, options, params.stream); + // Run the separate reduction kernel if needed. + runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount, params.stream); + } + } + +private: inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler, int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV, int tileSizeQ, int tileSizeKv, int numTokensPerPage, bool reuseSmemKForV, bool uses2CtaMma, bool sparseMla, bool skipsSoftmax) const @@ -170,9 +357,9 @@ class TllmGenFmhaKernel "Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, " "headDimV=%d", headDimPerCtaV, headDimQk, headDimV); - // The numTokensPerPage must be power of 2. - TLLM_CHECK_WITH_INFO( - (numTokensPerPage & (numTokensPerPage - 1)) == 0, "The numTokensPerPage must be power of 2."); + // The numTokensPerPage must be 0 (non-paged layouts) or a power of 2 (paged layouts). + TLLM_CHECK_WITH_INFO(numTokensPerPage == 0 || (numTokensPerPage & (numTokensPerPage - 1)) == 0, + "The numTokensPerPage must be 0 or power of 2, got %d.", numTokensPerPage); TLLM_CHECK_WITH_INFO(tileSizeQ <= 128 && tileSizeKv <= 128, "The tileSizeQ and tileSizeKv must be <= 128."); TLLM_CHECK_WITH_INFO((tileSizeQ & (tileSizeQ - 1)) == 0 && (tileSizeKv & (tileSizeKv - 1)) == 0, "The tileSizeQ and tileSizeKv must be power of 2."); @@ -197,7 +384,8 @@ class TllmGenFmhaKernel | (static_cast(kernelType) << 8) | (static_cast(scheduler) << 12) | (static_cast(multiCtasKvMode) << 16) | (static_cast(headDimPerCtaV >> 3) << 18) | (static_cast(headDimQk >> 3) << 26) | (static_cast(headDimV >> 3) << 34) - | (static_cast(tileSizeKv >> 6) << 42) | (static_cast(log2(numTokensPerPage)) << 44) + | (static_cast(tileSizeKv >> 6) << 42) + | (static_cast(numTokensPerPage > 0 ? static_cast(log2(numTokensPerPage)) : 0) << 44) | (static_cast(log2(tileSizeQ)) << 49) | (static_cast(reuseSmemKForV) << 53) | (static_cast(uses2CtaMma) << 54) | (static_cast(sparseMla) << 55) | (static_cast(skipsSoftmax) << 56); @@ -211,642 +399,509 @@ class TllmGenFmhaKernel kernelMeta.m2CtaMma, kernelMeta.mSparseMla, kernelMeta.mSkipsSoftmaxWhenPossible); } - std::pair checkIfKernelExist(RunnerParams const& params) const - { - // Some conditions to check if the kernel is supported. - // This is meant to avoid occupying unnecessary hashId bits. - if (params.mHeadDimQk % 8 != 0 || params.mHeadDimV % 8 != 0) - { - return std::make_pair(false, "HeadDimQk and HeadDimV must be divisible by 8"); - } - - // The selectKernelParams that might be updated. - SelectKernelParams selectKernelParams{params}; - // Select the kernel. - selectKernel(params, selectKernelParams); - // Hash the runner params. - auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams); - return std::make_pair(mFunctions.find(hashId) != mFunctions.end(), info); - } - - std::pair loadKernel( - RunnerParams const& params, SelectKernelParams const& selectKernelParams) const + std::pair hashFromFmhaOptions(FmhaOptions const& options) const { - auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams); - auto const findIter = mFunctions.find(hashId); - - // Add debug info when kernels are not found. - TLLM_CHECK_WITH_INFO(findIter != mFunctions.end(), "Trtllm-gen kernels not found: " + info); + // uses2CtaMma: "2CTA MMA kernel variant" (MLA KeepsMmaAb with clusterDimX=2). + // CGA scaling (clusterDimX *= mMaxNumCtasKv) is applied only at launch time in launchFmhaKernel, + // so options.mClusterDimX here is the unscaled value from the autotuner. + bool uses2CtaMma = (options.mClusterDimX == 2); + // Debug info. + std::string info = "dtypeQ=" + std::to_string(static_cast(mDtypeQ)) + ", dtypeKv=" + + std::to_string(static_cast(mDtypeKv)) + ", dtypeOut=" + std::to_string(static_cast(mDtypeOut)) + + ", sm=" + std::to_string(mSM) + ", qkvLayout=" + std::to_string(static_cast(options.mQkvLayout)) + + ", maskType=" + std::to_string(static_cast(options.mMaskType)) + + ", kernelType=" + std::to_string(static_cast(options.mFmhaKernelType)) + + ", tileScheduler=" + std::to_string(static_cast(options.mTileScheduler)) + + ", multiCtasKvMode=" + std::to_string(static_cast(options.mMultiCtasKvMode)) + ", headDimPerCtaV=" + + std::to_string(options.mHeadDimPerCtaV) + ", headDimQk=" + std::to_string(options.mHeadDimQk) + + ", headDimV=" + std::to_string(options.mHeadDimV) + ", tileSizeQ=" + std::to_string(options.mTileSizeQ) + + ", tileSizeKv=" + std::to_string(options.mTileSizeKv) + ", numTokensPerPage=" + + std::to_string(options.mNumTokensPerPage) + ", reuseSmemKForV=" + std::to_string(options.mReuseSmemKForV) + + ", uses2CtaMma=" + std::to_string(uses2CtaMma) + ", sparseMla=" + std::to_string(options.mIsSparseMla) + + ", skipsSoftmax=" + std::to_string(options.mSkipsSoftmaxWhenPossible); - auto const& kernelMeta = mKernelMeta[findIter->second.mMetaInfoIndex]; - const CUfunction func = findIter->second.mDeviceFunction; - // Return the kernel function and kernel meta. - return std::make_pair(func, kernelMeta); + TLLM_LOG_DEBUG("Searching for kernel traits: " + info); + return std::make_pair(hashID(static_cast(options.mQkvLayout), static_cast(options.mMaskType), + static_cast(options.mFmhaKernelType), static_cast(options.mTileScheduler), + static_cast(options.mMultiCtasKvMode), static_cast(options.mHeadDimPerCtaV), + static_cast(options.mHeadDimQk), static_cast(options.mHeadDimV), + static_cast(options.mTileSizeQ), static_cast(options.mTileSizeKv), + static_cast(options.mNumTokensPerPage), options.mReuseSmemKForV, uses2CtaMma, + options.mIsSparseMla, options.mSkipsSoftmaxWhenPossible), + info); } - void run(RunnerParams const& params) const + std::string const& getExecPath() const { - // The selectKernelParams that might be updated. - SelectKernelParams selectKernelParams{params}; - // The parameters for launching the kernel. - CtaLaunchParams ctaLaunchParams; - // The iteration index (used to detect a deadlock of selecting new kernels). - int selectKernelIter = 0; - // While loop. - while (true) + static std::string execPathStr; + if (execPathStr.empty()) { - // Any value >= 2 should work here, but we set it larger in case that we might have more complicated - // heuristic in the future. - TLLM_CHECK_WITH_INFO(selectKernelIter < 8, "A deadlock is detected when selecting trtllm-gen kernels."); - - // Select the kernel. - selectKernel(params, selectKernelParams); - // Load the kernel. - auto [func, kernelMeta] = loadKernel(params, selectKernelParams); - - // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension. - computeNumCtas(ctaLaunchParams, params, kernelMeta, selectKernelParams); - - // Need to select a new kernel if mSelectNewKernel is true. - if (selectKernelParams.mSelectNewKernel) + // Get build directory relative path from CMake macro + // This is the relative path from project root to build directory + std::string buildRelPath = "cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha"; +#ifdef TRTLLM_FMHA_BUILD_DIR + // Try to extract relative path from absolute path + // TRTLLM_FMHA_BUILD_DIR is the absolute build directory path + std::string buildAbsDir = TRTLLM_FMHA_BUILD_DIR; + // Extract relative path by finding "cpp/build" in the absolute path + size_t pos = buildAbsDir.find("cpp/build"); + if (pos != std::string::npos) { - selectKernelIter++; - continue; - } - // Prepare custom mask for spec-decoding generation kernels. - if (params.mLayerIdx == 0 && params.mIsSpecDecTree) - { - runPrepareCustomMask(kernelMeta, params, params.stream); + buildRelPath = buildAbsDir.substr(pos); } +#endif - // Prepare the kernel parameters. - auto kernelParams = KernelParams::setKernelParams( - params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv); - - // Prepare kernel parameters list for cuLaunchKernelEx. - void* kernelParamsList[] = {&kernelParams}; - CUlaunchConfig launch_config; - launch_config.blockDimX = kernelMeta.mThreadsPerCTA; - launch_config.blockDimY = 1; - launch_config.blockDimZ = 1; - launch_config.gridDimX = ctaLaunchParams.mNumCtasX; - launch_config.gridDimY = ctaLaunchParams.mNumCtasY; - launch_config.gridDimZ = ctaLaunchParams.mNumCtasZ; - launch_config.hStream = params.stream; - launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes; - - // Debug info. - TLLM_LOG_DEBUG("TRTLLM-Gen launch info: kernelName = %s", kernelMeta.mFuncName); - TLLM_LOG_DEBUG( - "TRTLLM-Gen launch info: maxSeqLenQ = %d, " - "maxSeqLenKv = %d, " - "numHeadsQ = %d, " - "numHeadsKv = %d, batchSize = %d, kernelType = %d", - params.mMaxSeqLenQ, params.mMaxSeqLenKv, params.mNumHeadsQ, params.mNumHeadsKv, params.mBatchSize, - static_cast(params.mKernelType)); - TLLM_LOG_DEBUG("TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d", - ctaLaunchParams.mNumCtasX, ctaLaunchParams.mNumCtasY, ctaLaunchParams.mNumCtasZ, - ctaLaunchParams.mClusterDimX); - - CUlaunchAttribute launch_attribute[3]; - launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION; - launch_attribute[0].value.clusterDim.x = ctaLaunchParams.mClusterDimX; - launch_attribute[0].value.clusterDim.y = 1; - launch_attribute[0].value.clusterDim.z = 1; - launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE; - launch_attribute[1].value.clusterSchedulingPolicyPreference = ctaLaunchParams.mClusterDimX > 1 - ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD - : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT; - launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION; - launch_attribute[2].value.programmaticStreamSerializationAllowed = tensorrt_llm::common::getEnvEnablePDL(); - - launch_config.attrs = launch_attribute; - launch_config.numAttrs = 3; - - // Add setting for non-portable cluster size. - if (ctaLaunchParams.mClusterDimX > 8) - { - TLLM_CU_CHECK(mDriver->cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED, - 1 // Enable non-portable cluster sizes - )); - } + // Always use pip show to find installation location at runtime + char const* cmd = "pip show tensorrt_llm 2>/dev/null"; - // Force using GmemReduction for the multiCtasKvMode if the CgaSmemReduction needs more than one wave (due - // to the cluster occupancy limit). - // TODO: find a better heuristic of using CgaSmemReduction. - if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) + // Buffer to store the output + std::array buffer; + std::string result; + // Open pipe to command +#ifdef _MSC_VER + FILE* pipe = _popen(cmd, "r"); +#else + FILE* pipe = popen(cmd, "r"); +#endif + if (pipe) { - // The maximum number of active clusters that could co-exist. - int maxActiveClusters = 1; - TLLM_CU_CHECK(mDriver->cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config)); - // Use the GmemReduction instead if it needs more than one wave. - if (maxActiveClusters * ctaLaunchParams.mClusterDimX - < (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ)) + // Read the output + while (fgets(buffer.data(), buffer.size(), pipe) != nullptr) { - selectKernelParams.mForceGmemReduction = true; - selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction; - // continue to select a new kernel. - continue; + result += buffer.data(); } - } +// Close the pipe +#ifdef _MSC_VER + _pclose(pipe); +#else + pclose(pipe); +#endif + // Parse the location using regex + // `pip show tensorrt_llm` will output something like: + // Location: /usr/local/lib/python3.12/dist-packages + // Editable project location: /code + std::regex locationRegex("(Location|Editable project location): (.+)"); + // Find all matches + auto match_begin = std::sregex_iterator(result.begin(), result.end(), locationRegex); + auto match_end = std::sregex_iterator(); + + // Get the number of matches + auto match_count = std::distance(match_begin, match_end); + + if (match_count > 0) + { + std::string location; + bool foundEditable = false; - TLLM_CU_CHECK(mDriver->cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr)); + // First, try to find "Editable project location" (preferred) + for (auto it = match_begin; it != match_end; ++it) + { + std::string matchType = it->str(1); + if (matchType == "Editable project location") + { + location = it->str(2); + foundEditable = true; + break; + } + } - // Run the separate reduction kernel if needed. - runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount, params.stream); + // If not found, use "Location" as fallback + if (!foundEditable) + { + for (auto it = match_begin; it != match_end; ++it) + { + std::string matchType = it->str(1); + if (matchType == "Location") + { + location = it->str(2); + break; + } + } + } - // Break the while op. - break; - } - } + // If still not found, use the last match as fallback + if (location.empty()) + { + TLLM_LOG_WARNING("No location found, using the last match as fallback."); + auto last_match_iter = match_begin; + std::advance(last_match_iter, match_count - 1); + location = last_match_iter->str(2); + } -private: - // Is it MLA generation kernel ? - inline bool isMlaGenKernel(RunnerParams const& params) const - { - return params.mHeadDimQk == 576 && params.mHeadDimV == 512; - } + // Trim whitespace + location.erase(location.find_last_not_of(" \n\r\t") + 1); - void computeNumCtas(CtaLaunchParams& ctaLaunchParams, RunnerParams const& params, KernelMeta const& kernelMeta, - SelectKernelParams& selectKernelParams) const - { - bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 && params.mMaxSeqLenQ <= 16 - && params.mHeadDimQk == 576 && params.mHeadDimV == 512; - // Do we need to select a new kernel ? - selectKernelParams.mSelectNewKernel = false; - - // The number of Ctas per Q sequence. - int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ; - // The generation-phase kernels might need to group both tokensQ and headsQ into one CTA. - if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) - { - // Each CTA handles one tokenQ by default for spec-decoding generation kernel. - if (!kernelMeta.mGroupsTokensHeadsQ) - { - numCtasPerSeqQ = params.mMaxSeqLenQ; + // Build the exec path: try candidate paths in order of priority. + std::vector candidatePaths; + if (foundEditable) + { + candidatePaths.push_back(std::filesystem::path(location) / buildRelPath); + } + auto fmhaIncludeSuffix + = std::filesystem::path("tensorrt_llm") / "include" / "trtllm_gen_kernels" / "fmha"; + candidatePaths.push_back(std::filesystem::path(location) / fmhaIncludeSuffix); + + bool pathFound = false; + for (auto const& candidate : candidatePaths) + { + if (std::filesystem::exists(candidate)) + { + execPathStr = (candidate / "numb").string(); + pathFound = true; + break; + } + } + TLLM_CHECK_WITH_INFO(pathFound, + "FMHA NVRTC kernel headers not found in any candidate path. " + "FMHA JIT compilation may fail. Please check the installation of TensorRT-LLM."); + } } else { - // Compute numTokensPerCtaQ where each CTA must process complete numGroupedHeadsQ. - // Note that each CTA must process complete numHeadsQPerKv. - int numTokensPerCtaQ = kernelMeta.mStepQ / params.mNumHeadsQPerKv; - // Group both headsQ and tokensQ into one CTA. - numCtasPerSeqQ = tc::divUp(params.mMaxSeqLenQ, numTokensPerCtaQ); + TLLM_LOG_WARNING("Failed to find TensorRT-LLM installation, NVRTC FMHA path will be unavailable."); } } + return execPathStr; + } - // Compute the grid dimension Y. - int numHeadsPerCta = kernelMeta.mGroupsHeadsQ ? std::min(params.mNumHeadsQPerKv, kernelMeta.mStepQ) : 1; - int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta; - TLLM_CHECK_WITH_INFO( - numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ, "The numHeadsQ/numHeadsKv is not supported."); - // Take the number of headDim CTAs. - TLLM_CHECK_WITH_INFO( - kernelMeta.mHeadDimV % selectKernelParams.mHeadDimPerCtaV == 0, "The headDimPerCtaV is not supported."); - int numCtasPerHeadDim = kernelMeta.mHeadDimV / selectKernelParams.mHeadDimPerCtaV; - // Compute the current numCtasX. - int numCtasX = numCtasPerSeqQ; - // Update the numCtasY. - int numCtasY = numCtasForAllHeadsQ * numCtasPerHeadDim; - // Compute the grid dimension Z. - int numCtasZ = params.mBatchSize; - // The 2CtaMma kernels will use 2 Ctas in the x dimension (only used by MLA generation kernels) for heads, - // so numCtasPerHeadDim and numCtasForAllHeadsQ will be handled by the 2Ctas in the x dimension. - if (isMlaGenKernel(params) && selectKernelParams.mUses2CtaMma) - { - TLLM_CHECK_WITH_INFO( - numCtasForAllHeadsQ == 2 && numCtasPerHeadDim == 2, "Internal error: numCtasPerHeadDim should be 2."); - numCtasX *= 2; - numCtasY /= (numCtasForAllHeadsQ * numCtasPerHeadDim); - } + // Prepare pointers for TMA descriptors. + static std::tuple getDevicePtrs( + TllmGenFmhaRunnerParams const& runnerParams, int32_t bitsPerElt) + { + // Declare the q, k, v ptrs. + void const *qPtr{runnerParams.qPtr}, *kPtr{runnerParams.kPtr}, *vPtr{runnerParams.vPtr}; - // First split the seqLenKv into multiple CTAs if the utilization is not full. - // The number of Ctas per KV sequence. - int numCtasPerSeqKv = 1; - // Consider the multiCtasKvMode for better GPU utilization. - if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) + // Set Q, K and V pointer from packed QKV tensor. + if (isPackedQkv(runnerParams.mQkvLayout)) { - // The maximum attention window (the maximum number of tokensKv that will be attended to). - int maxAttentionWindow{params.mMaxSeqLenKv}; - // The sparseMla only selects topK tokensKv. - if (params.mSparseMla) - { - maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK); - } - // Some of the tilesKv will be skipped if the sliding window attention or chunked attention is used. - if (isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)) - { - if (params.mMaxSeqLenKv > params.mAttentionWindowSize) - { - // Consider that the first tileKv might contain tokensKv that is out of the attention window. - maxAttentionWindow - = std::min(params.mMaxSeqLenKv, params.mAttentionWindowSize + kernelMeta.mTileSizeKv - 1); - } - else - { - maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mChunkedAttentionSize); - } - } - - // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do. - // The factor of 2 is applied here to ensure the reduction overhead does not outweigh the benefits of a - // shorter mainloop. - int const maxNumCtasPerSeqKv = (maxAttentionWindow + 2 * kernelMeta.mStepKv - 1) / (2 * kernelMeta.mStepKv); - // Compute numCtasPerSeqKv. - numCtasPerSeqKv = std::min(maxNumCtasPerSeqKv, - std::max(1, int32_t(params.mMultiProcessorCount / (numCtasX * numCtasY * numCtasZ)))); - // Update the numCtasX. - numCtasX *= numCtasPerSeqKv; - // The current total number of CTAs. - int totalNumCtas = numCtasX * numCtasZ * numCtasY; - // Disable the multiCtasKvMode if there is only one CtaKv. - if (numCtasPerSeqKv <= 1) - { - selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::Disabled; - // Enable the persistent scheduler for better performance. - selectKernelParams.mTileScheduler = TileScheduler::Persistent; - // Need to select a different kernel. - selectKernelParams.mSelectNewKernel = true; - } - else if (totalNumCtas < params.mMultiProcessorCount && isMlaGenKernel(params) && !params.mSparseMla - && selectKernelParams.mTileSizeKv == 128 && tensorrt_llm::common::getEnvUseTileSizeKv64ForTrtllmGen()) - { - // Use smaller tileSizeKv to fully utilize the SMs. - selectKernelParams.mTileSizeKv = 64; - // Need to select a different kernel. - selectKernelParams.mSelectNewKernel = true; - } - - // Enable the CgaSmemReduction if the numCtasPerSeqKv <= 16 as the maximum cluster dimension is 16. - // Only the swapsMmaAbForGeneration kernel supports the CgaSmemReduction for now. - if (!isDsv3MinLatencyMode && numCtasPerSeqKv > 1 && numCtasPerSeqKv <= 16 - && isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) - && isGmemReduction(selectKernelParams.mMultiCtasKvMode) && !selectKernelParams.mForceGmemReduction) - { - selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction; - // Need to select a different kernel. - selectKernelParams.mSelectNewKernel = true; - } - - // Add the debug info when multiCtasKvMode is enabled. - if (numCtasPerSeqKv > 1) - { - TLLM_LOG_DEBUG( - "TRTLLM-Gen launch info: multiCtasKvMode is enabled with tileSizeKv = %d, numCtasPerSeqKv = %d, " - "numCtasPerSeqQ = " - "%d, numCtasY = %d, numCtasZ = %d", - selectKernelParams.mTileSizeKv, numCtasPerSeqKv, numCtasPerSeqQ, numCtasY, numCtasZ); - } + qPtr = runnerParams.qkvPtr; + kPtr = reinterpret_cast(reinterpret_cast(runnerParams.qkvPtr) + + runnerParams.mNumHeadsQ * runnerParams.mHeadDimQk * bitsPerElt / 8 /*bits*/); + vPtr = reinterpret_cast(reinterpret_cast(runnerParams.qkvPtr) + + (runnerParams.mNumHeadsQ + runnerParams.mNumHeadsKv) * runnerParams.mHeadDimQk * bitsPerElt + / 8 /*bits*/); } - - // The cluster size in the X dimension. - int clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1; - if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) + // Set K and V pointer from pagedKv tensor. + else if (isPagedKv(runnerParams.mQkvLayout)) { - // Note 2CtaMma and CgaSmemReduction cannot be used together currently. - clusterDimX *= numCtasPerSeqKv; + // Note that the offsets will be fully handled by the pageIdx buffer. + kPtr = runnerParams.kvPtr; + vPtr = runnerParams.kvPtr; } - - // Compute the current number of CTAs in total. - int totalNumCtas = numCtasX * numCtasZ * numCtasY; - - // Then split the headDimV into multiple CTAs if there are still unused SMs. - if (isMlaGenKernel(params) && !selectKernelParams.mReuseSmemKForV && !selectKernelParams.mSelectNewKernel - && !selectKernelParams.mUses2CtaMma) + // Set K and V pointer from contiguousQAnddKv tensor. + else if (isContiguousKv(runnerParams.mQkvLayout)) { - // Split the headDimV into multiple CTAs if the utilization is not full. - // It doesn't work with reuseSmemKForV currently. - // TODO: find better heuristic of splitting headDimV across multiple CTAs. - - int corrFactor = isDsv3MinLatencyMode ? 1 : 2; - if (selectKernelParams.mHeadDimPerCtaV == 512 && totalNumCtas * corrFactor <= params.mMultiProcessorCount) - { - // Use smaller headDimPerCtaV to fully utilize the SMs. - selectKernelParams.mHeadDimPerCtaV - = totalNumCtas * 2 * corrFactor <= params.mMultiProcessorCount ? 128 : 256; - // Need to select a different kernel. - selectKernelParams.mSelectNewKernel = true; - } + kPtr = runnerParams.kvPtr; + // The maximum headDim of K and V. + // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv. + int32_t const maxHeadDimKv{std::max(runnerParams.mHeadDimQk, runnerParams.mHeadDimV)}; + vPtr = reinterpret_cast(reinterpret_cast(runnerParams.kvPtr) + + runnerParams.mNumHeadsKv * runnerParams.mMaxSeqLenCacheKv * maxHeadDimKv * bitsPerElt / 8 /*bits*/); } - // Update the parameters for launching the kernel. - ctaLaunchParams.mMaxNumCtasQ = numCtasPerSeqQ; - ctaLaunchParams.mMaxNumCtasKv = numCtasPerSeqKv; - ctaLaunchParams.mNumCtasX = numCtasX; - ctaLaunchParams.mNumCtasY = numCtasY; - ctaLaunchParams.mNumCtasZ = numCtasZ; - ctaLaunchParams.mClusterDimX = clusterDimX; + // Return the pointers. + return std::make_tuple(qPtr, kPtr, vPtr); } - // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation. - bool useSwapsMmaAbMlaGenKernel(RunnerParams const& params) const + void setFmhaData(RunnerParams const& params, FmhaOptions const& options, FmhaData& fmhaData) const { - // Use the SwapsMmaAbForGeneration kernel for MLA generation when the following conditions are met: - // 1. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned later). - // 2. The numCtas (after splitting the heads across multiple CTAs) <= params.mMultiProcessorCount. - - // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do. - // Here we assume the stepKv is 256. - int const maxNumCtasPerSeqKv = (params.mMaxSeqLenKv + 256 - 1) / 256; - // The number of Ctas. - int const numCtas - = static_cast(params.mBatchSize * params.mMaxSeqLenQ * tc::divUp(params.mNumHeadsQPerKv, 16)); - if (numCtas == 0) - { - return false; - } - // Compute numCtasPerSeqKv. - int const numCtasPerSeqKv - = std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas))); - // Compute the seqLenPerCtaKv. - int const seqLenPerCtaKv = (params.mMaxSeqLenKv + numCtasPerSeqKv - 1) / numCtasPerSeqKv; - // Whether we should use the SwapsMmaAbForGeneration kernel for MLA generation. - return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount; + // Fill MetaData + fmhaData.mMetaData.cumSeqLensQPtrD = params.cumSeqLensQPtr; + fmhaData.mMetaData.cumSeqLensKvPtrD = params.cumSeqLensKvPtr; + fmhaData.mMetaData.seqLensKvD = params.seqLensKvPtr; + fmhaData.mMetaData.firstSparseMaskOffsetsKvPtrD = params.firstSparseMaskOffsetsKvPtr; + fmhaData.mMetaData.kvPageIdxD = params.kvPageIdxPtr; + fmhaData.mMetaData.inflateMax = 0.0F; // Default value for inflate max + fmhaData.mMetaData.startTokenIdxSfO = params.mSfStartTokenIdx; + + // Fill Scales + fmhaData.mScales.kSfBasePtr = params.kvSfPtr; + fmhaData.mScales.vSfBasePtr = params.kvSfPtr; + fmhaData.mScales.scaleSoftmaxLog2D = params.scaleSoftmaxLog2Ptr; + fmhaData.mScales.outputScaleD = params.outputScalePtr; + fmhaData.mScales.kvSfScaleD = params.kvSfScalePtr; + fmhaData.mScales.oSfScaleD = params.oSfScalePtr; + // Sage Attention scaling factors (set to nullptr if not available) + fmhaData.mScales.sageAttnSfsQPtrD = nullptr; + fmhaData.mScales.sageAttnSfsKPtrD = nullptr; + fmhaData.mScales.sageAttnSfsPPtrD = nullptr; + fmhaData.mScales.sageAttnSfsVPtrD = nullptr; + // Host-side scale values (from params) + TLLM_CHECK_WITH_INFO(params.mScaleQ != 0.f, "mScaleQ must not be zero (used as divisor in softmaxScale)."); + fmhaData.mScales.softmaxScale + = (1.f / (std::sqrt(static_cast(params.mHeadDimQk)) * params.mScaleQ)) * M_LOG2E; + + fmhaData.mScales.kvSfScale = 1.f; // Default value; per-token scale from kvSfScaleD when set + fmhaData.mScales.oSfScale = 1.f; // Default value; per-token scale from oSfScaleD (e2m1/NVFP4 O) when set + fmhaData.mScales.oSfPtrD = params.oSfPtr; + + // Get qkv pointers. + auto [qPtr, kPtr, vPtr] = getDevicePtrs(params, tg::dtypeGetNumBits(options.mDtypeKv)); + // Fill InputBuffers + fmhaData.mInputBuffers.qBasePtr = qPtr; + fmhaData.mInputBuffers.kBasePtr = kPtr; + fmhaData.mInputBuffers.vBasePtr = vPtr; + fmhaData.mInputBuffers.attentionSinksPtrD = params.attentionSinksPtr; + fmhaData.mInputBuffers.customMaskPtrD = params.customMaskPtr; + fmhaData.mInputBuffers.customMaskOffsetsPtrD = params.customMaskOffsetsPtr; + + // Fill OutputBuffers + fmhaData.mOutputBuffers.oPtrD = params.oPtr; + fmhaData.mOutputBuffers.multiCtasKvCounterPtrD = params.multiCtasKvCounterPtr; + // Split multiCtasKvScratchPtr into partialStats and partialO + // Note: The split calculation is done in setKernelParams with kernelMeta.mStepQ + // For FmhaData, we store the base pointer and let the kernel params handle the split + fmhaData.mOutputBuffers.partialStatsPtrD = reinterpret_cast(params.multiCtasKvScratchPtr); + // The partial buffers' pointers when the multiCtasKv mode is enabled. + int64_t partialStatsBufferSize = params.mMultiProcessorCount * options.mTileSizeQ * options.mNumInstsQ; + // partialO comes after partialStats, but exact offset depends on kernelMeta + // This will be properly set in setKernelParams + fmhaData.mOutputBuffers.partialOPtrD = fmhaData.mOutputBuffers.partialStatsPtrD + partialStatsBufferSize; + fmhaData.mOutputBuffers.skipSoftmaxStatsPtrD = nullptr; // Not available in params (would need to be added) + fmhaData.mOutputBuffers.softmaxStatsD = params.softmaxStatsPtr; + fmhaData.mOutputBuffers.oDebugPtrD = nullptr; // Debug output not supported in TensorRT-LLM + + // Print all primitive type variables in FmhaData for debugging } - // Selects a heuristic kernel for MLA generation. - void selectMlaGenerationKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const + //////////////////////////////////////////////////////////////////////////////////////////////////// + // Convert Data_type to trtllm::gen::Dtype + //////////////////////////////////////////////////////////////////////////////////////////////////// + + tg::Dtype dataTypeToDtype(Data_type dataType) const { - // We use the low-latency kernel (SwapsMmaAbForGeneration with tileSizeQ = 16) when any of the following - // conditions are met: - // 1. The number of headsQPerKv is <= 32. - // 2. The number of headsQPerKv is < 128 for sparseMla. - // 3. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned later) and - // the numCtas (after splitting the heads across multiple CTAs) <= params.mMultiProcessorCount. - // The sparseMla kernel will always use the 2CTA high-throughput kernel. - - // The kernel type. - FmhaKernelType& kernelType = selectKernelParams.mKernelType; - // The tile size for Q. - int& tileSizeQ = selectKernelParams.mTileSizeQ; - - // Check the conditions. - if (params.mNumHeadsQPerKv <= 32 || (params.mSparseMla && params.mNumHeadsQPerKv < 128) - || useSwapsMmaAbMlaGenKernel(params)) + switch (dataType) { - kernelType = FmhaKernelType::SwapsMmaAbForGeneration; - // Currently, only tileSizeQ = 8 or 16 are supported. - tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16; - } - else - { - // Otherwise, we use the high-throughput kernel. - kernelType = FmhaKernelType::KeepsMmaAbForGeneration; - // Use the tileSizeQ = 64 for MLA high-throughput generation kernels. - tileSizeQ = 64; - // Always use the separate reduction kernel. - if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) - { - selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel; - } - // The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128. - TLLM_CHECK_WITH_INFO(!params.mSparseMla || params.mNumHeadsQPerKv == 128, - "The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128, got %d", - params.mNumHeadsQPerKv); - // The 2CTA keepsMmaAbForGeneration kernel is used when the numHeadsQPerKv is 128. - if (params.mNumHeadsQPerKv == 128) - { - selectKernelParams.mUses2CtaMma = true; - // Each Cta only handles 256 headDimV. - selectKernelParams.mHeadDimPerCtaV = 256; - } + case DATA_TYPE_BOOL: return tg::Dtype::Bool; + case DATA_TYPE_FP16: return tg::Dtype::Fp16; + case DATA_TYPE_FP32: return tg::Dtype::Fp32; + case DATA_TYPE_INT4: + // Note: DATA_TYPE_INT4 could map to MxInt4 (block format) + // Adjust based on your use case + return tg::Dtype::MxInt4; + case DATA_TYPE_INT8: return tg::Dtype::Int8; + case DATA_TYPE_INT32: return tg::Dtype::Int32; + case DATA_TYPE_BF16: return tg::Dtype::Bfloat16; + case DATA_TYPE_E2M1: return tg::Dtype::E2m1; + case DATA_TYPE_E4M3: return tg::Dtype::E4m3; + case DATA_TYPE_E5M2: return tg::Dtype::E5m2; + default: + // Fallback or throw error + return tg::Dtype::Void; } } - // Selects a heuristic tileSizeQ if groupsTokensHeadsQ is true. - void selectTileSizeQForGqaGeneration(RunnerParams const& params, SelectKernelParams& selectKernelParams) const + void parseOptionsFromRunnerParams(RunnerParams const& params, FmhaOptions& options) const { - - // Define the per-tile mainloop cost model for different tileSizeQ choices. - std::unordered_map kernelMainloopCost = { - {128, 2.2}, // Cost factor when tileSizeQ = 128 - {64, 1.68}, // Cost factor when tileSizeQ = 64 - {32, 1.48}, // Cost factor when tileSizeQ = 32 - {16, 1.2}, // Cost factor when tileSizeQ = 16 - {8, 1.0} // Cost factor when tileSizeQ = 8 - }; - - // Define the per-tile reduction cost model for different tileSizeQ choices. - std::unordered_map kernelReductionCost = { - {128, 1.32}, // Reduction cost factor when tileSizeQ = 128 - {64, 1.2}, // Reduction cost factor when tileSizeQ = 64 - {32, 1.08}, // Reduction cost factor when tileSizeQ = 32 - {16, 1.03}, // Reduction cost factor when tileSizeQ = 16 - {8, 1.0} // Reduction cost factor when tileSizeQ = 8 - }; - - // The reduction cost emulated as a sequence length factor. - float const kernelReductionSeqLenFactor = 128.0f; - - // The parameters for launching the kernel. - CtaLaunchParams ctaLaunchParams; - // The copy of the selectKernelParams, which makes sure it won't modify the original selectKernelParams when - // computing the number of CTAs. - SelectKernelParams selectKernelParamsCopy = selectKernelParams; - // Load the kernel. - auto [func, kernelMeta] = loadKernel(params, selectKernelParamsCopy); - // Compute numCtasX, numCtasY and numCtasZ. - computeNumCtas(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy); - - // If there are no free SMs or tileSizeQ is already the smallest one, skip the heuristic selection. - if (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ * 2 - > params.mMultiProcessorCount - || selectKernelParamsCopy.mTileSizeQ <= 8) + // Basic dimensions + options.mBatchSize = params.mBatchSize; + options.mMaxSeqLenQ = params.mMaxSeqLenQ; + options.mMinSeqLenQ = params.mMaxSeqLenQ; + // For context self-attention without prior KV cache, TRT-LLM passes + // mMaxSeqLenKv=0. trtllm-gen requires mMaxSeqLenKv>0, so use mMaxSeqLenQ + // as the effective KV length (Q produces KV of equal length). + options.mMaxSeqLenKv = (isContextKernel(params.mKernelType) && params.mMaxSeqLenKv == 0) ? params.mMaxSeqLenQ + : params.mMaxSeqLenKv; + options.mMinSeqLenKv = options.mMaxSeqLenKv; + + // Variable sequence length support + options.mSumOfSeqLensQ = params.mSumOfSeqLensQ; + options.mSumOfSeqLensKv = params.mSumOfSeqLensKv; + + // Head configuration + options.mNumHeadsQ = params.mNumHeadsQ; + options.mNumHeadsKv = params.mNumHeadsKv; + options.mNumHeadsQPerKv = params.mNumHeadsQPerKv; + options.mHeadDimQk = params.mHeadDimQk; + options.mHeadDimV = params.mHeadDimV; + + // Layout and mask configuration + options.mQkvLayout = params.mQkvLayout; + options.mMaskType = params.mMaskType; + options.mFmhaKernelType = params.mKernelType; + options.mTileScheduler = params.mTileScheduler; + + // Multi-CTA KV mode (bool -> enum conversion) + options.mMultiCtasKvMode = params.mMultiCtasKvMode ? tensorrt_llm::kernels::MultiCtasKvMode::GmemReduction + : tensorrt_llm::kernels::MultiCtasKvMode::Disabled; + options.mStoresSoftmaxStats = true; + + // Attention features + options.mUseBlockSparseAttention = params.mUseBlockSparseAttention; + options.mAttentionWindowSize = params.mAttentionWindowSize; + options.mChunkedAttentionSize = params.mChunkedAttentionSize == INT_MAX ? 0 : params.mChunkedAttentionSize; + + // Sparse MLA + options.mIsSparseMla = params.mSparseMla; + options.mSparseMlaTopK = params.mSparseMlaTopK; + + // Softmax optimization + options.mSkipSoftmaxThresholdScaleFactor = params.mSkipSoftmaxThresholdScaleFactor; + options.mSkipsSoftmaxWhenPossible = params.mSkipSoftmaxThresholdScaleFactor != 0.0f; + + // Paged KV cache + options.mMaxNumPagesPerSeqKv = params.mMaxNumPagesPerSeqKv; + options.mNumTokensPerPage = params.mNumTokensPerPage; + options.mNumPagesInMemPool = params.mNumPagesInMemPool; + + options.mEnablesAutoTuner = true; + options.mIsMlaGen = isMlaGenKernel(params); + options.mDtypeQ = dataTypeToDtype(mDtypeQ); + options.mDtypeKv = dataTypeToDtype(mDtypeKv); + options.mDtypeOut = dataTypeToDtype(mDtypeOut); + options.mSupportsVarSeqLens = true; + if (options.mQkvLayout != QkvLayout::PackedQkv) { - // No need to select the kernel further. - return; + options.mSupportsDiffSeqLensForQAndKv = true; } - // Candidate tile sizes for tileSizeQ to explore. - int const candidateTileSizesQ[] = {128, 64, 32, 16, 8}; + // Enables the optimization to skip the correction step when possible. + options.mSkipsCorrWhenPossible = true; - // The default tileSizeQ. - int defaultTileSizeQ = selectKernelParamsCopy.mTileSizeQ; - // The selected tileSizeQ. - int selectedTileSizeQ = selectKernelParamsCopy.mTileSizeQ; + // Enables interleaveSfV by default. + options.mInterleaveSfV = true; - // The minimum modeling kernel time. - float globalModelingKernelTime = FLT_MAX; - // Loop over each candidate tile size. - for (int tileSizeQ : candidateTileSizesQ) - { - // Only consider candidates <= default tileSizeQ. - if (tileSizeQ > defaultTileSizeQ) - { - continue; - } - // If tileSizeQ < mNumHeadsQPerKv, this will result in 0, causing division by zero. - if (tileSizeQ < params.mNumHeadsQPerKv) - { - continue; - } + // Enables PDL if specified. + options.mEnablesPdl = tensorrt_llm::common::getEnvEnablePDL(); - // Update the tileSizeQ. - selectKernelParamsCopy.mTileSizeQ = tileSizeQ; - if (tileSizeQ >= 64) - { - selectKernelParamsCopy.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration; - } - else - { - selectKernelParamsCopy.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration; - } - // Load the kernel. - std::tie(func, kernelMeta) = loadKernel(params, selectKernelParamsCopy); - - // Compute the number of CTAs. - computeNumCtas(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy); - - // Compute the seqLenPerCtaKv. - int32_t seqLenPerCtaKv - = tc::divUp(tc::divUp(params.mMaxSeqLenKv, kernelMeta.mStepKv), ctaLaunchParams.mMaxNumCtasKv) - * kernelMeta.mStepKv; - - // Compute the modeling kernel time = mainloop cost + reduction cost. - float modelingKernelTime = kernelMainloopCost[tileSizeQ] * seqLenPerCtaKv - + kernelReductionCost[tileSizeQ] * kernelReductionSeqLenFactor * ctaLaunchParams.mMaxNumCtasKv; - - // Compute the total number of CTAs. - int32_t numCtas = ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ; - // Compute the number of waves. - int32_t numWaves = tc::divUp(numCtas, params.mMultiProcessorCount); - // Compute the total modeling kernel time. - modelingKernelTime *= numWaves; - - // If this candidate has a lower time than the global minimum, update the global minimum. - if (modelingKernelTime < globalModelingKernelTime) - { - globalModelingKernelTime = modelingKernelTime; - selectedTileSizeQ = tileSizeQ; - } - } + // spec-decoding + bool isContext = params.mKernelType == FmhaKernelType::Context; + options.mIsCustomSpecDecodingGen = !isContext && params.mMaxSeqLenQ > 1 && params.mIsSpecDecTree; + options.mIsCausalSpecDecodingGen = !isContext && params.mMaxSeqLenQ > 1 && !params.mIsSpecDecTree; + options.mNumSpecDecodingTokens = !isContext && params.mMaxSeqLenQ > 1 ? params.mMaxSeqLenQ : 0; - // Update the tileSizeQ. - selectKernelParams.mTileSizeQ = selectedTileSizeQ; - // Update the kernel type. - if (selectKernelParams.mTileSizeQ >= 64) - { - selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration; - } - else - { - selectKernelParams.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration; - } + options.mIsTrtllmLayout = true; } - // Selects a heuristic kernel for GQA generation. - void selectGqGenerationKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const + void populateJsonConfig(FmhaOptions const& options, std::ostringstream& sstream) const { - - // The kernel type. - FmhaKernelType& kernelType = selectKernelParams.mKernelType; - // The tile size for Q. - int& tileSizeQ = selectKernelParams.mTileSizeQ; - - // Check the conditions. - if (params.mIsSpecDecTree) + sstream << "{\n"; + sstream << "\"clusterDimX\": " << options.mClusterDimX << ",\n"; + // The 2CTA UTCMMA is used by default if the clusterDimX is set to 2. + if (options.mClusterDimX == 2) { - - bool isSupported = params.mNumHeadsQPerKv <= 16 && (params.mHeadDimQk == 64 || params.mHeadDimQk == 128); - if (isSupported) - { - kernelType = FmhaKernelType::KeepsMmaAbForGeneration; - // Only support tileSizeQ = 128 for tree-based speculative decoding. - tileSizeQ = 128; - } - else - { - TLLM_LOG_ERROR( - "Tree-based speculative decoding is not supported with numHeadsQPerKv = %d and headDimQk = %d " - "by TRTLLM-GEN", - params.mNumHeadsQPerKv, params.mHeadDimQk); - } - - // No need to select the kernel further. - return; + sstream << "\"usesTwoCtasForMma\": true,\n"; } - - // Mixed precision kernels don't work with groupsTokensHeadsQ = true for now. - if (mDtypeQ != mDtypeKv) + // Use dynamic cluster dimensions if the CGA reduction is used. + if (isCgaSmemReduction(options.mMultiCtasKvMode)) { - tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16; - kernelType = FmhaKernelType::SwapsMmaAbForGeneration; - return; + sstream << "\"usesDynamicClusterDims\": true,\n"; } - // The number of tokensQ and headsQ that can be grouped into one CTA. - int numTokensHeadsQ = params.mNumHeadsQPerKv * params.mMaxSeqLenQ; - // When numHeadsQPerKv >= 64, use KeepsMmaAbForGeneration kernel. - if (numTokensHeadsQ <= 8) - { - tileSizeQ = 8; - kernelType = FmhaKernelType::SwapsMmaAbForGeneration; - } - else if (numTokensHeadsQ <= 16) - { - tileSizeQ = 16; - kernelType = FmhaKernelType::SwapsMmaAbForGeneration; - } - else if (numTokensHeadsQ <= 32) + // Disable checksTaskSchedules as there are multiple acquire/commit, wait/release steps in one + // loop. And the number of loops are not the same in different tasks. + sstream << "\"checksTaskSchedules\": false,\n"; + + if (options.mIsExportingCubin) { - tileSizeQ = 32; - kernelType = FmhaKernelType::SwapsMmaAbForGeneration; + sstream << "\"compileDefs\": [\"-DTLLM_EXPORT_CUBIN\"],\n"; } - else if (numTokensHeadsQ <= 64) + + // Set compile flags for E2M1 KV kernel benchmark. + // NOTE(tizheng): This is to be removed after compiler fixes PTX exposure of QMUL4. See Fp4Utils.h for details. + if (options.mChecksResults == 0 && options.mDtypeKv == tg::Dtype::E2m1) { - tileSizeQ = 64; - kernelType = FmhaKernelType::KeepsMmaAbForGeneration; + TLLM_LOG_INFO("Forcing -DTLLM_BENCHMARK_E2M1_KV_CACHE for E2m1 Kv. The results are not correct."); + sstream << "\"compileDefs\": [\"-DTLLM_BENCHMARK_E2M1_KV_CACHE\"],\n"; } - else + + // Enable programmatic dependent launch. + sstream << "\"enablesPdl\": " << ((options.mEnablesPdl) ? "true" : "false") << ",\n"; + + // Postpone the waitsForPrimaryGrid to loading smemQ/smemKv in order to hide the latency as much as possible. + // This avoids adding the cudaGridDependencySynchronize in the very beginning of the kernel. + sstream << "\"gridWaitForPrimaryEarlyExit\": false,\n"; + + // This forces the schedule to be printed and for the generator to look for deadlocks. It may + // detect false-positive. If that's the case, disable that feature. + sstream << "\"printsFullSchedule\": false,\n"; + + sstream << "\"skipsKernelGen\": " << ((options.mSkipsKernelGen) ? "true" : "false") << ",\n"; + sstream << "\"smVersion\": \"" << tg::cudaArchToString(options.mCudaArch) << "\",\n"; + + // Loads scales from gmem when it is quantized. + if (options.mDtypeQ == tg::Dtype::E4m3 || options.mDtypeKv == tg::Dtype::E4m3 + || options.mDtypeOut == tg::Dtype::E4m3 || options.mDtypeQ == tg::Dtype::E2m1 + || options.mDtypeKv == tg::Dtype::E2m1 || options.mDtypeOut == tg::Dtype::E2m1) { - tileSizeQ = 128; - kernelType = FmhaKernelType::KeepsMmaAbForGeneration; + sstream << "\"loadsScalesFromGmem\": true,\n"; } - // When maxSeqLenQ > 1, use an experimental kernel-timing model to select the best kernel that groups both - // tokensQ and headsQ into one CTA. - if (params.mMaxSeqLenQ > 1) + // The code uses CUDA PTX. + sstream << "\"usesCudaPtx\": true,\n"; + + if (options.mTileScheduler == TileScheduler::Persistent) { - selectTileSizeQForGqaGeneration(params, selectKernelParams); + sstream << "\"skipsFirstProdAcquiresLastConsReleases\": false,\n"; } + // Reduce the number of anti-dependencies in the generated code. + // See https://nvbugs/4940327 + // WARNING: Increase this might lead to more register usage and even spills. Please finetune it carefully. + sstream << "\"antiDepWeight\": 25,\n"; + + sstream << "\"usesNvRtc\": " + << "true" + << ",\n"; + sstream << "\"usesTma\": true\n"; + sstream << "}\n"; } - // Select a kernel based on the heuristic. - void selectKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const + void launchFmhaKernel(KernelParams const& kernelParams, KernelMeta const& kernelMeta, CUfunction const& func, + tg::CudaRunner::Grid const& grid, FmhaOptions const& options, CUstream stream) const { - - // Select the kernel based on the kernel type. - if (isGenerationKernel(params.mKernelType) && isMlaGenKernel(params)) - { - selectMlaGenerationKernel(params, selectKernelParams); - } - else if (isGenerationKernel(params.mKernelType)) + int launchedClusterDimX = options.mClusterDimX; + if (isCgaSmemReduction(options.mMultiCtasKvMode)) { - selectGqGenerationKernel(params, selectKernelParams); + launchedClusterDimX *= options.mMaxNumCtasKv; } - // Enable sliding window or chunked causal if the max kv sequence length exceeds attention window size or - // chunked attention size. - // This is supported by causal-mask context kernels and generation-phase kernels. - if ((selectKernelParams.mMaskType == TrtllmGenAttentionMaskType::Causal || !isContextKernel(params.mKernelType)) - && (params.mMaxSeqLenKv > params.mAttentionWindowSize || params.mChunkedAttentionSize != INT_MAX)) - { - TLLM_CHECK_WITH_INFO(params.mMaxSeqLenKv <= params.mAttentionWindowSize - || params.mMaxSeqLenKv <= params.mChunkedAttentionSize, - "Sliding window attention and chunked attention should not be used together"); - selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal; - } + // Prepare kernel parameters list for cuLaunchKernelEx. + void* kernelParamsList[] = {const_cast(static_cast(&kernelParams))}; + CUlaunchConfig launch_config; + launch_config.blockDimX = kernelMeta.mThreadsPerCTA; + launch_config.blockDimY = 1; + launch_config.blockDimZ = 1; + launch_config.gridDimX = grid[0]; + launch_config.gridDimY = grid[1]; + launch_config.gridDimZ = grid[2]; + launch_config.hStream = stream; + launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes; - // SparseMla kernels use a fixed numTokensPerPage = 1. - if (params.mSparseMla) - { - selectKernelParams.mNumTokensPerPage = 1; - } - else if (!isPagedKv(params.mQkvLayout)) + // Debug info. + TLLM_LOG_DEBUG("TRTLLM-Gen launch info: kernelName = %s", kernelMeta.mFuncName); + TLLM_LOG_DEBUG( + "TRTLLM-Gen launch info: maxSeqLenQ = %d, " + "maxSeqLenKv = %d, " + "numHeadsQ = %d, " + "numHeadsKv = %d, batchSize = %d, kernelType = %d", + options.mMaxSeqLenQ, options.mMaxSeqLenKv, options.mNumHeadsQ, options.mNumHeadsKv, options.mBatchSize, + static_cast(options.mFmhaKernelType)); + TLLM_LOG_DEBUG("TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d", + launch_config.gridDimX, launch_config.gridDimY, launch_config.gridDimZ, launchedClusterDimX); + + CUlaunchAttribute launch_attribute[3]; + launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION; + launch_attribute[0].value.clusterDim.x = launchedClusterDimX; + launch_attribute[0].value.clusterDim.y = 1; + launch_attribute[0].value.clusterDim.z = 1; + launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE; + launch_attribute[1].value.clusterSchedulingPolicyPreference + = launchedClusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT; + launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION; + launch_attribute[2].value.programmaticStreamSerializationAllowed = tensorrt_llm::common::getEnvEnablePDL(); + + launch_config.attrs = launch_attribute; + launch_config.numAttrs = 3; + + // Add setting for non-portable cluster size. + if (launchedClusterDimX > 8) { - // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels. - selectKernelParams.mNumTokensPerPage = 0; + TLLM_CU_CHECK(mDriver->cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED, + 1 // Enable non-portable cluster sizes + )); } + + TLLM_CU_CHECK(mDriver->cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr)); } std::pair hashFromRunnerParams( @@ -882,6 +937,38 @@ class TllmGenFmhaKernel info); } + tg::CudaArch intToCudaArch(int smVersion) const + { + switch (smVersion) + { + case 90: return tg::CudaArch::Sm90a; + case 100: return tg::CudaArch::Sm100a; + case 103: return tg::CudaArch::Sm103a; + default: assert(false && "Unsupported CUDA architecture"); return tg::CudaArch::Sm100a; + } + } + + int cudaArchToInt(tg::CudaArch cudaArch) const + { + switch (cudaArch) + { + case tg::CudaArch::Sm90a: return 90; + case tg::CudaArch::Sm100a: return 100; + case tg::CudaArch::Sm100f: return 100; + case tg::CudaArch::Sm103a: return 103; + default: assert(false && "Unsupported CUDA architecture"); return 100; + } + } + + // Is it MLA generation kernel ? + inline bool isMlaGenKernel(RunnerParams const& params) const + { + return params.mHeadDimQk == 576 && params.mHeadDimV == 512; + } + + // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension. + using CtaInfo = std::tuple; + Data_type mDtypeQ, mDtypeKv, mDtypeOut; std::shared_ptr mDriver; KernelMeta const* mKernelMeta; @@ -896,6 +983,8 @@ class TllmGenFmhaKernel }; std::unordered_map mFunctions; + + FmhaInterface mFmhaInterface{false, 1}; }; //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -905,8 +994,8 @@ class TllmFmhaKernelFactory public: using KernelType = TllmGenFmhaKernel; - KernelType const* getKernels(const typename KernelType::KernelMeta* pKernelList, unsigned int nbKernels, - Data_type dtypeQ, Data_type dtypeKv, Data_type dtypeOut, unsigned int sm) + KernelType* getKernels(const typename KernelType::KernelMeta* pKernelList, unsigned int nbKernels, Data_type dtypeQ, + Data_type dtypeKv, Data_type dtypeOut, unsigned int sm) { static std::mutex s_mutex; std::lock_guard lg(s_mutex); @@ -947,8 +1036,7 @@ class TllmFmhaKernelFactory std::unordered_map> mKernels; }; -inline TllmGenFmhaKernel const* getTllmFmhaKernels( - Data_type dtypeQ, Data_type dtypeKv, Data_type dtypeOut, unsigned int sm) +inline TllmGenFmhaKernel* getTllmFmhaKernels(Data_type dtypeQ, Data_type dtypeKv, Data_type dtypeOut, unsigned int sm) { #ifndef EXCLUDE_SM_100F diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.cu b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.cu index 1a0cca54dab9..96080ef7c7ba 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.cu +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.cu @@ -15,6 +15,7 @@ */ #include "fmhaReduction.h" +#include "fmhaRunnerParams.h" #include "kernelUtils.h" #include "tensorrt_llm/common/config.h" #include "tensorrt_llm/common/envUtils.h" @@ -32,8 +33,8 @@ namespace kernels template -__global__ void __launch_bounds__(NumThreadsPerCta, 2) fmhaReductionKernel(KernelParams const params, bool sparseMla, - int32_t numCtasForReduction, int32_t numCtasForAllHeads, int32_t numHeadDimCtasV) +__global__ void __launch_bounds__(NumThreadsPerCta, 2) fmhaReductionKernel(fmha::KernelParams const params, + bool sparseMla, int32_t numCtasForReduction, int32_t numCtasForAllHeads, int32_t numHeadDimCtasV) { // clang-format off @@ -310,7 +311,7 @@ __global__ void __launch_bounds__(NumThreadsPerCta, 2) fmhaReductionKernel(Kerne //////////////////////////////////////////////////////////////////////////////////////////////////// -void runFmhaReduction(TllmGenFmhaKernelMetaInfo const& kernelMeta, KernelParams const& params, +void runFmhaReduction(TllmGenFmhaKernelMetaInfo const& kernelMeta, fmha::KernelParams const& params, int32_t multiProcessorCount, cudaStream_t stream) { @@ -372,7 +373,7 @@ void runFmhaReduction(TllmGenFmhaKernelMetaInfo const& kernelMeta, KernelParams config.numAttrs = 1; // Select the kernel function pointer. - void (*kernel)(KernelParams const, bool, int32_t, int32_t, int32_t) = nullptr; + void (*kernel)(fmha::KernelParams const, bool, int32_t, int32_t, int32_t) = nullptr; if (headDimPerCtaV == 128) { SELECT_FMHA_REDUCTION_KERNEL(128); diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.h index c717e333c680..f829c6d2db26 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.h +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaReduction.h @@ -17,9 +17,8 @@ #pragma once #include "cubin/kernelMetaInfo.h" -#include "fmhaRunnerParams.h" -#include "kernelParams.h" #include "tensorrt_llm/common/config.h" +#include "trtllmGen_fmha_export/KernelParamsDecl.h" TRTLLM_NAMESPACE_BEGIN @@ -28,7 +27,7 @@ namespace kernels //////////////////////////////////////////////////////////////////////////////////////////////////// -void runFmhaReduction(TllmGenFmhaKernelMetaInfo const& kernelMeta, KernelParams const& params, +void runFmhaReduction(TllmGenFmhaKernelMetaInfo const& kernelMeta, fmha::KernelParams const& params, int32_t multiProcessorCount, cudaStream_t stream); //////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunner.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunner.h index b42a61a81868..8431bd4bbb7f 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunner.h +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunner.h @@ -56,7 +56,7 @@ class TllmGenFmhaRunner // The total device memory. size_t mTotalDeviceMemory; // The class that stores all the kernels. - TllmGenFmhaKernel const* mKernel; + TllmGenFmhaKernel* mKernel; }; } // namespace kernels diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h index 0d5d386bef00..d286eab8df49 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h @@ -71,8 +71,6 @@ enum class FmhaKernelType SwapsMmaAbForGeneration, // Keep tensor A and tensor B of Mma. KeepsMmaAbForGeneration, - // Speculative decoding (Medusa and Eagle) generation-phase attention kernels, where seqLenQ > 1. - SpecDecodingGeneration }; //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -89,9 +87,8 @@ FMHA_KERNEL_TYPE_FUNCTION(Context) FMHA_KERNEL_TYPE_FUNCTION(Generation) FMHA_KERNEL_TYPE_FUNCTION(SwapsMmaAbForGeneration) FMHA_KERNEL_TYPE_FUNCTION(KeepsMmaAbForGeneration) -FMHA_KERNEL_TYPE_FUNCTION(SpecDecodingGeneration) -#undef QKV_LAYOUT_FUNCTION +#undef FMHA_KERNEL_TYPE_FUNCTION //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -244,7 +241,7 @@ struct TllmGenFmhaRunnerParams // The output scaling factor buffer. void* oSfPtr; // The sequence lengths for Q. - int const* seqlensQPtr; + int const* seqLensQPtr; // Head dimension for Q and K. int mHeadDimQk; diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/kernelParams.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/kernelParams.h deleted file mode 100644 index 9c380f175371..000000000000 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/kernelParams.h +++ /dev/null @@ -1,920 +0,0 @@ -/* - * Copyright (c) 2020-2024, NVIDIA CORPORATION. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#pragma once - -#ifdef _WIN32 -#define _USE_MATH_DEFINES -#include -#endif - -#include -#include -#include - -#include "tensorrt_llm/common/assert.h" -#include "tensorrt_llm/common/config.h" -#include "tensorrt_llm/common/cudaUtils.h" -#include "tensorrt_llm/kernels/multiHeadAttentionCommon.h" - -#include "fmhaRunnerParams.h" - -TRTLLM_NAMESPACE_BEGIN - -namespace kernels -{ - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// -// CCCL >= 3.1.0 (CUDA CTK 13.1) introduces the fast_mod_div math operations. -// The following code makes sure that the host initialization works with older CUDA CTK versions. -// - -// Refer to https://github.com/NVIDIA/cccl/blob/main/libcudacxx/include/cuda/__cmath/fast_modulo_division.h#L76-L81 -// about how to compute the fast modulo division. -struct FastModDivInt32 -{ -public: - FastModDivInt32(int32_t divisor) - : mDivisor(divisor) - { - // Explicitly initialize the unused member variable to avoid compiler warnings. - mAdd = 0; - mShift = std::max(0, ceilLog2(mDivisor) - 1); - mMultiplier = static_cast(ceilDiv(uint64_t(1) << (32 + mShift), static_cast(mDivisor))); - } - -private: - template - T ceilDiv(T a, T b) - { - return (a + b - 1) / b; - } - - int32_t ceilLog2(int32_t value) const - { - return static_cast(std::ceil(std::log2(value))); - } - -private: - int32_t mDivisor = 1; - uint32_t mMultiplier = 0; - uint32_t mAdd = 0; - int32_t mShift = 0; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -struct KernelParams -{ - // TMA descriptor for Q. - CUtensorMap tmaQ_; - // TMA descriptor for K. - CUtensorMap tmaK_; - // TMA descriptor for V. - CUtensorMap tmaV_; - // The descriptor for O. - CUtensorMap tmaO_; - - // For FP4 KV cache, additional scaling factors are needed. - // TMA descriptor for K scaling factor. - CUtensorMap tmaKSf_; - // TMA descriptor for V scaling factor. - CUtensorMap tmaVSf_; - - // grid dimensions, these might differ from actual grid the kernel is launched with - // for persistent kernels on Hopper GPUs. - int32_t logicalGridDimX, logicalGridDimY, logicalGridDimZ; - - // The output pointer (used by STG for last tile). - void* ptrO; - // The output SF pointer (used for FP4 output). - void* ptrSfO; - - // The attention sinks pointer (additional value per head in the denominator of the softmax). - float const* ptrAttentionSinks; - // The cumulative sequence lengths for Q. - int32_t const* ptrCumSeqLensQ; - // The cumulative sequence lengths for K/V. - int32_t const* ptrCumSeqLensKv; - // The packed custom mask. - uint32_t const* ptrCustomMask; - // The packed custom mask's offsets of each sequence. - int64_t const* ptrCustomMaskOffsets; - // The debug output matrix O - float* ptrDebugO; - // The first sparseMask offsets in the Kv sequence dimension. - int32_t const* ptrFirstSparseMaskOffsetsKv; - // The counter for the multiCtasKv mode. - int32_t* ptrMultiCtasKvCounter; - // The device output scale for FP8 quantization. Only needed by trt-llm fp8 kernels as the sca- - // les have to be on the device currently. - float const* ptrOutputScale; - // The page indexes of the paged-kv buffer with shape of [batchSize, 2, maxNumPagesPerSeq]. - int32_t const* ptrPageIdxKv; - // The partial matrix O for each CtaKv when the multiCtasKv mode is enabled. - void* ptrPartialO; - // The partial softmax stats (max/sum)for each CtaKv when the multiCtasKv mode is enabled. - float2* ptrPartialStats; - // The scaling factors for K. - float const* ptrSageAttnSfsK; - // The scaling factors for P. - float const* ptrSageAttnSfsP; - // The scaling factors for Q. - float const* ptrSageAttnSfsQ; - // The scaling factors for V. - float const* ptrSageAttnSfsV; - // The device scaling factor for softmax (multiplied by log2 to use faster exp2). Only needed by - // trt-llm fp8 kernels as the scales have to be on the device currently. - float const* ptrScaleSoftmaxLog2; - // The SF scale for Kv on device. Only needed by trt-llm kernels as the scales have to be on the device currently. - float const* ptrScaleSfKv; - // The SF scale for O on device. Only needed by trt-llm kernels as the scales have to be on the device currently. - float const* ptrScaleSfO; - // The sequence lengths for K/V. Required by pagedKv kernels to avoid unnecessary computation - // based on (ptrCumSeqLensKv[batchIdx + 1] - ptrCumSeqLensKv[batchIdx]). - int32_t const* ptrSeqLensKv; - // Reserved buffer. - int32_t* ptrReservedBuffer; - // The softmax stats buffer. - float2* ptrSoftmaxStats; - - // The attention window size for sliding window attention. - int32_t mAttentionWindowSize; - // The batch size - int32_t mBatchSize; - // The chunked attention size in log2. - int32_t mChunkedAttentionSizeLog2; - // The factor to add to the maximum value to increase the probability - // of skip correction during next iterations. - float mInflateMax; - // The log of the Sage Attention block size for K. - int32_t mLogNumEltsPerSageAttnBlkK; - // The log of the Sage Attention block size for P. - int32_t mLogNumEltsPerSageAttnBlkP; - // The log of the Sage Attention block size for Q. - int32_t mLogNumEltsPerSageAttnBlkQ; - // The log of the Sage Attention block size for V. - int32_t mLogNumEltsPerSageAttnBlkV; - // The sequence lengths for Q and K/V. - int32_t mMaxSeqLenQ, mMaxSeqLenKv; - // The maximum number of CTAs for Q. - int32_t mMaxNumCtasQ; - // The maximum number of CTAs for K/V. - int32_t mMaxNumCtasKv; - // The maximum number of pages per sequence for paged-kv buffer. - int32_t mMaxNumPagesPerSeqKv; - // The number of heads for K/V. - int32_t mNumHeadsKv; - // The number of heads for Q. - int32_t mNumHeadsQ; - // The number of Q heads per K/V head (i.e. mNumHeadsQ / mNumHeadsKv). - int32_t mNumHeadsQPerKv; - // The number of headsQ per K/V head as a fast_mod_div divisor. - FastModDivInt32 mNumHeadsQPerKvDivisor{1}; - // The hidden size of O. - int64_t mNumHiddenEltsO; - // The total number of pages in the paged-kv memory pool. - int32_t mNumPagesInMemPool; - // The number of tokensQ per CTA (used for groupsHeadsTokensQ generation kernel). - int32_t mNumTokensPerCtaQ; - // The number of tokens per page (used if dynamic numTokensPerPage is enabled). - int32_t mNumTokensPerPageLog2; - // The output scale for FP8 quantization. - float mOutputScale; - // The scaling factor for softmax (multiplied by log2 to use faster exp2). - float mScaleSoftmaxLog2; - // The SF scale for Kv. - float mScaleSfKv; - // The SF scale for O. - float mScaleSfO; - // Threshold to decide whether warp skips softmax ops - float mSkipSoftmaxThresholdScaleFactor; - // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase - // kernel when inflight batching is enabled in TRT-LLM. - int32_t mStartTokenIdx; - // The sum of sequence lengths for Q and K/V. - int32_t mSumOfSeqLensQ, mSumOfSeqLensKv; - // The top k value for sparse MLA. - int32_t mSparseMlaTopK; - // The flag to use block sparse attention. - bool mUseBlockSparseAttention; - // Whether the indices for K & V pages are shared as unified index (vLLM/FlashInfer). - bool mUsesSharedPagedKvIdx; - - // Create the TMA shape/stride for Q. - template - static auto makeTmaShapeStrideQ(FmhaOptions const& options, bool groupsHeadsQ, bool groupsTokensHeadsQ, - int32_t tileSizeQ, int32_t numEltsInClampedHeadDimQ) - { - - // - // The Q has shape of [numTokens * numHeadsQPerKv, numHeadsKv * 1, headDim] - // when grouping headsQ, otherwise it would be [numTokens, numHeadsQPerKv * numHeadsKv, - // headDim]. - - // The number of grouped heads for the A matrix of MMA. - int32_t numGroupedHeads{1}; - if (groupsHeadsQ) - { - numGroupedHeads = std::min(tileSizeQ, options.mNumHeadsQPerKv); - } - - // The number of heads. - int32_t numHeads{options.mNumHeadsQ}; - if (groupsHeadsQ) - { - numHeads /= numGroupedHeads; - } - // Make sure the math works. - TLLM_CHECK_WITH_INFO(numHeads * numGroupedHeads == options.mNumHeadsQ, "internal error"); - - // The number of tokens. - int32_t numTokens{options.mSumOfSeqLensQ}; - - // This maps to flattened TMA shape for Q: (headDim, numTokens, numHeads). - auto shape = std::vector{static_cast(options.mHeadDimQk), - static_cast(numGroupedHeads), static_cast(numHeads), static_cast(numTokens)}; - - // The hidden dimension when the tensor contains only Q (i.e. not QKV packed). - int32_t const hiddenDimQ{options.mNumHeadsQ * options.mHeadDimQk}; - - // The hidden dimension when the Q, K and V tensors are packed. - int32_t hiddenDimQkv{hiddenDimQ}; - if (isPackedQkv(options.mQkvLayout)) - { - TLLM_CHECK_WITH_INFO(!groupsHeadsQ, "internal error"); - hiddenDimQkv += options.mNumHeadsKv * (options.mHeadDimQk + options.mHeadDimV); - } - - // The stride between tokens. - int32_t strideTokens{hiddenDimQkv}; - - // The stride between heads. - int32_t strideHeads{groupsHeadsQ ? numGroupedHeads * options.mHeadDimQk : options.mHeadDimQk}; - - // The stride between grouped heads. - int32_t strideGroupedHeads{options.mHeadDimQk}; - - // Assemble the stride (1, strideTokens, strideHeads). - // Swap the first two dimension as mentioned before. - auto stride = std::vector{1, static_cast(strideGroupedHeads), - static_cast(strideHeads), static_cast(strideTokens)}; - - // The tile shape for TMA. - auto tileShapes = std::vector{ - static_cast(numEltsInClampedHeadDimQ), 1, 1, static_cast(tileSizeQ)}; - // The number of tokensQ per CTA. - int32_t numTokensPerCtaQ{tileSizeQ}; - // Re-compute the number of tokensQ per CTA if groupsHeadsQ is enabled. - if (groupsHeadsQ) - { - if (groupsTokensHeadsQ) - { - // Currently, it requires each CTA to process complete headsQ (i.e. numGroupedHeads) at a - // time, so it allows paddings in the end. Removing paddings needs re-organizing the Q - // tensor to [numTokensQ, numGroupedHeads, numHeads, headDimQ] and we might want to revisit - // this in the future. - numTokensPerCtaQ = static_cast(numTokensPerCtaQ / numGroupedHeads); - } - else - { - numGroupedHeads = tileSizeQ; - numTokensPerCtaQ = 1; - } - tileShapes = std::vector{static_cast(numEltsInClampedHeadDimQ), - static_cast(numGroupedHeads), 1, static_cast(numTokensPerCtaQ)}; - } - - return std::make_tuple(shape, stride, tileShapes, numTokensPerCtaQ); - } - - // Create the TMA shape/stride for O. - template - static auto makeTmaShapeStrideO(FmhaOptions const& options) - { - - // - // TODO: refactor this as makeTmaShapeStrideQ when removing cutlass tma copy. - // - - // The number of tokens. - int32_t numTokens{options.mSumOfSeqLensQ}; - - // The number of heads per K/V head. - int32_t numHeadsQPerKv{options.mNumHeadsQPerKv}; - - // The batch dimension. - int32_t batchSize{1}; - - // The cute tensor shape for Q/O: (numTokens, headDim, ((numHeadsKv, numHeadsQPerKv), - // batchSize)). This maps to flattened TMA shape for Q/O: (headDim, numTokens, numHeadsKv. - // numHeadsQPerKv, batchSize). Note that TMA descriptor expects the first dimension's stride to - // be 1, so swap the first two dimension so that the headDim dimension comes first. - auto shape = std::vector{static_cast(options.mHeadDimV), static_cast(numTokens), - static_cast(options.mNumHeadsKv), static_cast(numHeadsQPerKv), - static_cast(batchSize)}; - - // The hidden dimension. - int32_t const hiddenDimO{options.mNumHeadsQ * options.mHeadDimV}; - - // The stride between tokens. - int32_t strideTokens{hiddenDimO}; - - // The stride between Q heads. - int32_t strideHeadsQ{options.mNumHeadsKv * options.mHeadDimV}; - - // The stride between sequences. - int32_t strideBatch{0}; - - // The stride in between K/V heads. - int32_t strideHeadsKv{options.mHeadDimV}; - // Assemble the stride (strideTokens, 1, ((strideHeadsKv, strideHeadsQ), strideBatch)). - // Swap the first two dimension as mentioned before. - auto stride - = std::vector{1, static_cast(strideTokens), static_cast(strideHeadsKv), - static_cast(strideHeadsQ), static_cast(strideBatch)}; - - return std::make_tuple(shape, stride); - } - - // Create the shape for K and V. - template - static auto makeShapeKv(FmhaOptions const& options, KernelParams const& params) - { - - // The number of keys/vals. WARNING: The if/else-if are sorted by priority. - int32_t numKeysVals{options.mMaxSeqLenKv}; - if (isPagedKv(options.mQkvLayout)) - { - numKeysVals = options.mNumTokensPerPage; - } - else if (isContiguousKv(options.mQkvLayout)) - { - numKeysVals = options.mMaxSeqLenCacheKv; - } - else - { - numKeysVals = options.mSumOfSeqLensKv; - } - - // The number of heads per K/V head (packed in the sequence length for mGroupsHeadsQ). - int32_t numHeadsKv{options.mNumHeadsKv}; - - // The batch dimension. WARNING: The if/else-if are sorted by priority. - int32_t batchSize{options.mBatchSize}; - if (isPagedKv(options.mQkvLayout)) - { - batchSize = params.mNumPagesInMemPool; - } - else if (isContiguousKv(options.mQkvLayout)) - { - batchSize = options.mBatchSize; - } - else - { - batchSize = 1; - } - - // Return the number of keys and batch. - return std::make_tuple(numKeysVals, numHeadsKv, batchSize); - } - - // Compute the strides for K and V. - template - static auto makeStrideKv(FmhaOptions const& options, Data_type dtypeKv, bool isK) - { - - // The maximum headDim of K and V. - // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv. - int32_t const maxHeadDimKv{std::max(options.mHeadDimQk, options.mHeadDimV)}; - // The hidden dimension for the keys/vals. - int32_t const hiddenDimK{options.mNumHeadsKv * options.mHeadDimQk}; - int32_t const hiddenDimV{options.mNumHeadsKv * options.mHeadDimV}; - int32_t const maxHiddenDimKv{std::max(hiddenDimK, hiddenDimV)}; - // The hidden dimension when Q, K and V are packed together. - int32_t const hiddenDimQkv{ - options.mNumHeadsQ * options.mHeadDimQk + options.mNumHeadsKv * (options.mHeadDimQk + options.mHeadDimV)}; - - // The stride between the different keys/vals. - int32_t strideKeysVals{isK ? hiddenDimK : hiddenDimV}; - if (isPagedKv(options.mQkvLayout)) - { - strideKeysVals = maxHeadDimKv; - } - else if (isPackedQkv(options.mQkvLayout)) - { - strideKeysVals = hiddenDimQkv; - } - else if (isContiguousKv(options.mQkvLayout)) - { - strideKeysVals = maxHeadDimKv; - } - else if (isSeparateQkv(options.mQkvLayout) && !isK && options.mHeadDimQkNope > 0 && dtypeKv != DATA_TYPE_E4M3) - { - // Non-FP8 context MLA: tensor V is not contiguous. The token stride is mNumHeadsKv * (mHeadDimQkNope + - // mHeadDimV). - strideKeysVals = options.mNumHeadsKv * (options.mHeadDimQkNope + options.mHeadDimV); - } - - // The stride between heads. - int32_t strideHeads{isK ? options.mHeadDimQk : options.mHeadDimV}; - if (isPagedKv(options.mQkvLayout)) - { - strideHeads = options.mNumTokensPerPage * maxHeadDimKv; - } - else if (isContiguousKv(options.mQkvLayout)) - { - strideHeads = options.mMaxSeqLenCacheKv * maxHeadDimKv; - } - - // The stride between batch items. WARNING: The order of if/else-if matters. - int32_t strideBatch{options.mMaxSeqLenKv * hiddenDimK}; - if (isPagedKv(options.mQkvLayout)) - { - strideBatch = options.mNumTokensPerPage * maxHiddenDimKv; - } - else if (isContiguousKv(options.mQkvLayout)) - { - strideBatch = 2 * options.mNumHeadsKv * options.mMaxSeqLenCacheKv * maxHeadDimKv; - } - else - { - // Always variable seqlens. - strideBatch = 0; - } - - // The 3 strides (the other ones are 1 and 0). - return std::make_tuple(strideKeysVals, strideHeads, strideBatch); - } - - // Create the TMA shape/stride for K. - template - static auto makeTmaShapeStrideKv(FmhaOptions const& options, KernelParams const& params, Data_type dtypeKv, - bool isK, bool storeTransformedKvInTmem) - { - // The shape elements. - auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params); - // The stride elements. - auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, dtypeKv, isK); - - // The headDim. - // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv. - int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV; - if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) - { - headDim = std::max(options.mHeadDimQk, options.mHeadDimV); - } - - // For K, the cute layout: (numKeys, headDim, ((numHeadsQPerKv, numHeadsKv), - // batchSize)):(strideKeys, _1, _0, strideHeads, strideBatch). Cute swaps the first two - // dimension (to make sure stride of first dimension is 1) and ignores the numHeadsQPerKv - // dimension (it's stride is always 0). For V, the headDim dimension is already the first - // dimension so no swapping is needed. - - // Therefore, the resulting TMA layout is 4D: (headDim, numKeys, numHeadsKv, batchSize):(1, - // strideKeys, strideHeads, strideBatch) - - // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements. - // The column index and strides needs to divide by 2. - auto const colIdxDivisor = dtypeKv == DATA_TYPE_E2M1 ? 2 : 1; - // When storeTransformedKvInTmem is true, the dimensions reflect FP4 element dimensions, thus - // no need to divide. - - auto shape - = std::vector{static_cast(storeTransformedKvInTmem ? headDim : headDim / colIdxDivisor), - static_cast(numKeys), static_cast(options.mNumHeadsKv), - static_cast(batchSize)}; - auto stride = std::vector{1, static_cast(strideKeys / colIdxDivisor), - static_cast(strideHeads / colIdxDivisor), static_cast(strideBatch / colIdxDivisor)}; - - return std::make_tuple(shape, stride); - } - - // Create the TMA shape/stride for KV scaling factors. - template - static auto makeTmaShapeStrideKvSf( - FmhaOptions const& options, KernelParams const& params, Data_type dtypeKv, bool isK) - { - // The shape elements. - auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params); - // The stride elements. - auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, dtypeKv, isK); - - // The headDim. - // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv. - int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV; - if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) - { - headDim = std::max(options.mHeadDimQk, options.mHeadDimV); - } - - // The number of elements per SF. - int32_t NumEltsPerSf = 16; - - // The KV shape is: (headDim, numKeys, numHeadsKv, batchSize) - // Therefore, the KV SF shape should be (headDim / NumEltsPerSf, numKeys, numHeadsKv, - // batchSize). Considering the TMA requires box width to be multiple of 16B, without changing the - // underlying layout, we reshape into (16, numKeys * headDim / NumEltsPerSf / 16, numHeadsKv, - // batchSize) - - // Note that it only works for pagedKv layout. - TLLM_CHECK_WITH_INFO(isPagedKv(options.mQkvLayout), "The qkvLayout is not supported."); - - auto shape = std::vector{16, static_cast(numKeys * headDim / NumEltsPerSf / 16), - static_cast(options.mNumHeadsKv), static_cast(batchSize)}; - auto stride = std::vector{1, 16, static_cast(strideHeads / NumEltsPerSf), - static_cast(strideBatch / NumEltsPerSf)}; - - return std::make_tuple(shape, stride); - } - - // Prepare pointers for TMA descriptors. - static std::tuple getDevicePtrs( - TllmGenFmhaRunnerParams const& runnerParams, int32_t bitsPerElt) - { - // Declare the q, k, v ptrs. - void const *qPtr{runnerParams.qPtr}, *kPtr{runnerParams.kPtr}, *vPtr{runnerParams.vPtr}; - - // Set Q, K and V pointer from packed QKV tensor. - if (isPackedQkv(runnerParams.mQkvLayout)) - { - qPtr = runnerParams.qkvPtr; - kPtr = reinterpret_cast(reinterpret_cast(runnerParams.qkvPtr) - + runnerParams.mNumHeadsQ * runnerParams.mHeadDimQk * bitsPerElt / 8 /*bits*/); - vPtr = reinterpret_cast(reinterpret_cast(runnerParams.qkvPtr) - + (runnerParams.mNumHeadsQ + runnerParams.mNumHeadsKv) * runnerParams.mHeadDimQk * bitsPerElt - / 8 /*bits*/); - } - // Set K and V pointer from pagedKv tensor. - else if (isPagedKv(runnerParams.mQkvLayout)) - { - // Note that the offsets will be fully handled by the pageIdx buffer. - kPtr = runnerParams.kvPtr; - vPtr = runnerParams.kvPtr; - } - // Set K and V pointer from contiguousQAnddKv tensor. - else if (isContiguousKv(runnerParams.mQkvLayout)) - { - kPtr = runnerParams.kvPtr; - // The maximum headDim of K and V. - // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv. - int32_t const maxHeadDimKv{std::max(runnerParams.mHeadDimQk, runnerParams.mHeadDimV)}; - vPtr = reinterpret_cast(reinterpret_cast(runnerParams.kvPtr) - + runnerParams.mNumHeadsKv * runnerParams.mMaxSeqLenCacheKv * maxHeadDimKv * bitsPerElt / 8 /*bits*/); - } - - // Return the pointers. - return std::make_tuple(qPtr, kPtr, vPtr); - } - - // Build tma descriptors. - template - static CUtensorMap buildNdTmaDescriptor(FmhaOptions const& options, Data_type dtypeElt, - std::vector const& shapes, std::vector const& strides, - std::vector const& tileShapes, void* gmemAddr, bool swizzled = true, bool unpack4b = false) - { - CUtensorMap desc{}; - // The data type. - CUtensorMapDataType tmaDataFormat; - if (dtypeElt == DATA_TYPE_E2M1) - { - tmaDataFormat = unpack4b ? CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN16B : CU_TENSOR_MAP_DATA_TYPE_UINT8; - } - else if (dtypeElt == DATA_TYPE_E4M3) - { - tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_UINT8; - } - else if (dtypeElt == DATA_TYPE_FP16) - { - tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_FLOAT16; - } - else if (dtypeElt == DATA_TYPE_BF16) - { - tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_BFLOAT16; - } - else - { - TLLM_CHECK_WITH_INFO(false, "Unexpected dtype %d", static_cast(dtypeElt)); - } - - // The swizzle type. - CUtensorMapSwizzle swizzleType; - int32_t numBytesInLeadingDim = tileShapes[0] * get_size_in_bits(dtypeElt) / 8 /*bits*/; - if (!swizzled) - { - swizzleType = CU_TENSOR_MAP_SWIZZLE_NONE; - } - else if (tmaDataFormat == CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN16B) - { - swizzleType = CU_TENSOR_MAP_SWIZZLE_128B; - } - else if ((numBytesInLeadingDim % 128) == 0) - { - swizzleType = CU_TENSOR_MAP_SWIZZLE_128B; - } - else if ((numBytesInLeadingDim % 64) == 0) - { - swizzleType = CU_TENSOR_MAP_SWIZZLE_64B; - } - else if ((numBytesInLeadingDim % 32) == 0) - { - swizzleType = CU_TENSOR_MAP_SWIZZLE_32B; - } - else - { - TLLM_CHECK_WITH_INFO(false, "Unexpected numBytesInLeadingDim %d", numBytesInLeadingDim); - } - - // Check gmem address must be 16B-aligned - TLLM_CHECK((reinterpret_cast(gmemAddr) & 0b1111) == 0); - - // Check shape must be in range [1, 2^32] - int32_t dim = shapes.size(); - // Max five dimension and min 2 dimension. - TLLM_CHECK((dim <= 5) && (dim >= 2)); - // Check shape range. - for (int32_t ii = 0; ii < dim; ++ii) - { - TLLM_CHECK(shapes[ii] >= (uint64_t(1))); // Size must be min 1 - TLLM_CHECK(shapes[ii] <= (uint64_t(1) << 32)); // Size must be max 2^32 - } - - // TMA descriptor does not store the zeroth stride and assumes it is 1. - TLLM_CHECK(static_cast(strides.size()) == dim); - TLLM_CHECK(strides[0] == 1); - - // Build strides in bytes. - // cuTensorMapEncodeTiled ignores the stride of the first dimension (implicitly 1). - std::vector stridesInBytes(dim - 1); - for (int32_t ii = 0; ii < dim - 1; ++ii) - { - stridesInBytes[ii] - = strides[ii + 1] * std::max(get_size_in_bits(dtypeElt), static_cast(8)) / 8 /*bit*/; - } - - // Set tile strides to 0; - std::vector tileStrides(dim, 1); - - // Build the descriptor. - CUresult result = cuTensorMapEncodeTiled(&desc, tmaDataFormat, - /*tensorRank=*/dim, gmemAddr, shapes.data(), stridesInBytes.data(), tileShapes.data(), tileStrides.data(), - /*interleave=*/CU_TENSOR_MAP_INTERLEAVE_NONE, swizzleType, - /*l2Promotion=*/CU_TENSOR_MAP_L2_PROMOTION_L2_128B, - /*oobFill=*/CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE); - - if (result != CUDA_SUCCESS) - { - char const* err_str; - cuGetErrorString(result, &err_str); - // Note that the error is thrown out before launching fmha kernels, so it is highly possible that - // the errors are broadcasted by previous kernels. Please enable CUDA_LAUNCH_BLOCKING or use cuda-gdb - // for more details. - std::cerr << "Error: Failed to initialize the TMA descriptor due to " << err_str << std::endl; - std::cerr << "tmaFormat: " << static_cast(tmaDataFormat) << " dim: " << dim << " gmem: " << gmemAddr - << std::endl; - std::cerr << "Shape: " << shapes[0] << " " << shapes[1] << " " << shapes[2] << " " << shapes[3] << " " - << shapes[4] << std::endl; - std::cerr << "Stride: " << stridesInBytes[0] << " " << stridesInBytes[1] << " " << stridesInBytes[2] << " " - << stridesInBytes[3] << std::endl; - std::cerr << "tileShapes: " << tileShapes[0] << " " << tileShapes[1] << " " << tileShapes[2] << " " - << tileShapes[3] << " " << tileShapes[4] << std::endl; - std::cerr << "tileStrides: " << tileStrides[0] << " " << tileStrides[1] << " " << tileStrides[2] << " " - << tileStrides[3] << " " << tileStrides[4] << std::endl; - std::cerr << "swizzleType: " << int(swizzleType) << std::endl; - TLLM_CHECK(false); - } - - return desc; - } - - // Setup the kernel parameters. - template - static KernelParams setKernelParams( - FmhaOptions_ const& options, KernelMeta const& kernelMeta, int32_t maxNumCtasQ, int32_t maxNumCtasKv) - { - - // Create the return struct. - KernelParams params; - - // Get the device pointers for TMA descriptors. - auto [qPtr, kPtr, vPtr] = getDevicePtrs(options, get_size_in_bits(kernelMeta.mDataTypeKv)); - - // The maximum headDim of K and V. - // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv. - int32_t const maxHeadDimKv{std::max(options.mHeadDimQk, options.mHeadDimV)}; - - // Set the number of pages in the memory pool for paged K/V cache. - if (isPagedKv(options.mQkvLayout)) - { - params.mNumPagesInMemPool = options.mNumPagesInMemPool == 0 - ? options.mMaxNumPagesPerSeqKv * 2 * options.mBatchSize - : options.mNumPagesInMemPool; - } - - // The number of elements in 128B for Q. - int32_t numEltsIn128BQ = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeQ); - // The number of head elts (per token) in each block of shared memory. - int32_t numEltsInClampedHeadDimQ = std::min(numEltsIn128BQ, options.mHeadDimQk); - - // Shape/stride for gmem tensor Q. - auto [shapeQ, strideQ, tileShapeQ, numTokensPerCtaQ] = makeTmaShapeStrideQ(options, kernelMeta.mGroupsHeadsQ, - kernelMeta.mGroupsTokensHeadsQ, kernelMeta.mTileSizeQ, numEltsInClampedHeadDimQ); - // Build tma descriptor for Q. - params.tmaQ_ = buildNdTmaDescriptor( - options, kernelMeta.mDataTypeQ, shapeQ, strideQ, tileShapeQ, const_cast(qPtr)); - - // The number of keys per tile. - int32_t numKeysPerTile = isPagedKv(options.mQkvLayout) - ? std::min(options.mNumTokensPerPage, kernelMeta.mTileSizeKv) - : kernelMeta.mTileSizeKv; - // The number of elements in 128B for Q. - int32_t numEltsIn128BKv = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeKv); - // The number of head elts (per token) in each block of shared memory (see above explanation). - // HeadDim will be split into multiple headDimStages (128) if maxHeadDimKv > 128. - int32_t numEltsInClampedHeadDimKv = std::min({numEltsIn128BKv, maxHeadDimKv, 128}); - - // Do we have to transform K/V before MMA? - bool const transformsKv{kernelMeta.mDataTypeKv != kernelMeta.mDataTypeQ}; - // Whether store transformed K/V in TMEM. - bool const isSwapsMmaAb = isSwapsMmaAbForGenerationKernel(static_cast(kernelMeta.mKernelType)); - bool const storeTransformedKvInTmem{kernelMeta.mDataTypeKv == DATA_TYPE_E2M1 - && kernelMeta.mDataTypeQ == DATA_TYPE_E4M3 && maxHeadDimKv >= 128 && isSwapsMmaAb}; - - // Shape/stride for gmem tensor Kv. - auto [shapeK, strideK] - = makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ true, storeTransformedKvInTmem); - auto [shapeV, strideV] - = makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ false, storeTransformedKvInTmem); - // Whether swizzle is needed for K/V. - bool const swizzleKv{storeTransformedKvInTmem || !transformsKv}; - // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements. - auto const numEltsDivisor = kernelMeta.mDataTypeKv == DATA_TYPE_E2M1 && !storeTransformedKvInTmem ? 2 : 1; - // The tileShapes for K/V. - std::vector tileShapeKv(shapeK.size(), 1); - tileShapeKv[0] = numEltsInClampedHeadDimKv / numEltsDivisor; - tileShapeKv[1] = numKeysPerTile; - - // If sparse MLA is enabled, the shape and stride for K need to be updated for 2D layout (numTokensKvInPagedKv, - // headDimQk). - if (options.mSparseMla) - { - shapeK = std::vector{static_cast(options.mHeadDimQk), static_cast(INT_MAX)}; - strideK = std::vector{1, static_cast(options.mHeadDimQk)}; - tileShapeKv[1] = 1; - } - - // Build tma descriptor for K. - params.tmaK_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeK, strideK, tileShapeKv, - const_cast(kPtr), - /*swizzled = */ swizzleKv, /*unpack4b = */ storeTransformedKvInTmem); - // Build tma descriptor for V. - params.tmaV_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeV, strideV, tileShapeKv, - const_cast(vPtr), - /*swizzled = */ swizzleKv, /*unpack4b = */ storeTransformedKvInTmem); - // If the KV dtype is E2m1, additional scaling factors are needed for dequant. - if (kernelMeta.mDataTypeKv == DATA_TYPE_E2M1) - { - // The number of elements per SF. - int32_t NumEltsPerSf = 16; - // Compute the shape and stride for SF tensor. - // FIXME: assume K and V uses the same shape. - auto [shapeKvSf, strideKvSf] - = makeTmaShapeStrideKvSf(options, params, kernelMeta.mDataTypeKv, /*isK*/ true); - - // The tileShapes for K/V. - std::vector tileShapeKvSf(shapeKvSf.size(), 1); - tileShapeKvSf[0] = 16; - tileShapeKvSf[1] = numKeysPerTile * maxHeadDimKv / NumEltsPerSf / 16; - - // The tile box is reshaped from (headDim / NumEltsPerSf, tileSizeKv) into (16, tileSizeKv * - // headDim / NumEltsPerSf / 16). See makeTmaShapeStrideKvSf for details. Build tma descriptor - // for K SF. - params.tmaKSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf, tileShapeKvSf, - const_cast(options.kvSfPtr), - /*swizzled = */ false); - - // Build tma descriptor for V SF. - params.tmaVSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf, tileShapeKvSf, - const_cast(options.kvSfPtr), - /*swizzled = */ false); - } - - // Shape/stride for gmem tensor O. - auto [shapeO, strideO] = makeTmaShapeStrideO(options); - // The tileShapes for O. - std::vector tileShapeO(shapeO.size(), 1); - tileShapeO[0] = numEltsInClampedHeadDimQ; - tileShapeO[1] = kernelMeta.mTileSizeQ; - // Build tma descriptor for O. - params.tmaO_ = buildNdTmaDescriptor( - options, kernelMeta.mDataTypeQ, shapeO, strideO, tileShapeO, const_cast(options.oPtr)); - - // Set the other kernel parameters. - params.ptrAttentionSinks = options.attentionSinksPtr; - params.ptrCumSeqLensQ = options.cumSeqLensQPtr; - params.ptrCumSeqLensKv = options.cumSeqLensKvPtr; - - // The packed custom mask. - params.ptrCustomMask = options.customMaskPtr; - // The packed custom mask's offsets of each sequence. - params.ptrCustomMaskOffsets = options.customMaskOffsetsPtr; - // The first sparseMask offsets in the Kv sequence dimension. - params.ptrFirstSparseMaskOffsetsKv = options.firstSparseMaskOffsetsKvPtr; - - // The output buffer. - params.ptrO = options.oPtr; - // The output scaling factor buffer. - params.ptrSfO = options.oSfPtr; - - // TRT-LLM restrictions: the quantization scales must be on the device. - params.ptrOutputScale = options.outputScalePtr; - - // The sequence lengths for Kv. - params.ptrSeqLensKv = options.seqLensKvPtr; - - // The partial buffers' pointers when the multiCtasKv mode is enabled. - int64_t partialStatsBufferSize = options.mMultiProcessorCount * kernelMeta.mStepQ; - params.ptrMultiCtasKvCounter = options.multiCtasKvCounterPtr; - params.ptrPartialStats = reinterpret_cast(options.multiCtasKvScratchPtr); - params.ptrPartialO = params.ptrPartialStats + partialStatsBufferSize; - - params.ptrPageIdxKv = options.kvPageIdxPtr; - params.ptrScaleSoftmaxLog2 = options.scaleSoftmaxLog2Ptr; - - params.ptrScaleSfKv = options.kvSfScalePtr; - params.ptrScaleSfO = options.oSfScalePtr; - - // The softmax stats buffer with shape of [numTokensQ x numHeadsQ]. - // The max/sum values are packed into float2. - params.ptrSoftmaxStats = options.softmaxStatsPtr; - - params.mAttentionWindowSize = options.mAttentionWindowSize; - if (isSlidingOrChunkedCausalMask(static_cast(kernelMeta.mMaskType)) - && options.mChunkedAttentionSize != INT_MAX) - { - TLLM_CHECK_WITH_INFO((options.mChunkedAttentionSize & (options.mChunkedAttentionSize - 1)) == 0, - "Chunked attention size must be a power of 2"); - params.mChunkedAttentionSizeLog2 = std::log2(options.mChunkedAttentionSize); - } - else - { - // Default 0 means that chunked attention is disabled. - params.mChunkedAttentionSizeLog2 = 0; - } - params.mMaxSeqLenQ = options.mMaxSeqLenQ; - params.mMaxSeqLenKv = options.mMaxSeqLenKv; - params.mMaxNumCtasQ = maxNumCtasQ; - params.mMaxNumCtasKv = maxNumCtasKv; - params.mMaxNumPagesPerSeqKv = options.mMaxNumPagesPerSeqKv; - params.mSumOfSeqLensQ = options.mSumOfSeqLensQ; - params.mSumOfSeqLensKv = options.mSumOfSeqLensKv; - params.mBatchSize = options.mBatchSize; - params.mNumHeadsQ = options.mNumHeadsQ; - params.mNumHeadsKv = options.mNumHeadsKv; - params.mNumHeadsQPerKv = options.mNumHeadsQPerKv; - params.mNumHeadsQPerKvDivisor = FastModDivInt32{options.mNumHeadsQPerKv}; - params.mNumHiddenEltsO = options.mNumHeadsQ * options.mHeadDimQk; - params.mNumTokensPerCtaQ = numTokensPerCtaQ; - params.mNumTokensPerPageLog2 = 0; - if (isPagedKv(options.mQkvLayout)) - { - TLLM_CHECK_WITH_INFO((options.mNumTokensPerPage & (options.mNumTokensPerPage - 1)) == 0, - "NumTokensPerPage must be a power of 2"); - params.mNumTokensPerPageLog2 = static_cast(std::log2(options.mNumTokensPerPage)); - } - params.mOutputScale = 1.f; - params.mScaleSoftmaxLog2 = (1.f / (std::sqrt((float) (options.mHeadDimQk)) * options.mScaleQ)) * M_LOG2E; - params.mStartTokenIdx = options.mSfStartTokenIdx; - // The sparseMlaTopK needs to be a multiple of 4 as we use 16B cpAsync instructions for the indices. - TLLM_CHECK_WITH_INFO( - !options.mSparseMla || (options.mSparseMlaTopK % 4) == 0, "SparseMlaTopK must be a multiple of 4"); - params.mSparseMlaTopK = options.mSparseMlaTopK; - params.mUseBlockSparseAttention = options.mUseBlockSparseAttention; - // Whether the indices for K & V pages are shared as unified index (vLLM/FlashInfer). - // Always false for TRTLLM paged kv cache layout. - params.mUsesSharedPagedKvIdx = false; - params.mSkipSoftmaxThresholdScaleFactor = options.mSkipSoftmaxThresholdScaleFactor; - return params; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace kernels - -TRTLLM_NAMESPACE_END diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/aarch64-linux-gnu/libTrtLlmGen.a b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/aarch64-linux-gnu/libTrtLlmGen.a new file mode 100644 index 000000000000..33a9b64f75cd --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/aarch64-linux-gnu/libTrtLlmGen.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:db7db5a5742f0094db2ddf22fe3f576aa90e4352a2da7186b1190494c67d35ba +size 117623526 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/aarch64-linux-gnu/libTrtLlmGenFmhaLib.a b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/aarch64-linux-gnu/libTrtLlmGenFmhaLib.a new file mode 100644 index 000000000000..f4d0c327fd14 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/aarch64-linux-gnu/libTrtLlmGenFmhaLib.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9f1c4d3a535d56b7dff478a1ad7731f8541a1845a6dff9e1a93e1b5b91c98f58 +size 22480460 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/x86_64-linux-gnu/libTrtLlmGen.a b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/x86_64-linux-gnu/libTrtLlmGen.a new file mode 100644 index 000000000000..8d2d1b62dc82 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/x86_64-linux-gnu/libTrtLlmGen.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ec7346bdccebea8ce64cf3bbb859397f6b68f3181ea6bd18fcf7ab5fbcc65833 +size 117165000 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/x86_64-linux-gnu/libTrtLlmGenFmhaLib.a b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/x86_64-linux-gnu/libTrtLlmGenFmhaLib.a new file mode 100644 index 000000000000..24ea24d2ec9f --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/lib/x86_64-linux-gnu/libTrtLlmGenFmhaLib.a @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c23dba5557e0bef3aae7a8d9019952a3669f30ed104179d284e7793589c4b224 +size 21980526 diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu index af267c59013b..58e8a2c6c366 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu @@ -16,6 +16,7 @@ #include "prepareCustomMask.h" #include "tensorrt_llm/common/config.h" +#include "tensorrt_llm/common/cudaUtils.h" #include #include #include @@ -31,21 +32,78 @@ __device__ __host__ inline int32_t ceilDiv(int32_t a, int32_t b) return (a + b - 1) / b; } +__global__ void computeCustomMaskOffsetsKernel( + TllmGenFmhaRunnerParams runnerParams, int32_t stepQ, int32_t stepKv, unsigned long long* globalCounter) +{ + int32_t batchSize = runnerParams.mBatchSize; + int32_t numHeadsQPerKv = runnerParams.mNumHeadsQPerKv; + int32_t tileSizeQPerCta = stepQ; + int32_t tileSizeKvPerCta = stepKv; + int32_t const* seqLensKvPtr = runnerParams.seqLensKvPtr; + int32_t const* firstSparseMaskOffsetsKvPtr = runnerParams.firstSparseMaskOffsetsKvPtr; + + typedef cub::BlockScan BlockScan; + __shared__ typename BlockScan::TempStorage temp_storage; + + int idx = blockIdx.x * blockDim.x + threadIdx.x; + int64_t maskSize = 0; + + if (idx < batchSize) + { + + int32_t seqLenQ = runnerParams.seqLensQPtr[idx]; + int32_t seqLenKv = seqLensKvPtr[idx]; + int32_t firstSparseMaskOffsetKv = firstSparseMaskOffsetsKvPtr[idx]; + + int32_t numTilesQ = (seqLenQ * numHeadsQPerKv + tileSizeQPerCta - 1) / tileSizeQPerCta; + int32_t firstSparseTile = firstSparseMaskOffsetKv / tileSizeKvPerCta; + int32_t numCustomMaskTilesKv = (seqLenKv + tileSizeKvPerCta - 1) / tileSizeKvPerCta - firstSparseTile; + + maskSize = static_cast(numTilesQ * numCustomMaskTilesKv * stepQ * stepKv / 32); + } + + int64_t prefixOffset; + int64_t blockSum; + BlockScan(temp_storage).ExclusiveSum(maskSize, prefixOffset, blockSum); + + __shared__ unsigned long long blockBase; + if (threadIdx.x == 0) + blockBase = atomicAdd(globalCounter, (unsigned long long) blockSum); + __syncthreads(); + + if (idx < batchSize) + runnerParams.customMaskOffsetsPtr[idx] = static_cast(blockBase) + prefixOffset; +} + +void launchComputeCustomMaskOffsetsKernel( + TllmGenFmhaRunnerParams const& runnerParams, int32_t stepQ, int32_t stepKv, cudaStream_t stream) +{ + int32_t batchSize = runnerParams.mBatchSize; + + unsigned long long* d_globalCounter; + cudaMallocAsync(&d_globalCounter, sizeof(unsigned long long), stream); + cudaMemsetAsync(d_globalCounter, 0, sizeof(unsigned long long), stream); + + int blockSize = 128; + int gridSize = (batchSize + blockSize - 1) / blockSize; + computeCustomMaskOffsetsKernel<<>>(runnerParams, stepQ, stepKv, d_globalCounter); + + cudaFreeAsync(d_globalCounter, stream); +} + // Input: customMaskInput (generalPackedCustoMaskPtr) shape: [batch_size, seqLenQ, ceilDiv(seqLenKv-firstSparse, 32)] // Output: customMaskInput shape:[batch_size,numTilesQ, numTilesKv, numInstsQ, numInstsKv, tileSizeQ, tileSizeKv] // Output: customMaskOffsets shape:[batch_size] // Output: firstSparseMaskOffsetsKv shape:[batch_size] __global__ void prepareCustomMaskBuffersKernelForKeepsMmaAb( - TllmGenFmhaRunnerParams runnerParams, TllmGenFmhaKernelMetaInfo kernelMeta) + TllmGenFmhaRunnerParams runnerParams, int32_t stepQ, int32_t stepKv, int32_t tileSizeQ, int32_t tileSizeKv) { int32_t const batchSize = runnerParams.mBatchSize; int32_t const numHeadsQPerKv = runnerParams.mNumHeadsQPerKv; - int32_t const tileSizeQ = kernelMeta.mTileSizeQ; - int32_t const tileSizeKv = kernelMeta.mTileSizeKv; - int32_t const numInstsQ = kernelMeta.mStepQ / kernelMeta.mTileSizeQ; - int32_t const numInstsKv = kernelMeta.mStepKv / kernelMeta.mTileSizeKv; - int32_t const tileSizeQPerCta = kernelMeta.mStepQ; - int32_t const tileSizeKvPerCta = kernelMeta.mStepKv; + int32_t const numInstsQ = stepQ / tileSizeQ; + int32_t const numInstsKv = stepKv / tileSizeKv; + int32_t const tileSizeQPerCta = stepQ; + int32_t const tileSizeKvPerCta = stepKv; int32_t const* seqLensKvPtr = runnerParams.seqLensKvPtr; int64_t* customMaskOffsetsPtr = runnerParams.customMaskOffsetsPtr; @@ -69,7 +127,7 @@ __global__ void prepareCustomMaskBuffersKernelForKeepsMmaAb( int32_t const adjustedFirstSparseMaskOffsetKv = firstSparseMaskTileOffsetKv * tileSizeKvPerCta; // The sequence length of tensor Q. - int32_t const seqLenQ = runnerParams.seqlensQPtr[batchIdx]; + int32_t const seqLenQ = runnerParams.seqLensQPtr[batchIdx]; // The sequence length of tensor KV. int32_t const seqLenKv = seqLensKvPtr[batchIdx]; @@ -151,72 +209,10 @@ __global__ void prepareCustomMaskBuffersKernelForKeepsMmaAb( } } -__global__ void computeCustomMaskOffsetsKernel( - TllmGenFmhaKernelMetaInfo kernelMeta, TllmGenFmhaRunnerParams runnerParams, unsigned long long* globalCounter) -{ - int32_t batchSize = runnerParams.mBatchSize; - int32_t numHeadsQPerKv = runnerParams.mNumHeadsQPerKv; - int32_t tileSizeQPerCta = kernelMeta.mStepQ; - int32_t tileSizeKvPerCta = kernelMeta.mStepKv; - int32_t const* seqLensKvPtr = runnerParams.seqLensKvPtr; - int32_t const* firstSparseMaskOffsetsKvPtr = runnerParams.firstSparseMaskOffsetsKvPtr; - - typedef cub::BlockScan BlockScan; - __shared__ typename BlockScan::TempStorage temp_storage; - - int idx = blockIdx.x * blockDim.x + threadIdx.x; - int64_t maskSize = 0; - - if (idx < batchSize) - { - - int32_t seqLenQ = runnerParams.seqlensQPtr[idx]; - int32_t seqLenKv = seqLensKvPtr[idx]; - int32_t firstSparseMaskOffsetKv = firstSparseMaskOffsetsKvPtr[idx]; - - int32_t numTilesQ = (seqLenQ * numHeadsQPerKv + tileSizeQPerCta - 1) / tileSizeQPerCta; - int32_t firstSparseTile = firstSparseMaskOffsetKv / tileSizeKvPerCta; - int32_t numCustomMaskTilesKv = (seqLenKv + tileSizeKvPerCta - 1) / tileSizeKvPerCta - firstSparseTile; - - maskSize = static_cast(numTilesQ * numCustomMaskTilesKv * kernelMeta.mStepQ * kernelMeta.mStepKv / 32); - } - - int64_t prefixOffset; - int64_t blockSum; - BlockScan(temp_storage).ExclusiveSum(maskSize, prefixOffset, blockSum); - - __shared__ unsigned long long blockBase; - if (threadIdx.x == 0) - blockBase = atomicAdd(globalCounter, (unsigned long long) blockSum); - __syncthreads(); - - if (idx < batchSize) - runnerParams.customMaskOffsetsPtr[idx] = static_cast(blockBase) + prefixOffset; -} - -void launchComputeCustomMaskOffsetsKernel( - TllmGenFmhaKernelMetaInfo const& kernelMeta, TllmGenFmhaRunnerParams const& runnerParams, cudaStream_t stream) -{ - - int32_t batchSize = runnerParams.mBatchSize; - - unsigned long long* d_globalCounter; - cudaMallocAsync(&d_globalCounter, sizeof(unsigned long long), stream); - cudaMemsetAsync(d_globalCounter, 0, sizeof(unsigned long long), stream); - - int blockSize = 128; - int gridSize = (batchSize + blockSize - 1) / blockSize; - computeCustomMaskOffsetsKernel<<>>(kernelMeta, runnerParams, d_globalCounter); - - cudaFreeAsync(d_globalCounter, stream); -} - -// Post-processing kernel to write adjusted firstSparseMaskOffsetsKv after all work is done -__global__ void adjustFirstSparseMaskOffsetsKernel( - TllmGenFmhaRunnerParams runnerParams, TllmGenFmhaKernelMetaInfo kernelMeta) +__global__ void adjustFirstSparseMaskOffsetsKernel(TllmGenFmhaRunnerParams runnerParams, int32_t stepKv) { int32_t const batchSize = runnerParams.mBatchSize; - int32_t const tileSizeKvPerCta = kernelMeta.mStepKv; + int32_t const tileSizeKvPerCta = stepKv; int32_t const idx = blockIdx.x * blockDim.x + threadIdx.x; if (idx >= batchSize) return; @@ -227,13 +223,13 @@ __global__ void adjustFirstSparseMaskOffsetsKernel( firstSparseMaskOffsetsKvPtr[idx] = adjusted; } -void launchPrepareCustomMaskBuffersKernelForKeepsMmaAb( - TllmGenFmhaRunnerParams const& runnerParams, TllmGenFmhaKernelMetaInfo const& kernelMeta, cudaStream_t stream) +void launchPrepareCustomMaskBuffersKernelForKeepsMmaAb(TllmGenFmhaRunnerParams const& runnerParams, int32_t stepQ, + int32_t stepKv, int32_t tileSizeQ, int32_t tileSizeKv, cudaStream_t stream) { int32_t const batchSize = runnerParams.mBatchSize; int32_t const maxSeqLenQ = runnerParams.mMaxSeqLenQ; int32_t const numHeadsQPerKv = runnerParams.mNumHeadsQPerKv; - int32_t const tileSizeKvPerCta = kernelMeta.mStepKv; + int32_t const tileSizeKvPerCta = stepKv; // Total Q tokens (flattened across heads) int32_t const maxTotalQTokens = maxSeqLenQ * numHeadsQPerKv; @@ -253,40 +249,38 @@ void launchPrepareCustomMaskBuffersKernelForKeepsMmaAb( dim3 gridDim(batchSize, numBlocksY, numBlocksZ); dim3 blockDim(qTokensPerBlock, kvTokensPerBlock, 1); - prepareCustomMaskBuffersKernelForKeepsMmaAb<<>>(runnerParams, kernelMeta); + prepareCustomMaskBuffersKernelForKeepsMmaAb<<>>( + runnerParams, stepQ, stepKv, tileSizeQ, tileSizeKv); // Ensure adjusted firstSparse offsets are written only after all blocks finish { int const blockSize = 128; int const gridSize = (batchSize + blockSize - 1) / blockSize; - adjustFirstSparseMaskOffsetsKernel<<>>(runnerParams, kernelMeta); + adjustFirstSparseMaskOffsetsKernel<<>>(runnerParams, stepKv); } } -//////////////////////////////////////////////////////////////////////////////////////////////////// - -void runPrepareCustomMask( - TllmGenFmhaKernelMetaInfo const& kernelMeta, TllmGenFmhaRunnerParams const& runnerParams, cudaStream_t stream) +void runPrepareCustomMask(TllmGenFmhaRunnerParams const& runnerParams, FmhaKernelType kernelType, int32_t stepQ, + int32_t stepKv, int32_t tileSizeQ, int32_t tileSizeKv, cudaStream_t stream) { - if (isKeepsMmaAbForGenerationKernel(static_cast(kernelMeta.mKernelType))) + if (isKeepsMmaAbForGenerationKernel(static_cast(kernelType))) { - int cta_tile_size = kernelMeta.mStepQ * kernelMeta.mStepKv; + int cta_tile_size = stepQ * stepKv; if (cta_tile_size > 128 * 128 * 2) { TLLM_LOG_ERROR( - "TRTLLM-GEN needs larger buffer for custom mask preparation please enlarge it according to the " + "TRTLLM-GEN needs larger buffer for custom mask preparation please enlarge it according to the " "formula: tile_size_q * tile_size_k * num_instances_q * num_instances_k"); return; } // Step 1: Compute offsets on GPU using prefix sum - launchComputeCustomMaskOffsetsKernel(kernelMeta, runnerParams, stream); + launchComputeCustomMaskOffsetsKernel(runnerParams, stepQ, stepKv, stream); // Step 2: Compute custom mask buffers - launchPrepareCustomMaskBuffersKernelForKeepsMmaAb(runnerParams, kernelMeta, stream); + launchPrepareCustomMaskBuffersKernelForKeepsMmaAb(runnerParams, stepQ, stepKv, tileSizeQ, tileSizeKv, stream); TLLM_CUDA_CHECK(cudaGetLastError()); } else { - TLLM_LOG_ERROR( - "TRTLLM-GEN does not support kernel type: %d for custom mask preparation", runnerParams.mKernelType); + TLLM_LOG_ERROR("TRTLLM-GEN does not support kernel type: %d for custom mask preparation", kernelType); } } diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h index 86160a0aeafb..027ba2aace8a 100644 --- a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h @@ -15,7 +15,6 @@ */ #pragma once -#include "cubin/kernelMetaInfo.h" #include "fmhaRunnerParams.h" #include "tensorrt_llm/common/config.h" @@ -26,8 +25,8 @@ namespace kernels //////////////////////////////////////////////////////////////////////////////////////////////////// -void runPrepareCustomMask( - TllmGenFmhaKernelMetaInfo const& kernelMeta, TllmGenFmhaRunnerParams const& runnerParams, cudaStream_t stream); +void runPrepareCustomMask(TllmGenFmhaRunnerParams const& runnerParams, FmhaKernelType kernelType, int32_t stepQ, + int32_t stepKv, int32_t tileSizeQ, int32_t tileSizeKv, cudaStream_t stream); //////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaAutoTuner.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaAutoTuner.h new file mode 100644 index 000000000000..44fb40b5df52 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaAutoTuner.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "FmhaOptions.h" + +namespace fmha { + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +// Calculate the numCtasX, numCtasY and numCtasZ. +std::tuple computeNumCtas(FmhaOptions& options, + int32_t multiProcessorCount, + bool enablesLogging = true); + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +// AutoTuner to select the kernel based on the heuristics. +// We might also use performance tests to select the best one from the candidates in the future. +// Ensure that multiProcessorCount is obtained from the current device's properties; +// if it does not match the current device, FmhaAutoTuner may fail to choose the optimal Fmha +// configuration. +class FmhaAutoTuner { + +public: + // The constructor. + FmhaAutoTuner(FmhaOptions const& options, + FmhaOptionsFromArgs const& optionsFromArgs, + int32_t multiProcessorCount) + : mMultiProcessorCount(multiProcessorCount) + , mOptions(options) + , mOptionsFromArgs(optionsFromArgs) {} + +public: + // Get the mmaOpsPerClk. + static int32_t getMmaOpsPerClk(FmhaOptions const& options); + + // Select the GQA generation kernel. + void selectGqaGenerationKernel(); + + // Select the kernel and update the options. + std::tuple selectKernel(); + + // Select the MLA generation kernel. + void selectMlaGenerationKernel(); + +private: + // Enables the cgaReduction if all clusters can be launched in one wave. + void enableCgaReduction(int32_t numCtasX, int32_t numCtasY, int32_t numCtasZ); + + // Get the cluster size. + int32_t getClusterSize(); + + // Get the swapsMmaAbTileSizeQ. + int32_t getSwapsMmaAbTileSizeQ() const; + + // Get the maximum number of active clusters for a given cluster size which considers the + // floorsweeping configurations. + int32_t getMaxNumActiveClusters(int32_t clusterSize); + + // Selects the tileSizeQ for GQA generation kernels. + void selectTileSizeQForGqaGeneration(); + + // Set ctaDim. + void setCtaDim(); + + // Set mHeadDimPerStageKv. + void setHeadDimPerStageKv(); + + // Sets the kernel type and tileSizeQ for GQA generation kernels. + void setGqaKernelTypeAndTileSizeQ(); + + // Set the numInstsQ and numInstsKv. + void setNumInstsQAndKv(FmhaOptions& options, bool forceSet = false, bool updateSetFlags = true); + + // Set mNumKPartitionsMmaPv and mNumKPartitionsTileP. + void setNumKPartitionsMmaPvAndTileP(); + + // Set MMA order, interleavesMufuAndSums, and usesOrderedSequence. + void setMmaOrder(); + + // Set softmax configs. + void setSoftmaxConfigs(); + +private: + // The ctaDim. + int mCtaDim{512}; + // The multiProcessorCount. + int mMultiProcessorCount; + // The FmhaOptions. + FmhaOptions mOptions; + // The FmhaOptionsFromArgs. + FmhaOptionsFromArgs mOptionsFromArgs; +}; + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace fmha \ No newline at end of file diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaInterface.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaInterface.h new file mode 100644 index 000000000000..6d6c1d854600 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaInterface.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "FmhaOptions.h" +#include + +#ifdef TLLM_GEN_EXPORT_INTERFACE +#ifdef TLLM_GEN_EXPORT_FLASHINFER +#include "flashinferMetaInfo.h" +#endif // TLLM_GEN_EXPORT_FLASHINFER +#endif // TLLM_GEN_EXPORT_INTERFACE + +namespace fmha { +//////////////////////////////////////////////////////////////////////////////////////////////////// +// +// FmhaData +// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct FmhaData { + struct MetaData { + // The cumulative sequence lengths for Q. The shape is [batchSize + 1]. + int32_t const* cumSeqLensQPtrD; + + // The cumulative sequence lengths for K/V. The shape is [batchSize + 1], or [numHeadsKv * + // (batchSize + 1)] for sparse attention. + int32_t const* cumSeqLensKvPtrD; + + // The first sparseMask tile offset in the Kv sequence dimension, and adjusted to multiple + // of tileSizeKvPerCta. The shape is [batchSize] + int32_t const* firstSparseMaskOffsetsKvPtrD; + + // The value added to the new maximum value in case it is larger than the previous maximum. + // This way we artificially inflate the maximum value (without additional compute cost) + // to increase the probability of skip correction at next iterations of the pipeline loop. + // [0..8] is a reasonable range of values for this. + float inflateMax; + + // page indexes of Kv. The shape is [batchSize, 2, maxNumPagesPerSeqKv], or [numHeadsKv * + // batchSize, 2, maxNumPagesPerSeqKv] for sparse attention. + int32_t const* kvPageIdxD; + + // The sequence lengths of K/V. The shape is [batchSize], or [numHeadsKv * batchSize] for sparse + // attention. + int32_t const* seqLensKvD; + + // Start token index in the O scaling-factor tensor. Used for FP4 SF offset in generation when + // inflight batching is enabled (TRT-LLM). Context uses 0. + int32_t startTokenIdxSfO{0}; + }; + + struct Scales { + // FP4 scaling factors for KV cache + void const* kSfBasePtr; + void const* vSfBasePtr; + + // FP4 scaling factors for input/output + float kvSfScale; + float oSfScale; + float const* kvSfScaleD; + float const* oSfScaleD; + + // output scale for FP8 per tensor attention + float const* outputScaleD; + + // Sage Attn scaling factors for Q, K, P, V + float const* sageAttnSfsQPtrD; + float const* sageAttnSfsKPtrD; + float const* sageAttnSfsPPtrD; + float const* sageAttnSfsVPtrD; + + // The scaling factor applied after Q*K^T (i.e. 1/sqrt(headDim). + float softmaxScale; + float const* scaleSoftmaxLog2D; + + // FP4 scaling factors for O + void* oSfPtrD; + }; + + struct InputBuffers { + // The input tensor for Q. The shape is [sumOfSeqLensQ, hiddenDimQ] + void const* qBasePtr; + + // The input tensor for K, V. The shape is [sumOfSeqLensKv, hiddenDimKv] or + // [sumOfSeqLensKv * numHeadsKv, hiddenDimKv] for sparse attention. + void const* kBasePtr; + void const* vBasePtr; + + // Attention sinks + float const* attentionSinksPtrD; + + // Custom mask + uint32_t const* customMaskPtrD; + int64_t const* customMaskOffsetsPtrD; + }; + + struct OutputBuffers { + // Device counters used to synchronize CTAs before the final reduction in multiCtasKvMode. + int32_t* multiCtasKvCounterPtrD; + + // Partial output and softmaxStats for each CtaKv when the multiCtasKv mode is enabled. + void* partialOPtrD; + float2* partialStatsPtrD; + + // Skip-softmax statistics. + int* skipSoftmaxStatsPtrD; + + // Softmax stats. + float2* softmaxStatsD; + + // Debug + void* oDebugPtrD; + + // The output tensor for O. The shape is [sum(seqLensQ), hiddenDimO] + void* oPtrD; + + }; + + MetaData mMetaData; + Scales mScales; + InputBuffers mInputBuffers; + OutputBuffers mOutputBuffers; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// +// FmhaInterface +// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +class FmhaInterface { +public: + using ModuleCache = std::unordered_map>; + + FmhaInterface(bool exportsCubin = false, int32_t numRotations = 1, bool verbose = false) + : mExportsCubin(exportsCubin) + , mNumRotations(numRotations) + , mVerbose(verbose) { + setVerbose(verbose); + } + + // Set the verbosity level for logging. When false, TLLM_LOG_INFO messages are suppressed. + void setVerbose(bool verbose); + + void generateAndCompileKernel(FmhaConfig& fmhaConfig) const; + + std::string getKernelName(FmhaConfig const& fmhaConfig) const; + + int32_t run(FmhaConfig const& config, + FmhaData& data, + cudaStream_t cudaStream, + int32_t multiProcessorCount, + int32_t rotatedKernelInstanceIdx) const; + +private: + // Whether to export the cubin file. + bool mExportsCubin; + // The number of rotations + int32_t mNumRotations; + // Whether to log info messages. + bool mVerbose; +}; + +} // namespace fmha diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaOptions.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaOptions.h new file mode 100644 index 000000000000..15b5eef22f80 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/FmhaOptions.h @@ -0,0 +1,546 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "KernelTraits.h" +#include +#include +#include +#include +#include + +namespace fmha { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// FmhaOptions class. +// Inherits from KernelConfigBase to share common configuration variables with KernelConfig. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct FmhaOptions : public KernelConfigBase { + // Relative error tolerance. + float mAtol{1e-2f}; + // Attention windows size of sliding window attention. Disabled by default. + int mAttentionWindowSize{0}; + // Batch size. + int mBatchSize{2}; + // Whether to verify the correctness. 0: No check, 1: partial, 2: full. + int mChecksResults{2}; + // The chunked attention size (default 0 means no chunking). + int mChunkedAttentionSize{0}; + // Dry-run: print a log but does not actually generate anything + bool mDryRun{false}; + // Enable the auto tuner. + bool mEnablesAutoTuner{false}; + // Whether is exporting cubin. + bool mIsExportingCubin{false}; + + // Whether running inside TRTLLM (affects KV stride computation for MLA). + bool mIsTrtllmLayout{false}; + // Whether the kernel is under tracing + bool mIsTracing{false}; + // The maximum number of CTAs per sequenceKv (multiCtasKvMode). + // This is used to limit the number of CTAs per sequenceKv for the multiCtasKvMode. + int mMaxNumCtasPerSeqKv{INT_MAX}; + // The maximum number of CTAs for Q. + int mMaxNumCtasQ{1}; + // The maximum number of CTAs for K/V. + int mMaxNumCtasKv{1}; + // The maximum number of pages per sequence in the paged-kv buffer. + int mMaxNumPagesPerSeqKv{512 / 32}; + // Sequence length for Q and K/V. + int mMaxSeqLenQ{512}, mMaxSeqLenKv{512}; + // The minimum first sparseMask offset in the Kv sequence dimension. + // Default 0 means that all tokensKv need custom masking. + int mMinFirstSparseMaskOffsetKv{0}; + // The minimum sequence length (used to generate variable Q sequence length). + int mMinSeqLenQ{INT_MAX}; + // The minimum sequence length (used to generate variable Kv sequence length). + int mMinSeqLenKv{INT_MAX}; + // Benchmark steps. + int mNumBenchmarkSteps{1}; + // The number of Ctas per sequenceKv from the arguments. + // It is used to fine-tune the multiCtasKvMode performance. + int mNumCtasPerSeqKv{-1}; + // The number of loop iterations for schedulePrinter, which can helps identify deadlocks. + int mNumLoopItersForPrint{2}; + // The number of pages in memory pool. + int mNumPagesInMemPool{0}; + // The number of causal-mask spec-decoding tokens (it is fixed in the batch). + int mNumSpecDecodingTokens{0}; + // Warmup steps. + int mNumWarmUpSteps{0}; + // The maximum number of waves for the multiCtasKvMode. + int mMaxNumWavesForCtasKvMode{1}; + // The attention output scale. + float mOutputScale{1.f}; + // Relative error tolerance. + float mRtol{1e-1f}; + // Whether to skip kernel generation (for debug purpose). + bool mSkipsKernelGen{false}; + // The threshold to skip softmax operations when possible according to the below expression. + float mSkipSoftmaxThresholdScaleFactor{0}; + // The topK value for sparse MLA kernel. + int mSparseMlaTopK{2048}; + // The sum of sequence lengths for Q and K/V. + int mSumOfSeqLensQ{512 * 2}, mSumOfSeqLensKv{512 * 2}; + // Whether the indices for K & V pages are shared as unified index (vLLM/FlashInfer). + bool mUsesSharedPagedKvIdx{false}; + // Level of verbose information. + int mVerbosity{1}; + + // Convert the fmhaOptions to a JSON object. + void toJson(nlohmann::json& j) const { + // First, serialize the base class members. + KernelConfigBase::toJson(j); + + // Then, serialize the FmhaOptions-specific members. + TO_JSON(mAtol); + TO_JSON(mAttentionWindowSize); + TO_JSON(mBatchSize); + TO_JSON(mChecksResults); + TO_JSON(mChunkedAttentionSize); + TO_JSON(mDryRun); + TO_JSON(mEnablesAutoTuner); + TO_JSON(mIsExportingCubin); + TO_JSON(mIsTracing); + TO_JSON(mMaxNumCtasPerSeqKv); + TO_JSON(mMaxNumCtasQ); + TO_JSON(mMaxNumCtasKv); + TO_JSON(mMaxNumPagesPerSeqKv); + TO_JSON(mMaxSeqLenQ); + TO_JSON(mMaxSeqLenKv); + TO_JSON(mMinFirstSparseMaskOffsetKv); + TO_JSON(mMinSeqLenQ); + TO_JSON(mMinSeqLenKv); + TO_JSON(mNumBenchmarkSteps); + TO_JSON(mNumCtasPerSeqKv); + TO_JSON(mNumLoopItersForPrint); + TO_JSON(mNumPagesInMemPool); + TO_JSON(mNumSpecDecodingTokens); + TO_JSON(mNumWarmUpSteps); + TO_JSON(mMaxNumWavesForCtasKvMode); + TO_JSON(mOutputScale); + TO_JSON(mRtol); + TO_JSON(mSkipsKernelGen); + TO_JSON(mSkipSoftmaxThresholdScaleFactor); + TO_JSON(mSparseMlaTopK); + TO_JSON(mSumOfSeqLensQ); + TO_JSON(mSumOfSeqLensKv); + TO_JSON(mUsesSharedPagedKvIdx); + TO_JSON(mVerbosity); + } + +#undef TO_JSON +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +struct FmhaOptionsFromArgs { + // Relative error tolerance. + bool mIsAtolSet{false}; + // The head dimension per stage for Kv. + bool mIsHeadDimPerStageKvSet{false}; + // The head dimension for Q and K. + bool mIsHeadDimQkSet{false}; + // The head dimension for Q and K. + bool mIsHeadDimVSet{false}; + // Whether to interleave MUFU and sums. + bool mIsInterleavesMufuAndSumsSet{false}; + // Whether to use interleaved SF layout for tileV. (Only valid when KV cache is NVFP4). + bool mIsInterleaveSfVSet{false}; + // The MMA order. + bool mIsMmaOrderSet{false}; + // The number of delayed cvt elts. + bool mIsNumDelayedCvtEltsSet{false}; + // The number of instances for Kv. + bool mIsNumInstsKvSet{false}; + // The number of instances for Q. + bool mIsNumInstsQSet{false}; + // The number of leading exp elts. + bool mIsNumLeadingExpEltsSet{false}; + // The number of prefetched fmas. + bool mIsNumPrefetchedFmasSet{false}; + // Relative error tolerance. + bool mIsRtolSet{false}; + // Tile scheduler type. + bool mIsTileSchedulerSet{false}; + // Whether to use an ordered sequence between softmax0 and softmax1. + bool mIsUsesOrderedSequenceSet{false}; + // The tileSize for Q. + bool mIsTileSizeQSet{false}; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// +// FmhaConfig +// +//////////////////////////////////////////////////////////////////////////////////////////////////// +struct FmhaConfig { + // The generated configuration JSON string. + std::string mGenCfgJsonStr{""}; + // The function name of the kernel. + std::string mFunctionName{""}; + // The execution path of the kernel. + char const* mExecPath{nullptr}; + // The CUDA runner. + tg::CudaRunner* mCudaRunner{nullptr}; + // The GenCfg object. + tg::GenCfg* mGenCfg{nullptr}; + // The number of threads per CTA. + int32_t mCtaDim{0}; + // The grid dimensions. + tg::CudaRunner::Grid mGrid; + // The cluster dimensions. + tg::CudaRunner::Cluster mCluster; + // The Fmha options. + FmhaOptions mOptions{}; + // The CUDA architecture. + tg::CudaArch mSm{tg::CudaArch::Sm100a}; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Check if the options are valid or not. +inline void checkFmhaOptions(FmhaOptions const& options, + FmhaOptionsFromArgs const& optionsFromArgs) { + TLLM_CHECK_ERROR(!(options.mGroupsHeadsQ && isPackedQkv(options.mQkvLayout)), + "Grouping Q heads doesn't work with the packedQkv layout"); + // Only mNumInstsQ = 2, mNumInstsKv = 1 or mNumInstsQ = 1, mNumInstsKv = 2 or mNumInstsQ == 1, + // mNumInstsKv == 1 are supported. + TLLM_CHECK_ERROR(((options.mNumInstsQ * options.mNumInstsKv) <= 2), + "Only two tile instances are supported"); + + // The number of instances for Q and Kv must be set together. + TLLM_CHECK_ERROR(optionsFromArgs.mIsNumInstsQSet == optionsFromArgs.mIsNumInstsKvSet, + "The number of instances for Q and Kv must be set together"); + + // Do we swap A/B for the generation kernel. + bool const swapsMmaAb{isSwapsMmaAbForGenerationKernel(options.mFmhaKernelType)}; + // Check if tileSizeQ is valid. + if (swapsMmaAb) { + // NumHeadsQ can be distributed to multiple CTAs for MQA kernels. + TLLM_CHECK_ERROR(options.mNumHeadsKv == 1 || options.mNumHeadsQPerKv <= 64, + "The number of heads per group cannot exceed 64"); + } + + // Check if the tileSizeKv is valid or not. + int32_t tileSizeKv = options.mTileSizeKv; + if (swapsMmaAb) { + TLLM_CHECK_ERROR(tileSizeKv == 128 || tileSizeKv == 64, + "The SwapsMmaAbForGeneration kernels only support tileSizeKv 64 or 128"); + } else { + // TileSizeKv must be a power of 2. + bool const isPowOf2{(tileSizeKv & (tileSizeKv - 1)) == 0}; + int const maxTileSizeKv = tg::isArchHopper(options.mCudaArch) ? 256 : 128; + TLLM_CHECK_ERROR(tileSizeKv >= 16 && tileSizeKv <= maxTileSizeKv && isPowOf2, "Not supported"); + } + + // Check if head dim is valid. + auto headDimQk{options.mHeadDimQk}, headDimV{options.mHeadDimV}; + if (swapsMmaAb && headDimQk == headDimV) { + TLLM_CHECK_ERROR(headDimQk == 64 || headDimQk == 128 || headDimQk == 256, + "The headDim must be 64 or 128 or 256"); + } + // MLA kernels. + if (headDimQk != headDimV) { + if (tg::isArchHopper(options.mCudaArch)) { + TLLM_CHECK_ERROR(headDimQk > headDimV, + "Only headDimQk > headDimV MLA kernels have been verified for Hopper"); + } else { + if (isContextKernel(options.mFmhaKernelType)) { + TLLM_CHECK_ERROR(headDimQk == 192 && headDimV == 128, + "Only headDimQk = 192, headDimV = 128 MLA kernels have been verified"); + } else { + TLLM_CHECK_ERROR(options.mIsMlaGen && ((headDimQk == 576 && headDimV == 512) || + (headDimQk == 320 && headDimV == 256)), + "Only headDimQk = 576, headDimV = 512 or headDimQk = 320, headDimV = 256 " + "MLA kernels have been verified"); + } + } + } + + // Check if headDimPerCtaV is valid. + if (options.mHeadDimPerCtaV != options.mHeadDimV && options.mHeadDimPerCtaV != 0 && + options.mHeadDimPerStageKv != 0) { + // The number of elements per CTA must be a multiple of the number of elements per stage. + TLLM_CHECK_ERROR(options.mHeadDimPerCtaV % options.mHeadDimPerStageKv == 0, + "mHeadDimPerStageKv=", + options.mHeadDimPerStageKv, + " must divide mHeadDimPerCtaV=", + options.mHeadDimPerCtaV); + // The head dimension must be a multiple of the number of elements per CTA. + TLLM_CHECK_ERROR(options.mHeadDimV % options.mHeadDimPerCtaV == 0, + "mHeadDimPerCtaV=", + options.mHeadDimPerCtaV, + " must divide mHeadDimV=", + options.mHeadDimV); + } + + // Check if headDimPerStageKv is valid. + if (swapsMmaAb && (options.mHeadDimQk > 128 || options.mHeadDimV > 128) && + tg::isArchBlackwell(options.mCudaArch) && optionsFromArgs.mIsHeadDimPerStageKvSet) { + TLLM_CHECK_ERROR( + options.mHeadDimPerStageKv == 128, + "HeadDimPerStageKv must be 128 for swapsMmaAbForGeneration kernels on Blackwell"); + } + + // Make sure the 2Cta option is valid. + if (options.mClusterDimX == 2) { + // Note that the tileSizeQ and tileSizeKv should be the tileSizes of D in BMM1. + TLLM_CHECK_ERROR(options.mTileSizeQ == 64, "The tileSizeQ must be 64 for 2Cta option"); + TLLM_CHECK_ERROR(options.mTileSizeKv == 128 || options.mTileSizeKv == 256, + "The tileSizeKv must be 128 or 256 for 2Cta option"); + } + + // Make sure numSpecDecodingTokens is only enabled with causal-mask/custom-mask spec-decoding + // kernels. + if (options.mNumSpecDecodingTokens > 1) { + // Make sure it is causal-mask spec-decoding kernel. + TLLM_CHECK_ERROR( + options.mIsCausalSpecDecodingGen || options.mIsCustomSpecDecodingGen, + "The numSpecDecodingTokens > 1 requires causal-mask/custom-mask spec-decoding kernels"); + // Make sure it is not a context-phase kernel. + TLLM_CHECK_ERROR(!isContextKernel(options.mFmhaKernelType), + "The numSpecDecodingTokens > 1 requires generation-phase kernels"); + } + + // Make sure ReuseSMemKForV option is valid. + if (options.mReuseSmemKForV) { + TLLM_CHECK_ERROR(options.mIsMlaGen && swapsMmaAb, + "Only MlaGen kernels support reusing smemK for V."); + TLLM_CHECK_ERROR( + options.mHeadDimV == options.mHeadDimPerCtaV || options.mHeadDimPerCtaV == 0, + "Spliting headDimV across multiple CTAs doesn't work with reusing smemK for V."); + TLLM_CHECK_ERROR((tg::dtypeGetNumBits(options.mDtypeKv) * options.mTileSizeKv) <= + 8 * 128 /*16*64*/, + "The shared memory size is not sufficient to support reusing smemK for V. " + "Consider using smaller tileSizeKv."); + } + +#ifdef TLLM_PUBLIC_RELEASE + if (options.mDtypeKv == tg::Dtype::E2m1 && !options.mIsTrtllmLayout) { + TLLM_CHECK_ERROR(false, "E2m1 KV cache is not supported with public compiler."); + } +#endif // TLLM_PUBLIC_RELEASE + + // PackedQkv layout does not support supportsDiffSeqLensForQAndKv. + TLLM_CHECK_ERROR(!(isPackedQkv(options.mQkvLayout) && options.mSupportsDiffSeqLensForQAndKv), + "PackedQkv layout does not support supportsDiffSeqLensForQAndKv"); + // Q does not support E2m1 dtype. + TLLM_CHECK_ERROR(options.mDtypeQ != tg::Dtype::E2m1, "Q does not suppot E2m1 dtype"); + // Make sure correct attention window size is set. + TLLM_CHECK_ERROR(!isSlidingOrChunkedCausalMask(options.mMaskType) || + options.mAttentionWindowSize > 0 || options.mChunkedAttentionSize > 0, + "Please set correct sliding attention window size or chunked attention size"); + if (options.mChunkedAttentionSize > 0) { + TLLM_CHECK_ERROR(options.mAttentionWindowSize >= options.mMaxSeqLenKv, + "sliding attention window size must be greater than or equal to maxSeqLenKv"); + TLLM_CHECK_ERROR(options.mChunkedAttentionSize % (options.mTileSizeKv * options.mNumInstsKv) == + 0, + "Chunked attention size must be a multiple of the tileSizePerCtaKv"); + TLLM_CHECK_ERROR((options.mChunkedAttentionSize & (options.mChunkedAttentionSize - 1)) == 0, + "Chunked attention size must be power of 2"); + } + + // Special options for FP4. + if (options.mDtypeOut == tg::Dtype::E2m1) { + // FP4 output only supports fuseEpilogueIntoCorr. + TLLM_CHECK_ERROR(options.mFuseEpilogueIntoCorr, + "FP4 output only supports fuseEpilogueIntoCorr"); + // Make sure the number of sf per row can be divided by 4, required for interleaved SF layout. + // Details can be seen in DtypeUtils.h: E2m1Utils::getSfOffset. + int32_t hiddenDim = options.mNumHeadsQ * headDimQk; + auto kernelTraits = getKernelTraitsFromOptions(options); + TLLM_CHECK_ERROR((hiddenDim / kernelTraits.mNumEltsPerSf) % 4 == 0, + "Current hiddenDim is not supported for FP4 output"); + } + + // If we decide to use Sage Attention, the number of elements per block must be a power-of-two. + if (options.mNumEltsPerSageAttnBlkQ != 0) { + int numEltsPerBlk{options.mNumEltsPerSageAttnBlkQ}; + TLLM_CHECK_ERROR((numEltsPerBlk & (numEltsPerBlk - 1)) == 0, + "mNumEltsPerSageAttnBlkQ=", + options.mNumEltsPerSageAttnBlkQ, + " must be a power-of-two (or 0)"); + } + if (options.mNumEltsPerSageAttnBlkK != 0) { + int numEltsPerBlk{options.mNumEltsPerSageAttnBlkK}; + TLLM_CHECK_ERROR((numEltsPerBlk & (numEltsPerBlk - 1)) == 0, + "mNumEltsPerSageAttnBlkK=", + options.mNumEltsPerSageAttnBlkK, + " must be a power-of-two (or 0)"); + } + if (options.mNumEltsPerSageAttnBlkP != 0) { + int numEltsPerBlk{options.mNumEltsPerSageAttnBlkP}; + TLLM_CHECK_ERROR((numEltsPerBlk & (numEltsPerBlk - 1)) == 0, + "mNumEltsPerSageAttnBlkP=", + options.mNumEltsPerSageAttnBlkP, + " must be a power-of-two (or 0)"); + } + if (options.mNumEltsPerSageAttnBlkV != 0) { + int numEltsPerBlk{options.mNumEltsPerSageAttnBlkV}; + TLLM_CHECK_ERROR((numEltsPerBlk & (numEltsPerBlk - 1)) == 0, + "mNumEltsPerSageAttnBlkV=", + options.mNumEltsPerSageAttnBlkV, + " must be a power-of-two (or 0)"); + } + + // The CGA reduction. + if (isCgaSmemReduction(options.mMultiCtasKvMode)) { + TLLM_CHECK_ERROR(options.mTileScheduler == TileScheduler::Static, + "CGA reduction is only supported with static tile scheduler."); + } + + // Make sure block sparse attention is only enabled with paged Kv layout. + if (options.mUseBlockSparseAttention) { + TLLM_CHECK_ERROR(isPagedKv(options.mQkvLayout), + "Block sparse attention is only supported with paged Kv layout."); + } + + // Currently, for performance reason, only numTokensPerPage >= tileSizeKv is supported for + // dynamic numTokensPerPage. + if (options.mDynamicNumTokensPerPage) { + TLLM_CHECK_ERROR(options.mNumTokensPerPage >= options.mTileSizeKv, + "NumTokensPerPage must be larger than or equal to tileSizeKv"); + } + + // Make sure the multiCtasKvMode is valid if numCtasPerSeqKv is set. + if (options.mNumCtasPerSeqKv > 1) { + TLLM_CHECK_ERROR(!isDisabled(options.mMultiCtasKvMode), + "Please set the correct multiCtasKvMode for numCtasPerSeqKv > 1."); + } + + // The sparseMla kernels. + if (options.mIsSparseMla) { + TLLM_CHECK_ERROR(isPagedKv(options.mQkvLayout), + "PagedKv layout is required for sparse MLA kernels."); + TLLM_CHECK_ERROR(options.mSparseMlaTopK % 4 == 0, + "SparseMlaTopK must be a multiple of 4 in order to use 16bytes cpAsync loads"); + } + + // Always enable skipsSoftmaxWhenPossible for outputSkipSoftmaxStats. + if (options.mOutputSkipSoftmaxStats) { + TLLM_CHECK_ERROR(options.mSkipsSoftmaxWhenPossible, + "The outputSkipSoftmaxStats option requires skipsSoftmaxWhenPossible to be " + "enabled."); + } + + // For headDim 256, mixed precision Qkv or tileSizeQ = 128 requires numInstsQ == 1 and numInstsKv + // == 1. + if (options.mHeadDimQk == 256 && options.mHeadDimV == 256 && optionsFromArgs.mIsNumInstsQSet && + optionsFromArgs.mIsNumInstsKvSet) { + if (options.mDtypeQ != options.mDtypeKv || + (optionsFromArgs.mIsTileSizeQSet && options.mTileSizeQ == 128)) { + TLLM_CHECK_ERROR(options.mNumInstsQ == 1 && options.mNumInstsKv == 1, + "For headDim 256, mixed precision (dtypeQ != dtypeKv) or tileSizeQ = 128 " + "requires numInstsQ == " + "1 and numInstsKv == 1."); + } + } + + // The mGroupsTokensHeadsQ only works with GQA generation kernels. + if (options.mGroupsTokensHeadsQ) { + TLLM_CHECK_ERROR(!isContextKernel(options.mFmhaKernelType), + "mGroupsTokensHeadsQ should only be enabled for generation kernels."); + TLLM_CHECK_ERROR(options.mDtypeKv != tg::Dtype::E2m1, + "mGroupsTokensHeadsQ doesn't work with E2m1 dtypeKv."); + TLLM_CHECK_ERROR(!options.mIsMlaGen, + "MLA gen kernels haven't supported mGroupsTokensHeadsQ yet."); + } + + + + if (options.mMmaOrder != MmaOrder::Pv0_Qk0_Pv1_Qk1) { + TLLM_CHECK_ERROR(options.mNumInstsQ == 2, + "MMA order ", + mmaOrderToString(options.mMmaOrder), + " is only supported with numInstsQ == 2."); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Update the fmha options if needed. +inline void updateFmhaOptions(FmhaOptions& options, FmhaOptionsFromArgs const& optionsFromArgs) { + // Set default absolute/relative tolerance for different data types. + if ((options.mDtypeQ == tg::Dtype::Fp16) || (options.mDtypeQ == tg::Dtype::Bfloat16)) { + // Use smaller tolerance for float16/bfloat16 if it is not set. + if (options.mDtypeOut == tg::Dtype::E4m3) { + if (!optionsFromArgs.mIsAtolSet) { + options.mAtol = 2e-2f; + } + if (!optionsFromArgs.mIsRtolSet) { + options.mRtol = 2e-3f; + } + } else if (options.mDtypeOut == tg::Dtype::E2m1) { + if (!optionsFromArgs.mIsAtolSet) { + options.mAtol = 0.15f; + } + if (!optionsFromArgs.mIsRtolSet) { + options.mRtol = 0.01f; + } + } else { + if (!optionsFromArgs.mIsAtolSet) { + options.mAtol = 5e-3f; + } + if (!optionsFromArgs.mIsRtolSet) { + options.mRtol = 1e-3f; + } + } + } else if (options.mDtypeKv == tg::Dtype::E2m1) { + if (!optionsFromArgs.mIsAtolSet) { + options.mAtol = 0.3f; + } + if (!optionsFromArgs.mIsRtolSet) { + options.mRtol = 0.1f; + } + } else if (options.mDtypeOut == tg::Dtype::E2m1) { + if (!optionsFromArgs.mIsAtolSet) { + options.mAtol = 0.15f; + } + if (!optionsFromArgs.mIsRtolSet) { + options.mRtol = 0.1f; + } + } + TLLM_LOG_TRACE("Reference atol = ", options.mAtol, ", rtol = ", options.mRtol, " is used."); + + // + // Update sequence lengths parameters. + // + + // Update maxSeqLenQ. + if (options.mSingleTokenQ) { + options.mMaxSeqLenQ = 1; + } + + // Update minSeqLenQ, minSeqLenK. + options.mMinSeqLenQ = std::min(options.mMinSeqLenQ, options.mMaxSeqLenQ); + options.mMinSeqLenKv = std::min(options.mMinSeqLenKv, options.mMaxSeqLenKv); + + // Check if sequence lengths are valid. + TLLM_CHECK_ERROR(options.mMinSeqLenQ > 0 && options.mMinSeqLenKv > 0, + "Invalid sequence lengths."); + + // Enable variable sequence if minSeqLenQ < maxSeqLenQ or minSeqLenKv < maxSeqLenKv. + options.mSupportsVarSeqLens |= + (options.mMinSeqLenQ < options.mMaxSeqLenQ) || (options.mMinSeqLenKv < options.mMaxSeqLenKv); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace fmha diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelConfigBase.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelConfigBase.h new file mode 100644 index 000000000000..fb375ccdffcc --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelConfigBase.h @@ -0,0 +1,659 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#ifndef TLLM_FMHA_TRTLLM_COMPAT +#include +#endif // TLLM_FMHA_TRTLLM_COMPAT +#include +#include +#include +#include +#include + +namespace tg = trtllm::gen; + +namespace fmha { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// When TLLM_FMHA_TRTLLM_COMPAT is defined, enum types, toString specializations, and utility +// functions are provided by trtllmGenExportCompat.h instead (using TRT-LLM type aliases). +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TLLM_FMHA_TRTLLM_COMPAT + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Macros to simplify JSON serialization +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TO_JSON +#define TO_JSON(field) j[#field] = toString(field); +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// Enum types. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +enum class AttentionMaskType { + // Dense mask. + Dense = 0, + // Causal mask. + Causal, + // Sliding window causal mask or chunked attention causal mask. + SlidingOrChunkedCausal, + // Custom mask. + Custom +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper functions to check the mask type. + +#define ATTENTION_MASK_TYPE_FUNCTION(MaskType) \ + __host__ __device__ inline bool is##MaskType##Mask(AttentionMaskType maskType) { \ + return (maskType == AttentionMaskType::MaskType); \ + } + +ATTENTION_MASK_TYPE_FUNCTION(Dense) +ATTENTION_MASK_TYPE_FUNCTION(Causal) +ATTENTION_MASK_TYPE_FUNCTION(SlidingOrChunkedCausal) +ATTENTION_MASK_TYPE_FUNCTION(Custom) + +#undef ATTENTION_MASK_TYPE_FUNCTION + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +enum class FmhaKernelType { + // The context-phase kernels. + Context = 0, + // Choose the best generation kernel based on the heuristic: + // use SwapsMmaAbForGeneration kernels when numTokensQ (including grouped + // headsQ) <= 16, otherwise not. + Generation, + // Swap tensor A and tensor B of Mma, which only supports numTokensQ (including grouped headsQ) + // up to 16. + SwapsMmaAbForGeneration, + // Keep tensor A and tensor B of Mma when there are enough numTokensQ (including grouped + // headsQ) for the softmaxTask warps and correctionTask warps + // in order to make sure all threads have work to do. + KeepsMmaAbForGeneration +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper functions to check the fmha kernel type. + +#define FMHA_KERNEL_TYPE_FUNCTION(KernelType) \ + __host__ __device__ inline bool is##KernelType##Kernel(FmhaKernelType kernelType) { \ + return (kernelType == FmhaKernelType::KernelType); \ + } + +FMHA_KERNEL_TYPE_FUNCTION(Context) +FMHA_KERNEL_TYPE_FUNCTION(Generation) +FMHA_KERNEL_TYPE_FUNCTION(SwapsMmaAbForGeneration) +FMHA_KERNEL_TYPE_FUNCTION(KeepsMmaAbForGeneration) + +#undef FMHA_KERNEL_TYPE_FUNCTION + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This enum defines the order of operations in each iteration of the MMA main loop. +// Only used when numInstsQ == 2. +enum class MmaOrder { + // 2 instances: PV0[i] - QK0[i+1] - PV1[i] - QK1[i+1]. + Pv0_Qk0_Pv1_Qk1 = 0, + // 2 instances: QK0[i+1] - PV0[i] - QK1[i+1] - PV1[i]. + Qk0_Pv0_Qk1_Pv1, + // 2 instances: QK0[i+1] - QK1[i+1] - PV0[i] - PV1[i]. + Qk0_Qk1_Pv0_Pv1, +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline std::string mmaOrderToString(MmaOrder mmaOrder) { + switch (mmaOrder) { + case MmaOrder::Pv0_Qk0_Pv1_Qk1: + return "Pv0_Qk0_Pv1_Qk1"; + case MmaOrder::Qk0_Pv0_Qk1_Pv1: + return "Qk0_Pv0_Qk1_Pv1"; + case MmaOrder::Qk0_Qk1_Pv0_Pv1: + return "Qk0_Qk1_Pv0_Pv1"; + default: + assert(false); + return "Invalid MmaOrder"; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline MmaOrder stringToMmaOrder(const char* str) { + if (!strcmp(str, "Pv0_Qk0_Pv1_Qk1")) { + return MmaOrder::Pv0_Qk0_Pv1_Qk1; + } else if (!strcmp(str, "Qk0_Pv0_Qk1_Pv1")) { + return MmaOrder::Qk0_Pv0_Qk1_Pv1; + } else if (!strcmp(str, "Qk0_Qk1_Pv0_Pv1")) { + return MmaOrder::Qk0_Qk1_Pv0_Pv1; + } else { + assert(false); + return MmaOrder::Pv0_Qk0_Pv1_Qk1; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The multiCtasKvMode. +enum class MultiCtasKvMode { + // Disable the multiCtasKvMode. + Disabled = 0, + // Do the reduction through the global memory and atomic counters. + GmemReduction, + // Same as GmemReduction, but use a separate kernel for the reduction. + // It is only supported/needed for 2-CTA or 1-CTA keepsMmaAbForGeneration MLA kernels with large + // reduction tiles. + GmemReductionWithSeparateKernel, + // Do the reduction through the CGA remote shared memory. + CgaSmemReduction +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper functions to check the multiCtasKvMode. +#define MULTI_CTAS_KV_MODE_FUNCTION(Mode) \ + __host__ __device__ inline bool is##Mode(MultiCtasKvMode multiCtasKvMode) { \ + return (multiCtasKvMode == MultiCtasKvMode::Mode); \ + } + +MULTI_CTAS_KV_MODE_FUNCTION(Disabled) +MULTI_CTAS_KV_MODE_FUNCTION(GmemReduction) +MULTI_CTAS_KV_MODE_FUNCTION(GmemReductionWithSeparateKernel) +MULTI_CTAS_KV_MODE_FUNCTION(CgaSmemReduction) + +#undef MULTI_CTAS_KV_MODE_FUNCTION + +// Helper functions to check if the multiCtasKvMode is supported. +__host__ __device__ inline bool supportsMultiCtasKvMode(MultiCtasKvMode multiCtasKvMode) { + return (multiCtasKvMode != MultiCtasKvMode::Disabled); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline std::string multiCtasKvModeToString(MultiCtasKvMode multiCtasKvMode) { + switch (multiCtasKvMode) { + case MultiCtasKvMode::Disabled: + return "Disabled"; + case MultiCtasKvMode::GmemReduction: + return "GmemReduction"; + case MultiCtasKvMode::GmemReductionWithSeparateKernel: + return "GmemReductionWithSeparateKernel"; + case MultiCtasKvMode::CgaSmemReduction: + return "CgaSmemReduction"; + default: + TLLM_LOG_ERROR("Unsupported multiCtasKvMode."); + return ""; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline MultiCtasKvMode stringToMultiCtasKvMode(const char* str) { + if (!strcmp(str, "disabled")) { + return MultiCtasKvMode::Disabled; + } else if (!strcmp(str, "gmemReduction")) { + return MultiCtasKvMode::GmemReduction; + } else if (!strcmp(str, "gmemReductionWithSeparateKernel")) { + return MultiCtasKvMode::GmemReductionWithSeparateKernel; + } else if (!strcmp(str, "cgaSmemReduction")) { + return MultiCtasKvMode::CgaSmemReduction; + } else { + TLLM_LOG_ERROR("Unsupported multiCtasKvMode ", str); + return MultiCtasKvMode::Disabled; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Note that (batchSize, seqLen) dimensions will be packed as sumOfSeqLens without paddings for +// variable sequence lengths. +enum class QkvLayout { + // Separate Q, K and V buffers. The shape is [batchSize, seqLen, numHeads, headDim]. + SeparateQkv = 0, + // Single buffer for Q, K and V. Shape: [batchSize, seqLen, numHeadsQ + 2*numHeadsKv, headDim]. + PackedQkv, + // Paged buffer for K and V. Its shape is [batchSize, 2, maxNumPagesPerSeq] where 2 corresponds + // to K and V. That buffer stores the logical page indices of the paged-KV memory pool. Each + // "page" of that pool is a contiguous buffer of shape [numHeadsKv, pageSize, headDim]. + PagedKv, + // Contiguous buffer for Q with shape [batchSize, seqLen, numHeads, headDim] and contiguous buf- + // fer for K/V with shape [batchSize, 2, numHeads, maxSeqLen, headDim]. + ContiguousKv, +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper functions to check the QkvLayout type. + +#define QKV_LAYOUT_FUNCTION(LayoutType) \ + __host__ __device__ inline bool is##LayoutType(QkvLayout qkvLayout) { \ + return (qkvLayout == QkvLayout::LayoutType); \ + } + +QKV_LAYOUT_FUNCTION(SeparateQkv) +QKV_LAYOUT_FUNCTION(PackedQkv) +QKV_LAYOUT_FUNCTION(PagedKv) +QKV_LAYOUT_FUNCTION(ContiguousKv) + +#undef QKV_LAYOUT_FUNCTION + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline std::string qkvLayoutToString(QkvLayout qkvLayout) { + switch (qkvLayout) { + case QkvLayout::SeparateQkv: + return "SeparateQkv"; + case QkvLayout::PackedQkv: + return "PackedQkv"; + case QkvLayout::PagedKv: + return "PagedKv"; + case QkvLayout::ContiguousKv: + return "ContiguousKv"; + default: + TLLM_LOG_ERROR("Unsupported qkv layout."); + return ""; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +enum class TileScheduler { + // Static scheduler (Non-persistent). + Static = 0, + // Persistent scheduler. + Persistent +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template __host__ __device__ inline T ceilDiv(T m, T n) { + return (m + n - 1) / n; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// Serialization helpers (toString functions). +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Generic toString for numeric types. +template inline std::string toString(T e) { + return std::to_string(e); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(bool flag) { + return (flag ? "true" : "false"); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(AttentionMaskType e) { + switch (e) { + case AttentionMaskType::Dense: + return "Dense"; + case AttentionMaskType::Causal: + return "Causal"; + case AttentionMaskType::SlidingOrChunkedCausal: + return "SlidingOrChunkedCausal"; + case AttentionMaskType::Custom: + return "Custom"; + default: + TLLM_LOG_ERROR("Unsupported enum."); + return ""; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(tg::CudaArch arch) { + return tg::cudaArchToString(arch); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(FmhaKernelType e) { + switch (e) { + case FmhaKernelType::Context: + return "Context"; + case FmhaKernelType::Generation: + return "Gen"; + case FmhaKernelType::SwapsMmaAbForGeneration: + return "SwapsAbForGen"; + case FmhaKernelType::KeepsMmaAbForGeneration: + return "KeepsAbForGen"; + default: + TLLM_LOG_ERROR("Unsupported enum."); + return ""; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(MultiCtasKvMode mode) { + return multiCtasKvModeToString(mode); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(TileScheduler scheduler) { + switch (scheduler) { + case TileScheduler::Static: + return "Static"; + case TileScheduler::Persistent: + return "Persistent"; + default: + TLLM_LOG_ERROR("Unsupported enum."); + return ""; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(QkvLayout e) { + return qkvLayoutToString(e); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(tg::Dtype e) { + return tg::dtypeToString(e); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline std::string toString(MmaOrder e) { + return mmaOrderToString(e); +} + +#endif // !TLLM_FMHA_TRTLLM_COMPAT (enum types, toString, helpers) + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// KernelConfigBase: Base class shared between FmhaOptions and KernelConfig. +// This struct contains all common configuration variables that are directly shared +// between FmhaOptions (user-facing configuration) and KernelConfig (kernel compilation config). +// FmhaOptions is used to initialize KernelConfig. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct KernelConfigBase { + // Whether to balance the workload for causal mask. + bool mBalancesWorkloadForCausalMask{false}; + // The cluster dimension in the X dimension. + int mClusterDimX{1}; + // Annotate the masking code path with ColdBlock to indicate less traversed path. + bool mColdBlockTmemS{true}; + // The CUDA arch. + tg::CudaArch mCudaArch{tg::CudaArch::Sm100a}; + // The data type of MMA accumulators. + tg::Dtype mDtypeAcc{tg::Dtype::Fp32}; + // The data type of the elements of Q. + tg::Dtype mDtypeQ{tg::Dtype::E4m3}; + // The data type of the elements of K/V. + tg::Dtype mDtypeKv{tg::Dtype::E4m3}; + // The data type of the elements of O. + tg::Dtype mDtypeOut{tg::Dtype::E4m3}; + // Whether to use dynamic numTokensPerPage. + bool mDynamicNumTokensPerPage{false}; + // Whether to use fp16 softmax. + bool mEnablesFp16Softmax{false}; + // Do we enable max value inflation? + bool mEnablesInflateMax{false}; + // Whether 2 instances of the softmax task could be merged ? + bool mEnablesSoftmaxTaskMerge{true}; + // Whether to enable the programmatic dependent launch. + bool mEnablesPdl{false}; + // Whether to enable detection of repeated sequences. + bool mEnablesRepeatedSeqDetect{false}; + // Is it causal-mask spec-decoding generation kernel ? + bool mIsCausalSpecDecodingGen{false}; + // Is it custom-mask spec-decoding generation kernel ? + bool mIsCustomSpecDecodingGen{false}; + // Is it Multi-Latent Attention (MLA) generation kernel ? + bool mIsMlaGen{false}; + // Is it Multi-Latent Attention (MLA) sparse generation kernel ? + bool mIsSparseMla{false}; + // The kernel type under different cases. + FmhaKernelType mFmhaKernelType{FmhaKernelType::Context}; + // Always skip correction + bool mForcesSkipCorr{false}; + // Store tensor to gmem directly in the end of the correction task. + // True: vectorized store. False: TMA store using dedicated warp. + bool mFuseEpilogueIntoCorr{true}; + // Whether to transform K/V in the correction task. + bool mFuseTransformKvIntoCorr{true}; + // Whether to group the headsQ into one CTA. + bool mGroupsHeadsQ{false}; + // Whether to group both tokensQ and headsQ into one CTA. + bool mGroupsTokensHeadsQ{false}; + // The head dimension per CTA for V. + int32_t mHeadDimPerCtaV{0}; + // The head dimension per stage for K/V. + int32_t mHeadDimPerStageKv{0}; + // The attention head size for Q and K. + int32_t mHeadDimQk{128}; + // The attention head size for V. + int32_t mHeadDimV{128}; + // Whether to interleave MUFU and sums in the softmax loop. + bool mInterleavesMufuAndSums{false}; + // Whether to use interleaved SF layout for tileV. (Only valid when KV cache is NVFP4) + bool mInterleaveSfV{false}; + // Attention mask type. + AttentionMaskType mMaskType{AttentionMaskType::Dense}; + // The MMA order (only used when numInstsQ == 2). + MmaOrder mMmaOrder{MmaOrder::Pv0_Qk0_Pv1_Qk1}; + // The multiCtasKvMode. + MultiCtasKvMode mMultiCtasKvMode{MultiCtasKvMode::Disabled}; + // Delay downcast until N-th exps to hide exp latency (17 clks); must be a multiple of 4. + int mNumDelayedCvtElts{12}; + // The number of elements per block for Sage Attention (for K). 0 => we don't use Sage Attention. + int mNumEltsPerSageAttnBlkK{0}; + // The number of elements per block for Sage Attention (for P). 0 => we don't use Sage Attention. + int mNumEltsPerSageAttnBlkP{0}; + // The number of elements per block for Sage Attention (for Q). 0 => we don't use Sage Attention. + int mNumEltsPerSageAttnBlkQ{0}; + // The number of elements per block for Sage Attention (for V). 0 => we don't use Sage Attention. + int mNumEltsPerSageAttnBlkV{0}; + // The number of elements per SMEM stage for K/V. + int mNumEltsPerSmemStageKv{0}; + // Use FlashAttention4-style softmax emulation for the last N exp2 calls. + int mNumEmuExp2Elts{0}; + // Number of Q heads. + int mNumHeadsQ{4}; + // Number of Q heads per KV head. + int mNumHeadsQPerKv{1}; + // Number of KV heads. + int mNumHeadsKv{4}; + // The number of instances of tileQ, where each warpgroup handles one instance. + int32_t mNumInstsQ{2}; + // The number of instances of tileKv, where each warpgroup handles one instance. + int32_t mNumInstsKv{1}; + // The k-partition factor for BMM2 O = P * V. Can start BMM2 while softmax is in flight. + // Beneficial only when BMM1 cycles == softmax cycles where neither dominates. + int mNumKPartitionsMmaPv{2}; + // Signal at the last N remaining exps to cover the OrderedSequenceBarriers latency (~40 clks). + int mNumLeadingExpElts{6}; + // Delay exp until N-th FMAs to hide FMA latency (7 clks); must be a multiple of 2. + int mNumPrefetchedFmas{4}; + // The paged-kv configurations. The number of tokens in one pageKv. + int32_t mNumTokensPerPage{32}; + // How many warps are doing V transposition + int mNumTransposeWarps{4}; + // Whether to output debug tensors. + bool mOutputDebugTensors{false}; + // Does the kernel output stats on skipped softmax blocks? + bool mOutputSkipSoftmaxStats{false}; + // Input layout. + QkvLayout mQkvLayout{QkvLayout::SeparateQkv}; + // Do we reuse the shared memory buffer of K for V (for MLA Gen). + bool mReuseSmemKForV{false}; + // Do we schedule exps in pairs? + int mSchedExpPairs{false}; + // Separate task for loadK and loadV + bool mSeparateLoadKvTask{false}; + // Separate resource for smemK and smemV + bool mSeparateSmemKv{false}; + // Is only one tokenQ used ? (normally generation kernels). + bool mSingleTokenQ{false}; + // Whether to only process one tokenQ per CTA in the Q dimension. + bool mSingleTokenQPerCta{false}; + // Do we skip the correction step when possible? + bool mSkipsCorrWhenPossible{false}; + // Do we skip the softmax operations when possible? + bool mSkipsSoftmaxWhenPossible{false}; + // Whether to store the softmax stats to global memory. + bool mStoresSoftmaxStats{false}; + // Whether to enable different sequence length for Q and K/V. + bool mSupportsDiffSeqLensForQAndKv{false}; + // Whether to use variable sequence length. + bool mSupportsVarSeqLens{false}; + // Whether to swap A and B tensors for Mmas. This should be used for small-M cases like the + // generation phase. + bool mSwapsMmaAb{false}; + // Tile scheduler type. + TileScheduler mTileScheduler{TileScheduler::Static}; + // The tile size (in the sequence dimension) for K/V, which is considered as the tileSizeND of + // BMM1. + int32_t mTileSizeKv{128}; + // The tile size (in the sequence dimension) for Q, which is considered as the tileSizeMD of BMM1. + int32_t mTileSizeQ{128}; + // Transpose V in smem for MMA. + bool mTransposeSmemV{false}; + // Unroll first and last iteration to reduce branching at the expense of code size. + bool mUnrollFirstLastIter{true}; + // The number of MMA-K partitions for the P. + int mNumKPartitionsTileP{2}; + // The number of MMA-K partitions for the V. + int mNumKPartitionsTileV{1}; + // Whether to use attention sinks (additional value in the denominator of the softmax). + bool mUsesAttentionSinks{false}; + // Whether to use block sparse attention. + bool mUseBlockSparseAttention{false}; + // Whether to use an ordered sequence between softmax0 and softmax1. + bool mUsesOrderedSequence{true}; + // Whether to use CGA reduction (deprecated, kept for benchmarking). + bool mUsesCgaReduction{false}; + // Switch warps opportunistically during rowsum to unblock softmax sequence. + bool mWarpSwitchTmemSoftmax{true}; + // Switch warps opportunistically during correction to unblock softmax sequence. + bool mWarpSwitchTmemCorr{true}; + // Switch warps opportunistically during max reduction to unblock softmax sequence. + bool mWarpSwitchTmemS{true}; + + // Default constructor. + KernelConfigBase() = default; + + // Convert the base options to a JSON object. + void toJson(nlohmann::json& j) const { + TO_JSON(mBalancesWorkloadForCausalMask) + TO_JSON(mClusterDimX) + TO_JSON(mColdBlockTmemS) + TO_JSON(mCudaArch) + TO_JSON(mDtypeAcc) + TO_JSON(mDtypeQ) + TO_JSON(mDtypeKv) + TO_JSON(mDtypeOut) + TO_JSON(mDynamicNumTokensPerPage) + TO_JSON(mEnablesFp16Softmax) + TO_JSON(mEnablesInflateMax) + TO_JSON(mEnablesSoftmaxTaskMerge) + TO_JSON(mEnablesPdl) + TO_JSON(mEnablesRepeatedSeqDetect) + TO_JSON(mIsCausalSpecDecodingGen) + TO_JSON(mIsCustomSpecDecodingGen) + TO_JSON(mIsMlaGen) + TO_JSON(mIsSparseMla) + TO_JSON(mFmhaKernelType) + TO_JSON(mForcesSkipCorr) + TO_JSON(mFuseEpilogueIntoCorr) + TO_JSON(mFuseTransformKvIntoCorr) + TO_JSON(mGroupsHeadsQ) + TO_JSON(mGroupsTokensHeadsQ) + TO_JSON(mHeadDimPerCtaV) + TO_JSON(mHeadDimPerStageKv) + TO_JSON(mHeadDimQk) + TO_JSON(mHeadDimV) + TO_JSON(mInterleavesMufuAndSums) + TO_JSON(mInterleaveSfV) + TO_JSON(mMaskType) + TO_JSON(mMmaOrder) + TO_JSON(mMultiCtasKvMode) + TO_JSON(mNumDelayedCvtElts) + TO_JSON(mNumEltsPerSageAttnBlkK) + TO_JSON(mNumEltsPerSageAttnBlkP) + TO_JSON(mNumEltsPerSageAttnBlkQ) + TO_JSON(mNumEltsPerSageAttnBlkV) + TO_JSON(mNumEltsPerSmemStageKv) + TO_JSON(mNumEmuExp2Elts) + TO_JSON(mNumHeadsQ) + TO_JSON(mNumHeadsQPerKv) + TO_JSON(mNumHeadsKv) + TO_JSON(mNumInstsQ) + TO_JSON(mNumInstsKv) + TO_JSON(mNumKPartitionsMmaPv) + TO_JSON(mNumLeadingExpElts) + TO_JSON(mNumPrefetchedFmas) + TO_JSON(mNumTokensPerPage) + TO_JSON(mNumTransposeWarps) + TO_JSON(mOutputDebugTensors) + TO_JSON(mOutputSkipSoftmaxStats) + TO_JSON(mQkvLayout) + TO_JSON(mReuseSmemKForV) + TO_JSON(mSchedExpPairs) + TO_JSON(mSeparateLoadKvTask) + TO_JSON(mSeparateSmemKv) + TO_JSON(mSingleTokenQ) + TO_JSON(mSingleTokenQPerCta) + TO_JSON(mSkipsCorrWhenPossible) + TO_JSON(mSkipsSoftmaxWhenPossible) + TO_JSON(mStoresSoftmaxStats) + TO_JSON(mSupportsDiffSeqLensForQAndKv) + TO_JSON(mSupportsVarSeqLens) + TO_JSON(mSwapsMmaAb) + TO_JSON(mTileScheduler) + TO_JSON(mTileSizeKv) + TO_JSON(mTileSizeQ) + TO_JSON(mTransposeSmemV) + TO_JSON(mUnrollFirstLastIter) + TO_JSON(mNumKPartitionsTileP) + TO_JSON(mNumKPartitionsTileV) + TO_JSON(mUsesAttentionSinks) + TO_JSON(mUseBlockSparseAttention) + TO_JSON(mUsesCgaReduction) + TO_JSON(mUsesOrderedSequence) + TO_JSON(mWarpSwitchTmemSoftmax) + TO_JSON(mWarpSwitchTmemCorr) + TO_JSON(mWarpSwitchTmemS) + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace fmha diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelParams.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelParams.h new file mode 100644 index 000000000000..d8d516d72816 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelParams.h @@ -0,0 +1,882 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "KernelParamsDecl.h" +#include + +#ifdef TLLM_ENABLE_CUDA +#include +#include +#include +#else +// Fake Cutlass data types for compilation (on Mac). +namespace cutlass { +struct float_e4m3_t {}; +struct half_t {}; +struct bfloat16_t {}; +} // namespace cutlass +#endif + +namespace fmha { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace tg = trtllm::gen; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace KernelParamsSetup { +#ifdef TLLM_ENABLE_CUDA +static CUtensorMap buildNdTmaDescriptor(tg::Dtype dtypeElt, + const std::vector& shapes, + const std::vector& strides, + const std::vector& tileShapes, + void* gmemAddr, + bool swizzled = true, + bool unpack4b = false) { + CUtensorMap desc{}; + // The data type. + CUtensorMapDataType tmaDataFormat{CU_TENSOR_MAP_DATA_TYPE_FLOAT32}; + if (dtypeElt == tg::Dtype::E2m1) { + tmaDataFormat = + unpack4b ? CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN16B : CU_TENSOR_MAP_DATA_TYPE_UINT8; + } else if (dtypeElt == tg::Dtype::E4m3) { + tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_UINT8; + } else if (dtypeElt == tg::Dtype::Fp16) { + tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_FLOAT16; + } else if (dtypeElt == tg::Dtype::Bfloat16) { + tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_BFLOAT16; + } else { + std::cerr << "Unexpected dtype " << static_cast(dtypeElt) << std::endl; + assert(false); + } + + // The swizzle type. + CUtensorMapSwizzle swizzleType{CU_TENSOR_MAP_SWIZZLE_NONE}; + int32_t numBytesInLeadingDim = tileShapes[0] * tg::dtypeGetNumBits(dtypeElt) / 8 /*bits*/; + if (!swizzled) { + swizzleType = CU_TENSOR_MAP_SWIZZLE_NONE; + } else if (tmaDataFormat == CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN16B) { + swizzleType = CU_TENSOR_MAP_SWIZZLE_128B; + } else if ((numBytesInLeadingDim % 128) == 0) { + swizzleType = CU_TENSOR_MAP_SWIZZLE_128B; + } else if ((numBytesInLeadingDim % 64) == 0) { + swizzleType = CU_TENSOR_MAP_SWIZZLE_64B; + } else if ((numBytesInLeadingDim % 32) == 0) { + swizzleType = CU_TENSOR_MAP_SWIZZLE_32B; + } else { + std::cerr << "Unexepected numBytesInLeadingDim " << numBytesInLeadingDim << std::endl; + assert(false); + } + + // Check gmem address must be 16B-aligned + assert((reinterpret_cast(gmemAddr) & 0b1111) == 0); + + // Check shape must be in range [1, 2^32] + int32_t dim = shapes.size(); + // Max five dimension and min 2 dimension. + assert((dim <= 5) && (dim >= 2)); + // Check shape range. + for (int32_t ii = 0; ii < dim; ++ii) { + assert(shapes[ii] >= (uint64_t(1))); // Size must be min 1 + assert(shapes[ii] <= (uint64_t(1) << 32)); // Size must be max 2^32 + } + + // TMA descriptor does not store the zeroth stride and assumes it is 1. + assert(static_cast(strides.size()) == dim); + assert(strides[0] == 1); + + // Build strides in bytes. + // cuTensorMapEncodeTiled ignores the stride of the first dimention (implicitly 1). + std::vector stridesInBytes(dim - 1); + for (int32_t ii = 0; ii < dim - 1; ++ii) { + stridesInBytes[ii] = strides[ii + 1] * std::max(tg::dtypeGetNumBits(dtypeElt), 8) / 8; + } + + // Set tile strides to 0; + std::vector tileStrides(dim, 1); + + // Build the descriptor. + CUresult result = cuTensorMapEncodeTiled(&desc, + tmaDataFormat, + /*tensorRank=*/dim, + gmemAddr, + shapes.data(), + stridesInBytes.data(), + tileShapes.data(), + tileStrides.data(), + /*interleave=*/CU_TENSOR_MAP_INTERLEAVE_NONE, + swizzleType, + /*l2Promotion=*/CU_TENSOR_MAP_L2_PROMOTION_L2_128B, + /*oobFill=*/CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE); + + if (result != CUDA_SUCCESS) { + // Get the error string. + const char* errStr = nullptr; + cuGetErrorString(result, &errStr); + std::cerr << "Error: Failed to initialize the TMA descriptor " << errStr << std::endl; + std::cerr << "tmaFormat: " << static_cast(tmaDataFormat) << " dim: " << dim + << " gmem: " << gmemAddr << std::endl; + std::cerr << "Shape: " << shapes[0] << " " << shapes[1] << " " << shapes[2] << " " << shapes[3] + << std::endl; + std::cerr << "Stride: " << stridesInBytes[0] << " " << stridesInBytes[1] << " " + << stridesInBytes[2] << std::endl; + std::cerr << "tileShapes: " << tileShapes[0] << " " << tileShapes[1] << " " << tileShapes[2] + << " " << tileShapes[3] << std::endl; + std::cerr << "tileStrides: " << tileStrides[0] << " " << tileStrides[1] << " " << tileStrides[2] + << " " << tileStrides[3] << std::endl; + std::cerr << "swizzleType: " << int(swizzleType) << std::endl; + assert(false); + } + + return desc; +} + +// Create the TMA shape/stride for Q. +template +static auto makeTmaShapeStrideQ(FmhaOptions const& options, KernelTraits_ const& kernelTraits) { + + // + // The Q has shape of [numTokens * numHeadsQPerKv, numHeadsKv * 1, headDim] + // when grouping headsQ, otherwise it would be [numTokens, numHeadsQPerKv * numHeadsKv, + // headDim]. + + // The headDim for Q and K. + int headDimQk{options.mHeadDimQk}; + // The headDim for V. + int headDimV{options.mHeadDimV}; + + // The number of grouped heads for the A matrix of MMA. + int32_t numGroupedHeads{1}; + if (options.mGroupsHeadsQ) { + numGroupedHeads = std::min(options.mTileSizeQ, options.mNumHeadsQPerKv); + } + + // The number of heads. + int32_t numHeads{options.mNumHeadsQ}; + if (options.mGroupsHeadsQ) { + numHeads /= numGroupedHeads; + } + // Make sure the math works. + assert(numHeads * numGroupedHeads == options.mNumHeadsQ && "internal error"); + + // The number of tokens. + int32_t numTokens{options.mSumOfSeqLensQ}; + + // This maps to flattened TMA shape for Q: (headDim, numTokens, numHeads). + auto shape = std::vector{static_cast(headDimQk), + static_cast(numGroupedHeads), + static_cast(numHeads), + static_cast(numTokens)}; + + // The hidden dimension when the tensor contains only Q (i.e. not QKV packed). + int32_t const hiddenDimQ{options.mNumHeadsQ * headDimQk}; + + // The hidden dimension when the Q, K and V tensors are packed. + int32_t hiddenDimQkv{hiddenDimQ}; + if (isPackedQkv(options.mQkvLayout)) { + assert(!options.mGroupsHeadsQ && "internal error"); + hiddenDimQkv += options.mNumHeadsKv * (headDimQk + headDimV); + } + + // The stride between grouped heads. + int32_t strideGroupedHeads{headDimQk}; + // The stride between heads. + int32_t strideHeads{numGroupedHeads * strideGroupedHeads}; + // The stride between tokens. + int32_t strideTokens{hiddenDimQkv}; + + // Assemble the stride (1, strideTokens, strideHeads). + // Swap the first two dimension as mentioned before. + auto stride = std::vector{1, + static_cast(strideGroupedHeads), + static_cast(strideHeads), + static_cast(strideTokens)}; + + // The tile shape for TMA. + auto tileShapes = + std::vector{static_cast(kernelTraits.mNumEltsInClampedHeadDimQ), + 1, + 1, + static_cast(options.mTileSizeQ)}; + // The tileSizePerCtaQ. + int32_t tileSizePerCtaQ{options.mTileSizeQ * options.mNumInstsQ}; + // The number of tokensQ per CTA. + int32_t numTokensPerCtaQ{tileSizePerCtaQ}; + // Re-compute the number of tokensQ per CTA if groupsHeadsQ is enabled. + if (options.mGroupsHeadsQ) { + if (options.mGroupsTokensHeadsQ) { + // Currently, it requires each CTA to process complete headsQ (i.e. numGroupedHeads) at a + // time, so it allows paddings in the end. Removing paddings needs re-organizing the Q + // tensor to [numTokensQ, numGroupedHeads, numHeads, headDimQ] and we might want to revisit + // this in the future. + numTokensPerCtaQ = static_cast(numTokensPerCtaQ / numGroupedHeads); + } else { + numGroupedHeads = tileSizePerCtaQ; + numTokensPerCtaQ = 1; + } + tileShapes = + std::vector{static_cast(kernelTraits.mNumEltsInClampedHeadDimQ), + static_cast(numGroupedHeads), + 1, + static_cast(numTokensPerCtaQ)}; + } + + return std::make_tuple(shape, stride, tileShapes, numTokensPerCtaQ); +} + +// Create the TMA shape/stride for O. +template static auto makeTmaShapeStrideO(FmhaOptions const& options) { + + // The TmaO (i.e. mFuseEpilogueIntoCorr = true) should not be used when mGroupsHeadsQ is true. + assert((!options.mGroupsHeadsQ || options.mFuseEpilogueIntoCorr) && + "GroupsHeadsQ is not supported"); + + // The number of tokens. + int32_t numTokens{options.mMaxSeqLenQ}; + if (options.mSupportsVarSeqLens) { + numTokens = options.mSumOfSeqLensQ; + } + + // The batch dimension. + int32_t batchSize{options.mBatchSize}; + if (options.mSupportsVarSeqLens) { + batchSize = 1; + } + + // The shape for O is [batchSize/1, numTokens, numHeads, 1] (fastest-moving dim on the right). + auto shape = std::vector{static_cast(options.mHeadDimV), + static_cast(options.mNumHeadsQ), + static_cast(numTokens), + static_cast(batchSize)}; + + // The strides. + std::vector strides(4, uint64_t{0}); + // The inner-most stride must be 1. + strides[0] = 1; + // The stride between heads. + strides[1] = strides[0] * options.mHeadDimV; + // The stride between tokens. + strides[2] = strides[1] * options.mNumHeadsQ; + // The stride between sequences. + strides[3] = options.mSupportsVarSeqLens ? uint64_t{0} : strides[2] * options.mMaxSeqLenQ; + + return std::make_tuple(shape, strides); +} + +// Create the shape for K and V. +template +static auto makeShapeKv(FmhaOptions const& options, KernelParams const& params) { + + // The number of keys/vals. WARNING: The if/else-if are sorted by priority. + int32_t numKeysVals{options.mMaxSeqLenKv}; + if (isPagedKv(options.mQkvLayout)) { + numKeysVals = options.mNumTokensPerPage; + } else if (isContiguousKv(options.mQkvLayout)) { + numKeysVals = options.mMaxSeqLenKv; + } else if (options.mSupportsVarSeqLens) { + numKeysVals = options.mSumOfSeqLensKv; + } + + // The number of heads per K/V head (packed in the sequence length for mGroupsHeadsQ). + int32_t numHeadsKv{options.mNumHeadsKv}; + + // The batch dimension. WARNING: The if/else-if are sorted by priority. + int32_t batchSize{options.mBatchSize}; + if (isPagedKv(options.mQkvLayout)) { + batchSize = params.mNumPagesInMemPool; + } else if (isContiguousKv(options.mQkvLayout)) { + batchSize = options.mBatchSize; + } else if (options.mSupportsVarSeqLens) { + batchSize = 1; + } + + // Return the number of keys and batch. + return std::make_tuple(numKeysVals, numHeadsKv, batchSize); +} + +// Compute the strides for K and V. +template static auto makeStrideKv(FmhaOptions const& options, bool isK) { + + // The headDim for Q and K. + int headDimQk{options.mHeadDimQk}; + // The headDim for V. + int headDimV{options.mHeadDimV}; + // The maximum headDim for K and V. + int maxHeadDimKv{std::max(headDimQk, headDimV)}; + + // The hidden dimension when Q, K and V are packed together. + int32_t const hiddenDimQkv{(options.mNumHeadsQ + options.mNumHeadsKv) * headDimQk + + options.mNumHeadsKv * headDimV}; + + int32_t strideKeysVals{}; + int32_t strideHeads{}; + int32_t strideBatch{}; + + if (options.mIsTrtllmLayout) { + // TRT-LLM KV cache layout: K/V token strides differ; context MLA uses non-contiguous V layout. + int32_t const hiddenDimK{options.mNumHeadsKv * headDimQk}; + int32_t const hiddenDimV{options.mNumHeadsKv * headDimV}; + int32_t const maxHiddenDimKv{std::max(hiddenDimK, hiddenDimV)}; + + strideKeysVals = isK ? hiddenDimK : hiddenDimV; + if (isPagedKv(options.mQkvLayout)) { + strideKeysVals = maxHeadDimKv; + } else if (isPackedQkv(options.mQkvLayout)) { + strideKeysVals = hiddenDimQkv; + } else if (isContiguousKv(options.mQkvLayout)) { + strideKeysVals = maxHeadDimKv; + } else if (isSeparateQkv(options.mQkvLayout) && !isK && options.mHeadDimQk == 192 && + options.mDtypeKv != tg::Dtype::E4m3) { + // Non-FP8 context MLA: tensor V is not contiguous. + strideKeysVals = options.mNumHeadsKv * (options.mHeadDimQk - 64 + options.mHeadDimV); + } + + strideHeads = isK ? headDimQk : headDimV; + if (isPagedKv(options.mQkvLayout)) { + strideHeads = options.mNumTokensPerPage * maxHeadDimKv; + } else if (isContiguousKv(options.mQkvLayout)) { + strideHeads = options.mMaxSeqLenKv * maxHeadDimKv; + } + + strideBatch = options.mMaxSeqLenKv * maxHiddenDimKv; + if (isPagedKv(options.mQkvLayout)) { + strideBatch = options.mNumTokensPerPage * maxHiddenDimKv; + } else if (isContiguousKv(options.mQkvLayout)) { + strideBatch = 2 * options.mMaxSeqLenKv * maxHiddenDimKv; + } else if (options.mSupportsVarSeqLens) { + strideBatch = 0; + } else if (isPackedQkv(options.mQkvLayout)) { + strideBatch = options.mMaxSeqLenKv * hiddenDimQkv; + } + } else { + // Default (trtllm-gen internal test): single hidden dim for K/V token stride. + int32_t const hiddenDimK{options.mNumHeadsKv * maxHeadDimKv}; + + strideKeysVals = hiddenDimK; + if (isPagedKv(options.mQkvLayout)) { + strideKeysVals = maxHeadDimKv; + } else if (isPackedQkv(options.mQkvLayout)) { + strideKeysVals = hiddenDimQkv; + } else if (isContiguousKv(options.mQkvLayout)) { + strideKeysVals = maxHeadDimKv; + } + + strideHeads = isK ? headDimQk : headDimV; + if (isPagedKv(options.mQkvLayout)) { + strideHeads = options.mNumTokensPerPage * maxHeadDimKv; + } else if (isContiguousKv(options.mQkvLayout)) { + strideHeads = options.mMaxSeqLenKv * maxHeadDimKv; + } else if (isSeparateQkv(options.mQkvLayout)) { + strideHeads = maxHeadDimKv; + } + + strideBatch = options.mMaxSeqLenKv * hiddenDimK; + if (isPagedKv(options.mQkvLayout)) { + strideBatch = options.mNumTokensPerPage * hiddenDimK; + } else if (isContiguousKv(options.mQkvLayout)) { + strideBatch = 2 * options.mMaxSeqLenKv * hiddenDimK; + } else if (options.mSupportsVarSeqLens) { + strideBatch = 0; + } else if (isPackedQkv(options.mQkvLayout)) { + strideBatch = options.mMaxSeqLenKv * hiddenDimQkv; + } + } + + return std::make_tuple(strideKeysVals, strideHeads, strideBatch); +} + +// Create the TMA shape/stride for K. +template +static auto makeTmaShapeStrideKv(FmhaOptions const& options, + KernelParams const& params, + bool isK, + bool storeTransformedKvInTmem) { + // The shape elements. + auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params); + // The stride elements. + auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK); + + // Therefore, the resulting TMA layout is 4D: (headDim, numKeys, numHeadsKv, batchSize):(1, + // strideKeys, strideHeads, strideBatch) + + // For K the headDim may include extra RoPE coefficients. + auto headDim = isK ? options.mHeadDimQk : options.mHeadDimV; + // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements. + // The column index and strides needs to divide by 2. + auto const colIdxDivisor = options.mDtypeKv == tg::Dtype::E2m1 ? 2 : 1; + // When mStoreTransformedKvInTmem is true, the dimensions reflect FP4 element dimensions, thus + // no need to divide. + auto shape = std::vector{ + static_cast(storeTransformedKvInTmem ? headDim : headDim / colIdxDivisor), + static_cast(numKeys), + static_cast(options.mNumHeadsKv), + static_cast(batchSize)}; + auto stride = std::vector{1, + static_cast(strideKeys / colIdxDivisor), + static_cast(strideHeads / colIdxDivisor), + static_cast(strideBatch / colIdxDivisor)}; + + return std::make_tuple(shape, stride); +} + +// Create the TMA shape/stride for KV scaling factors. +template +static auto makeTmaShapeStrideKvSf(FmhaOptions const& options, + KernelTraits_ const& kernelTraits, + KernelParams const& params, + bool isK) { + // The shape elements. + auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params); + // The stride elements. + auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK); + + // The number of elements per SF. + int32_t NumEltsPerSf = kernelTraits.mNumEltsPerSf; + + // The KV shape is: (headDim, numKeys, numHeadsKv, batchSize) + // Therefore, the KV SF shape should be (headDim / NumEltsPerSf, numKeys, numHeadsKv, + // batchSize). Considering the TMA requires box width to be multiple of 16B, without chaning the + // underlying layout, we reshape into (16, numKeys * headDim / NumEltsPerSf / 16, numHeadsKv, + // batchSize) + + // Note that it only works for pagedKv layout. + assert(isPagedKv(options.mQkvLayout)); + + // For K the headDim may include extra RoPE coefficients. + auto headDim = isK ? options.mHeadDimQk : options.mHeadDimV; + + auto shape = std::vector{16, + static_cast(numKeys * headDim / NumEltsPerSf / 16), + static_cast(options.mNumHeadsKv), + static_cast(batchSize)}; + auto stride = std::vector{1, + 16, + static_cast(strideHeads / NumEltsPerSf), + static_cast(strideBatch / NumEltsPerSf)}; + + return std::make_tuple(shape, stride); +} + +// Update the kernel parameters. +template +static KernelParams updateKernelParams(FmhaOptions_ const& options, + KernelParams const& params, + void const* qBasePtr, + void const* kBasePtr, + void const* vBasePtr, + void* oBasePtr, + void const* kSfBasePtr, + void const* vSfBasePtr) { + return setKernelParams(options, + params.logicalGridDimX, + params.logicalGridDimY, + params.logicalGridDimZ, + params.ptrCumSeqLensQ, + params.ptrCumSeqLensKv, + params.ptrSeqLensKv, + qBasePtr, + kBasePtr, + vBasePtr, + kSfBasePtr, + vSfBasePtr, + params.ptrPageIdxKv, + params.ptrOutputScale, + params.ptrScaleSoftmaxLog2, + params.ptrScaleSfKv, + params.ptrScaleSfO, + params.ptrCustomMask, + params.ptrCustomMaskOffsets, + params.ptrFirstSparseMaskOffsetsKv, + params.ptrSageAttnSfsQ, + params.ptrSageAttnSfsK, + params.ptrSageAttnSfsP, + params.ptrSageAttnSfsV, + params.ptrAttentionSinks, + oBasePtr, + params.ptrSfO, + params.ptrMultiCtasKvCounter, + params.ptrPartialO, + params.ptrPartialStats, + params.ptrSkipSoftmaxStats, + params.ptrSoftmaxStats, + params.ptrDebugO, + params.mScaleSoftmaxLog2, + params.mInflateMax, + params.mScaleSfKv, + params.mScaleSfO, + params.mStartTokenIdxSfO, + params.mUseBlockSparseAttention, + params.mUsesSharedPagedKvIdx); +} + +// Setup the kernel parameters. +template +static KernelParams setKernelParams(FmhaOptions_ const& options, + int32_t logicalGridDimX, + int32_t logicalGridDimY, + int32_t logicalGridDimZ, + int const* cumSeqLensQPtrD, + int const* cumSeqLensKvPtrD, + int const* seqLensKvPtrD, + void const* qBasePtr, + void const* kBasePtr, + void const* vBasePtr, + void const* kSfBasePtr, + void const* vSfBasePtr, + int const* kvPageIdxD, + float const* outputScaleD, + float const* scaleSoftmaxLog2D, + float const* kvSfScaleD, + float const* oSfScaleD, + uint32_t const* customMaskPtrD, + int64_t const* customMaskOffsetsPtrD, + int32_t const* firstSparseMaskOffsetsKvPtrD, + float const* ptrSageAttnSfsQ, + float const* ptrSageAttnSfsK, + float const* ptrSageAttnSfsP, + float const* ptrSageAttnSfsV, + float const* ptrAttentionSinks, + void* oPtrD, + void* oSfPtrD, + int* multiCtasKvCounterPtrD, + void* partialOPtrD, + float2* partialStatsPtrD, + int* skipSoftmaxStatsPtrD, + float2* softmaxStatsD, + void* oDebugPtrD, + float softmaxScale, + float inflateMax, + float kvSfScale, + float oSfScale, + int32_t startTokenIdxSfO, + bool useBlockSparseAttention, + bool usesSharedPagedKvIdx) { + + // Create the return struct. + KernelParams params; + + params.logicalGridDimX = logicalGridDimX; + params.logicalGridDimY = logicalGridDimY; + params.logicalGridDimZ = logicalGridDimZ; + + // Set the number of pages in the memory pool for paged K/V cache. + if (isPagedKv(options.mQkvLayout)) { + params.mNumPagesInMemPool = options.mNumPagesInMemPool == 0 + ? options.mMaxNumPagesPerSeqKv * 2 * options.mBatchSize + : options.mNumPagesInMemPool; + } + + // Get the kernel traits from options. + auto kernelTraits = getKernelTraitsFromOptions(options); + + // Shape/stride for gmem tensor Q. + auto [shapeQ, strideQ, tileShapeQ, numTokensPerCtaQ] = makeTmaShapeStrideQ(options, kernelTraits); + // Build tma descriptor for Q. + params.tmaQ_ = + buildNdTmaDescriptor(options.mDtypeQ, shapeQ, strideQ, tileShapeQ, const_cast(qBasePtr)); + + // Build tma descriptor for K. Do we have to transform K/V before MMA? + bool const transformsKv{options.mDtypeKv != options.mDtypeQ}; + // Whether store transformed K/V in TMEM. + bool const storeTransformedKvInTmem{kernelTraits.mStoreTransformedKvInTmem}; + // Whether swizzle is needed for K/V. + bool const swizzleKv{storeTransformedKvInTmem ? true : !transformsKv}; + // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements. + auto const numEltsDivisor = + options.mDtypeKv == tg::Dtype::E2m1 && !storeTransformedKvInTmem ? 2 : 1; + + // Shape/stride for gmem tensor Kv. + auto [shapeK, strideK] = + makeTmaShapeStrideKv(options, params, /*isK*/ true, storeTransformedKvInTmem); + + // The tileShapes for K/V. + std::vector tileShapeKv(shapeK.size(), 1); + tileShapeKv[0] = kernelTraits.mNumEltsInClampedHeadDimKv / numEltsDivisor; + tileShapeKv[1] = kernelTraits.mNumKeysPerTile; + // K and V might use different tileShapes. + std::vector tileShapeK(tileShapeKv); + std::vector tileShapeV(tileShapeKv); + // If there is only one page per tile, each CTA will only load half of NumKeysPerTile for K. + if (options.mClusterDimX == 2 && kernelTraits.mNumKeysPerTile == kernelTraits.mTileSizeKv) { + tileShapeK[1] /= 2; + } + + // If sparse MLA is enabled, the shape and stride for K need to be updated for 2D layout + // (numTokensKvInPagedKv, headDimQk). + if (options.mIsSparseMla) { + shapeK = std::vector{ + static_cast(options.mHeadDimQk), + static_cast(params.mNumPagesInMemPool * options.mNumTokensPerPage)}; + strideK = std::vector{1, static_cast(options.mHeadDimQk)}; + tileShapeK[1] = 1; + } + + // Create the TMA descriptor. + params.tmaK_ = buildNdTmaDescriptor(options.mDtypeKv, + shapeK, + strideK, + tileShapeK, + const_cast(kBasePtr), + /*swizzled = */ swizzleKv, + /*unpack4b=*/storeTransformedKvInTmem); + + // Shape/stride for gmem tensor V. + auto [shapeV, strideV] = + makeTmaShapeStrideKv(options, params, /*isK*/ false, storeTransformedKvInTmem); + // Build the tma descriptor for V. + params.tmaV_ = buildNdTmaDescriptor(options.mDtypeKv, + shapeV, + strideV, + tileShapeV, + // MlaGen kernels reuse the same buffer for K and V. + const_cast(options.mIsMlaGen ? kBasePtr : vBasePtr), + /*swizzled = */ swizzleKv, + /*unpack4b=*/storeTransformedKvInTmem); + + // If the KV dtype is E2m1, additional scaling factors are needed for dequant. + if (options.mDtypeKv == tg::Dtype::E2m1) { + // The maximum headDim for K and V. + int maxHeadDimKv{std::max(options.mHeadDimQk, options.mHeadDimV)}; + // The number of elements per SF. + int32_t NumEltsPerSf = kernelTraits.mNumEltsPerSf; + // Compute the shape and stride for SF tensor. + // FIXME: assume K and V uses the same shape. + auto [shapeKvSf, strideKvSf] = + makeTmaShapeStrideKvSf(options, kernelTraits, params, /*isK*/ true); + // The tileShapes for K/V. + std::vector tileShapeKvSf(shapeKvSf.size(), 1); + tileShapeKvSf[0] = 16; + tileShapeKvSf[1] = kernelTraits.mNumKeysPerTile * maxHeadDimKv / NumEltsPerSf / 16; + + // The tile box is reshaped from (headDim / NumEltsPerSf, tileSizeKv) into (16, tileSizeKv * + // headDim / NumEltsPerSf / 16). See makeTmaShapeStrideKvSf for details. Build tma descriptor + // for K SF. + // If multiple headDimStages are used, we will load the full headDim's SFs to avoid reshaping + // SFs layout. + params.tmaKSf_ = buildNdTmaDescriptor(tg::Dtype::E4m3, + shapeKvSf, + strideKvSf, + tileShapeKvSf, + const_cast(kSfBasePtr), + /*swizzled = */ false); + + // Build tma descriptor for V SF. + params.tmaVSf_ = buildNdTmaDescriptor(tg::Dtype::E4m3, + shapeKvSf, + strideKvSf, + tileShapeKvSf, + const_cast(vSfBasePtr), + /*swizzled = */ false); + } + + // Shape/stride for gmem tensor O. + auto [shapeO, strideO] = makeTmaShapeStrideO(options); + + // The tileShapes for O (in the inner-most dimension and in the token dimension). + std::vector tileShapeO(shapeO.size(), 1); + tileShapeO[0] = kernelTraits.mNumEltsInClampedHeadDimQ; + tileShapeO[2] = options.mTileSizeQ; + + // Build tma descriptor for O. + params.tmaO_ = + buildNdTmaDescriptor(options.mDtypeQ, shapeO, strideO, tileShapeO, const_cast(oPtrD)); + + // Set the attention sinks pointer. + params.ptrAttentionSinks = ptrAttentionSinks; + + // The cumulative sequence lengths for Q. + params.ptrCumSeqLensQ = cumSeqLensQPtrD; + // The cumulative sequence lengths for K/V. + params.ptrCumSeqLensKv = cumSeqLensKvPtrD; + + // The packed custom mask. + params.ptrCustomMask = customMaskPtrD; + // The packed custom mask's offsets of each sequence. + params.ptrCustomMaskOffsets = customMaskOffsetsPtrD; + // The first sparseMask offsets in the Kv sequence dimension. + params.ptrFirstSparseMaskOffsetsKv = firstSparseMaskOffsetsKvPtrD; + + // The debug buffers. + params.ptrDebugO = static_cast(oDebugPtrD); + + // The skip softmax stats buffer. + params.ptrSkipSoftmaxStats = skipSoftmaxStatsPtrD; + + // The softmax stats buffer. + params.ptrSoftmaxStats = options.mStoresSoftmaxStats ? softmaxStatsD : nullptr; + + // The output buffer. + params.ptrO = oPtrD; + params.ptrSfO = oSfPtrD; + + // TRT-LLM restrictions: the quantization scales must be on the device. It will only be loaded + // when -loadsScalesFromGmem true -dtypeElt e4m3 are specified. + params.ptrOutputScale = outputScaleD; + + // The partial buffers' pointers when the multiCtasKv mode is enabled. + params.ptrMultiCtasKvCounter = multiCtasKvCounterPtrD; + params.ptrPartialO = partialOPtrD; + params.ptrPartialStats = partialStatsPtrD; + params.ptrPageIdxKv = kvPageIdxD; + params.ptrSageAttnSfsK = ptrSageAttnSfsK; + params.ptrSageAttnSfsP = ptrSageAttnSfsP; + params.ptrSageAttnSfsQ = ptrSageAttnSfsQ; + params.ptrSageAttnSfsV = ptrSageAttnSfsV; + params.ptrScaleSoftmaxLog2 = scaleSoftmaxLog2D; + params.ptrScaleSfKv = kvSfScaleD; + params.ptrScaleSfO = oSfScaleD; + + // The sequence lengths for K/V. + params.ptrSeqLensKv = seqLensKvPtrD; + + + params.mAttentionWindowSize = options.mAttentionWindowSize; + if (options.mChunkedAttentionSize > 0) { + // The chunked attention size is a power of 2 (verified in FmhaOptions.h). + params.mChunkedAttentionSizeLog2 = std::log2(options.mChunkedAttentionSize); + } else { + params.mChunkedAttentionSizeLog2 = 0; + } + params.mBatchSize = options.mBatchSize; + + params.mInflateMax = inflateMax; + + // Compute the logs for the numbers of elements in the Sage Attention blocks. + int32_t logNumEltsPerSageAttnBlkK{-1}; + if (options.mNumEltsPerSageAttnBlkK == -1) { + logNumEltsPerSageAttnBlkK = 32; + } else if (options.mNumEltsPerSageAttnBlkK != 0) { + logNumEltsPerSageAttnBlkK = (int)log2f((float)options.mNumEltsPerSageAttnBlkK); + } + int32_t logNumEltsPerSageAttnBlkP{-1}; + if (options.mNumEltsPerSageAttnBlkP == -1) { + logNumEltsPerSageAttnBlkP = 32; + } else if (options.mNumEltsPerSageAttnBlkP != 0) { + logNumEltsPerSageAttnBlkP = (int)log2f((float)options.mNumEltsPerSageAttnBlkP); + } + int32_t logNumEltsPerSageAttnBlkQ{-1}; + if (options.mNumEltsPerSageAttnBlkQ == -1) { + logNumEltsPerSageAttnBlkQ = 32; + } else if (options.mNumEltsPerSageAttnBlkQ != 0) { + logNumEltsPerSageAttnBlkQ = (int)log2f((float)options.mNumEltsPerSageAttnBlkQ); + } + int32_t logNumEltsPerSageAttnBlkV{-1}; + if (options.mNumEltsPerSageAttnBlkV == -1) { + logNumEltsPerSageAttnBlkV = 32; + } else if (options.mNumEltsPerSageAttnBlkV != 0) { + logNumEltsPerSageAttnBlkV = (int)log2f((float)options.mNumEltsPerSageAttnBlkV); + } + + // Set the Sage Attention params. + params.mLogNumEltsPerSageAttnBlkK = logNumEltsPerSageAttnBlkK; + params.mLogNumEltsPerSageAttnBlkQ = logNumEltsPerSageAttnBlkQ; + params.mLogNumEltsPerSageAttnBlkP = logNumEltsPerSageAttnBlkP; + params.mLogNumEltsPerSageAttnBlkV = logNumEltsPerSageAttnBlkV; + + // Compute the log of numTokensPerPage + int32_t numTokensPerPageLog2{-1}; + if (options.mDynamicNumTokensPerPage) { + TLLM_CHECK_ERROR((options.mNumTokensPerPage & (options.mNumTokensPerPage - 1)) == 0, + "NumTokensPerPage must be power of 2"); + numTokensPerPageLog2 = (int)log2f((float)options.mNumTokensPerPage); + } + params.mNumTokensPerPageLog2 = numTokensPerPageLog2; + + params.mMaxSeqLenQ = options.mMaxSeqLenQ; + params.mMaxSeqLenKv = options.mMaxSeqLenKv; + params.mMaxNumCtasQ = options.mMaxNumCtasQ; + params.mMaxNumCtasKv = options.mMaxNumCtasKv; + params.mMaxNumPagesPerSeqKv = options.mMaxNumPagesPerSeqKv; + params.mNumHeadsKv = options.mNumHeadsKv; + params.mNumHeadsQ = options.mNumHeadsQ; + params.mNumHeadsQPerKv = options.mNumHeadsQPerKv; + params.mNumHeadsQPerKvDivisor = trtllm::dev::fast_mod_div(options.mNumHeadsQPerKv); + params.mNumHiddenEltsO = options.mNumHeadsQ * options.mHeadDimV; + params.mNumTokensPerCtaQ = numTokensPerCtaQ; + params.mOutputScale = options.mOutputScale; + params.mScaleSoftmaxLog2 = softmaxScale; + params.mScaleSfKv = kvSfScale; + params.mScaleSfO = oSfScale; + params.mStartTokenIdxSfO = startTokenIdxSfO; + params.mSumOfSeqLensQ = options.mSumOfSeqLensQ; + params.mSumOfSeqLensKv = options.mSumOfSeqLensKv; + params.mSkipSoftmaxThresholdScaleFactor = options.mSkipSoftmaxThresholdScaleFactor; + params.mSparseMlaTopK = options.mSparseMlaTopK; + + // Set the block sparse attention flag. + params.mUseBlockSparseAttention = useBlockSparseAttention; + // Set the shared paged KV index flag. + params.mUsesSharedPagedKvIdx = usesSharedPagedKvIdx; + return params; +} +#else +// Update the kernel parameters. +template +static KernelParams updateKernelParams(FmhaOptions_ const&, + KernelParams const&, + void const*, + void const*, + void const*, + void*, + void const*, + void const*) { + return KernelParams{}; +} + +// Setup the kernel parameters. +template +static KernelParams setKernelParams(FmhaOptions_ const&, + int32_t, + int32_t, + int32_t, + int const*, + int const*, + int const*, + void const*, + void const*, + void const*, + int const*, + float const*, + uint32_t const*, + int64_t const*, + int32_t const*, + float const*, + float const*, + float const*, + float const*, + void*, + int*, + void*, + float2*, + int*, + float2*, + void*, + float, + float, + float, + int32_t, + bool, + bool) { + return KernelParams{}; +} +#endif +} // namespace KernelParamsSetup + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace fmha diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelParamsDecl.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelParamsDecl.h new file mode 100644 index 000000000000..1ffaa62c059c --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelParamsDecl.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include + +// NOTE: Keep this code dependency free. It has to be included by the device code and has to be +// compilable with NVRTC. + +namespace fmha { + +struct KernelParams { +#ifdef TLLM_ENABLE_CUDA + // TMA descriptor for Q. + CUtensorMap tmaQ_; + // TMA descriptor for K. + CUtensorMap tmaK_; + // TMA descriptor for V. + CUtensorMap tmaV_; + // The descriptor for O. + CUtensorMap tmaO_; + + // For FP4 KV cache, additional scaling factors are needed. + + // TMA descriptor for K scaling factor. + CUtensorMap tmaKSf_; + // TMA descriptor for V scaling factor. + CUtensorMap tmaVSf_; +#endif + + // grid dimensions, these might differ from actual grid the kernel is launched with + // for persistent kernels on Hopper GPUs. + int32_t logicalGridDimX, logicalGridDimY, logicalGridDimZ; + + // The output pointer (used by STG for last tile). + void* ptrO; + // The output SF pointer (used for FP4 output). + void* ptrSfO; + // The attention sinks pointer (additional value per head in the denominator of the softmax). + float const* ptrAttentionSinks; + // The cumulative sequence lengths for Q. + int32_t const* ptrCumSeqLensQ; + // The cumulative sequence lengths for K/V. + int32_t const* ptrCumSeqLensKv; + // The packed custom mask. + uint32_t const* ptrCustomMask; + // The packed custom mask's offsets of each sequence. + int64_t const* ptrCustomMaskOffsets; + // The debug output matrix O + float* ptrDebugO; + // The first sparseMask offsets in the Kv sequence dimension. + int32_t const* ptrFirstSparseMaskOffsetsKv; + // The counter for the multiCtasKv mode. + int32_t* ptrMultiCtasKvCounter; + // The device output scale for FP8 quantization. Only needed by trt-llm fp8 kernels as the sca- + // les have to be on the device currently. + float const* ptrOutputScale; + // The page indexes of the paged-kv buffer with shape of [batchSize, 2, maxNumPagesPerSeq]. + int32_t const* ptrPageIdxKv; + // The partial matrix O for each CtaKv when the multiCtasKv mode is enabled. + void* ptrPartialO; + // The partial softmax stats (max/sum)for each CtaKv when the multiCtasKv mode is enabled. + float2* ptrPartialStats; + // The scaling factors for K. + float const* ptrSageAttnSfsK; + // The scaling factors for P. + float const* ptrSageAttnSfsP; + // The scaling factors for Q. + float const* ptrSageAttnSfsQ; + // The scaling factors for V. + float const* ptrSageAttnSfsV; + // The device scaling factor for softmax (multiplied by log2 to use faster exp2). Only needed by + // trt-llm fp8 kernels as the scales have to be on the device currently. + float const* ptrScaleSoftmaxLog2; + // The SF scale for Kv on device. Only needed by trt-llm kernels as the scales have to be on the + // device currently. + float const* ptrScaleSfKv; + // The SF scale for O on device. Only needed by trt-llm kernels as the scales have to be on the + // device currently. + float const* ptrScaleSfO; + // The sequence lengths for K/V. Required by pagedKv kernels to avoid unnecessary computation + // based on (ptrCumSeqLensKv[batchIdx + 1] - ptrCumSeqLensKv[batchIdx]). + int32_t const* ptrSeqLensKv; + // When collecting skip softmax stats, store them here + // Note that softmax and BMM2 are skipped at different granularity (warp vs tile) + // [0] -> skipped softmax warp blocks; [1] -> total softmax warp blocks. + // [2] -> skipped BMM2s; [3] -> total BMM2s. + int32_t* ptrSkipSoftmaxStats; + // The softmax stats buffer. + float2* ptrSoftmaxStats; + + // The attention window size for sliding window attention. + int32_t mAttentionWindowSize; + // The batch size + int32_t mBatchSize; + // The chunked attention size in log2. + int32_t mChunkedAttentionSizeLog2; + // The factor to add to the maximum value to increase the probability + // of skip correction during next iterations. + float mInflateMax; + // The log of the Sage Attention block size for K. + int32_t mLogNumEltsPerSageAttnBlkK; + // The log of the Sage Attention block size for P. + int32_t mLogNumEltsPerSageAttnBlkP; + // The log of the Sage Attention block size for Q. + int32_t mLogNumEltsPerSageAttnBlkQ; + // The log of the Sage Attention block size for V. + int32_t mLogNumEltsPerSageAttnBlkV; + // The sequence lengths for Q and K/V. + int32_t mMaxSeqLenQ, mMaxSeqLenKv; + // The maximum number of CTAs for Q. + int32_t mMaxNumCtasQ; + // The maximum number of CTAs for K/V. + int32_t mMaxNumCtasKv; + // The maximum number of pages per sequence for paged-kv buffer. + int32_t mMaxNumPagesPerSeqKv; + // The number of heads for K/V. + int32_t mNumHeadsKv; + // The number of heads for Q. + int32_t mNumHeadsQ; + // The number of Q heads per K/V head (i.e. mNumHeadsQ / mNumHeadsKv). + int32_t mNumHeadsQPerKv; + // The number of headsQ per K/V head as a fast_mod_div divisor. + trtllm::dev::fast_mod_div mNumHeadsQPerKvDivisor{1}; + // The hidden size of O. + int64_t mNumHiddenEltsO; + // The total number of pages in the paged-kv memory pool. + int32_t mNumPagesInMemPool; + // The number of tokensQ per CTA (used for groupsHeadsTokensQ generation kernel). + int32_t mNumTokensPerCtaQ; + // The number of tokens per page (used if dynamic numTokensPerPage is enabled). + int32_t mNumTokensPerPageLog2; + // The output scale for FP8 quantization. + float mOutputScale; + // The scaling factor for softmax (multiplied by log2 to use faster exp2). + float mScaleSoftmaxLog2; + // The SF scale for Kv. + float mScaleSfKv; + // The SF scale for O. + float mScaleSfO; + // Threshold to decide whether warp skips softmax ops + float mSkipSoftmaxThresholdScaleFactor; + // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase + // kernel when inflight batching is enabled in TRT-LLM. + int32_t mStartTokenIdxSfO; + // The sum of sequence lengths for Q and K/V. + int32_t mSumOfSeqLensQ, mSumOfSeqLensKv; + // The sparseMla topK value. + int32_t mSparseMlaTopK; + // The flag to use block sparse attention. + bool mUseBlockSparseAttention; + // Whether the indices for K & V pages are shared as unified index (vLLM/FlashInfer). + bool mUsesSharedPagedKvIdx{false}; + + // Note: No implementation functions here as they use STL which is not available in NVRTC +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace fmha diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelTraits.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelTraits.h new file mode 100644 index 000000000000..46ddcdc34a59 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/KernelTraits.h @@ -0,0 +1,1185 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#ifdef TLLM_FMHA_TRTLLM_COMPAT +#include "trtllmGenExportCompat.h" +#else +#include +#include "KernelConfigBase.h" +#include "KernelParams.h" +#include +#include +#include +#endif // TLLM_FMHA_TRTLLM_COMPAT +#include +#include +#include + +namespace fmha { + +struct KernelConfig : public KernelConfigBase { + // The data type of softmax. + tg::Dtype mDtypeSoftmax; + // The maximum attention head size for K and V. + int32_t mMaxHeadDimKv; + // The number of elements in the packed uint32_t element for Q. + int32_t mNumEltsPerUInt32Q; + // The number of elements in the packed uint32_t element for K/V. + int32_t mNumEltsPerUInt32Kv; + // The number of elements in the packed uint32_t element for O. + int32_t mNumEltsPerUInt32O; + // The number of stages of the Epilogue buffer. + int32_t mNumStagesEpilogue; + // The number of stages of the persistent work id pipeline. + int32_t mNumStagesWorkId; + // The number of stages of the KV shared memory buffer. + int32_t mNumStagesKv; + // The number of stages of the K shared memory buffer. + int32_t mNumStagesK; + // The number of stages of the V shared memory buffer. + int32_t mNumStagesV; + // The number of stages of the pageOffsetsKv shared memory buffer. + int32_t mNumStagesPageOffsetsKv; + // The number of stages of the Q shared memory buffer. + int32_t mNumStagesQ; + // The number of stages of the transformed KV shared memory buffer. + int32_t mNumStagesTransformedKv; + // The number of stages of the transposed V shared memory buffer. + int32_t mNumStagesTransposedV; + // The number of tmem cols we will allocate once. + int32_t mNumTmemCols; + // Does it support pagedKv tensors? + bool mSupportsPagedKv; + // The softmax statistics tile size. + int32_t mTileSizeStats; + // Epilogue tile sizes for each instance in the M dimension. + int32_t mTileSizeEpilogueM; + // Epilogue tile sizes for each instance in the N dimension. + int32_t mTileSizeEpilogueN; + // The TileSizeEpilogueN in uint32_t. + int32_t mTileSizeEpilogueNInUInt32; + // Split epilogueM into multiple tiles to use fewer registers. Each thread handles one uint32_t. + int32_t mTileSizeStgEpilogueM; + // The Tmem to Smem copy atom size of each iteration in a epilogue tile. + int32_t mTmemCpAtomSizeEpilogue; + // The copy atom size for copying softmax output to TMEM. + int32_t mTmemCpAtomSizeP; + + // The default constructor. + KernelConfig() {} + + // The constructor where values are set. + template + KernelConfig(FmhaOptions_ const& options) + : KernelConfigBase(options) // Copy all base class members from options. + , mSupportsPagedKv{options.mQkvLayout == QkvLayout::PagedKv} { + // Override mHeadDimPerCtaV with computed value if it was 0. + if (mHeadDimPerCtaV == 0) { + mHeadDimPerCtaV = mHeadDimV; + } + + // The data type of softmax computation. + if (options.mEnablesFp16Softmax) { + // E4m3 kernels will also use Fp16 for softmax computation. + mDtypeSoftmax = (mDtypeQ == tg::Dtype::Bfloat16) ? tg::Dtype::Bfloat16 : tg::Dtype::Fp16; + } + + // The maximum headDim for K and V. + mMaxHeadDimKv = std::max(mHeadDimQk, mHeadDimV); + + // The tileSizeN of the tileB in each CTA, which is computed as tileSizeND / clusterDimX. + int32_t tileSizeNB = mTileSizeKv / options.mClusterDimX; + + // Is it the DS MLA-generation kernel with keepsMmaAb? + bool keepsMmaAbForDsMlaGen = mIsMlaGen && + isKeepsMmaAbForGenerationKernel(options.mFmhaKernelType) && + (mHeadDimQk == 576 && mHeadDimV == 512); + + // Set the number of stages of the Q shared memory buffer. + // When numTileKv is equal to 2, setting mNumStagesQ to 2 can also improve performance with the + // persistent tile scheduler. + mNumStagesQ = 2; + if (mSwapsMmaAb) { + // Assume maximum 32KB of smemQ can be used considering smemP and smemKv usage. + // This will be finetuned later. + int64_t totalNumBitsQ = 32 * 1024 * 8; + // The number of bits per tileQ. + int64_t numBitsPerTileQ = tg::dtypeGetNumBits(mDtypeQ) * mTileSizeQ * mHeadDimQk; + // The number of stages. + mNumStagesQ = std::min(2, static_cast(ceilDiv(totalNumBitsQ, numBitsPerTileQ))); + } else if (mNumInstsQ == 1 && options.mTileScheduler == TileScheduler::Static) { + mNumStagesQ = 1; + } + + // Set numStagesQ for headDim > 128 kernels. + if (mNumInstsQ * mNumInstsKv == 1) { + TLLM_CHECK_INFO(mTileSizeQ == 64 || (mHeadDimQk > 128 && mHeadDimV > 128), + "Consider using numInstsQ = 2 for better performance."); + // There is no enough shared memory for 2 stages when the headDim is not split into multiple + // stages. + if (mHeadDimPerStageKv == 0 && keepsMmaAbForDsMlaGen) { + mNumStagesQ = 1; + } else { + // There is no enough shared memory for 2 stages when 16bit kv data type is used. + mNumStagesQ = int32_t{2 * 8 /*bits*/ / std::max(tg::dtypeGetNumBits(mDtypeQ), 8)}; + } + } + + // The number of stages of the KV shared memory buffer. + if (tg::isArchHopper(options.mCudaArch)) { + mNumStagesTransformedKv = 0; + mNumStagesQ = mNumInstsQ; + + // The minimal amount of stages for the kernel to run + mNumStagesK = 1; + mNumStagesV = 1; + mNumStagesTransposedV = mTransposeSmemV ? 1 : 0; + + // How much data in smem eash stage takes + int32_t numBytesPerSmemStageQ = mTileSizeQ * mHeadDimQk * dtypeGetNumBits(mDtypeQ) / 8; + int32_t numBytesPerSmemStageK = + mTileSizeKv * std::max(mHeadDimQk, mHeadDimV) * dtypeGetNumBits(mDtypeKv) / 8; + int32_t numBytesPerSmemStageV = + mTileSizeKv * std::max(mHeadDimQk, mHeadDimV) * dtypeGetNumBits(mDtypeKv) / 8; + + // How much smem we have left + int32_t numFreeBytes = 227 * 1024; + // Take into account barriers in smem + numFreeBytes -= 4 * 1024; + // Take into account the minimal amount of stages + numFreeBytes -= mNumInstsQ * numBytesPerSmemStageQ; + numFreeBytes -= mNumStagesK * numBytesPerSmemStageK; + numFreeBytes -= mNumStagesV * numBytesPerSmemStageV; + numFreeBytes -= mNumStagesTransposedV * numBytesPerSmemStageV; + + // Increment all the stages if smem allows + if (numFreeBytes - numBytesPerSmemStageK >= 0) { + ++mNumStagesK; + numFreeBytes -= numBytesPerSmemStageK; + } + + if (mTransposeSmemV && (numFreeBytes - numBytesPerSmemStageV >= 0)) { + ++mNumStagesTransposedV; + numFreeBytes -= numBytesPerSmemStageV; + } + + if (numFreeBytes - numBytesPerSmemStageV >= 0) { + ++mNumStagesV; + numFreeBytes -= numBytesPerSmemStageV; + } + + mNumStagesKv = mNumStagesK + mNumStagesV; + } else { + + + // If dtypeQ != dtypeKv, the kv elements will be converted to dtypeQ in smemTransformedKv, + // so the number of stages will be computed based on dtypeQ. + mNumStagesKv = 3; + + // When the headDim is not split into multiple stages, we can use at most 4 stages for e4m3 + // data type. + if (mHeadDimPerStageKv == 0 && keepsMmaAbForDsMlaGen) { + TLLM_CHECK_ERROR(options.mSeparateSmemKv, "Not supported"); + mNumStagesKv = int32_t{4 * 8 /*bits*/ / std::max(tg::dtypeGetNumBits(mDtypeQ), 8)}; + } else if (keepsMmaAbForDsMlaGen) { + // For DS MLA-generation kernels with keepsMmaAb, we can only have at most 8 stages for e4m3 + // data type. + mNumStagesKv = int32_t{(tileSizeNB == 64 ? 14 : 8) * 8 /*bits*/ / + std::max(tg::dtypeGetNumBits(mDtypeQ), 8)}; + } else if (mReuseSmemKForV) { + // Only MlaGen kernels support reusing smemK for V. More limitations can be found in + // checkFmhaOptions. + mNumStagesKv = (mHeadDimQk + mHeadDimPerStageKv - 1) / mHeadDimPerStageKv * 2; + } else if (mNumInstsQ == 1) { + // The numHeadDimBytes (padded to multiple of 128B) + int32_t numHeadDimBytes = ceilDiv(tg::dtypeGetNumBits(mDtypeQ) * mHeadDimQk / 8, 128) * 128; + // The total number of KB for smemQ. + int32_t totalNumKBSmemQ = numHeadDimBytes * mTileSizeQ / 1024; + // The maximum buffer size for smemKv (at most 144KB for KV, and at most 218KB for Qkv). + int32_t maxBufferSizeKBForSmemKv = std::min(144, 218 - totalNumKBSmemQ * mNumStagesQ); + // Calculate the number of stages for smemKv. + mNumStagesKv = calculateNumStagesKv(maxBufferSizeKBForSmemKv); + } + mNumStagesTransformedKv = tg::dtypeGetNumBits(mDtypeKv) >= 8 ? 2 : 4; + mNumStagesTransposedV = 0; + // Set mNumStagesK and mNumStagesV to reasonable values. + mNumStagesK = mNumStagesKv / 2; + mNumStagesV = mNumStagesKv - mNumStagesK; + } + + // The number of stages of the pageOffsetsKv shared memory buffer. + mNumStagesPageOffsetsKv = 6; + TLLM_CHECK_ERROR(mNumStagesPageOffsetsKv >= 2, + "The numStagesPageOffsetsKv must be >= 2 as it is shared by both K and V"); + + // Set the number of tmem cols we will allocate once. + mNumTmemCols = 512; + // Set the softmax statistics tile size. + mTileSizeStats = 32; + // Set epilogue tile sizes for each instance in the M dimension. + mTileSizeEpilogueM = mTileSizeQ; + // Set epilogue tile sizes for each instance in the N dimension. Preferably 128B. + mTileSizeEpilogueN = + std::min(int32_t{128 * 8 /*bits*/ / tg::dtypeGetNumBits(mDtypeQ)}, mHeadDimV); + // Set the Tmem to Smem copy atom size of each iteration in a epilogue tile. + mTmemCpAtomSizeEpilogue = 16; + + // Set the number of stages of the Epilogue buffer. + mNumStagesEpilogue = std::min(2, std::max(1, mHeadDimV / mTileSizeEpilogueN)); + // The number of stages of the persistent work id pipeline. + mNumStagesWorkId = 2; + + // Make sure Tmem copy atom size never overreaches the size of the tile. + TLLM_CHECK_ERROR(mTmemCpAtomSizeEpilogue <= mTileSizeEpilogueN, "Invalid size"); + + // Set the number of Q elements in the packed uint32_t element. + mNumEltsPerUInt32Q = 32 / tg::dtypeGetNumBits(mDtypeQ); + // Set the number of KV elements in the packed uint32_t element. + mNumEltsPerUInt32Kv = 32 / tg::dtypeGetNumBits(mDtypeKv); + // Set the number of O elements in the packed uint32_t element. + mNumEltsPerUInt32O = 32 / tg::dtypeGetNumBits(mDtypeOut); + + // The tmemTileSizeND. + int32_t tmemTileSizeND = mTileSizeKv; + // If the tileSizeQ is 64, the 2x2 warp layout (M=128 2CTA MMA) results in only half of the + // TMEM columns being processed by each thread. + if (mTileSizeQ == 64) { + tmemTileSizeND /= options.mClusterDimX; + } + + // The maximum tmemCpAtomSizeP. + int32_t maxTmemCpAtomSizeP = tmemTileSizeND / mNumEltsPerUInt32Q; + TLLM_CHECK_ERROR(tmemTileSizeND % mNumEltsPerUInt32Q == 0, "The tileSizeKv is not supported"); + // Set the copy atom size for copying softmax output to TMEM. + if (mDtypeQ == tg::Dtype::E4m3) { + // !!! + // WARNING: On e4m3 kernels, 16 leads to more scoreboard dependencies in softmax SASS + // sequence. + // !!! + mTmemCpAtomSizeP = std::min(32, maxTmemCpAtomSizeP); + } else if (mDtypeQ == tg::Dtype::Fp16 || mDtypeQ == tg::Dtype::Bfloat16) { + // !!! + // WARNING: On half-precision kernels, 32 leads to excessive spill in softmax SASS sequence. + // !!! + mTmemCpAtomSizeP = std::min(16, maxTmemCpAtomSizeP); + } else { + TLLM_LOG_ERROR("Unexpected dtype ", static_cast(mDtypeQ)); + } + + // The paged-kv configurations. The number of tokens in one pageKv. + mNumTokensPerPage = mSupportsPagedKv ? options.mNumTokensPerPage : mTileSizeKv; + + // The swizzle patterns require the row dimension (seqLen dimension) to be equal to or larger + // than 8. Otherwise, the final shared memory tensor, after multiple copies, won't match the + // expected swizzle pattern. + TLLM_CHECK_ERROR(mSupportsPagedKv || (((mNumTokensPerPage & (mNumTokensPerPage - 1)) == 0) && + (mNumTokensPerPage >= 8)), + "NumTokensPerPage must be power-of-2 and equal or large than 8"); + + // The TileSizeEpilogueN in uint32_t. + TLLM_CHECK_ERROR(mTileSizeEpilogueN % mNumEltsPerUInt32Q == 0, "Invalid size"); + mTileSizeEpilogueNInUInt32 = mTileSizeEpilogueN / mNumEltsPerUInt32Q; + + // Split epilogueM into multiple tiles to use fewer registers. Each thread handles one + // uint32_t. + mTileSizeStgEpilogueM = 32 / mTileSizeEpilogueNInUInt32; + } + +private: + // Calculate the number of stages for K/V. + int32_t calculateNumStagesKv(int32_t bufferSizeKB) { + // The total number of bits for K/V. + int64_t totalNumBitsKv = bufferSizeKB * 1024 * 8; + // The head dimension per stage for K/V. + int32_t headDimPerStageKv = mHeadDimPerStageKv == 0 ? mHeadDimQk : mHeadDimPerStageKv; + // The number of bits per tileKv. + int64_t numBitsPerTileKv = + std::max(tg::dtypeGetNumBits(mDtypeQ), 8) * mTileSizeKv * headDimPerStageKv; + // The number of stages. + return std::max(1, static_cast(totalNumBitsKv / numBitsPerTileKv)); + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct MmaTraits { + // The data type of Mma. + tg::Dtype mDtypeMma; + // The Atom Mn for Q tensor. + int32_t mAtomQMn; + // The Atom Mn for K tensor. + int32_t mAtomKMn; + // The Atom Mn for P tensor (softmax output). + int32_t mAtomPMn; + int32_t mTilePMn; + // The Atom Mn for V tensor. + int32_t mAtomVMn; + // The Atom Mma for Q * K^T. + int32_t mAtomQkM; + int32_t mAtomQkN; + int32_t mAtomQkK; + // The Tile shape for Q * K^T accumulators (same as Atom shape). + int32_t mTileQkM; + int32_t mTileQkN; + // The number of accumulator registers per thread. + int32_t mNumQkEltsPerThread; + // The Atom Mma for P * V. + int32_t mAtomPvM; + int32_t mAtomPvN; + int32_t mAtomPvK; + // The Tile shape for P * V accumulators (same as Atom shape). + int32_t mTilePvM; + int32_t mTilePvN; + int32_t mValidTilePvN; + // Whether to use UTCMMA in 2-CTA mode. + bool mUseUtcmma2CtaMode; + // The number of accumulator registers per thread. + int32_t mNumPvEltsPerThread; + // The default constructor. + MmaTraits() {} + + // The constructor. + template + MmaTraits(FmhaOptions_ const& options) + : mDtypeMma{options.mDtypeQ} { + + // Whether to use 2-CTA mode for UTCMMA. + mUseUtcmma2CtaMode = options.mClusterDimX == 2; + // For now, 128x128x16 is not supported. It requires 228KB of shared memory but the way we + // generate code leads to an oversubscription of shared memory. To fix that limitation, we + // would have to separate how we allocate shared memory to avoid aligning barriers on 1,024B + // boundaries. + TLLM_CHECK_ERROR(options.mHeadDimV == 32 || options.mHeadDimV == 64 || + options.mHeadDimV == 128 || options.mHeadDimV % 128 == 0, + "Unsupported HeadDim for BMM2-N ", + options.mHeadDimV); + + // Whether MMA dtype is FP8. + bool isMmaFp8 = mDtypeMma == tg::Dtype::E4m3; + + // The Atom Mn for Q tensor. + mAtomQMn = options.mTileSizeQ; + // The Atom Mn for K tensor. + mAtomKMn = options.mTileSizeKv; + + // The Atom Mn for P tensor (softmax output). + mAtomPMn = mAtomQMn; + mTilePMn = mAtomPMn; + + // The Atom Mn for V tensor. + mAtomVMn = options.mHeadDimV; + + // The Atom Mma for Q * K^T. + mAtomQkM = options.mSwapsMmaAb ? options.mTileSizeKv : options.mTileSizeQ; + mAtomQkN = options.mSwapsMmaAb ? options.mTileSizeQ : options.mTileSizeKv; + { + mAtomQkK = isMmaFp8 ? 32 : 16; + } + + if (tg::isArchHopper(options.mCudaArch) && options.mTransposeSmemV && + (options.mNumTransposeWarps == 4)) { + // Make sure the accumulator of a single MMA instruction is smaller than 128 regs, + // otherwise it would not compile with ctaSize=512, + // even if we increase registers for the warp with setmaxnreg + mAtomQkN = std::min(mAtomQkN, 128); + } + + // The Tile shape for Q * K^T accumulators (same as Atom shape). + mTileQkM = mAtomQkM; + mTileQkN = mAtomQkN; + + // The number of accumulator registers per thread. + mNumQkEltsPerThread = mAtomQkN; + + // The Atom Mma for P * V - M/N dimensions. + // + // For DeepSeek MLA, we force the MMA's headDim to be 128 as we distribute the headDim + // over multiple MMAs. + mAtomPvM = options.mSwapsMmaAb ? std::min(128, options.mHeadDimV) : options.mTileSizeQ; + mAtomPvN = options.mSwapsMmaAb ? options.mTileSizeQ + : std::min(128 * options.mClusterDimX, options.mHeadDimV); + + if (tg::isArchHopper(options.mCudaArch) && (options.mNumInstsQ == 1)) { + mAtomPvN = std::min(128 * options.mClusterDimX, options.mHeadDimV / 2); + } + + if (tg::isArchHopper(options.mCudaArch) && options.mTransposeSmemV && + (options.mNumTransposeWarps == 4)) { + // Make sure the accumulator of a single MMA instruction is smaller than 128 regs, + // otherwise it would not compile with ctaSize=512, + // even if we increase registers for the warp with setmaxnreg + mAtomPvN = std::min(mAtomPvN, 128); + } + + // The K dimension. + { + mAtomPvK = isMmaFp8 ? 32 : 16; + } + + // The Tile shape for P * V accumulators (same as Atom shape). + mTilePvM = mAtomPvM; + mTilePvN = mAtomPvN; + mValidTilePvN = options.mSwapsMmaAb ? mAtomQMn : mAtomPvN; + + // Check if TilePvM is valid or not. + TLLM_CHECK_ERROR(mTilePvM == 64 || mTilePvM == 128, + "Invalid TilePvM as MMA only supports 64 or 128. mTilePvM=", + mTilePvM); + + // The number of accumulator registers per thread. + // Note that when TilePvM is 64, each threads only load 16 data paths from TMEM. + mNumPvEltsPerThread = (mValidTilePvN * mTilePvM) / 128; + + // Update the MMA instruction shapes considering the 2Cta mode. + if (mUseUtcmma2CtaMode) { + // The base MMA instruction shape is set to tileD's shape, which is (M / 2) x N. + // As a result, we need to multiply the M dimension by 2. + mAtomQkM *= 2; + mAtomPvM *= 2; + } + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper functions to get the number of head dimension stages for V. +// When the head dimension exceeds headDimPerStageKv, we must wrap it over multiple columns. +inline int32_t getNumHeadDimStagesV(int headDimPerCtaV, int headDimPerStageKv) { + int numHeadDimStages{1}; + if (headDimPerCtaV > headDimPerStageKv && headDimPerStageKv > 0) { + numHeadDimStages *= (headDimPerCtaV + headDimPerStageKv - 1) / headDimPerStageKv; + } + return numHeadDimStages; +} + +struct KernelTraits : public KernelConfig, public MmaTraits { + + // The tile size for the correction step. + int32_t mCorrTileSize; + // Whether to cross-interleave TMEM columns for S and P across instances. When true, tmemP0 + // shares columns with tmemS1 and tmemP1 shares columns with tmemS0. Used when P does not have + // dedicated columns (mSeparateTmemColsForSAndP false) to avoid data races. orderedSequence syncs + // LDTM/STTM across instances. + bool mInterleavesTmemSAndP; + // The number of head elts (per token) in each block of shared memory (see above explanation). + int32_t mNumEltsInClampedHeadDimKv; + // The number of head elts (per token) in each block of shared memory (see above explanation). + int32_t mNumEltsInClampedHeadDimQ; + // The number of FP4 elements per scaling factor. + int32_t mNumEltsPerSf; + // The K SMEM tile size. + int32_t mNumEltsPerSmemStageK; + // The KV SMEM tile size. + int32_t mNumEltsPerSmemStageKv; + // The V SMEM tile size. + int32_t mNumEltsPerSmemStageV; + // The number of keys per tile. + int32_t mNumKeysPerTile; + // The number of page offsets loaded per stage. + int32_t mNumLoadedPageOffsetsPerStage; + // The number of warps for loadTask. + int32_t mNumLoadTaskWarps; + // The number of transform stages for SmemTransformedKv. + int32_t mNumSmemTransformStages; + // The number of TMEM columns for each stage of K/V. + int32_t mNumTmemColsPerStageKv; + // The number of TMEM columns for P. + int32_t mNumTmemColsP; + // The number of TMEM columns for S. + int32_t mNumTmemColsS; + // The K SMEM transaction size. + int32_t mNumTxBytesK; + // The KV SMEM transaction size. + int32_t mNumTxBytesKv; + // The V SMEM transaction size. + int32_t mNumTxBytesV; + // Whether to use separate TMEM columns for S and P to avoid potential data races. + bool mSeparateTmemColsForSAndP; + // Use separate TMEM columns for TmemS and TmemStat to avoid potential data races. + bool mSeparateTmemColsForSAndStats; + // The size of the K/V tile per stage. + int32_t mSmemKvTileSize; + // Whether to store the transformed K/V in the TMEM. + bool mStoreTransformedKvInTmem; + // Whether to store the softmax local in shared memory (true: SMEM, false: TMEM). + bool mStoresSoftmaxLocalInSmem; + + // The default constructor. + KernelTraits() + : KernelConfig() + , MmaTraits() {} + + // The constructor. + template + KernelTraits(FmhaOptions_ const& options) + : KernelConfig(options) + , MmaTraits(options) { + + // The tile size for the correction step. + mCorrTileSize = std::min(mValidTilePvN, 64); + + // The number of keys per tile. + mNumKeysPerTile = std::min(mNumTokensPerPage, mTileSizeKv); + + // The number of page offsets loaded by all threads. + mNumLoadedPageOffsetsPerStage = 32; + // SparseMla uses numTokensPerPage = 1 so more pageOffsets need to be loaded per stage. + if (options.mIsSparseMla) { + TLLM_CHECK_ERROR((mTileSizeKv % mNumKeysPerTile) == 0, + "mTileSizeKv must be divisible by mNumKeysPerTile"); + // FIXME(perkzz): In loadScheduleForTwoInstsOrTwoStagesKv, K0 and K1 are prefetched at the + // start, but freqInfo for the Task does not properly skip the initial unrolled steps, which + // can result in a deadlock. Additionally, for robustness, the KV ordering should be made + // consistent between loadPageOffsetsKvTask (KVKV) and loadTask (KKVKVK). + mNumLoadedPageOffsetsPerStage = 2 * (mTileSizeKv / mNumKeysPerTile); + } + + // The number of warps for loadTask. + // The sparseMla kernels use 4 warps as it uses gather4 to gather sparse kv in the token + // granularity (same as page size 1). + mNumLoadTaskWarps = (options.mIsSparseMla ? 4 : 1); + + if (!tg::isArchHopper(options.mCudaArch)) { + // Make sure the sizes for the epilogue satisfy the following conditions: + TLLM_CHECK_ERROR(mSwapsMmaAb || + (mTileSizeEpilogueM == mTileSizeQ && mHeadDimV % mTileSizeEpilogueN == 0), + "Not supported"); + } + + // Make sure the two Mmas have the same K dimension. + { + // For other architectures, the K dimension of BMM1 and BMM2 must be the same. + TLLM_CHECK_ERROR(mAtomQkK == mAtomPvK, "BMM1-K and BMM2-K must be the same"); + } + + // Verify that the head dim is compatible with the K dimension of the MMA atom. + TLLM_CHECK_ERROR((mHeadDimQk % mAtomQkK) == 0, "HeadDim % BMM1-K must be 0"); + + // The head dimension for K/V. + auto headDimKv = options.mHeadDimPerStageKv != 0 ? options.mHeadDimPerStageKv : mMaxHeadDimKv; + auto headDimK = options.mHeadDimPerStageKv != 0 ? options.mHeadDimPerStageKv : mHeadDimQk; + auto headDimV = options.mHeadDimPerStageKv != 0 ? options.mHeadDimPerStageKv : mHeadDimV; + + // In shared memory, the elements are stored as 2D blocks. For each one of those blocks, the + // fastest moving dimension is the head dimension (even for V where the transposition happens + // in the MMA). To be able to issue fast copies from shared memory to the tensor cores within + // the main loop (and avoid bank conflicts), the number of contiguous channel elements must + // fit in at most 128B. If the head dimension is larger than what fits in 128B, multiple + // blocks are needed to store the elements. If the head dimension is not large enough to fill + // 128B worth of data, the number of channels per token in each SMEM block must be clamped + // (the hardware can efficiently deal with 32B, 64B and 128B per token). + + // The number of elements in 128B for Q. + int32_t numEltsIn128BQ = mNumEltsPerUInt32Q /*4B*/ * 32; + // The number of head elts (per token) in each block of shared memory (see above explanation). + mNumEltsInClampedHeadDimQ = std::min(numEltsIn128BQ, mHeadDimQk); + + // The number of elements in 128B for Q. + int32_t numEltsIn128BKv = mNumEltsPerUInt32Kv /*4B*/ * 32; + // The number of head elts (per token) in each block of shared memory (see above explanation). + TLLM_CHECK_ERROR(mHeadDimQk == mHeadDimV || headDimKv >= numEltsIn128BKv, + "Different mNumEltsInClampedHeadDim for K and V might be needed"); + mNumEltsInClampedHeadDimKv = std::min(numEltsIn128BKv, headDimKv); + + // The HW is designed to have NumEltsIn128B elements consumed by 4 UTC?Mmas in the K + // dimension. + { + TLLM_CHECK_ERROR(numEltsIn128BQ == mAtomQkK * 4, "Internal error"); + } + + // TmemS and TmemStats can use different TMEM columns to avoid potential data-races when + // (numTmemSCols + numTmemStatsCols) * mNumInstsQ * mNumInstsKv <= 256. + mNumTmemColsS = mTileQkN; + if (mUseUtcmma2CtaMode && mAtomQkM == 128) { + // Only need half the number of TMEM columns for S if M=128 2CTA UTCMMA instruction is used. + mNumTmemColsS /= 2; + } + + // The number of transform stages for SmemTransformedKv. + mNumSmemTransformStages = 2; + + // Note: mInterleaveSfV and mUsesSharedPagedKvIdx are inherited from KernelConfigBase. + + // The number of FP4 elements per scaling factor. + mNumEltsPerSf = 16; + // The number of FP4 SF per row. + int32_t numSfPerRow = mMaxHeadDimKv / mNumEltsPerSf; + + // The head dimension bytes for K/V. + auto headDimBytesKv = headDimKv * tg::dtypeGetNumBits(mDtypeKv) / 8; + auto headDimBytesK = headDimK * tg::dtypeGetNumBits(mDtypeKv) / 8; + auto headDimBytesV = headDimV * tg::dtypeGetNumBits(mDtypeKv) / 8; + // The tileSizeNB of the BMM1, which is computed as tileSizeND / clusterDimX. + int32_t tileSizeNB = mTileSizeKv / options.mClusterDimX; + + // Whether to store the transformed K/V in the TMEM. Currently only swapsMmaAb generation + // phase kernels are supported. Only supports E2M1 Kv and E4M3 Q. HeadDimPerStageKv should be + // 128, this is a limitation of TMA load of type CU_TENSOR_MAP_DATA_TYPE_16U6_ALIGN16B. + auto transformedKvHeadDim = mHeadDimPerStageKv == 0 ? mHeadDimQk : mHeadDimPerStageKv; + mStoreTransformedKvInTmem = options.mDtypeKv == tg::Dtype::E2m1 && + options.mDtypeQ == tg::Dtype::E4m3 && + (transformedKvHeadDim == 128) && mSwapsMmaAb; + + // The number of TMEM columns for S. + int32_t numTmemColsS = mNumTmemColsS * 2; + // The number of instances Qkv. + auto numInstsQkv = mNumInstsQ * mNumInstsKv; + // The number of TMEM columns for O. + int32_t numTmemColsO = + getNumHeadDimStagesV(mHeadDimPerCtaV, transformedKvHeadDim) * mAtomPvN * numInstsQkv; + // Number of TMEM columns for P (each TMEM column is 32-bit wide). + // SwapsMmaAb uses shared memory for P, so no need to allocate TMEM columns for P. + mNumTmemColsP = mSwapsMmaAb ? 0 : ceilDiv(mNumTmemColsS * tg::dtypeGetNumBits(mDtypeQ), 32); + + // Check if enough TMEM columns are available for separate tmemP and tmemStats. + { + // Separate TMEM columns for S and P have only been implemented for context kernels. + // Using both mSeparateTmemColsForSAndP and mStoresSoftmaxLocalInSmem degrades performance + // with Pv0_Qk0_Pv1_Qk1 order. Separate TMEM for S and P is not used in this scenario. + // TODO: Add support for separate TMEM S and P in keepsMmaAb kernels. + mSeparateTmemColsForSAndP = (mNumInstsQ == 2) && (mMmaOrder == MmaOrder::Qk0_Pv0_Qk1_Pv1 || + mMmaOrder == MmaOrder::Qk0_Qk1_Pv0_Pv1); + mInterleavesTmemSAndP = false; + mSeparateTmemColsForSAndStats = false; + if (!isValidTmemAllocation(numTmemColsS, numTmemColsO) && mSeparateTmemColsForSAndP) { + mSeparateTmemColsForSAndP = false; + // If not enough TMEM columns for separate tmemP and tmemStats, try to use cross-interleaved + // S and P to save TMEM columns. + if ((mMmaOrder == MmaOrder::Qk0_Pv0_Qk1_Pv1 || mMmaOrder == MmaOrder::Qk0_Qk1_Pv0_Pv1)) { + mInterleavesTmemSAndP = true; + } + } + mSeparateTmemColsForSAndStats = true; + mStoresSoftmaxLocalInSmem = false; + // Store softmaxStats to shared memory for mInterleavesTmemSAndP or mSeparateTmemColsForSAndP + // is true. as it gives slight performance improvement (the hypothesis is that using TMEM for + // stats has more contention with tmemP/tmemS). + if (mInterleavesTmemSAndP || mSeparateTmemColsForSAndP) { + mStoresSoftmaxLocalInSmem = true; + mSeparateTmemColsForSAndStats = false; + } else if (!isValidTmemAllocation(numTmemColsS, numTmemColsO)) { + mSeparateTmemColsForSAndStats = false; + } + } + + // The number of TMEM columns for Stats. + int32_t numTmemColsStats = mSeparateTmemColsForSAndStats ? mTileSizeStats * 2 : 0; + + // Determine the number of stages if mStoreTransformedKvInTmem is true. + mNumTmemColsPerStageKv = 0; + if (mStoreTransformedKvInTmem) { + // The number of TMEM columns for each stage of E2m1 K/V. + mNumTmemColsPerStageKv = (transformedKvHeadDim * mTileSizeKv) / (4 * 128); + // The number of TMEM columns for K/V. + int32_t numTmemColsKv = mNumTmemCols - numTmemColsS - numTmemColsStats - numTmemColsO; + // The number of stages for K/V. + mNumStagesTransformedKv = numTmemColsKv / mNumTmemColsPerStageKv; + } + + // Sanity checks if we're using separate TMEM columns for S and P. + if (mSeparateTmemColsForSAndP) { + // Check that enough TMEM columns are available. + int32_t numTmemColsNeeded = numTmemColsS + numTmemColsStats + numTmemColsO + + (mInterleavesTmemSAndP ? 0 : 2 * mNumTmemColsP); + TLLM_CHECK_ERROR_FMT( + mNumTmemCols - numTmemColsNeeded >= 0, + "Not enough TMEM columns available. Have %d, need %d (S: %d, stats: %d, O: %d, P: %d)", + mNumTmemCols, + numTmemColsNeeded, + numTmemColsS, + numTmemColsStats, + numTmemColsO, + 2 * mNumTmemColsP); + // Check that we're not storing transformed K/V in TMEM. + TLLM_CHECK_ERROR(!mStoreTransformedKvInTmem, + "StoreTransformedKvInTmem incompatible with SeparateTmemColsForSAndP"); + } + // Sanity checks for cross-interleaved S and P. + if (mInterleavesTmemSAndP) { + TLLM_CHECK_ERROR(mNumInstsQ == 2 && mNumInstsKv == 1, + "InterleaveTmemSAndP requires numInstsQ == 2 and numInstsKv == 1"); + TLLM_CHECK_ERROR(!mStoreTransformedKvInTmem, + "StoreTransformedKvInTmem incompatible with InterleaveTmemSAndP"); + } + + // The size of the K/V tile per stage. + // Each CtaX in the cluster only needs to load half N of tensor B if the 2Cta Utcmma + // instruction is used. + mSmemKvTileSize = tileSizeNB * headDimKv; + // The size of the K/V scaling factor tile per stage. + int32_t smemKvSfTileSize = mDtypeKv == tg::Dtype::E2m1 ? tileSizeNB * numSfPerRow : 0; + // Calculate the mNumEltsPerSmemStageKv. + if (mDtypeKv == tg::Dtype::E2m1 && !mStoreTransformedKvInTmem) { + // When mStoreTransformedKvInTmem is false, input FP4 elements are packed in 8-bit + // containers. Therefore the number of elements should be halved. When + // mStoreTransformedKvInTmem is true, since CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN16B is used + // for TMA loading, each 8 4-bit elements are padded to 16B. In average, each element + // occupies 8 bit, therefore no need to halve the number of elements. + mNumEltsPerSmemStageKv = mSmemKvTileSize / 2 + smemKvSfTileSize; + } else { + // The number of elements per stage for K/V. + mNumEltsPerSmemStageKv = mSmemKvTileSize + smemKvSfTileSize; + } + + // Align each SMEM stage to 1024B when mStoreTransformedKvInTmem is true, as SWIZZLE_128B is + // used for TMA loading. + if (mStoreTransformedKvInTmem) { + mNumEltsPerSmemStageKv = ceilDiv(mNumEltsPerSmemStageKv, 1024) * 1024; + } + + // Calculate the transaction size for K/V. + mNumTxBytesKv = mSmemKvTileSize * tg::dtypeGetNumBits(mDtypeKv) / 8 + + smemKvSfTileSize * 1 /*byte per sf element*/; + // Align the transaction size to 128B for TMA loading. + if (headDimBytesKv > 128) { + mNumTxBytesKv = (mNumTxBytesKv / headDimBytesKv) * ceilDiv(headDimBytesKv, 128) * 128; + } + + // Calculate the transaction size for K. + mNumTxBytesK = tileSizeNB * headDimBytesK; + // Align the transaction size to 128B for TMA loading. + if (headDimBytesK > 128) { + mNumTxBytesK = tileSizeNB * ceilDiv(headDimBytesK, 128) * 128; + } + // The K SMEM tile size. + mNumEltsPerSmemStageK = (mNumTxBytesK * 8) / tg::dtypeGetNumBits(mDtypeKv); + + // Calculate the transaction size for V. + mNumTxBytesV = tileSizeNB * headDimBytesV; + // Align the transaction size to 128B for TMA loading. + if (headDimBytesV > 128) { + mNumTxBytesV = tileSizeNB * ceilDiv(headDimBytesV, 128) * 128; + } + // The V SMEM tile size. + mNumEltsPerSmemStageV = (mNumTxBytesV * 8) / tg::dtypeGetNumBits(mDtypeKv); + } + + // Check if the TMEM allocation is valid. + bool isValidTmemAllocation(int32_t numTmemColsS, int32_t numTmemColsO) const { + // The number of TMEM columns needed when separate TMEM columns for S and Stats are used. + int32_t numTmemColsNeeded = numTmemColsS + numTmemColsO; + if (mSeparateTmemColsForSAndStats) { + numTmemColsNeeded += mTileSizeStats * 2; + } + if (mSeparateTmemColsForSAndP) { + numTmemColsNeeded += 2 * mNumTmemColsP; + } + // Check if the TMEM allocation is valid. + return mNumTmemCols >= numTmemColsNeeded; + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Create KernelTraits from FmhaOptions (or any options type that KernelTraits can be constructed +// from). +template +inline KernelTraits getKernelTraitsFromOptions(FmhaOptions_ const& options) { + return KernelTraits(options); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +// +// clang-format off +// The TMEM allocation is organized as follows. +// +// If mSeparateTmemColsForSAndStats is true: +// [...................................FullTmem......................................................] +// [...TmemS0....][...TmemS1....][TmemStat0][TmemStat1][..TmemO0..][..TmemO1..][..TmemTransformedKv..] +// [TmemP0] [TmemP1] +// +// If mSeparateTmemColsForSAndP is true: +// [...................................FullTmem.....................................................] +// [.......TmemS0........][.......TmemS1........][TmemP0][TmemP1][.....TmemO0.....][.....TmemO1.....] +// [TmemStat0] [TmemStat1] +// +// If mSeparateTmemColsForSAndP and mSeparateTmemColsForSAndStats are both true: +// [...................................FullTmem.....................................................] +// [..TmemS0..][..TmemS1..][TmemStat0][TmemStat1][..TmemP0..][..TmemP1..][...TmemO0...][...TmemO1...] +// +// If mInterleavesTmemSAndP is true (cross-interleaved S and P across instances): +// [...................................FullTmem.....................................................] +// [.......TmemS0........][........TmemS1........][.........TmemO0.........][.......TmemO1..........] +// When not enough tmem columns for separate stats: [TmemStat1][TmemP1] in S0, [TmemStat0][TmemP0] in S1. +// When enough tmem columns for stats (mSeparateTmemColsForSAndStats): stats use dedicated columns +// after S ([TmemStat0][TmemStat1]); only P shares with S: tmemP0 with tmemS1, tmemP1 with tmemS0. +// Used when mSeparateTmemColsForSAndP is false. orderedSequence syncs LDTM/STTM across instances. +// +// Otherwise, the TMEM allocation is organized as follows: +// [...................................FullTmem.....................................................] +// [.......TmemS0........][.......TmemS1........][..TmemO0..][..TmemO1..][....TmemTransformedKv.....] +// [TmemStat0][TmemP0] [TmemStat1][TmemP1] +// clang-format on +// +inline int32_t getTmemAllocationS0(KernelTraits) { + return 0; +} + +inline int32_t getTmemAllocationS1(KernelTraits traits) { + return getTmemAllocationS0(traits) + traits.mNumTmemColsS; +} + +inline int32_t getTmemAllocationS(KernelTraits traits, int ii) { + return ii == 0 ? getTmemAllocationS0(traits) : getTmemAllocationS1(traits); +} + + +// Code-gen-only Expr overloads (require Expr.h, Kernel.h, TmemTile.h). +#ifndef TLLM_FMHA_TRTLLM_COMPAT + +inline tg::Expr const* getTmemAllocationS(tg::Kernel* kernel, + KernelTraits traits, + tg::Expr const* instId) { + return TLLM_MAKE_OBJ(tg::ExprFromTernaryOp, + kernel, + tg::Dtype::Int32, + TLLM_MAKE_OBJ(tg::BinEq, kernel, instId, kernel->getInt0()), + kernel->getInt(getTmemAllocationS0(traits)), + kernel->getInt(getTmemAllocationS1(traits))); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +inline int32_t getTmemAllocationStats0(KernelTraits traits) { + // TmemS and TmemStats can use different TMEM columns to avoid potential data-races. + return traits.mSeparateTmemColsForSAndStats ? (getTmemAllocationS1(traits) + traits.mNumTmemColsS) + : getTmemAllocationS0(traits); +} + +inline int32_t getTmemAllocationStats1(KernelTraits traits) { + // TmemS and TmemStats can use different TMEM columns to avoid potential data-races. + return traits.mSeparateTmemColsForSAndStats + ? (getTmemAllocationStats0(traits) + traits.mTileSizeStats) + : getTmemAllocationS1(traits); +} + +inline int32_t getTmemAllocationStats(KernelTraits traits, int ii) { + return ii == 0 ? getTmemAllocationStats0(traits) : getTmemAllocationStats1(traits); +} + +inline tg::Expr const* getTmemAllocationStats(tg::Kernel* kernel, + KernelTraits traits, + tg::Expr const* instId) { + return TLLM_MAKE_OBJ(tg::ExprFromTernaryOp, + kernel, + tg::Dtype::Int32, + TLLM_MAKE_OBJ(tg::BinEq, kernel, instId, kernel->getInt0()), + kernel->getInt(getTmemAllocationStats0(traits)), + kernel->getInt(getTmemAllocationStats1(traits))); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +inline int32_t getTmemAllocationP0(KernelTraits traits) { + if (traits.mInterleavesTmemSAndP) { + // P0 shares columns with S1 (cross-interleaved across instances). + return getTmemAllocationS1(traits) + + ((traits.mSeparateTmemColsForSAndStats || traits.mStoresSoftmaxLocalInSmem) + ? 0 + : traits.mTileSizeStats); + } else if (traits.mSeparateTmemColsForSAndP) { + return traits.mSeparateTmemColsForSAndStats + ? (getTmemAllocationStats1(traits) + traits.mTileSizeStats) + : getTmemAllocationS1(traits) + traits.mNumTmemColsS; + } else { + return getTmemAllocationS0(traits) + + (traits.mSeparateTmemColsForSAndStats ? 0 : traits.mTileSizeStats); + } +} + +inline int32_t getTmemAllocationP1(KernelTraits traits) { + if (traits.mInterleavesTmemSAndP) { + // P1 shares columns with S0 (cross-interleaved across instances). + return getTmemAllocationS0(traits) + + ((traits.mSeparateTmemColsForSAndStats || traits.mStoresSoftmaxLocalInSmem) + ? 0 + : traits.mTileSizeStats); + } else if (traits.mSeparateTmemColsForSAndP) { + return getTmemAllocationP0(traits) + traits.mNumTmemColsP; + } else { + return getTmemAllocationS1(traits) + + (traits.mSeparateTmemColsForSAndStats ? 0 : traits.mTileSizeStats); + } +} + +inline int32_t getTmemAllocationP(KernelTraits traits, int ii) { + return ii == 0 ? getTmemAllocationP0(traits) : getTmemAllocationP1(traits); +} + +inline tg::Expr const* getTmemAllocationP(tg::Kernel* kernel, + KernelTraits traits, + tg::Expr const* instId) { + return TLLM_MAKE_OBJ(tg::ExprFromTernaryOp, + kernel, + tg::Dtype::Int32, + TLLM_MAKE_OBJ(tg::BinEq, kernel, instId, kernel->getInt0()), + kernel->getInt(getTmemAllocationP0(traits)), + kernel->getInt(getTmemAllocationP1(traits))); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +inline int32_t getTmemAllocationO0(KernelTraits traits) { + // Start with the end of TmemS/TmemStats/TmemP. + if (traits.mSeparateTmemColsForSAndP) { + return getTmemAllocationP1(traits) + traits.mNumTmemColsP; + } else if (traits.mSeparateTmemColsForSAndStats) { + return getTmemAllocationStats1(traits) + traits.mTileSizeStats; + } else { + return getTmemAllocationS1(traits) + traits.mNumTmemColsS; + } +} + +inline int32_t getTmemAllocationO1(KernelTraits traits) { + // When the head dimension exceeds headDimPerStageKv, we must wrap it over multiple columns. + return getTmemAllocationO0(traits) + + traits.mAtomPvN * getNumHeadDimStagesV(traits.mHeadDimPerCtaV, traits.mHeadDimPerStageKv); +} + +inline int32_t getTmemAllocationO(KernelTraits traits, int ii) { + return ii == 0 ? getTmemAllocationO0(traits) : getTmemAllocationO1(traits); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +inline int32_t getTmemAllocationTransformedKv(KernelTraits traits) { + // The number of instances Qkv. + auto numInstsQkv = traits.mNumInstsQ * traits.mNumInstsKv; + // The TMEM start offset of the transformed K/V. + return getTmemAllocationO1(traits) + + (getTmemAllocationO1(traits) - getTmemAllocationO0(traits)) * (numInstsQkv - 1); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +// +// For multi-stage processing (stages > 1), adjust column and row positions accordingly. +// Each headDimStage's TMEM D data is organized first across different columns, then across +// different rows (across the rows is only supported when tileSizeQ = 64). +// clang-format off +// Layout example: +// stage0: [row0, col0-127] +// stage1: [row0, col128-255] +// stage2: [row16, col0-127] +// stage3: [row16, col128-255] +// clang-format on + +inline int32_t getHeadDimStageTmemOffset(KernelTraits traits, + int headDimStageIdx, + bool isP = false, + int numTmemColsPerStage = 0) { + // The cluster dimension X. + int clusterDimX{traits.mUseUtcmma2CtaMode ? 2 : 1}; + // When the head dimension exceeds headDimPerStageKv, we must wrap it over multiple columns. + int numHeadDimStages{1}; + if (traits.mHeadDimPerCtaV > traits.mHeadDimPerStageKv && traits.mHeadDimPerStageKv > 0) { + numHeadDimStages *= + (traits.mHeadDimPerCtaV + traits.mHeadDimPerStageKv - 1) / traits.mHeadDimPerStageKv; + } else if (traits.mHeadDimPerCtaV * clusterDimX > 256 && !isP && !traits.mSwapsMmaAb) { + // The MmaPv might need multiple instructions to process the full headDimV, so the headDimOffset + // is also needed in TmemCorr. + // When swapsMmaAb is enabled, BMM2-M is always split into headDimStages (headDimPerStageKv > 0) + // when headDimV > 128, so no need to split into headDimStages here. + numHeadDimStages = ceilDiv(traits.mHeadDimPerCtaV * clusterDimX, traits.mAtomPvN); + } + + // Return 0 if the number of stages is 1. + if (numHeadDimStages == 1) { + return 0; + } + + // The number of TMEM columns per stage. + if (numTmemColsPerStage == 0) { + numTmemColsPerStage = traits.mAtomPvN; + } + + // The maximum number of headDimStages per row. + auto maxNumHeadDimStagesPerRow = 256 / numTmemColsPerStage; + // Make sure the headDimStageIdx is within valid range. + TLLM_CHECK_ERROR((headDimStageIdx + 1) * traits.mTileSizeQ * traits.mHeadDimPerStageKv <= + /* tmemRows */ 128 * /* tmemCols */ 256, + "Invalid headDimStageIdx"); + // The TMEM row offset. + int32_t tmemRowOffset{(headDimStageIdx / maxNumHeadDimStagesPerRow) * 16 * + tg::TmemTile::TmemRowScale}; + // The TMEM column offset. + int32_t tmemColOffset{(headDimStageIdx % maxNumHeadDimStagesPerRow) * numTmemColsPerStage}; + // The TMEM offset. + // Note that the tmemRowOffsetP must be aligned to the tmemRowOffsetO. + return isP ? tmemRowOffset : (tmemRowOffset + tmemColOffset); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline tg::Expr const* getHeadDimStageTmemOffset(tg::Kernel* kernel, + KernelTraits traits, + tg::Expr const* headDimStageIdx, + bool isP = false, + int numTmemColsPerStage = 0) { + + // The cluster dimension X. + int clusterDimX{traits.mUseUtcmma2CtaMode ? 2 : 1}; + // When the head dimension exceeds headDimPerStageKv, we must wrap it over multiple columns. + int numHeadDimStages{1}; + if (traits.mHeadDimPerCtaV > traits.mHeadDimPerStageKv && traits.mHeadDimPerStageKv > 0) { + numHeadDimStages *= + (traits.mHeadDimPerCtaV + traits.mHeadDimPerStageKv - 1) / traits.mHeadDimPerStageKv; + } else if (traits.mHeadDimPerCtaV * clusterDimX > 256 && !isP && !traits.mSwapsMmaAb) { + // The MmaPv might need multiple instructions to process the full headDimV, so the headDimOffset + // is also needed in TmemCorr. + // When swapsMmaAb is enabled, BMM2-M is always split into headDimStages (headDimPerStageKv > 0) + // when headDimV > 128, so no need to split into headDimStages here. + numHeadDimStages = ceilDiv(traits.mHeadDimPerCtaV * clusterDimX, traits.mAtomPvN); + } + // Return 0 if the number of stages is 1. + if (numHeadDimStages == 1) { + return kernel->getInt0(); + } + + // The number of TMEM columns per stage. + if (numTmemColsPerStage == 0) { + numTmemColsPerStage = traits.mAtomPvN; + } + + // The maximum number of headDimStages per row. + auto maxNumHeadDimStagesPerRow = 256 / numTmemColsPerStage; + + // Make sure the headDimStageIdx is within valid range. + if (headDimStageIdx->isCompTimeCstIntScalar()) { + tg::Int i{headDimStageIdx}; + TLLM_CHECK_ERROR((i.getVal() + 1) * traits.mTileSizeQ * traits.mHeadDimPerStageKv <= + /* tmemRows */ 128 * /* tmemCols */ 256, + "Invalid headDimStageIdx"); + } + + // The TMEM row offset. + auto tmemRowOffset = TLLM_MAKE_OBJ( + tg::BinMul, + kernel, + TLLM_MAKE_OBJ(tg::BinDiv, kernel, headDimStageIdx, kernel->getInt(maxNumHeadDimStagesPerRow)), + kernel->getInt(16 * tg::TmemTile::TmemRowScale)); + // The TMEM column offset. + auto tmemColOffset = TLLM_MAKE_OBJ( + tg::BinMul, + kernel, + TLLM_MAKE_OBJ(tg::BinMod, kernel, headDimStageIdx, kernel->getInt(maxNumHeadDimStagesPerRow)), + kernel->getInt(numTmemColsPerStage)); + // The TMEM offset. + // Note that the tmemRowOffsetP must be aligned to the tmemRowOffsetO. + return isP ? tmemRowOffset : TLLM_MAKE_OBJ(tg::BinAdd, kernel, tmemRowOffset, tmemColOffset); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// +// Return a diagram string describing how TMEM (tensor memory) is allocated for the FMHA kernel. +// +// TMEM is partitioned into column ranges used by: +// - tmemS: Q*K^T scores (BMM1 output), two instances (S0, S1) for pipelining. +// - tmemStats: Softmax row stats (e.g. max, sum); may share columns with S or be separate. +// - tmemP: Softmax output (P = softmax(S)), fed into BMM2; may share columns with S or be +// separate. +// - tmemO: P*V output (BMM2 result), two instances (O0, O1) for pipelining. +// - tmemTransformedKv: Optional storage for transformed K/V when mStoreTransformedKvInTmem is +// set. +// +// The exact layout depends on kernel options (SeparateTmemColsForSAndStats, +// SeparateTmemColsForSAndP, InterleavesTmemSAndP). Uses the same getTmemAllocation* helpers so the +// diagram matches codegen layout. +// +template +inline std::string getTmemAllocationDiagram(FmhaOptions_ const& options) { + KernelTraits traits(options); + int32_t const totalCols = traits.mNumTmemCols; + + int32_t const s0 = getTmemAllocationS0(traits); + int32_t const s1 = getTmemAllocationS1(traits); + int32_t const numColsS = traits.mNumTmemColsS; + int32_t const stats0 = getTmemAllocationStats0(traits); + int32_t const stats1 = getTmemAllocationStats1(traits); + int32_t const p0 = getTmemAllocationP0(traits); + int32_t const p1 = getTmemAllocationP1(traits); + int32_t const o0 = getTmemAllocationO0(traits); + int32_t const o1 = getTmemAllocationO1(traits); + int32_t const transformedKv = getTmemAllocationTransformedKv(traits); + + // Log kernelTraits related to TMEM allocation. + TLLM_LOG_INFO("KernelTraits related to TMEM allocation:"); + TLLM_LOG_INFO(" mSeparateTmemColsForSAndP: ", toString(traits.mSeparateTmemColsForSAndP)); + TLLM_LOG_INFO(" mInterleavesTmemSAndP: ", toString(traits.mInterleavesTmemSAndP)); + TLLM_LOG_INFO(" mSeparateTmemColsForSAndStats: ", + toString(traits.mSeparateTmemColsForSAndStats)); + TLLM_LOG_INFO(" mStoresSoftmaxLocalInSmem: ", toString(traits.mStoresSoftmaxLocalInSmem)); + TLLM_LOG_INFO(" mStoreTransformedKvInTmem: ", toString(traits.mStoreTransformedKvInTmem)); + + // Print the TMEM allocation diagram. + std::ostringstream oss; + oss << "TMEM allocation diagram (columns 0.." << totalCols << "):\n"; + + if (traits.mInterleavesTmemSAndP) { + oss << " Layout: cross-interleaved S and P (tmemP0 shares cols with tmemS1, tmemP1 with " + "tmemS0).\n"; + } else if (traits.mSeparateTmemColsForSAndP) { + oss << " Layout: separate columns for S and P.\n"; + } else if (traits.mSeparateTmemColsForSAndStats) { + oss << " Layout: separate columns for S and Stats.\n"; + } else { + oss << " Layout: default (Stats/P alias S columns).\n"; + } + + auto range = [](int32_t start, int32_t end) { + return "[" + std::to_string(start) + ".." + std::to_string(end) + ")"; + }; + + oss << " tmemS0: " << range(s0, s0 + numColsS) << " (" << numColsS << " cols)\n"; + oss << " tmemS1: " << range(s1, s1 + numColsS) << " (" << numColsS << " cols)\n"; + if (traits.mSeparateTmemColsForSAndStats && traits.mTileSizeStats > 0) { + oss << " tmemStats0: " << range(stats0, stats0 + traits.mTileSizeStats) << " (" + << traits.mTileSizeStats << " cols)\n"; + oss << " tmemStats1: " << range(stats1, stats1 + traits.mTileSizeStats) << " (" + << traits.mTileSizeStats << " cols)\n"; + } + if (traits.mSeparateTmemColsForSAndP) { + oss << " tmemP0: " << range(p0, p0 + traits.mNumTmemColsP) << " (" << traits.mNumTmemColsP + << " cols)\n"; + oss << " tmemP1: " << range(p1, p1 + traits.mNumTmemColsP) << " (" << traits.mNumTmemColsP + << " cols)\n"; + } else if (traits.mInterleavesTmemSAndP) { + oss << " tmemP0: (aliased with tmemS1)\n"; + oss << " tmemP1: (aliased with tmemS0)\n"; + } else if (!traits.mSwapsMmaAb) { + oss << " tmemP: (aliased with tmemS)\n"; + } + int32_t const numColsO0 = o1 - o0; + oss << " tmemO0: " << range(o0, o1) << " (" << numColsO0 << " cols)\n"; + oss << " tmemO1: " << range(o1, o1 + numColsO0) << " (" << numColsO0 << " cols)\n"; + if (traits.mStoreTransformedKvInTmem) { + int32_t const numColsKv = totalCols - transformedKv; + oss << " tmemTransformedKv: " << range(transformedKv, totalCols) << " (" << numColsKv + << " cols)\n"; + } + oss << " Total TMEM columns: " << totalCols; + return oss.str(); +} + +#endif // !TLLM_FMHA_TRTLLM_COMPAT (code-gen-only Expr overloads) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace fmha diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CuteUtils.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CuteUtils.h new file mode 100644 index 000000000000..82e4d5c1f790 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CuteUtils.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Conversion Utility to convert RMEM from one type to another. Used for conversion from AccumType +// to input/output type. +template +inline __device__ auto convert_type(Fragment const& tensor) { + // The number of the elements in the source. + constexpr int numel = decltype(size(tensor))::value; + // The converter. + cutlass::NumericArrayConverter convert_op; + // The data of the input. + auto const* data = reinterpret_cast*>(tensor.data()); + // Create the destination tensor (at least the array in registers). The src must be contiguous. + auto dst = convert_op(*data); + // Reconstruct the tensor. + return cute::make_tensor(cute::make_rmem_ptr(&dst), tensor.layout()); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassBarrier.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassBarrier.h new file mode 100644 index 000000000000..960076272193 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassBarrier.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassNamedBarrier class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This class is a modified copy of cutlass::arch::NamedBarrier in order to +// overwrite ReservedNamedBarrierCount to 0. +class CutlassNamedBarrier { + // Data Members: + + // Range = [1 , NUM_THREADS_PER_CTA] + // Range % warp-size (i.e 32) == 0 + uint32_t const num_threads_; + + // Range : [0, 15] + // Note that should be set to the final barrier ID, including ReserveNamedBarrierCount should be + // considered + uint32_t const id_; + +public: + // Constructor for CUTLASS users: + // effective barrier ID starts from ReservedNamedBarrierCount + CUTLASS_DEVICE + CutlassNamedBarrier(uint32_t num_threads, uint32_t id = 0) + : num_threads_(num_threads) + , id_(id + ReservedNamedBarrierCount) { + CUTLASS_ASSERT(id + ReservedNamedBarrierCount <= HardwareMaxNumNamedBarriers && + "Effective barrier_id should not exceed 16."); + } + + CUTLASS_DEVICE + void arrive_and_wait() const { + // Note: The value of id_ is already the final barrier id (set correctly in the constructor). + CutlassNamedBarrier::arrive_and_wait_internal(num_threads_, id_); + } + + CUTLASS_DEVICE + void arrive_and_wait_unaligned() const { + // Note: The value of id_ is already the final barrier id (set correctly in the constructor). + CutlassNamedBarrier::arrive_and_wait_internal_unaligned(num_threads_, id_); + } + + CUTLASS_DEVICE + void arrive() const { + // Note: The value of id_ is already the final barrier id (set correctly in the constructor). + CutlassNamedBarrier::arrive_internal(num_threads_, id_); + } + + CUTLASS_DEVICE + void arrive_unaligned() const { + // Note: The value of id_ is already the final barrier id (set correctly in the constructor). + CutlassNamedBarrier::arrive_internal_unaligned(num_threads_, id_); + } + + CUTLASS_DEVICE + void sync() const { CutlassNamedBarrier::arrive_and_wait(); } + + // Static variants + + // Calling interface for CUTLASS users: + // effective barrier ID starts from ReservedNamedBarrierCount + CUTLASS_DEVICE + static void arrive_and_wait(uint32_t num_threads, uint32_t barrier_id) { + arrive_and_wait_internal(num_threads, barrier_id + ReservedNamedBarrierCount); + } + + // Calling interface for CUTLASS users: + // effective barrier ID starts from ReservedNamedBarrierCount + CUTLASS_DEVICE + static void arrive(uint32_t num_threads, uint32_t barrier_id) { + arrive_internal(num_threads, barrier_id + ReservedNamedBarrierCount); + } + + // Calling interface for CUTLASS users: + // effective barrier ID starts from ReservedNamedBarrierCount + CUTLASS_DEVICE + static void sync(uint32_t num_threads, uint32_t barrier_id) { + sync_internal(num_threads, barrier_id + ReservedNamedBarrierCount); + } + +private: + CUTLASS_DEVICE + static void arrive_and_wait_internal(uint32_t num_threads, uint32_t barrier_id) { +#if CUDA_BARRIER_ENABLED + asm volatile("bar.sync %0, %1;" : : "r"(barrier_id), "r"(num_threads)); + cutlass::arch::synclog_emit_named_barrier_arrive_and_wait(__LINE__, num_threads, barrier_id); +#elif defined(__CUDA_ARCH__) + asm volatile("brkpt;\n" ::); +#endif + } + + CUTLASS_DEVICE + static void arrive_and_wait_internal_unaligned(uint32_t num_threads, uint32_t barrier_id) { +#if CUDA_BARRIER_ENABLED + asm volatile("barrier.sync %0, %1;" : : "r"(barrier_id), "r"(num_threads)); + cutlass::arch::synclog_emit_named_barrier_arrive_and_wait(__LINE__, num_threads, barrier_id); +#elif defined(__CUDA_ARCH__) + asm volatile("brkpt;\n" ::); +#endif + } + + CUTLASS_DEVICE + static void arrive_internal(uint32_t num_threads, uint32_t barrier_id) { +#if CUDA_BARRIER_ENABLED + cutlass::arch::synclog_emit_named_barrier_arrive(__LINE__, num_threads, barrier_id); + asm volatile("bar.arrive %0, %1;" : : "r"(barrier_id), "r"(num_threads)); +#elif defined(__CUDA_ARCH__) + asm volatile("brkpt;\n" ::); +#endif + } + + CUTLASS_DEVICE + static void arrive_internal_unaligned(uint32_t num_threads, uint32_t barrier_id) { +#if CUDA_BARRIER_ENABLED + cutlass::arch::synclog_emit_named_barrier_arrive(__LINE__, num_threads, barrier_id); + asm volatile("barrier.arrive %0, %1;" : : "r"(barrier_id), "r"(num_threads)); +#elif defined(__CUDA_ARCH__) + asm volatile("brkpt;\n" ::); +#endif + } + + CUTLASS_DEVICE + static void sync_internal(uint32_t num_threads, uint32_t barrier_id) { + CutlassNamedBarrier::arrive_and_wait_internal(num_threads, barrier_id); + } + +public: + // We do not reserve any NamedBarriers for CUTLASS' own use cases. + static const uint32_t ReservedNamedBarrierCount = 0; + static const uint32_t HardwareMaxNumNamedBarriers = 16; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassPipeline.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassPipeline.h new file mode 100644 index 000000000000..73359b75bd93 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassPipeline.h @@ -0,0 +1,1764 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "Utils.h" + +namespace cutlass { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// PipelineTmaMultiUmmaAsync class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This class customizes cutlass::PipelineTmaUmmaAsync to allow for multiple UMMA consumers. +// The TMA producer is consumed by more than one UMMA consumers. +template , + class AtomThrShape_MNK_ = cute::Shape> +class PipelineTmaMultiUmmaAsync + : public cutlass::PipelineTmaUmmaAsync { + +public: + static constexpr uint32_t Stages = Stages_; + using AtomThrShape_MNK = AtomThrShape_MNK_; + +private: + using Base = cutlass::PipelineTmaUmmaAsync; + +public: + using FullBarrier = typename Base::FullBarrier; + using EmptyBarrier = typename Base::EmptyBarrier; + using ProducerBarrierType = typename Base::ProducerBarrierType; + using ConsumerBarrierType = typename Base::ConsumerBarrierType; + using PipelineState = typename Base::PipelineState; + using SharedStorage = typename Base::SharedStorage; + using ThreadCategory = typename Base::ThreadCategory; + using Params = typename Base::Params; + + using McastDirection = cutlass::McastDirection; + + // Helper function to initialize barriers. + static CUTLASS_DEVICE void init_barriers(SharedStorage& storage, + int warpId, + Params params, + ClusterShape cluster_shape) { + if (warpId == params.initializing_warp) { + constexpr int producer_arv_cnt = 1; + auto atom_thr_shape = AtomThrShape_MNK{}; + + uint32_t multicast_consumer_arrival_count; + if constexpr (mcastDirection == cutlass::McastDirection::kRowCol) { + multicast_consumer_arrival_count = + (cute::size<0>(cluster_shape) / cute::size<0>(atom_thr_shape)) + + (cute::size<1>(cluster_shape) / cute::size<1>(atom_thr_shape)) - 1; + } else if constexpr (mcastDirection == cutlass::McastDirection::kRow) { + multicast_consumer_arrival_count = + cute::size<1>(cluster_shape) / cute::size<1>(atom_thr_shape); + } else { + multicast_consumer_arrival_count = + cute::size<0>(cluster_shape) / cute::size<0>(atom_thr_shape); + } + + cutlass::arch::detail::initialize_barrier_array_pair_aligned( + storage.full_barrier_, + storage.empty_barrier_, + producer_arv_cnt, + multicast_consumer_arrival_count * params.num_consumers); // Multi-UMMA consumers. + } + } + + // Constructor by default initializes barriers and calculates masks. + // These operations can be explicity deferred by specifying InitBarriers and InitMasks. + // If deferred, user code needs to guarantee init_masks and/or init_barriers is/are called. + template + CUTLASS_DEVICE PipelineTmaMultiUmmaAsync(SharedStorage& storage, + int32_t warpId, + Params params, + ClusterShape cluster_shape, + InitBarriers = {}, + InitMasks = {}) + : Base(storage, params, cluster_shape, cute::false_type{}, cute::false_type{}) { + static_assert(cute::is_same_v || + cute::is_same_v); + if constexpr (cute::is_same_v) { + init_barriers(storage, warpId, params, cluster_shape); + } + + static_assert(cute::is_same_v || + cute::is_same_v); + if constexpr (cute::is_same_v) { + if constexpr (mcastDirection == McastDirection::kRowCol) { + Base::init_masks(cluster_shape); + } else { + Base::init_masks(cluster_shape, mcastDirection); + } + } + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace cutlass + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace cutlass::gemm::kernel::detail { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// StaticPersistentPipelinedTileSchedulerSm90 class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Pipelined (work id in ring buffer) Static Persistent scheduler for SM90. +// Uses a producer-consumer pipeline where the producer computes work IDs +// ahead of time and stores them in shared memory ring buffer. +// Consumers read work IDs from shared memory instead of computing individually. +// Inherits from StaticPersistentTileScheduler via CRTP to reuse most functionality. +template +class StaticPersistentPipelinedTileSchedulerSm90 + : public cutlass::gemm::kernel::detail::StaticPersistentTileScheduler< + StaticPersistentPipelinedTileSchedulerSm90> { + +private: + using Base = cutlass::gemm::kernel::detail::StaticPersistentTileScheduler< + StaticPersistentPipelinedTileSchedulerSm90>; + using Self = StaticPersistentPipelinedTileSchedulerSm90; + using Sm90Scheduler = cutlass::gemm::kernel::detail::PersistentTileSchedulerSm90; + +public: + using typename Base::Arguments; + using typename Base::Params; + using typename Base::RasterOrder; + + using ClusterShape = ClusterShape_; + static constexpr uint32_t ClusterSize = cute::size(ClusterShape_{}); + static constexpr uint32_t Stages = Stages_; + + // Work ID response stored in shared memory ring buffer + using WorkTileInfo = + typename cutlass::gemm::kernel::detail::PersistentTileSchedulerSm90::WorkTileInfo; + using CLCResponse = + typename cutlass::gemm::kernel::detail::PersistentTileSchedulerSm100::CLCResponse; + + // Pipeline types for producer-consumer synchronization + using Pipeline = cutlass::PipelineCLCFetchAsync; + using SharedStorage = typename Pipeline::SharedStorage; + + static CUTLASS_DEVICE cute::tuple get_work_idx_m_and_n( + uint64_t blk_per_grid_dim, + cutlass::FastDivmodU64Pow2 const& divmod_cluster_shape_major, + cutlass::FastDivmodU64Pow2 const& divmod_cluster_shape_minor, + cutlass::FastDivmodU64 const& divmod_cluster_blk_major, + int32_t log_swizzle_size, + RasterOrder raster_order) { + return Sm90Scheduler::get_work_idx_m_and_n(blk_per_grid_dim, + divmod_cluster_shape_major, + divmod_cluster_shape_minor, + divmod_cluster_blk_major, + log_swizzle_size, + raster_order); + } + + // Ctor. + CUTLASS_DEVICE + explicit StaticPersistentPipelinedTileSchedulerSm90(Params const& params) + : Base(params) {} + + CUTLASS_DEVICE explicit StaticPersistentPipelinedTileSchedulerSm90(CLCResponse* clc_response_ptr, + Params const& params, + dim3 block_id_in_cluster) + : Base(params) + , clc_response_ptr_(clc_response_ptr) + , block_id_in_cluster_(block_id_in_cluster) {} + + // Returns invalid as the first tile will be fetched via fetch_next_work. + template + CUTLASS_DEVICE WorkTileInfo initial_work_tile_info(ClusterShape /* cluster_shape */) { + // Return invalid tile since work will be consumed via fetch_next_work + return WorkTileInfo::invalid_work_tile(); + } + + // Producer API. Compute work ID and store in shared memory. + CUTLASS_DEVICE + cutlass::PipelineState advance_to_next_work( + Pipeline& pipeline, + cutlass::PipelineState pipe_producer_state, + int32_t advance_count = 1) const { + // HACK: can't touch parent class in CUTLASS; so cast to non-const and call. + auto non_const_this = const_cast(static_cast(this)); + // Advance the linear index. + non_const_this->advance_to_next_work(advance_count); + // Calculate work id from linear index. + typename Base::WorkTileInfo work_id = Base::get_current_work(); + // Wait for buffer slot to become empty. + pipeline.producer_acquire(pipe_producer_state); + // Convert WorkTileInfo struct to 16B CLCResponse. + CLCResponse clc_response; + clc_response.data[0] = work_id.M_idx; + clc_response.data[1] = work_id.N_idx; + clc_response.data[2] = work_id.L_idx; + clc_response.data[3] = static_cast(work_id.is_valid_tile); + // Store work ID in shared memory ring buffer. + if constexpr (ClusterSize == 1) { + // Use direct store + manual barrier completion instead. + clc_response_ptr_[pipe_producer_state.index()] = clc_response; + // Fence between SM and SYNCS. + cutlass::arch::fence_view_async_shared(); + // Manually complete the transaction bytes that producer_acquire set up. + pipeline.producer_commit(pipe_producer_state); + } else { + CUTLASS_PRAGMA_UNROLL + for (uint32_t rank = 0; rank < ClusterSize; ++rank) { + uint32_t* current_clc_response_ptr = + reinterpret_cast(&clc_response_ptr_[pipe_producer_state.index()]); + uint32_t* remote_addr = + cuda_ptx::mapa(cuda_ptx::space_cluster, current_clc_response_ptr, rank); + uint64_t* remote_bar = + cuda_ptx::mapa(cuda_ptx::space_cluster, + reinterpret_cast(__cvta_shared_to_generic( + pipeline.producer_get_barrier(pipe_producer_state))), + rank); + if (cute::elect_one_sync()) { + cuda_ptx::st_async(remote_addr, clc_response.data, remote_bar); + } + } + } + // Advance the pipeline state. + ++pipe_producer_state; + // Return the new pipeline state. + return pipe_producer_state; + } + + // Consumer API. Read work ID from shared memory. + template + CUTLASS_DEVICE auto fetch_next_work(WorkTileInfo /* work_tile_info */, + TileSchedulerPipeline& scheduler_pipeline, + TileSchedulerPipelineState scheduler_pipe_consumer_state) { + + // Wait for producer to commit data. + scheduler_pipeline.consumer_wait(scheduler_pipe_consumer_state); + // Read work ID from shared memory. + CLCResponse clc_response = clc_response_ptr_[scheduler_pipe_consumer_state.index()]; + // Release the buffer slot for producer. + scheduler_pipeline.consumer_release(scheduler_pipe_consumer_state); + // Convert to WorkTileInfo. + WorkTileInfo new_work_tile; + new_work_tile.M_idx = clc_response.data[0]; + new_work_tile.N_idx = clc_response.data[1]; + new_work_tile.L_idx = clc_response.data[2]; + new_work_tile.is_valid_tile = clc_response.data[3] == 1; + // Add cluster offsets. + new_work_tile.M_idx += block_id_in_cluster_.x; + new_work_tile.N_idx += block_id_in_cluster_.y; + // Return work tile and flag indicating pipeline state should advance. + return cute::make_tuple(new_work_tile, true); + } + +private: + CLCResponse* clc_response_ptr_ = nullptr; + dim3 block_id_in_cluster_ = {0, 0, 0}; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Dynamic persistent tile scheduler that uses atomicAdd on a global counter for work distribution. +// This enables dynamic work-stealing among thread blocks, providing better load balancing +// when work tiles have varying execution times. +// Similar to StaticPersistentPipelinedTileSchedulerSm90 but uses atomic operations instead of +// static linear index increment. +template +class DynamicPersistentPipelinedTileSchedulerSm90 + : public cutlass::gemm::kernel::detail::StaticPersistentTileScheduler< + DynamicPersistentPipelinedTileSchedulerSm90> { + +private: + using Base = cutlass::gemm::kernel::detail::StaticPersistentTileScheduler< + DynamicPersistentPipelinedTileSchedulerSm90>; + using Self = DynamicPersistentPipelinedTileSchedulerSm90; + using Sm90Scheduler = cutlass::gemm::kernel::detail::PersistentTileSchedulerSm90; + +public: + using typename Base::Arguments; + using typename Base::Params; + using typename Base::RasterOrder; + + using ClusterShape = ClusterShape_; + static constexpr uint32_t ClusterSize = cute::size(ClusterShape_{}); + static constexpr uint32_t Stages = Stages_; + + // Work ID response stored in shared memory ring buffer + using WorkTileInfo = + typename cutlass::gemm::kernel::detail::PersistentTileSchedulerSm90::WorkTileInfo; + using CLCResponse = + typename cutlass::gemm::kernel::detail::PersistentTileSchedulerSm100::CLCResponse; + + // Pipeline types for producer-consumer synchronization + using Pipeline = cutlass::PipelineCLCFetchAsync; + using SharedStorage = typename Pipeline::SharedStorage; + + static CUTLASS_DEVICE cute::tuple get_work_idx_m_and_n( + uint64_t blk_per_grid_dim, + cutlass::FastDivmodU64Pow2 const& divmod_cluster_shape_major, + cutlass::FastDivmodU64Pow2 const& divmod_cluster_shape_minor, + cutlass::FastDivmodU64 const& divmod_cluster_blk_major, + int32_t log_swizzle_size, + RasterOrder raster_order) { + return Sm90Scheduler::get_work_idx_m_and_n(blk_per_grid_dim, + divmod_cluster_shape_major, + divmod_cluster_shape_minor, + divmod_cluster_blk_major, + log_swizzle_size, + raster_order); + } + + // Ctor. + CUTLASS_DEVICE + explicit DynamicPersistentPipelinedTileSchedulerSm90(Params const& params) + : Base(params) {} + + CUTLASS_DEVICE explicit DynamicPersistentPipelinedTileSchedulerSm90(CLCResponse* clc_response_ptr, + Params const& params, + dim3 block_id_in_cluster, + uint32_t* dPtrTileCounter) + : Base(params) + , clc_response_ptr_(clc_response_ptr) + , block_id_in_cluster_(block_id_in_cluster) + , dPtrTileCounter_(dPtrTileCounter) + , current_linear_idx_(0) { + // Compute initial linear index same as the Base class does. + if (params.raster_order_ == RasterOrder::AlongN) { + current_linear_idx_ = uint64_t(blockIdx.x) + uint64_t(blockIdx.y) * uint64_t(gridDim.x); + } else { + current_linear_idx_ = uint64_t(blockIdx.x) * uint64_t(gridDim.y) + uint64_t(blockIdx.y); + } + } + + // Returns invalid as the first tile will be fetched via fetch_next_work. + template + CUTLASS_DEVICE WorkTileInfo initial_work_tile_info(ClusterShape /* cluster_shape */) { + // Return invalid tile since work will be consumed via fetch_next_work + return WorkTileInfo::invalid_work_tile(); + } + + // Producer API. Atomically fetch next work index and store in shared memory. + CUTLASS_DEVICE + cutlass::PipelineState advance_to_next_work( + Pipeline& pipeline, + cutlass::PipelineState pipe_producer_state, + int32_t advance_count = 1) const { + // To bootstrap, get the current work id calculated from blockIdx to save one atomic operation. + // To continue, fetch the next work id from the dynamic scheduler. + if (advance_count > 0) { + // Only one thread per cluster performs the atomic operation. + if (cute::elect_one_sync()) { + // Use atomicAdd to get the next linear work index dynamically. + current_linear_idx_ = atomicAdd(dPtrTileCounter_, static_cast(advance_count)); + } + // Broadcast the linear index to all threads in the warp. + current_linear_idx_ = __shfl_sync(0xFFFFFFFF, current_linear_idx_, 0); + } + // Calculate work id from the linear index. + typename Base::WorkTileInfo work_id = + Base::get_current_work_for_linear_idx(current_linear_idx_); + // Wait for buffer slot to become empty. + pipeline.producer_acquire(pipe_producer_state); + // Convert WorkTileInfo struct to 16B CLCResponse. + CLCResponse clc_response; + clc_response.data[0] = work_id.M_idx; + clc_response.data[1] = work_id.N_idx; + clc_response.data[2] = work_id.L_idx; + clc_response.data[3] = static_cast(work_id.is_valid_tile); + // Store work ID in shared memory ring buffer. + if constexpr (ClusterSize == 1) { + // Use direct store + manual barrier completion instead. + clc_response_ptr_[pipe_producer_state.index()] = clc_response; + // Fence between SM and SYNCS. + cutlass::arch::fence_view_async_shared(); + // Manually complete the transaction bytes that producer_acquire set up. + pipeline.producer_commit(pipe_producer_state); + } else { + CUTLASS_PRAGMA_UNROLL + for (uint32_t rank = 0; rank < ClusterSize; ++rank) { + uint32_t* current_clc_response_ptr = + reinterpret_cast(&clc_response_ptr_[pipe_producer_state.index()]); + uint32_t* remote_addr = + cuda_ptx::mapa(cuda_ptx::space_cluster, current_clc_response_ptr, rank); + uint64_t* remote_bar = + cuda_ptx::mapa(cuda_ptx::space_cluster, + reinterpret_cast(__cvta_shared_to_generic( + pipeline.producer_get_barrier(pipe_producer_state))), + rank); + if (cute::elect_one_sync()) { + cuda_ptx::st_async(remote_addr, clc_response.data, remote_bar); + } + } + } + // Advance the pipeline state. + ++pipe_producer_state; + // Return the new pipeline state. + return pipe_producer_state; + } + + // Consumer API. Read work ID from shared memory. + template + CUTLASS_DEVICE auto fetch_next_work(WorkTileInfo /* work_tile_info */, + TileSchedulerPipeline& scheduler_pipeline, + TileSchedulerPipelineState scheduler_pipe_consumer_state) { + + // Wait for producer to commit data. + scheduler_pipeline.consumer_wait(scheduler_pipe_consumer_state); + // Read work ID from shared memory. + CLCResponse clc_response = clc_response_ptr_[scheduler_pipe_consumer_state.index()]; + // Release the buffer slot for producer. + scheduler_pipeline.consumer_release(scheduler_pipe_consumer_state); + // Convert to WorkTileInfo. + WorkTileInfo new_work_tile; + new_work_tile.M_idx = clc_response.data[0]; + new_work_tile.N_idx = clc_response.data[1]; + new_work_tile.L_idx = clc_response.data[2]; + new_work_tile.is_valid_tile = clc_response.data[3] == 1; + // Add cluster offsets. + new_work_tile.M_idx += block_id_in_cluster_.x; + new_work_tile.N_idx += block_id_in_cluster_.y; + // Return work tile and flag indicating pipeline state should advance. + return cute::make_tuple(new_work_tile, true); + } + + // Get the current linear index that was fetched by atomicAdd. + CUTLASS_DEVICE + uint64_t get_current_linear_idx() const { return current_linear_idx_; } + +private: + CLCResponse* clc_response_ptr_ = nullptr; + dim3 block_id_in_cluster_ = {0, 0, 0}; + uint32_t* dPtrTileCounter_ = nullptr; + uint64_t mutable current_linear_idx_ = 0; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace cutlass::gemm::kernel::detail + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassPipelineState utility function. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +__device__ PipelineState makePipelineState(PipelineState state, int stateIncr) { + return PipelineState::make_pipeline_state(state, stateIncr); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template __device__ PipelineState makeProdStartStateFrom(PipelineState) { + return PipelineState(0, 1, 0); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template __device__ PipelineState makeConsStartStateFrom(PipelineState) { + return PipelineState(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassOrderedSequenceBarrier class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template class CutlassOrderedSequenceBarrier { + + // The CUTLASS pipeline. + using Pipeline = cutlass::OrderedSequenceBarrier; + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + +public: + // The ctor. + inline explicit __device__ CutlassOrderedSequenceBarrier(SharedStorage& sharedStorage, + int warpId, + int group_id, + int group_size, + int barInitWarpId = 0) + : mParams{static_cast(group_id), static_cast(group_size), barInitWarpId} + , mPipeline( + /* storage */ sharedStorage, + /* params */ mParams + ) { +#if (__CUDA_ARCH__ >= 1000) + if (warpId == barInitWarpId) { + auto barrier_ptr = &sharedStorage.barrier_[0][0]; + int arv_cnt = mParams.group_size; + constexpr int Stages = SequenceDepth * SequenceLength; + cutlass::arch::detail::initialize_barrier_array_aligned( + barrier_ptr, + arv_cnt); + } +#else + // Init is done only by the one elected thread of the block + int lane_predicate = cute::elect_one_sync(); + if (warpId == barInitWarpId && lane_predicate) { + for (int d = 0; d < SequenceDepth; ++d) { + for (int l = 0; l < SequenceLength; ++l) { + sharedStorage.barrier_[d][l].init(mParams.group_size); + } + } + } +#endif + // Note: fence_barrier_init() will be invoked once after all barriers are initialized. + } + + // Signal completion of stage and move to the next stage + inline __device__ void arrive() { mPipeline.arrive(); } + + // Wait on a stage to be unlocked + inline __device__ void wait() { mPipeline.wait(); } + +private: + Params mParams; + Pipeline mPipeline; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassOrderedSequenceNamedBarrier class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// SequenceDepth = 1 +// SequenceLength = 2 +class CutlassOrderedSequenceNamedBarrier { + +public: + // The ctor. + inline explicit __device__ CutlassOrderedSequenceNamedBarrier(int group_id, + int group_size, + int namedBarId) + : mGroupId{group_id} + , mAllGroupsSize(group_size * 2) + , mNamedBarId(namedBarId) {} + + // Signal completion of stage and move to the next stage + inline __device__ void arrive() { + // If it is the 1st group + if (mGroupId == 0) { + asm volatile("bar.sync %0, %1;" ::"r"(mNamedBarId), "r"(mAllGroupsSize)); + } + } + + // Wait on a stage to be unlocked + inline __device__ void wait() { + // If it is the second group (group id == 1) then wait for the first group to arrive + // Otherwise (group id == 0) do nothing, just proceed unblocked + if (mGroupId == 1) { + asm volatile("bar.sync %0, %1;" ::"r"(mNamedBarId), "r"(mAllGroupsSize)); + } + } + +private: + int mGroupId; + int mAllGroupsSize; + int mNamedBarId; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassClusterBarrier class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template , + bool SyncsTwoCtasForMma = false> +class CutlassClusterBarrier { + + // The CUTLASS barrier. + using Barrier = cutlass::arch::ClusterBarrier; + +public: + // The shared memory storage same as the pipeline. + using SharedStorage = Barrier; + +public: + // Ctor. + inline __device__ CutlassClusterBarrier(SharedStorage& sharedStorage, + int32_t warpId, + int32_t numThreadsPerCta, + int32_t barInitWarpId = 0, + ClusterShape clusterShape = ClusterShape{}) + : mBarrierPtr{&sharedStorage} + , mClusterShape{clusterShape} { + + // The lead CTA does wait + arrive, and the follower CTA does arrive + wait. Specifically: + // 1. Follower CTAs arrives at lead CTA's barrier. + // 2. Lead CTA waits for all follower CTAs to arrive. + // 3. Lead CTA arrives at follower CTA's barrier one-by-one. + // 4. Follower CTA waits for lead CTA to arrive. + // Therefore, the expected arrival count for each role are: + // The expected arrival count of the leader CTA is (CGA_size - 1) * arvCnt. + // The expected arrival count of the follower CTAs is arvCnt. + + // The cluster size must be 2 if SyncsTwoCtasForMma is true. + static_assert(!SyncsTwoCtasForMma || cute::size<0>(clusterShape) == 2, "Not supported"); + + // The block rank in the cluster. + int const blockRank = cute::block_rank_in_cluster(); + // Note there could be multiple CTA pairs in the cluster if 2CTA UTCMMA is used. + // The lead CTA's rank. + int32_t const leadCtaRank = SyncsTwoCtasForMma ? (blockRank & 0xfffffffe) : 0; + int producerArriveCount = + SyncsTwoCtasForMma ? cute::size<0>(clusterShape) - 1 : cute::size(clusterShape) - 1; + // The expected arrival count for the current CTA. + int arriveCount = (blockRank == leadCtaRank ? producerArriveCount : 1) * numThreadsPerCta; + // Elect one thread to initialize the barrier. + if (cute::elect_one_sync() && warpId == barInitWarpId) { + mBarrierPtr->init(arriveCount); + } + } + + // Single instruction to arrive and wait. + inline __device__ void sync(int phase = 0) { + int numRanksInCluster = + (SyncsTwoCtasForMma ? cute::size<0>(mClusterShape) : cute::size(mClusterShape)); + // The block rank in the cluster. + int32_t const blockRank = cute::block_rank_in_cluster(); + // Note there could be multiple CTA pairs in the cluster if 2CTA UTCMMA is used. + // The lead CTA's rank. + int32_t const leadCtaRank = SyncsTwoCtasForMma ? (blockRank & 0xfffffffe) : 0; + // Follower CTA arrives at lead CTA. + mBarrierPtr->arrive(leadCtaRank, blockRank != leadCtaRank); + // Lead CTA waits on follower CTAs. Follower CTAs waits for the lead CTA. + mBarrierPtr->wait(phase); + // Lead CTA arrives at follower CTA's barrier one-by-one. + for (int ii = 1; ii < numRanksInCluster; ++ii) { + mBarrierPtr->arrive(leadCtaRank + ii, blockRank == leadCtaRank); + } + } + + // Single instruction to arrive and wait. + inline __device__ void sync(int phase, int numRanksInCluster) { + + // The block rank in the cluster. + int32_t const blockRank = cute::block_rank_in_cluster(); + // Note there could be multiple CTA pairs in the cluster if 2CTA UTCMMA is used. + // The lead CTA's rank. + int32_t const leadCtaRank = SyncsTwoCtasForMma ? (blockRank & 0xfffffffe) : 0; + // Follower CTA arrives at lead CTA. + mBarrierPtr->arrive(leadCtaRank, blockRank != leadCtaRank); + // Arrive on the lead CTA's barrier to taken into account the unused ranks. + if constexpr (!SyncsTwoCtasForMma) { + for (int ii = numRanksInCluster; + ii < (SyncsTwoCtasForMma ? cute::size<0>(mClusterShape) : cute::size(mClusterShape)); + ++ii) { + mBarrierPtr->arrive(leadCtaRank, blockRank == leadCtaRank); + } + } + // Lead CTA waits on follower CTAs. Follower CTAs waits for the lead CTA. + mBarrierPtr->wait(phase); + // Lead CTA arrives at follower CTA's barrier one-by-one. + for (int ii = 1; ii < numRanksInCluster; ++ii) { + mBarrierPtr->arrive(leadCtaRank + ii, blockRank == leadCtaRank); + } + } + + // Arrive on the barrier. + inline __device__ void arrive(int ctaIdx, bool pred = true) { mBarrierPtr->arrive(ctaIdx, pred); } + + // Wait on the barrier. + inline __device__ void wait(int phase) { mBarrierPtr->wait(phase); } + +private: + // Declare the barrier's shared pointer. + Barrier* mBarrierPtr; + // The clusterShape + ClusterShape mClusterShape; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassClusterTransactionBarrier class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template > +class CutlassClusterTransactionBarrier { + + // The CUTLASS barrier. + using Barrier = cutlass::arch::ClusterTransactionBarrier; + +public: + // The shared memory storage same as the pipeline. + using SharedStorage = Barrier; + +public: + // Ctor. + inline __device__ CutlassClusterTransactionBarrier(SharedStorage& sharedStorage, + int32_t warpId, + int32_t arriveCnt, + uint32_t transactionBytes, + int32_t barInitWarpId = 0, + ClusterShape = ClusterShape{}) + : mBarrierPtr{&sharedStorage} { + + // Elect one thread to initialize the barrier and set the expected transaction bytes. + if (warpId == barInitWarpId && cute::elect_one_sync()) { + mBarrierPtr->init(arriveCnt); + // Arrive and set the expected transaction bytes if provided. + // This is meant to avoid additional cluster_sync. + if (transactionBytes > 0) { + mBarrierPtr->arrive_and_expect_tx(transactionBytes); + } + } + } + + // Arrive and set the expected transaction bytes. + inline __device__ void arrive_and_expect_tx(int ctaIdx, + uint32_t transactionBytes, + bool pred = true) { + mBarrierPtr->arrive_and_expect_tx(ctaIdx, transactionBytes, pred); + } + + // Complete the transaction. + inline __device__ void complete_transaction(uint32_t dst_cta_id, + uint32_t transaction_bytes, + bool pred = true) { + mBarrierPtr->complete_transaction(dst_cta_id, transaction_bytes, pred); + } + + // Wait for the barrier. + inline __device__ void wait(int phase = 0) { mBarrierPtr->wait(phase); } + + // Get the barrier pointer. + inline __device__ uint64_t* getBarrierPtr() { return reinterpret_cast(mBarrierPtr); } + +private: + // Declare the barrier's shared pointer. + Barrier* mBarrierPtr; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassCpAsyncPipeline class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// UseCpAsyncWaitGroup changes the fencing of cp.async wrt other proxies: +// TRUE: user manually inserts cp.async.commit_group (LDGDEPBAR) before barrier arrival. +// FALSE: codegen auto-inserts cp.async.mbarrier.arrive (ARRIVES.LDGSTSBAR) before barrier arrival. +// In other words, when UseCpAsyncWaitGroup == true, this acts as simple arrive/wait pipeline. +template class CutlassCpAsyncPipeline { + + // The CUTLASS pipeline. + using Pipeline = cutlass::PipelineAsync; + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The state. + using PipelineState = typename Pipeline::PipelineState; + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + +public: + // Ctor. We may want to use mPipeline{sharedStorage, {}, cute::false_type{}} in the future. + inline explicit __device__ CutlassCpAsyncPipeline(SharedStorage& sharedStorage, + int32_t warpId, + int32_t prodArvCnt = 1, + int32_t consArvCnt = 1, + int32_t barInitWarpId = 0) + : mPipeline{sharedStorage, + Params{Pipeline::ThreadCategory::ProducerConsumer, + reinterpret_cast(prodArvCnt), + reinterpret_cast(consArvCnt), + cute::block_rank_in_cluster() /* dst_block_id */, + barInitWarpId}, + cute::false_type{}} { + // Initialize barriers. Doing this here instead of in cutlass avoids unnecessary shuffle of warp + // id for each pipeline and redundant predicates and branches. + if (warpId == barInitWarpId) { + cutlass::arch::detail::initialize_barrier_array_pair_aligned< + decltype(sharedStorage.full_barrier_), + decltype(sharedStorage.empty_barrier_), + Pipeline::Stages>(sharedStorage.full_barrier_, + sharedStorage.empty_barrier_, + prodArvCnt, + consArvCnt); + } + // Note: fence_barrier_init() will be invoked once after all barriers are initialized. + } + + // Consumer release the barrier. + inline __device__ void consumer_release(PipelineState const& state) { + mPipeline.consumer_release(state); + } + + // Consumer test if they have to wait at the barrier. + inline __device__ int32_t consumer_test_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_test_wait(state); + return reinterpret_cast(token); + } + + // Consumer try to wait at the barrier. + inline __device__ int32_t consumer_try_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_try_wait(state); + return reinterpret_cast(token); + } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ConsumerToken token = reinterpret_cast(t); + mPipeline.consumer_wait(state, token); + } + + // Producer acquire the barrier. + inline __device__ void producer_acquire(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ProducerToken token = reinterpret_cast(t); + mPipeline.producer_acquire(state, token); + } + + // Producer arrive at the barrier. + inline __device__ void producer_commit(PipelineState const& state) { + if constexpr (UseCpAsyncWaitGroup) { + mPipeline.producer_commit(state); + } else { + mPipeline.producer_commit(state, cutlass::arch::cpasync_barrier_arrive); + } + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(PipelineState const& state) { + mPipeline.producer_tail(state); + } + + // Producer get the barrier. It is only used by tma load. + inline __device__ int32_t producer_try_acquire(PipelineState const& state) { + cutlass::ProducerToken token = mPipeline.producer_try_acquire(state); + return reinterpret_cast(token); + } + + // Get pipeline + [[nodiscard]] inline __device__ Pipeline& get_pipeline() { return mPipeline; } + +private: + // The pipeline. + Pipeline mPipeline; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassTmaAsyncPipeline class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template > +class CutlassTmaAsyncPipeline { + // The CUTLASS pipeline. +#if (__CUDA_ARCH__ >= 1000) && (__CUDA_ARCH__ != 1040) + using Pipeline = cutlass::PipelineTmaTransformAsync; +#else + using Pipeline = cutlass::PipelineTmaAsync; +#endif + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The state. + using PipelineState = typename Pipeline::PipelineState; + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + // The producer's barrier type. + using ProducerBarrier = typename Pipeline::ProducerBarrierType; + // The FULL barrier type. + using FullBarrier = typename Pipeline::FullBarrier; + // The EMPTY barrier type. + using EmptyBarrier = typename Pipeline::EmptyBarrier; + +public: + // Ctor. + template , + typename InitBarriers = cute::true_type, + typename InitMasks = cute::true_type> + inline explicit __device__ CutlassTmaAsyncPipeline(SharedStorage& sharedStorage, + int32_t warpId, + int32_t transactionBytes = 0, + bool isLeader = false, + int32_t numConsumers = 0, + ClusterShape clusterShape = {}, + InitBarriers = {}, + InitMasks = {}, + int32_t barInitWarpId = 0) + : mPipeline{sharedStorage, + Params{reinterpret_cast(transactionBytes), + // FIXME: ThreadCategory::Consumer is required for the pipeline to init the + // multicast mask. That mask is passed by consumer_release to + // umma_arrive_multicast (even if not needed). We need to find a way to set + // it differently for consumer and producer (i.e. in the Task). + Pipeline::ThreadCategory::Consumer, + isLeader ? 1u : 0u, + reinterpret_cast(numConsumers), + /* num producers */ 1u, + barInitWarpId}, + clusterShape, + /*InitBarriers=*/cute::false_type{}, + InitMasks{}} + , mEmptyBarrierPtr{&sharedStorage.empty_barrier_[0]} + , mIsSignalingThread{threadIdx.x % numConsumers == 0} { + if constexpr (cute::is_same_v) { + // Initialize barriers. Doing this here instead of in cutlass avoids unnecessary shuffle of + // warp id for each pipeline and redundant predicates and branches. + if (warpId == barInitWarpId) { + constexpr int NumThreadsPerWarpGroup = 4 * 32; + uint32_t const producer_arv_cnt = 1u; + uint32_t const num_consumer_per_cluster = + cute::ceil_div(numConsumers, static_cast(NumThreadsPerWarpGroup)); +#if (__CUDA_ARCH__ >= 1000) && (__CUDA_ARCH__ != 1040) + auto atom_thr_shape = typename Pipeline::AtomThrShape_MNK{}; + uint32_t multicast_consumer_arrival_count = + (cute::size<0>(clusterShape) / cute::size<0>(atom_thr_shape) + + cute::size<1>(clusterShape) / cute::size<1>(atom_thr_shape) - 1) * + num_consumer_per_cluster; +#else + uint32_t multicast_consumer_arrival_count = numConsumers; // If cluster_size is 1 + if (cute::size(clusterShape) > 1) { + multicast_consumer_arrival_count = + (cute::size<0>(clusterShape) + cute::size<1>(clusterShape) - 1) * + num_consumer_per_cluster; + } +#endif + cutlass::arch::detail::initialize_barrier_array_pair_aligned< + decltype(sharedStorage.full_barrier_), + decltype(sharedStorage.empty_barrier_), + Pipeline::Stages>(sharedStorage.full_barrier_, + sharedStorage.empty_barrier_, + producer_arv_cnt, + multicast_consumer_arrival_count); + } + // Note: fence_barrier_init() will be invoked once after all barriers are initialized. + } + } + + // Consumer release the barrier. + inline __device__ void consumer_release(PipelineState const& state) { + // NOTE: The original pipeline uses `dst_blockid_` and `signaling_thread_` to call release. + // For CGA > 1, blockRank=X attempts to signal arrival to blockRank=0. + // This becomes an issue in cases where .2CTA commands are not used, and no cross-CGA + // pipelines are expected. We override this behavior by using standard `arrive` without + // relying on the CGA blockRank or `dst_block_id`. + if constexpr (IsMma2Sm) { + mPipeline.consumer_release(state); + } else { +#if (__CUDA_ARCH__ >= 1000) && (__CUDA_ARCH__ != 1040) + if (mIsSignalingThread) +#endif + { + mEmptyBarrierPtr[state.index()].arrive(); + } + } + } + + // Consumer test if they have to wait at the barrier.. + inline __device__ int32_t consumer_test_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_test_wait(state); + return reinterpret_cast(token); + } + + // Consumer try to wait at the barrier.. + inline __device__ int32_t consumer_try_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_try_wait(state); + return reinterpret_cast(token); + } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ConsumerToken token = reinterpret_cast(t); + mPipeline.consumer_wait(state, token); + } + + // Producer acquire the barrier. + // Arrive the producer barrier with the transaction_bytes at the same time. + inline __device__ void producer_acquire(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ProducerToken token = reinterpret_cast(t); + mPipeline.producer_acquire(state, token); + } + + // Producer arrive at the barrier. It does nothing. + inline __device__ void producer_commit(PipelineState const& state, uint32_t bytes = uint32_t{0}) { + mPipeline.producer_commit(state, bytes); + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(PipelineState const& state) { + mPipeline.producer_tail(state); + } + + // Producer try to acquire the barrier. + inline __device__ int32_t producer_try_acquire(PipelineState const& state) { + cutlass::ProducerToken token = mPipeline.producer_try_acquire(state); + return reinterpret_cast(token); + } + + // Producer test to acquire the barrier. (Not supported by CUTLASS directly) + inline __device__ int32_t producer_test_acquire(PipelineState const& state) { + auto barrier = producer_get_barrier(state); + auto phase = state.phase(); + cutlass::BarrierStatus status = cuda_ptx::mbarrier_test_wait_parity(barrier, phase) + ? cutlass::BarrierStatus::WaitDone + : cutlass::BarrierStatus::WaitAgain; + cutlass::ProducerToken token = cutlass::ProducerToken(status); + return reinterpret_cast(token); + } + + // Producer get the barrier. It is only used by tma load. + inline __device__ ProducerBarrier* producer_get_barrier(PipelineState const& state) { + return mPipeline.producer_get_barrier(state); + } + + // Get pipeline + [[nodiscard]] inline __device__ Pipeline& get_pipeline() { return mPipeline; } + +private: + // The pipeline. + Pipeline mPipeline; + EmptyBarrier* mEmptyBarrierPtr = nullptr; + bool mIsSignalingThread = false; + static constexpr bool IsMma2Sm = cute::size(AtomThrShapeMNK{}) > 1; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassTmaUmmaAsyncPipeline class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template , + class AtomThrShapeMNK = cute::Shape> +class CutlassTmaUmmaAsyncPipeline { + // The CUTLASS pipeline. + using Pipeline = cutlass::PipelineTmaUmmaAsync; + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The state. + using PipelineState = typename Pipeline::PipelineState; + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + // The producer's barrier type. + using ProducerBarrier = typename Pipeline::ProducerBarrierType; + // The EMPTY barrier type. + using EmptyBarrier = typename Pipeline::EmptyBarrier; + +public: + // Ctor. + template + inline explicit __device__ CutlassTmaUmmaAsyncPipeline(SharedStorage& sharedStorage, + int32_t warpId, + uint32_t transactionBytes, + bool isLeader, + ClusterShape clusterShape, + InitBarriers = {}, + InitMasks = {}, + int32_t barInitWarpId = 0) + : mPipeline{sharedStorage, + Params{transactionBytes, + // Set it to producer to not create the multicast mask as the umma_peer_mask + // is used instead (see below). + Pipeline::ThreadCategory::Producer, + // FIXME: This might not work if we are not using 2-CTA instructions, but + // just use multiple CTAs in the X dimension of the cluster. + size(clusterShape) == 1 || + (cute::block_id_in_cluster().x % cute::size<0>(AtomThrShapeMNK{}) == 0) + ? isLeader + : 0u, // is_leader + 0u, // num_consumers, unused + 0u, // num_produces, unused + barInitWarpId}, + clusterShape, + /*InitBarriers=*/cute::false_type{}, + InitMasks{}} + , mBlockIdMask{0} + , mEmptyBarrierPtr{&sharedStorage.empty_barrier_[0]} { + + if constexpr (cute::is_same_v) { + // Initialize barriers. Doing this here instead of in cutlass avoids unnecessary shuffle of + // warp id for each pipeline and redundant predicates and branches. + if (warpId == barInitWarpId) { + constexpr int producer_arv_cnt = 1; + auto atom_thr_shape = typename Pipeline::AtomThrShape_MNK{}; + uint32_t const multicast_consumer_arrival_count = + (cute::size<0>(clusterShape) / cute::size<0>(atom_thr_shape)) + + (cute::size<1>(clusterShape) / cute::size<1>(atom_thr_shape)) - 1; + cutlass::arch::detail::initialize_barrier_array_pair_aligned< + decltype(sharedStorage.full_barrier_), + decltype(sharedStorage.empty_barrier_), + Pipeline::Stages>(sharedStorage.full_barrier_, + sharedStorage.empty_barrier_, + producer_arv_cnt, + multicast_consumer_arrival_count); + } + // Note: fence_barrier_init() will be invoked once after all barriers are initialized. + } + + // Initialize the blockId mask. + init_block_id_mask(clusterShape); + } + + // Create the umma_peer_mask, which only encodes the current CTA pair in the cluster. + // This overrides the base implementation of init_block_id_mask, which creates the multicast + // mask that encodes all CTA pairs in the cluster. + // FIXME: we need to find a better way of dealing with this. + __device__ void init_block_id_mask(ClusterShape clusterShape, + dim3 blockIdInCluster = cute::block_id_in_cluster()) { + if constexpr (IsMma2Sm) { + auto cluster_layout = cute::make_layout(clusterShape); + mBlockIdMask = cutlass::detail::calculate_umma_peer_mask(clusterShape, + AtomThrShapeMNK{}, + blockIdInCluster); + } + } + + // Consumer release the barrier. + inline __device__ void consumer_release(PipelineState const& state) { + // Override the original consumer_release to use the umma_peer_mask instead of multicast mask. + uint64_t* smemPtr = reinterpret_cast(&mEmptyBarrierPtr[state.index()]); + if constexpr (IsMma2Sm) { + cutlass::arch::umma_arrive_multicast_2x1SM(smemPtr, mBlockIdMask); + } else { + cutlass::arch::umma_arrive(smemPtr); + } + } + + // Consumer try to wait at the barrier.. + inline __device__ int32_t consumer_try_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_try_wait(state); + return reinterpret_cast(token); + } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ConsumerToken token = reinterpret_cast(t); + mPipeline.consumer_wait(state, token); + } + + // Producer acquire the barrier. + // Arrive the producer barrier with the transaction_bytes at the same time. + inline __device__ void producer_acquire(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ProducerToken token = reinterpret_cast(t); + mPipeline.producer_acquire(state, token); + } + + // Producer arrive at the barrier. It does nothing. + inline __device__ void producer_commit(PipelineState const& state, uint32_t bytes = uint32_t{0}) { + mPipeline.producer_commit(state, bytes); + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(PipelineState const& state) { + mPipeline.producer_tail(state); + } + + // Producer try to acquire the barrier. + inline __device__ int32_t producer_try_acquire(PipelineState const& state) { + cutlass::ProducerToken token = mPipeline.producer_try_acquire(state); + return reinterpret_cast(token); + } + + // Producer get the barrier. It is only used by tma load. + inline __device__ ProducerBarrier* producer_get_barrier(PipelineState const& state) { + return mPipeline.producer_get_barrier(state); + } + + // Get pipeline + [[nodiscard]] inline __device__ Pipeline& get_pipeline() { return mPipeline; } + +private: + // The pipeline. + Pipeline mPipeline; + // The blockId mask. + uint16_t mBlockIdMask; + // The empty barrier pointer. + EmptyBarrier* mEmptyBarrierPtr; + // Does it use 2CTA UTCMMA ? + static constexpr bool IsMma2Sm = cute::size(AtomThrShapeMNK{}) > 1; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template , + class AtomThrShapeMNK = cute::Shape> +class CutlassTmaMultiUmmaAsyncPipeline { + // The CUTLASS pipeline. + using Pipeline = + cutlass::PipelineTmaMultiUmmaAsync; + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The state. + using PipelineState = typename Pipeline::PipelineState; + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + // The producer's barrier type. + using ProducerBarrier = typename Pipeline::ProducerBarrierType; + +public: + // Ctor. + template + inline explicit __device__ CutlassTmaMultiUmmaAsyncPipeline(SharedStorage& sharedStorage, + int32_t warpId, + uint32_t transactionBytes, + bool isLeader, + uint32_t numConsumers, + ClusterShape clusterShape, + InitBarriers = {}, + InitMasks = {}, + int32_t barInitWarpId = 0) + : mPipeline{sharedStorage, + warpId, + Params{reinterpret_cast(transactionBytes), + // FIXME: ThreadCategory::Consumer is required for the pipeline to init the + // multicast mask. That mask is passed by consumer_release to + // umma_arrive_multicast (even if not needed). We need to find a way to set + // it differently for consumer and producer (i.e. in the Task). + Pipeline::ThreadCategory::Consumer, + // FIXME: This might not work if we are not using 2-CTA instructions, but + // just use multiple CTAs in the X dimension of the cluster. + size(clusterShape) == 1 || + (cute::block_id_in_cluster().x % cute::size<0>(AtomThrShapeMNK{}) == 0) + ? isLeader + : 0u, // is_leader + numConsumers, // num_consumers + 0u, // num_producers, unused + barInitWarpId}, + clusterShape, + InitBarriers{}, + InitMasks{}} {} + + // Consumer release the barrier. + inline __device__ void consumer_release(PipelineState const& state) { + mPipeline.consumer_release(state); + } + + // Consumer try to wait at the barrier.. + inline __device__ int32_t consumer_try_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_try_wait(state); + return reinterpret_cast(token); + } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ConsumerToken token = reinterpret_cast(t); + mPipeline.consumer_wait(state, token); + } + + // Producer acquire the barrier. + // Arrive the producer barrier with the transaction_bytes at the same time. + inline __device__ void producer_acquire(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ProducerToken token = reinterpret_cast(t); + mPipeline.producer_acquire(state, token); + } + + // Producer arrive at the barrier. It does nothing. + inline __device__ void producer_commit(PipelineState const& state, uint32_t bytes = uint32_t{0}) { + mPipeline.producer_commit(state, bytes); + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(PipelineState const& state) { + mPipeline.producer_tail(state); + } + + // Producer try to acquire the barrier. + inline __device__ int32_t producer_try_acquire(PipelineState const& state) { + cutlass::ProducerToken token = mPipeline.producer_try_acquire(state); + return reinterpret_cast(token); + } + + // Producer get the barrier. It is only used by tma load. + inline __device__ ProducerBarrier* producer_get_barrier(PipelineState const& state) { + return mPipeline.producer_get_barrier(state); + } + + // Get pipeline + [[nodiscard]] inline __device__ Pipeline& get_pipeline() { return mPipeline; } + +private: + // The pipeline. + Pipeline mPipeline; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassUmmaAsyncPipeline class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template > +class CutlassUmmaAsyncPipeline { + // The CUTLASS pipeline. + using Pipeline = cutlass::PipelineUmmaAsync; + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The state. + using PipelineState = typename Pipeline::PipelineState; + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + // The producer's barrier type. + using ProducerBarrier = typename Pipeline::ProducerBarrierType; + // The EMPTY barrier type. + using EmptyBarrier = typename Pipeline::EmptyBarrier; + +public: + // Ctor. + template + inline explicit __device__ CutlassUmmaAsyncPipeline(SharedStorage& sharedStorage, + int32_t warpId, + int32_t consArvCnt, + ClusterShape clusterShape, + InitBarriers = {}, + InitMasks = {}, + int32_t barInitWarpId = 0) + : mPipeline{sharedStorage, + Params{Pipeline::ThreadCategory::Producer, // unused for UTCMMA.1CTA + 1u, // prod_cnt + reinterpret_cast(consArvCnt), // cons_cnt + cute::block_rank_in_cluster(), // dst block id + barInitWarpId}, + clusterShape, + /*InitBarriers=*/cute::false_type{}, + InitMasks{}} + , mEmptyBarrierPtr{&sharedStorage.empty_barrier_[0]} { + if constexpr (cute::is_same_v) { + // Initialize barriers. Doing this here instead of in cutlass avoids unnecessary shuffle of + // warp id for each pipeline and redundant predicates and branches. + if (warpId == barInitWarpId) { + cutlass::arch::detail::initialize_barrier_array_pair_aligned< + decltype(sharedStorage.full_barrier_), + decltype(sharedStorage.empty_barrier_), + Pipeline::Stages>(sharedStorage.full_barrier_, + sharedStorage.empty_barrier_, + 1u, + consArvCnt); + } + } + // Note: fence_barrier_init() will be invoked once after all barriers are initialized. + } + + // Consumer release the barrier. + inline __device__ void consumer_release(PipelineState const& state) { + // NOTE: The original pipeline uses `dst_blockid_` and `signaling_thread_` to call release. + // For CGA > 1, blockRank=X attempts to signal arrival to blockRank=0. + // This becomes an issue in cases where .2CTA commands are not used, and no cross-CGA + // pipelines are expected. We override this behavior by using standard `arrive` without + // relying on the CGA blockRank or `dst_block_id`. + if constexpr (IsMma2Sm) { + mPipeline.consumer_release(state); + } else { + mEmptyBarrierPtr[state.index()].arrive(); + } + } + + // Consumer try to wait at the barrier.. + inline __device__ int32_t consumer_try_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_try_wait(state); + return reinterpret_cast(token); + } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ConsumerToken token = reinterpret_cast(t); + mPipeline.consumer_wait(state, token); + } + + // Producer acquire the barrier. + inline __device__ void producer_acquire(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ProducerToken token = reinterpret_cast(t); + mPipeline.producer_acquire(state, token); + } + + // Producer arrive at the barrier. It does nothing. + inline __device__ void producer_commit(PipelineState const& state) { + mPipeline.producer_commit(state); + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(PipelineState const& state) { + mPipeline.producer_tail(state); + } + + // Producer try to acquire the barrier. + inline __device__ int32_t producer_try_acquire(PipelineState const& state) { + cutlass::ProducerToken token = mPipeline.producer_try_acquire(state); + return reinterpret_cast(token); + } + + // Get pipeline + [[nodiscard]] inline __device__ Pipeline& get_pipeline() { return mPipeline; } + +private: + // The pipeline. + Pipeline mPipeline; + EmptyBarrier* mEmptyBarrierPtr = nullptr; + static constexpr bool IsMma2Sm = cute::size(AtomThrShapeMNK{}) > 1; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassUmmaConsumerAsyncPipeline class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template > +class CutlassUmmaConsumerAsyncPipeline { + // The CUTLASS pipeline. + using Pipeline = cutlass::PipelineUmmaConsumerAsync; + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The state. + using PipelineState = typename Pipeline::PipelineState; + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + // The producer's barrier type. + using ProducerBarrier = typename Pipeline::ProducerBarrierType; + +public: + // Ctor. + template + inline explicit __device__ CutlassUmmaConsumerAsyncPipeline(SharedStorage& sharedStorage, + int32_t warpId, + int32_t prodCnt, + ClusterShape clusterShape, + InitBarriers = {}, + InitMasks = {}, + int32_t barInitWarpId = 0) + : mPipeline{sharedStorage, + // FIXME: ThreadCategory::Consumer is required for the pipeline to init the + // multicast mask. That mask is passed by consumer_release to + // umma_arrive_multicast (even if not needed). We need to find a way to set + // it differently for consumer and producer (i.e. in the Task). + Params{Pipeline::ThreadCategory::Consumer, + reinterpret_cast(prodCnt), // prod_cnt + 1u, // cons_cnt + 0u, // dst block id + barInitWarpId}, + clusterShape, + /*InitBarriers=*/cute::false_type{}, + InitMasks{}} { + if constexpr (cute::is_same_v) { + // Initialize barriers. Doing this here instead of in cutlass avoids unnecessary shuffle of + // warp id for each pipeline and redundant predicates and branches. + if (warpId == barInitWarpId) { + cutlass::arch::detail::initialize_barrier_array_pair_aligned< + decltype(sharedStorage.full_barrier_), + decltype(sharedStorage.empty_barrier_), + Pipeline::Stages>(sharedStorage.full_barrier_, sharedStorage.empty_barrier_, prodCnt, 1u); + } + } + // Note: fence_barrier_init() will be invoked once after all barriers are initialized. + } + + // Consumer release the barrier. + inline __device__ void consumer_release(PipelineState const& state) { + mPipeline.consumer_release(state); + } + + // Consumer try to wait at the barrier.. + inline __device__ int32_t consumer_try_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_try_wait(state); + return reinterpret_cast(token); + } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ConsumerToken token = reinterpret_cast(t); + mPipeline.consumer_wait(state, token); + } + + // Producer acquire the barrier. + inline __device__ void producer_acquire(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ProducerToken token = reinterpret_cast(t); + mPipeline.producer_acquire(state, token); + } + + // Producer arrive at the barrier. It does nothing. + inline __device__ void producer_commit(PipelineState const& state) { + if constexpr (UsesCpAsyncBarrierArrive) { + mPipeline.producer_commit(state, cutlass::arch::cpasync_barrier_arrive); + } else { + if constexpr (UsesFenceBeforeProdCommit) { + // Need a fence when we need to make the local STS visible to the other CTA in the CGA + asm volatile("{\n\t" + "fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;\n\t" + "}"); + } + mPipeline.producer_commit(state); + } + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(PipelineState const& state) { + mPipeline.producer_tail(state); + } + + // Producer try to acquire the barrier. + inline __device__ int32_t producer_try_acquire(PipelineState const& state) { + cutlass::ProducerToken token = mPipeline.producer_try_acquire(state); + return reinterpret_cast(token); + } + + // Get pipeline + [[nodiscard]] inline __device__ Pipeline& get_pipeline() { return mPipeline; } + +private: + // The pipeline. + Pipeline mPipeline; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// ClcFastDrain class +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template class ClcFastDrain { +public: + static constexpr int32_t DrainRate = DrainRate_; + + // Shared memory storage. + struct SharedStorage { + alignas(16) uint4 responses[DrainRate]; // 16 bytes per CLC response + alignas(8) uint64_t mbar; // mbarrier for async completion + }; + + // Constructor - initializes mbarrier + inline __device__ ClcFastDrain(SharedStorage& storage) + : mResponsesPtr(storage.responses) + , mMbarPtr(&storage.mbar) + , mParity(0) { + // Only one thread should initialize the mbarrier. + if (cute::elect_one_sync()) { + // Initialize mbarrier with arrival count of 1. + cuda_ptx::mbarrier_init(mMbarPtr, 1u); + cuda_ptx::fence_mbarrier_init(cuda_ptx::sem_release, cuda_ptx::scope_cluster); + } + } + + // Issue one batch of DrainRate CLC cancel queries. + inline __device__ int32_t drain_batch() { + int32_t const parity = mParity; + + // Only one thread issues commands + if (cute::elect_one_sync()) { + // Arrive at mbarrier and set expected transaction bytes. + cuda_ptx::mbarrier_arrive_expect_tx(cuda_ptx::sem_relaxed, + cuda_ptx::scope_cta, + cuda_ptx::space_shared, + mMbarPtr, + static_cast(sizeof(uint4) * DrainRate)); + + // Issue several back-to-back CLC try_cancel commands. +#pragma unroll + for (int32_t i = 0; i < DrainRate; ++i) { + cuda_ptx::clusterlaunchcontrol_try_cancel(&mResponsesPtr[i], mMbarPtr); + } + } + + // All threads wait for responses to arrive. + while (!cuda_ptx::mbarrier_try_wait_parity(mMbarPtr, static_cast(parity))) { + } + + // Count successful cancellations. + int32_t canceled_count = 0; +#pragma unroll + for (int32_t i = 0; i < DrainRate; ++i) { + uint4 const response = mResponsesPtr[i]; + if (cuda_ptx::clusterlaunchcontrol_query_cancel_is_canceled(response)) { + ++canceled_count; + } + } + + // Flip parity for next iteration. + mParity ^= 1; + + return canceled_count; + } + + // Drain all pending CTAs until queue is empty. + inline __device__ int32_t drain_all() { + int32_t total_drained = 0; + int32_t drained; + + do { + drained = drain_batch(); + total_drained += drained; + } while (drained > 0); + + return total_drained; + } + +private: + uint4* mResponsesPtr; + uint64_t* mMbarPtr; + int32_t mParity; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// CutlassWorkIdPipeline class. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template > +class CutlassWorkIdPipeline { + + // The CUTLASS pipeline. + using Pipeline = cutlass::PipelineCLCFetchAsync; + // The parameters to initialize the pipeline. + using Params = typename Pipeline::Params; + +public: + // The state. + using PipelineState = typename Pipeline::PipelineState; + // The shared memory storage. + using SharedStorage = typename Pipeline::SharedStorage; + +public: + // Ctor. + inline explicit __device__ CutlassWorkIdPipeline(SharedStorage& sharedStorage, + ClusterShape clusterShape = ClusterShape{}, + int32_t prodArvCnt = 1, + int32_t consArvCnt = 1, + int32_t prodBlkId = 0, + int32_t barInitWarpId = 0) + : mPipeline{sharedStorage, + Params{/*transaction_bytes=*/16, + /*role=*/Pipeline::ThreadCategory::NonParticipant, + /*is_leader=*/0, + /*num_consumers=*/0, + /*producer_blockid=*/reinterpret_cast(prodBlkId), + /*producer_arv_count=*/reinterpret_cast(prodArvCnt), + /*consumer_arv_count=*/reinterpret_cast(consArvCnt), + barInitWarpId}, + clusterShape} {} + + // Consumer release the barrier. + inline __device__ void consumer_release(PipelineState const& state) { + mPipeline.consumer_release(state); + } + + // Consumer try to wait at the barrier.. + [[nodiscard]] inline __device__ int32_t consumer_try_wait(PipelineState const& state) { + cutlass::ConsumerToken token = mPipeline.consumer_try_wait(state); + return reinterpret_cast(token); + } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ConsumerToken token = reinterpret_cast(t); + mPipeline.consumer_wait(state, token); + } + + // Producer acquire the barrier. + inline __device__ void producer_acquire(PipelineState const& state, int32_t t = int32_t{0}) { + cutlass::ProducerToken token = reinterpret_cast(t); + mPipeline.producer_acquire(state, token); + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(PipelineState const& state) { + mPipeline.producer_tail(state); + } + + // Producer get the barrier. It is only used by tma load. + [[nodiscard]] inline __device__ int32_t producer_try_acquire(PipelineState const& state) { + cutlass::ProducerToken token = mPipeline.producer_try_acquire(state); + return reinterpret_cast(token); + } + + // Get producer mbarrier address + [[nodiscard]] inline __device__ uint32_t producer_get_barrier(PipelineState const& state) { + return mPipeline.producer_get_barrier(state); + } + + // Get pipeline + [[nodiscard]] inline __device__ Pipeline& get_pipeline() { return mPipeline; } + + // Fast drain rate for CLC cancel operations + static constexpr int32_t FastDrainRate = 4; + + // Fast drain shared memory storage type + using FastDrainStorage = typename ClcFastDrain::SharedStorage; + + // Fast drain all pending CTAs using ClcFastDrain. + // This accelerates draining CTAs in queue instead of draining one-by-one, if we know we can have + // a clean break from the loop when, for example, rastering CTA in the non-batch dimension. + inline __device__ int32_t fast_drain_all(FastDrainStorage& fastDrainStorage) { + ClcFastDrain drainer(fastDrainStorage); + return drainer.drain_all(); + } + +private: + // The pipeline. + Pipeline mPipeline; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassUtils.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassUtils.h new file mode 100644 index 000000000000..efbc74d2ff89 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/CutlassUtils.h @@ -0,0 +1,1101 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Conversion functions. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to accept Array inputs. +inline __device__ cutlass::Array fadd2(cutlass::Array inA, + cutlass::Array inB) { + cutlass::Array output; + cute::add(reinterpret_cast(output), + reinterpret_cast(inA), + reinterpret_cast(inB)); + return output; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to accept Array inputs. +inline __device__ cutlass::Array fadd4(cutlass::Array inA, + cutlass::Array inB) { + // Extract the lower (Lo) and higher (Hi) parts of the input arrays. + auto aLo = cutlass::make_Array(inA[0], inA[1]); + auto bLo = cutlass::make_Array(inB[0], inB[1]); + auto aHi = cutlass::make_Array(inA[2], inA[3]); + auto bHi = cutlass::make_Array(inB[2], inB[3]); + + // Multiply pairs of elements (using the vectorized FFMA2 inst). + auto cLo = fadd2(aLo, bLo); + auto cHigh = fadd2(aHi, bHi); + + // Repack the 4 outputs into a single array of 4 floats. + cutlass::Array result = cutlass::make_Array(cLo[0], cLo[1], cHigh[0], cHigh[1]); + return result; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to accept Array inputs. +inline __device__ cutlass::Array ffma2(cutlass::Array inA, + cutlass::Array inB, + cutlass::Array inC) { + cutlass::Array output; + cute::fma(reinterpret_cast(output), + reinterpret_cast(inA), + reinterpret_cast(inB), + reinterpret_cast(inC)); + return output; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to accept Array inputs. +inline __device__ cutlass::Array fmul(cutlass::Array inA, + cutlass::Array inB) { + cutlass::Array output = {inA[0] * inB[0]}; + return output; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to accept Array inputs. +inline __device__ cutlass::Array fmul2(cutlass::Array inA, + cutlass::Array inB) { + cutlass::Array output; + cute::mul(reinterpret_cast(output), + reinterpret_cast(inA), + reinterpret_cast(inB)); + return output; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to accept Array inputs. +inline __device__ cutlass::Array fmul4(cutlass::Array inA, + cutlass::Array inB) { + // Extract the lower (Lo) and higher (Hi) parts of the input arrays. + auto aLo = cutlass::make_Array(inA[0], inA[1]); + auto bLo = cutlass::make_Array(inB[0], inB[1]); + auto aHi = cutlass::make_Array(inA[2], inA[3]); + auto bHi = cutlass::make_Array(inB[2], inB[3]); + + // Multiply pairs of elements (using the vectorized FFMA2 inst). + auto cLo = fmul2(aLo, bLo); + auto cHigh = fmul2(aHi, bHi); + + // Repack the 4 outputs into a single array of 4 floats. + cutlass::Array result = cutlass::make_Array(cLo[0], cLo[1], cHigh[0], cHigh[1]); + return result; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to accept Array inputs. +template +inline __device__ cutlass::Array fmulx(cutlass::Array inA, + cutlass::Array inB) { + cutlass::Array result; +#pragma unroll + for (int i = 0; i < x; i += 2) { + auto a = cutlass::make_Array(inA[i + 0], inA[i + 1]); + auto b = cutlass::make_Array(inB[i + 0], inB[i + 1]); + auto c = fmul2(a, b); + result[i + 0] = c[0]; + result[i + 1] = c[1]; + } + return result; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Type converters. +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ cutlass::Array castArray(cutlass::Array src) { + using Converter = + cutlass::NumericArrayConverter; + return Converter::convert(src); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ DstType castFromArray(cutlass::Array arr) { + return reinterpret_cast(arr); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ cutlass::Array castToArray(SrcType src) { + return reinterpret_cast const&>(src); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ cutlass::uint128_t convertBfloat16ToFp16(cutlass::uint128_t src) { + auto srcArray{castToArray(src)}; + return castFromArray(castArray(srcArray)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ cutlass::uint128_t convertE4m3ToBfloat16(uint64_t src) { + auto srcArray{castToArray(src)}; + return castFromArray(castArray(srcArray)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ cutlass::uint128_t convertE4m3ToFp16(uint64_t src) { + auto srcArray{castToArray(src)}; + return castFromArray(castArray(srcArray)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ cutlass::uint128_t convertFp16ToBfloat16(cutlass::uint128_t src) { + auto srcArray{castToArray(src)}; + return castFromArray(castArray(srcArray)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert packed e2m1 to fp16. +template +inline __device__ cutlass::Array convert_e2m1_to_fp16( + cutlass::Array const& src) { +#if defined(__CUDA_ARCH_FEAT_SM100_ALL) + if constexpr (N % 8 == 0) { + cutlass::Array dst; + auto ptrE2m1x8 = reinterpret_cast(src.data()); + auto ptrFp16x2 = reinterpret_cast(dst.data()); + +#pragma unroll + for (int i = 0; i < N / 8; i++) { + uint32_t const tmpE2m1x8 = ptrE2m1x8[i]; + + // Cast e2m1x8 to fp16x8. + uint32_t tmpF16x2[4]; + asm volatile("{\n" + ".reg .b8 byte0, byte1, byte2, byte3;\n" + "mov.b32 {byte0, byte1, byte2, byte3}, %4;\n" + "cvt.rn.f16x2.e2m1x2 %0, byte0;\n" + "cvt.rn.f16x2.e2m1x2 %1, byte1;\n" + "cvt.rn.f16x2.e2m1x2 %2, byte2;\n" + "cvt.rn.f16x2.e2m1x2 %3, byte3;\n" + "}\n" + : "=r"(tmpF16x2[0]), "=r"(tmpF16x2[1]), "=r"(tmpF16x2[2]), "=r"(tmpF16x2[3]) + : "r"(tmpE2m1x8)); +#pragma unroll + for (int j = 0; j < 4; j++) { + ptrFp16x2[4 * i + j] = tmpF16x2[j]; + } + } + + return dst; + } else +#endif + { + // Less efficient fallback. At this time, no specialization is available in cutlass, so this is + // using a generic and less efficient code path. + using ConverterE2m1ToFp16 = + cutlass::NumericArrayConverter; + return ConverterE2m1ToFp16::convert(src); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert packed ue8m0 to bfloat16. +template +inline __device__ cutlass::Array convert_ue8m0_to_bfloat16( + cutlass::Array const& src) { +#if defined(__CUDA_ARCH_FEAT_SM100_ALL) + if constexpr (N % 4 == 0) { + cutlass::Array dst; + auto ptrUe8m0x4 = reinterpret_cast(src.data()); + auto ptrBf16x2 = reinterpret_cast(dst.data()); + +#pragma unroll + for (int i = 0; i < N / 4; i++) { + uint32_t const tmpUe8m0x4 = ptrUe8m0x4[i]; + uint32_t tmpBf16x2[2]; + asm volatile("{\n" + ".reg .b16 lo, hi;\n" + "mov.b32 {lo, hi}, %2;\n" + "cvt.rn.bf16x2.ue8m0x2 %0, lo;\n" + "cvt.rn.bf16x2.ue8m0x2 %1, hi;\n" + "}\n" + : "=r"(tmpBf16x2[0]), "=r"(tmpBf16x2[1]) + : "r"(tmpUe8m0x4)); + ptrBf16x2[2 * i] = tmpBf16x2[0]; + ptrBf16x2[2 * i + 1] = tmpBf16x2[1]; + } + + return dst; + } else +#endif + { + // Fallback. + // Note: at this time, no specialization is available in cutlass, so this is using a generic and + // less efficient code path. + using ConverterUe8m0ToBf16 = + cutlass::NumericArrayConverter; + return ConverterUe8m0ToBf16::convert(src); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 bfloat16 to 2 floats. +template +inline __device__ cutlass::Array convert_bfloat16_to_float2(T const& src) { + static_assert(std::is_same_v || std::is_same_v, + "T must be uint32_t or float"); + auto srcArray{castToArray(src)}; + using Converter = cutlass::NumericArrayConverter; + return Converter::convert(srcArray); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float to bfloat16. +inline __device__ cutlass::Array convert_float_to_bfloat16( + cutlass::Array const& src) { + using Converter = + cutlass::NumericArrayConverter; + return Converter::convert(src); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 float16 to 2 floats. +template +inline __device__ cutlass::Array convert_float16_to_float2(T const& src) { + // 2xFP16 is packed as uint32_t or float. + static_assert(std::is_same_v || std::is_same_v, + "T must be uint32_t or float"); + auto srcArray{castToArray(src)}; + using Converter = cutlass::NumericArrayConverter; + return Converter::convert(srcArray); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 floats to 2 bfloat16. +inline __device__ cutlass::Array convert_float2_to_bfloat16( + cutlass::Array const& src) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array dst = Converter::convert(src); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 floats to 2 bfloat16 (represented as uint32_t). +inline __device__ uint32_t convert_float2_to_bfloat16(float in0, float in1) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array src = cutlass::make_Array(in0, in1); + cutlass::Array dst = Converter::convert(src); + return reinterpret_cast(dst); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 4 floats to 4 bfloat16. +inline __device__ cutlass::Array convert_float4_to_bfloat16( + cutlass::Array const& src) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array dst = Converter::convert(src); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float type Tensor to bfloat type Tensor. +template +inline __device__ auto convert_float2_to_bfloat16(cute::Tensor const& in) { + auto result = + cute::make_tensor(cute::shape(cute::recast_layout(in.layout()))); +#pragma unroll + for (int i = 0; i < size(in); i += 2) { + result(i / 2) = convert_float2_to_bfloat16(in(i + 0), in(i + 1)); + } + return result; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 floats to 2 e2m1. +inline __device__ cutlass::Array convert_float2_to_e2m1( + cutlass::Array const& array) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array dst = Converter::convert(array); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 4 floats to 4 e2m1. +inline __device__ cutlass::Array convert_float4_to_e2m1( + cutlass::Array const& array) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array dst = Converter::convert(array); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert floats to e2m1. +template +inline __device__ cutlass::Array convert_floatx_to_e2m1( + cutlass::Array const& array) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array dst = Converter::convert(array); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float to e4m3. +inline __device__ cutlass::Array convert_float_to_e4m3( + cutlass::Array const& in) { + // FIXME + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array src = cutlass::make_Array(in[0], in[0]); + cutlass::Array dst = Converter::convert(src); + // FIXME + cutlass::Array ret = + reinterpret_cast&>(dst); + return ret; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 floats to 2 e4m3. +inline __device__ cutlass::Array convert_float2_to_e4m3( + cutlass::Array const& array) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array dst = Converter::convert(array); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 4 floats to 4 e4m3. +inline __device__ cutlass::Array convert_float4_to_e4m3( + cutlass::Array const& array) { + using Converter = + cutlass::NumericArrayConverter; + cutlass::Array dst = Converter::convert(array); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 4 floats to 4 e4m3 (represented as uint32_t). +inline __device__ uint32_t convert_float4_to_e4m3(float in0, float in1, float in2, float in3) { + using Converter = cutlass::detail::NumericArrayConverterPacked4Element< + cutlass::float_e4m3_t, + float, + cutlass::FloatRoundStyle::round_to_nearest_satfinite>; + cutlass::Array src = cutlass::make_Array(in0, in1, in2, in3); + cutlass::Array dst = Converter::convert(src); + return reinterpret_cast(dst); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float type Tensor to e4m3 type Tensor. +template +inline __device__ auto convert_float4_to_e4m3(cute::Tensor const& in) { + auto result = + cute::make_tensor(cute::shape(cute::recast_layout(in.layout()))); +#pragma unroll + for (int i = 0; i < size(in); i += 4) { + result(i / 4) = convert_float4_to_e4m3(in(i + 0), in(i + 1), in(i + 2), in(i + 3)); + } + return result; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Passthrough +template +inline __device__ cutlass::Array convert_dtype_to_dtype(cutlass::Array const& array) { + return array; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// clamp half2 +inf/-inf +static inline __device__ uint16_t satfiniteFp16(uint16_t h) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 860 + uint16_t out, clamp_value; + clamp_value = 0x7bffu; + asm volatile("min.xorsign.abs.f16 %0, %1, %2;" : "=h"(out) : "h"(h), "h"(clamp_value)); + return out; +#elif defined(__CUDA_ARCH__) && __CUDA_ARCH__ == 800 + // bit representation of maximum and minimum value of half. + uint16_t umax = 0x7bffu; + uint16_t umin = 0xfbffu; + uint16_t out; + asm volatile("min.f16 %0, %1, %2;" : "=h"(out) : "h"(h), "h"(umax)); + asm volatile("max.f16 %0, %0, %1;" : "+h"(out) : "h"(umin)); + return out; +#else + // Take the absolute value of half. It should map to |Rx| in SASS. + uint16_t p; + asm volatile("abs.f16 %0, %1;" : "=h"(p) : "h"(h)); + + // Compute a mask for each fp16: 0xffff if +INF and 0x0000 otherwise. + uint16_t inf = 0x7c00u; + uint16_t mask; + asm volatile("set.eq.u32.f16 %0, %1, %2;" : "=h"(mask) : "h"(p), "h"(inf)); + + // Recreate the new value. 0x7bff is the max value for FP16. + p = (~mask & p) | (mask & 0x7bff); + + // Simply re-add the sign and we're done. + return p | (h & 0x8000); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// clamp half2 +inf/-inf +static inline __device__ uint32_t satfiniteFp16x2(uint32_t h2) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 860 + uint32_t out, clamp_value; + clamp_value = 0x7bff7bffu; + asm volatile("min.xorsign.abs.f16x2 %0, %1, %2;" : "=r"(out) : "r"(h2), "r"(clamp_value)); + return out; +#elif defined(__CUDA_ARCH__) && __CUDA_ARCH__ == 800 + // bit representation of maximum and minimum value of half2 + uint32_t umax = 0x7bff7bffu; + uint32_t umin = 0xfbfffbffu; + uint32_t out; + asm volatile("min.f16x2 %0, %1, %2;" : "=r"(out) : "r"(h2), "r"(umax)); + asm volatile("max.f16x2 %0, %0, %1;" : "+r"(out) : "r"(umin)); + return out; +#else + // Take the absolute value of h2. It should map to |Rx| in SASS. + uint32_t p2; + asm volatile("abs.f16x2 %0, %1;" : "=r"(p2) : "r"(h2)); + + // Compute a mask for each fp16: 0xffff if +INF and 0x0000 otherwise. + uint32_t inf2 = 0x7c007c00u; + uint32_t mask; + asm volatile("set.eq.u32.f16x2 %0, %1, %2;" : "=r"(mask) : "r"(p2), "r"(inf2)); + + // Recreate the new value. 0x7bff is the max value for FP16. + p2 = (~mask & p2) | (mask & 0x7bff7bff); + + // Simply re-add the sign and we're done. + return p2 | (h2 & 0x80008000); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert floats to half. +inline __device__ cutlass::Array convert_float_to_half( + cutlass::Array const& src) { + using Converter = cutlass:: + NumericArrayConverter; + return Converter::convert(src); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 floats to 2 half. +inline __device__ cutlass::Array convert_float2_to_half( + cutlass::Array const& src) { + using Converter = cutlass:: + NumericArrayConverter; + cutlass::Array h2 = Converter::convert(src); + uint32_t& dst = reinterpret_cast(h2); + dst = satfiniteFp16x2(dst); + return reinterpret_cast&>(dst); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 2 floats to 2 half (represented as uint32_t). +inline __device__ uint32_t convert_float2_to_half(float in0, float in1) { + using Converter = cutlass:: + NumericArrayConverter; + cutlass::Array src = cutlass::make_Array(in0, in1); + cutlass::Array h2 = Converter::convert(src); + uint32_t& dst = reinterpret_cast(h2); + return satfiniteFp16x2(dst); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float type Tensor to half type Tensor. +template +inline __device__ auto convert_float2_to_half(cute::Tensor const& in) { + auto result = + cute::make_tensor(cute::shape(cute::recast_layout(in.layout()))); +#pragma unroll + for (int i = 0; i < size(in); i += 2) { + result(i / 2) = convert_float2_to_half(in(i + 0), in(i + 1)); + } + return result; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert 4 floats to 4 half. +inline __device__ cutlass::Array convert_float4_to_half( + cutlass::Array const& src) { + using Converter = cutlass:: + NumericArrayConverter; + cutlass::Array dst = Converter::convert(src); + return dst; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to extract bit from uint32_t. +inline __device__ uint32_t extract_bit_from_uint32(uint32_t const& in, int32_t offset) { + return in & (1u << offset); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to extract bit from uint64_t. +inline __device__ uint32_t extract_bit_from_uint64(uint64_t const& in, int32_t offset) { + uint32_t u32 = reinterpret_cast(in)[offset / 32]; + return u32 & (1u << (offset % 32)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to extract bit from uint128_t. +inline __device__ uint32_t extract_bit_from_uint128(cutlass::uint128_t const& in, int32_t offset) { + uint32_t u32 = reinterpret_cast(in)[offset / 32]; + return u32 & (1u << (offset % 32)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the cluster size. +inline __device__ int32_t getClusterSize() { + auto shape = cute::cluster_shape(); + return static_cast(shape.x * shape.y * shape.z); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the cluster size. +inline __device__ int32_t getClusterDimX() { + auto shape = cute::cluster_shape(); + return shape.x; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the cluster size. +inline __device__ int32_t getClusterDimY() { + auto shape = cute::cluster_shape(); + return shape.y; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the cluster size. +inline __device__ int32_t getClusterDimZ() { + auto shape = cute::cluster_shape(); + return shape.z; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the CTA mask. +inline __device__ uint16_t getCtaMask() { + return uint16_t(1) << cute::block_rank_in_cluster(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the CTA mask with multicast for A. +inline __device__ uint16_t getCtaMaskMcastA() { + // The cta_idx.y == 0 CTAs are the leaders and do the multicast loads for all other CTAs in the + // row + // xooo + // xooo + // xooo + // xooo + auto block_id_in_cluster = cute::block_id_in_cluster(); + auto cluster_dim = cute::cluster_shape(); + + uint16_t base = 0; + for (auto block_id_y = 0; block_id_y < cluster_dim.y; block_id_y++) { + base |= uint16_t{1} << (cluster_dim.x * block_id_y); + } + return base << block_id_in_cluster.x; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the CTA mask with multicast for B. +inline __device__ uint16_t getCtaMaskMcastB() { + // For the 2-CTA GEMMs, the cta_idx.x = 0,2 CTAs load the first half of B while the cta_idx.y = + // 1,3 CTAs load the second half of B. The cta_idx.x == 0,1 CTAs are the leaders and do the + // multicast loads for cta_idx.x = 2,3 CTAs. + // |x |x |x |x | + // | x| x| x| x| + // |o |o |o |o | + // | o| o| o| o| + auto block_id_in_cluster = cute::block_id_in_cluster(); + auto cluster_dim = cute::cluster_shape(); + uint16_t base = 0; + for (auto block_id_x = 0; block_id_x < cluster_dim.x; block_id_x += 2) { + base |= uint16_t(1) << (cute::block_rank_in_cluster() + block_id_x); + } + return base; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the CTA mask with multicast for SfB. +inline __device__ uint16_t getCtaMaskMcastSfB() { + // The cta_idx.x == 0 CTAs are the leaders and do the multicast loads for all other CTAs in the + // column + // xxxx + // oooo + // oooo + // oooo + auto block_id_in_cluster = cute::block_id_in_cluster(); + auto cluster_dim = cute::cluster_shape(); + uint16_t base = 0; + for (auto block_id_x = 0; block_id_x < cluster_dim.x; block_id_x++) { + base |= uint16_t(1) << block_id_x; + } + return base << (block_id_in_cluster.y * cluster_dim.x); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the CTA rank in pair. +inline __device__ int32_t getCtaRankInPair() { + return static_cast(cute::block_rank_in_cluster() & 0x1u); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get if lead CTA in CGA with multicast for A. +inline __device__ uint16_t getIsLeadCtaInCgaMcastA() { + // The cta_idx.y == 0 CTAs are the leaders and do the multicast loads for all other CTAs in the + // row + // xooo + // xooo + // xooo + // xooo + return cute::block_id_in_cluster().y == 0; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get if lead CTA in CGA with multicast for B. +inline __device__ uint16_t getIsLeadCtaInCgaMcastB() { + // For the 2-CTA GEMMs, the cta_idx.x = 0,2 CTAs load the first half of B while the cta_idx.y = + // 1,3 CTAs load the second half of B. The cta_idx.x == 0,1 CTAs are the leaders and do the + // multicast loads for cta_idx.x = 2,3 CTAs. + // |x |x |x |x | + // | x| x| x| x| + // |o |o |o |o | + // | o| o| o| o| + return cute::block_id_in_cluster().x / 2 == 0; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get if lead CTA in CGA with multicast for B. +inline __device__ uint16_t getIsLeadCtaInCgaMcastSfB() { + // The cta_idx.x == 0 CTAs are the leaders and do the multicast loads for all other CTAs in the + // column + // xxxx + // oooo + // oooo + // oooo + return cute::block_id_in_cluster().x == 0; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to get the lead CTA rank. +inline __device__ int32_t getLeadCtaRank() { + return static_cast(cute::block_rank_in_cluster() & 0xfffffffe); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to construct smem matrix descriptor used in wgmma +inline __device__ uint64_t make_smem_desc(uint32_t start_address, + uint32_t start_address_imm, + uint32_t leading_byte_offset, + uint32_t stride_byte_offset, + uint32_t base_offset, + uint32_t layout_type) { + + cute::GmmaDescriptor desc; + desc.bitfield.start_address_ = (start_address + start_address_imm) >> 4; + desc.bitfield.leading_byte_offset_ = leading_byte_offset >> 4; + desc.bitfield.stride_byte_offset_ = stride_byte_offset >> 4; + desc.bitfield.base_offset_ = base_offset; + desc.bitfield.layout_type_ = layout_type; + return static_cast(desc); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ uint64_t make_smem_desc(T* start_address, + uint32_t start_address_imm, + uint32_t leading_byte_offset, + uint32_t stride_byte_offset, + uint32_t base_offset, + uint32_t layout_type) { + + return make_smem_desc(cute::cast_smem_ptr_to_uint(start_address), + start_address_imm, + leading_byte_offset, + stride_byte_offset, + base_offset, + layout_type); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Descriptor for UTC*MMA operations without block scaling. +union UtcmmaDescriptor { + uint32_t desc_; + + struct { + // Bitfield implementation avoids the need for shifts in assignment + uint16_t sparse_id2_ : 2, // bit [ 0, 2) : Sparse meta data id2 + sparse_flag_ : 1, // bit [ 2, 3) : 0 = dense. 1 = sparse. + saturate_ : 1, // bit [ 3, 4) : 0 = no saturate. 1 = saturate. 1 value valid only for S8 + c_format_ : 2, // bit [ 4, 6) : 0 = F16. 1 = F32, 2 = S32 + : 1, // + a_format_ : 3, // bit [ 7,10) : MXF8F6F4Format:0 = E4M3, 1 = E5M2, 3 = E2M3, 4 = E3M2, 5 = + // E2M1. F32F16Format: 0 = F16, 1 = BF16, 2 = TF32. S8: 0 unsigned 8 bit, 1 + // signed 8 bit. Boolean MMA: 0 Boolean + b_format_ : 3, // bit [10,13) : MXF8F6F4Format:0 = E4M3, 1 = E5M2, 3 = E2M3, 4 = E3M2, 5 = + // E2M1. F32F16Format: 0 = F16, 1 = BF16, 2 = TF32. S8: 0 unsigned 8 bit, 1 + // signed 8 bit. Boolean MMA: 0 Boolean + a_negate_ : 1, // bit [13,14) : 0 = no negate. 1 = negate. 1 value valid only for F32F16Format + // and MXF8F6F4Format + b_negate_ : 1, // bit [14,15) : 0 = no negate. 1 = negate. 1 value valid only for F32F16Format + // and MXF8F6F4Format + a_major_ : 1; // bit [15,16) : 0 = K-major. 1 = MN-major. Major value of 1 is only valid for + // E4M3, E5M2, INT8 (signed and unsigned), F16, BF16 and TF32 source formats + uint16_t + b_major_ : 1, // bit [16,17) : 0 = K-major. 1 = MN-major. Major value of 1 is only valid for + // E4M3, E5M2, INT8 (signed and unsigned), F16, BF16 and TF32 source formats + n_dim_ : 6, // bit [17,23) : 3 LSBs not included. Valid values range from 1 (N=8) to 32 + // (N=256). All values are not valid for all instruction formats + : 1, // + m_dim_ : 5, // bit [24,29) : 4 LSBs not included. Valid values are: 4 (M=64), 8 (M=128), 16 + // (M=256) + bit_29_ : 1, // + max_shift_ : 2; // bit [30,32) : Maximum shift for WS instruction. Encoded as follows: 0 = no + // shift, 1 = maximum shift of 8, 2 = maximum shift of 16, 3 = maximum shift + // of 32. + }; + + // Decay to a uint32_t + __host__ __device__ constexpr explicit operator uint32_t() const noexcept { return desc_; } +}; + +inline __device__ uint32_t make_utcmma_desc(uint32_t fmtC, + uint32_t fmtA, + uint32_t fmtB, + bool majorMA, + bool majorNB, + uint32_t instM, + uint32_t instN, + uint32_t instK, + bool isSparseA, + [[maybe_unused]] bool isQmma) { + // Setup the Instruction descriptors, see comment on UtcmmaDescriptor above. + UtcmmaDescriptor desc_mma{0}; + desc_mma.sparse_flag_ = static_cast(isSparseA); + desc_mma.c_format_ = fmtC; + desc_mma.a_format_ = fmtA; + desc_mma.b_format_ = fmtB; + desc_mma.a_major_ = majorMA; + desc_mma.b_major_ = majorNB; + desc_mma.n_dim_ = instN >> 3; + desc_mma.m_dim_ = instM >> 4; + return desc_mma.desc_; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Descriptor for UTC*MMA operations with block scaling. +union UtcmmaDescriptorBlock { + uint32_t desc_; + + struct { + // Bitfield implementation avoids the need for shifts in assignment + uint16_t : 2, // + sparse_flag_ : 1, // bit [2,3) : 0 = dense. 1 = sparse. + bit_3_ : 1, // + b_sf_id_ : 2, // bit [4,6) : Matrix B Scale Factor ID + : 1, // + a_format_ : 3, // bit [7,10) : MXF8F6F4Format:0 = E4M3, 1 = E5M2, 3 = E2M3, 4 = E3M2, 5 = + // E2M1. F32F16Format: 0 = F16, 1 = BF16, 2 = TF32. S8: 0 unsigned 8 bit, 1 + // signed 8 bit. BMMA: 0 Boolean + b_format_ : 3, // bit [10,13) : MXF8F6F4Format:0 = E4M3, 1 = E5M2, 3 = E2M3, 4 = E3M2, 5 = + // E2M1. F32F16Format: 0 = F16, 1 = BF16, 2 = TF32. S8: 0 unsigned 8 bit, 1 + // signed 8 bit. BMMA: 0 Boolean + a_negate_ : 1, // bit [13,14) : 0 = no negate. 1 = negate. 1 value valid only for F32F16Format + // and MXF8F6F4Format + b_negate_ : 1, // bit [14,15) : 0 = no negate. 1 = negate. 1 value valid only for F32F16Format + // and MXF8F6F4Format + a_major_ : 1; // bit [15,16) : 0 = K-major. 1 = MN-major. Major value of 1 is only valid for + // E4M3, E5M2, INT8 (signed and unsigned), F16, BF16 and TF32 source formats + uint16_t + b_major_ : 1, // bit [16,17) : 0 = K-major. 1 = MN-major. Major value of 1 is only valid for + // E4M3, E5M2, INT8 (signed and unsigned), F16, BF16 and TF32 source formats + n_dim_ : 6, // bit [17,23) : 3 LSBs not included. Valid values range from 1 (N=8) to 32 + // (N=256). All values are not valid for all instruction formats + scale_format_ : 1, // bit [23,24) : 0=E4M3, 1=E8M0 + : 2, + bit_26_ : 1, // bit [26, 27) : 0 = legacy, 1 = unique SfA + m_dim_ : 2, // bit [27,29) : 4 LSBs not included. Valid values are: 4 (M=64), 8 (M=128), 16 + // (M=256) + a_sf_id_ : 2, // bit [29,31) : Matrix A Scale Factor ID + k_size_ : 1; // bit [31,32) : MMA-K Dim. MXF8F6F4Format: 0=[dense: K32, sparse: K64]. + // S8Format: 0=[dense: K32, sparse: invalid]. MXF4Format: 0=[dense: K64, sparse: + // K128], 1=[dense: K96, sparse: invalid]. + }; + // Decay to a uint32_t + __host__ __device__ constexpr explicit operator uint32_t() const noexcept { return desc_; } +}; + +inline __device__ uint32_t make_utcmma_desc_block(uint32_t fmtSf, + uint32_t fmtA, + uint32_t fmtB, + bool majorMA, + bool majorNB, + uint32_t instM, + uint32_t instN, + uint32_t instK, + bool isSparseA, + [[maybe_unused]] int version, + uint32_t byteOffsetSfA, + uint32_t byteOffsetSfB, + [[maybe_unused]] bool isOmma) { + // Setup the Instruction descriptors, see comment on UtcmmaDescriptorBlock above. + UtcmmaDescriptorBlock desc_mma{0}; + // desc_mma.a_negate_ = 0 (no negate) + // desc_mma.b_negate_ = 0 (no negate) + desc_mma.sparse_flag_ = static_cast(isSparseA); + desc_mma.scale_format_ = fmtSf; + desc_mma.a_format_ = fmtA; + desc_mma.b_format_ = fmtB; + desc_mma.a_major_ = majorMA; + desc_mma.b_major_ = majorNB; + desc_mma.n_dim_ = instN >> 3; + desc_mma.m_dim_ = instM >> 7; + desc_mma.a_sf_id_ = byteOffsetSfA; + desc_mma.b_sf_id_ = byteOffsetSfB; + desc_mma.k_size_ = (instK == 96 ? 1 : 0); + return desc_mma.desc_; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Reduction helpers +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Returns the maximum of the absolute value of the given inputs among the group with NaNs filtered +// out. +template +inline __device__ float reduce_group_max_abs_f32(float value, int laneIdx) { + // CREDUX is a whole warp reduction. Reduction for smaller group size N is emulated by: + // - FSEL (only participating threads contribute to the reduction) + // - CREDUX (actual reduction) + // - IMAD.MOV (move the result) + // Times that with the number of groups in the warp to get rough number of instructions. + // On ther other hand, SHFL-based reduction is a log2(N) operation. In that sense: + // - When N = 32, CREDUX 1 instruction. SHFL 5 instructions. + // - When N = 16, CREDUX 3*2 instructions. SHFL 4 instructions. + // - When N = 8, CREDUX 3*4 instructions. SHFL 3 instructions. + // And so on. Taking account of the actual IPC on SM100 where FSEL/CREDUX/IMAD take 2 cycles and + // SHFL takes 4 cycles: + // - When N = 32, CREDUX 2 cycles. SHFL 20 cycles. + // - When N = 16, CREDUX 12 cycles. SHFL 16 cycles. + // - When N = 8, CREDUX 24 cycles. SHFL 12 cycles. + // As result, CREDUX is better when group size >= 16. +#if __CUDA_HAS_ARCH_FAMILY_SPECIFIC(100) + constexpr bool UseRedux = (GroupSize >= 16); +#else + constexpr bool UseRedux = false; +#endif + float out = value; + if constexpr (UseRedux) { + // CREDUX-based reduction. + constexpr int GroupExtent = GroupSize * GroupStride; +#pragma unroll + for (int offset = 0; offset < 32; offset += GroupExtent) { +#pragma unroll + for (int groupOffset = 0; groupOffset < GroupStride; groupOffset++) { + bool const isParticipating = (laneIdx >= offset && laneIdx < offset + GroupExtent && + laneIdx % GroupStride == groupOffset); + float const sharedValue = isParticipating ? out : 0.0f; + float reducedValue; + asm("redux.sync.max.abs.f32 %0, %1, 0xffffffff;\n" : "=f"(reducedValue) : "f"(sharedValue)); + if (isParticipating) { + out = reducedValue; + } + } + } + // Remove NaNs if all threads participate in redux instruction. + if constexpr (GroupStride == 1) { + out = fmaxf(out, 0.f); + } + } else { + // Ensure absolute value has been taken and filter out NaNs. + out = fmaxf(fabsf(out), 0.f); + // SHFL-based reduction. +#pragma unroll + for (int size = GroupSize; size > 1; size /= 2) { + int const xorStride = (size / 2) * GroupStride; + out = fmaxf(out, __shfl_xor_sync(0xffffffffu, out, xorStride)); + } + } + return out; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ float reinterpret_uint32_to_float(uint32_t val) { + return reinterpret_cast(val); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Returns the reciprocal of a non-zero fp32 value where only exponent bits are set. +__forceinline__ __device__ float scale_rcp_exp_only(float val) { + uint32_t bits = 0x7f000000u - reinterpret_cast(val); + return reinterpret_cast(bits); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ cutlass::Array sigmoid2_base2(cutlass::Array x) { + cutlass::Array result; + // Vector of ones. + cutlass::Array one = {1.0f, 1.0f}; + // Force using FMUL2 or compiler falls back to 2x `FADD Rd, Rz, -Rb`. + cutlass::Array negX = fmul2(-one, x); + // 2x MUFU.EX2. + cutlass::Array exp2NegX = {exp2f(negX[0]), exp2f(negX[1])}; + // Use FADD2. + cutlass::Array denom = fadd2(one, exp2NegX); + result[0] = 1.0f / denom[0]; + result[1] = 1.0f / denom[1]; + return result; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Returns the largest power-of-2 less than or equal to the absolute value of the input. +__forceinline__ __device__ float trunc_abs_float_to_pow2(float val) { + // Mask out sign and mantissa bits, only retain exponent. + constexpr uint32_t mask = 0x7f800000u; + uint32_t bits = reinterpret_cast(val) & mask; + return reinterpret_cast(bits); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Exp2Emu.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Exp2Emu.h new file mode 100644 index 000000000000..86c5c69aa94e --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Exp2Emu.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include + +namespace trtllm { +namespace dev { + +// FlashAttention4-style exp2 approximation +CUTLASS_DEVICE cutlass::Array exp2f2Emu(float x0, float x1) { + using namespace cute; + + const uint32_t input_min_bits = 0xC2FE0000; // -127.0 + const uint32_t round_out_bits = 0x4B400000; // 1.5 * 2^23 + // Polynomials to approximate exp2(x) in the [0, 1] interval + const uint32_t c1_bits = 0x3F31F519; + const uint32_t c2_bits = 0x3E6906A4; + const uint32_t c3_bits = 0x3D9DF09D; + // Constants converted to float + const float input_min = *reinterpret_cast(&input_min_bits); + const float round_out = *reinterpret_cast(&round_out_bits); + const float c1 = *reinterpret_cast(&c1_bits); + const float c2 = *reinterpret_cast(&c2_bits); + const float c3 = *reinterpret_cast(&c3_bits); + + // Safeguard minimum (rounding-out won't work otherwise) + float2 x_x2 = make_float2(cutlass::fast_max(input_min, x0), cutlass::fast_max(input_min, x1)); + + float2 round_out_x2 = make_float2(round_out, round_out); + + float2 int_x_at_lower_bits_x2, subnorm_x_x2, temp_x2; +#if defined(CUTE_ARCH_FFMA2_SM100_ENABLED) + asm volatile( + "add.rm.ftz.f32x2 %0, %3, %4;\n" // [s] [exponent bit represents 2^23] [mantissa has (1<<22) + + // floor(x)]. The (1<22) ensures exponent bit untouched if + // floor(x)<0. + "sub.rn.ftz.f32x2 %2, %0, %4;\n" // %2.x = floor(x). We don't directly call floor(x) because we + // need int32(floor(x)) to be in lower bits of %0.x + "sub.rn.ftz.f32x2 %1, %3, %2;\n" // 0 <= %3.x = x - floor(x) < 1 + : "=l"(reinterpret_cast(int_x_at_lower_bits_x2)), // %0 + "=l"(reinterpret_cast(subnorm_x_x2)), // %1 + "=l"(reinterpret_cast(temp_x2)) // %2 + : "l"(reinterpret_cast(x_x2)), // %3 + "l"(reinterpret_cast(round_out_x2))); // %4 +#else + asm volatile("add.rm.ftz.f32 %0, %6, %8;\n" + "sub.rn.ftz.f32 %4, %0, %8;\n" + "sub.rn.ftz.f32 %2, %6, %4;\n" + "add.rm.ftz.f32 %1, %7, %9;\n" + "sub.rn.ftz.f32 %5, %1, %9;\n" + "sub.rn.ftz.f32 %3, %7, %5;\n" + : "=f"(int_x_at_lower_bits_x2.x), // %0 + "=f"(int_x_at_lower_bits_x2.y), // %1 + "=f"(subnorm_x_x2.x), // %2 + "=f"(subnorm_x_x2.y), // %3 + "=f"(temp_x2.x), // %4 + "=f"(temp_x2.y) // %5 + : "f"(x_x2.x), // %6 + "f"(x_x2.y), // %7 + "f"(round_out_x2.x), // %8 + "f"(round_out_x2.y)); // %9 +#endif + + float2 c0_x2 = make_float2(1.f, 1.f); + float2 c1_x2 = make_float2(c1, c1); + float2 c2_x2 = make_float2(c2, c2); + float2 c3_x2 = make_float2(c3, c3); + + cute::fma(temp_x2, subnorm_x_x2, c3_x2, c2_x2); // temp <- (f * c3 + c2) + cute::fma(temp_x2, + subnorm_x_x2, + temp_x2, + c1_x2); // temp <- f * temp + c1 = f * (f * c3 + c2) + c1 + cute::fma(temp_x2, + subnorm_x_x2, + temp_x2, + c0_x2); // f * (f * (f * c3 + c2) + c1) + 1 \approx exp2(f) for 0 < f < 1 + + uint32_t int_x0_at_lower_bits, int_x1_at_lower_bits; + asm volatile("mov.b64 {%0, %1}, %2;\n" + : "=r"(int_x0_at_lower_bits), "=r"(int_x1_at_lower_bits) + : "l"(reinterpret_cast(int_x_at_lower_bits_x2))); + + // Mul exp2f(int_x) <=> Mul ((int_x << 23 + 127) <=> Add (int_x << 23) + uint32_t y0_bits = (int_x0_at_lower_bits << 23) + *reinterpret_cast(&temp_x2.x); + uint32_t y1_bits = (int_x1_at_lower_bits << 23) + *reinterpret_cast(&temp_x2.y); + + cutlass::Array y; + y[0] = *reinterpret_cast(&y0_bits); + y[1] = *reinterpret_cast(&y1_bits); + return y; +} +} // namespace dev +} // namespace trtllm \ No newline at end of file diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/FastMath.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/FastMath.h new file mode 100644 index 000000000000..9706c8c22052 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/FastMath.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Fast Modulo/Division using Precomputation (int32_t only) +// +// Portable standalone implementation based on NVIDIA CCCL library +// Original: +// https://github.com/NVIDIA/cccl/blob/main/libcudacxx/include/cuda/__cmath/fast_modulo_division.h +// +// Implements fast division and modulo operations by precomputing multipliers +// that replace slow division with fast multiplication + bit shifts. +// +// References: +// - Hacker's Delight, Second Edition, Chapter 10 +// - Labor of Division (Episode III): +// https://ridiculousfish.com/blog/posts/labor-of-division-episode-iii.html +// - Classic Round-Up Variant: https://arxiv.org/pdf/2412.03680 + +// Note that this portable header is a WAR for CTK < 13.1. CCCL fast_mod_div is supported since +// CTK 13.1. CCCL fast_mod_div should be adopted in the future. + +#pragma once + +#include +#include +#include + +#define FMD_HOST_DEVICE __host__ __device__ +#define FMD_DEVICE __device__ +#define FMD_FORCEINLINE inline + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Helper functions +//////////////////////////////////////////////////////////////////////////////////////////////////// + +FMD_HOST_DEVICE FMD_FORCEINLINE constexpr bool is_power_of_two(int32_t x) noexcept { + return x > 0 && (x & (x - 1)) == 0; +} + +FMD_HOST_DEVICE FMD_FORCEINLINE constexpr int ilog2(int32_t x) noexcept { + int log = 0; + uint32_t ux = static_cast(x); + while (ux >>= 1) { + ++log; + } + return log; +} + +FMD_HOST_DEVICE FMD_FORCEINLINE constexpr int ceil_ilog2(int32_t x) noexcept { + return is_power_of_two(x) ? ilog2(x) : ilog2(x) + 1; +} + +FMD_HOST_DEVICE FMD_FORCEINLINE constexpr uint64_t ceil_div(uint64_t a, uint64_t b) noexcept { + return (a + b - 1) / b; +} + +// Get high 32 bits of 32x32->64 bit multiplication +#if defined(__CUDA_ARCH__) +FMD_DEVICE FMD_FORCEINLINE uint32_t mul_hi(uint32_t a, uint32_t b) noexcept { + return __umulhi(a, b); +} +#else +FMD_HOST_DEVICE FMD_FORCEINLINE uint32_t mul_hi(uint32_t a, uint32_t b) noexcept { + return static_cast((static_cast(a) * b) >> 32); +} +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// fast_mod_div - Fast division and modulo for int32_t +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Fast division and modulo for int32_t using precomputed multipliers +// +// Note: Dividend must be non-negative (>= 0) +// +// Usage: +// fast_mod_div divisor(7); +// int32_t result = divisor.div(100); // Fast division: 14 +// int32_t remainder = divisor.mod(100); // Fast modulo: 2 +// +// Or using operator syntax: +// int32_t result = 100 / divisor; // 14 +// int32_t remainder = 100 % divisor; // 2 + +class fast_mod_div { +public: + fast_mod_div() = delete; + + // Constructor - precomputes division constants + FMD_HOST_DEVICE explicit fast_mod_div(int32_t divisor_arg) noexcept + : divisor_(divisor_arg) { + // Algorithm for signed integers (Hacker's Delight approach) + shift_ = ceil_ilog2(divisor_) - 1; + // K in range [32, 62] + int k = 32 + shift_; + uint64_t multiplier_large = ceil_div(uint64_t{1} << k, static_cast(divisor_)); + multiplier_ = static_cast(multiplier_large); + (void) add_; + } + + // Fast division + FMD_HOST_DEVICE FMD_FORCEINLINE int32_t div(int32_t dividend) const noexcept { + if (divisor_ == 1) { + return dividend; + } + + uint32_t udividend = static_cast(dividend); + uint32_t higher_bits = mul_hi(udividend, multiplier_); + return static_cast(higher_bits >> shift_); + } + + // Fast modulo + FMD_HOST_DEVICE FMD_FORCEINLINE int32_t mod(int32_t dividend) const noexcept { + return dividend - div(dividend) * divisor_; + } + + // Division operator overload + FMD_HOST_DEVICE FMD_FORCEINLINE friend int32_t operator/(int32_t dividend, + const fast_mod_div& d) noexcept { + return d.div(dividend); + } + + // Modulo operator overload + FMD_HOST_DEVICE FMD_FORCEINLINE friend int32_t operator%(int32_t dividend, + const fast_mod_div& d) noexcept { + return d.mod(dividend); + } + +private: + // Original divisor + int32_t divisor_ = 1; + // Magic multiplier + uint32_t multiplier_ = 0; + // Add value (compatible with cccl fast_mod_div) + uint32_t add_ = 0; + // Shift amount + int shift_ = 0; +}; + +} // namespace dev +} // namespace trtllm + +// Clean up macros if desired +#undef FMD_HOST_DEVICE +#undef FMD_DEVICE +#undef FMD_FORCEINLINE diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Fp4Utils.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Fp4Utils.h new file mode 100644 index 000000000000..00eaa16dddae --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Fp4Utils.h @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include "CutlassUtils.h" +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#include // __nvfp4* +#pragma GCC diagnostic pop + +typedef __nv_fp8x4_storage_t __nv_fp4x8_storage_t; +typedef unsigned long __nv_fp8x8_storage_t; + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void ldsmUnpackFp4Mode8x16Numx2(uint32_t& out0, + uint32_t& out1, + void const* srcMem) { + asm volatile("ldmatrix.sync.aligned.shared::cta.m8n16.x2.b8x16.b4x16_p64 {%0, %1}, [%2];" + : "=r"(out0), "=r"(out1) + : "l"(srcMem)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void ldsmUnpackFp4ModeTranspose16x16Numx1(uint32_t& out0, + uint32_t& out1, + void const* srcMem) { + asm volatile("ldmatrix.sync.aligned.shared::cta.m16n16.x1.trans.b8x16.b4x16_p64 {%0, %1}, [%2];" + : "=r"(out0), "=r"(out1) + : "l"(srcMem)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Fast reciprocal. +inline __device__ float reciprocal_approximate_ftz(float a) { + float b; + asm volatile("rcp.approx.ftz.f32 %0, %1;\n" : "=f"(b) : "f"(a)); + return b; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ cute::uint128_t e2m1ToFp16(uint32_t src) { + uint32_t outFp16[4]; + asm volatile("{\n" + ".reg .b8 byte0, byte1, byte2, byte3;\n" + "mov.b32 {byte0, byte1, byte2, byte3}, %4;\n" + "cvt.rn.f16x2.e2m1x2 %0, byte0;\n" + "cvt.rn.f16x2.e2m1x2 %1, byte1;\n" + "cvt.rn.f16x2.e2m1x2 %2, byte2;\n" + "cvt.rn.f16x2.e2m1x2 %3, byte3;\n" + "}\n" + : "=r"(outFp16[0]), "=r"(outFp16[1]), "=r"(outFp16[2]), "=r"(outFp16[3]) + : "r"(src)); + return *reinterpret_cast(&outFp16[0]); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void computeSfAndOutputScale(float& outputScale, + cutlass::float_e4m3_t& sfOut, + float const& amax, + float const& sfScale) { + // The reciprocal of E2M1_MAX. + float constexpr reciprocalOfE2m1Max = 1.f / 6.f; + // The FP32 sf. + float sfVal = sfScale * amax * reciprocalOfE2m1Max; + // The FP8 sf. + sfOut = cutlass::float_e4m3_t{sfVal}; + // Cast back to FP32. + sfVal = static_cast(sfOut); + + // The output scale. + // outputScale = reciprocal(fp32(fp8(sfVal * sfScale))) * reciprocal(sfScale)) + outputScale = + sfVal != 0.f ? reciprocal_approximate_ftz(sfVal * reciprocal_approximate_ftz(sfScale)) : 0.f; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void computeSfAndOutputScale(float& outputScale, + cutlass::float_e4m3_t& sfOut, + float const& amax, + float const& sfScale, + float const& sfScaleInv) { + // The reciprocal of E2M1_MAX. + float constexpr reciprocalOfE2m1Max = 1.f / 6.f; + // The FP32 sf. + float sfVal = sfScale * amax * reciprocalOfE2m1Max; + // The FP8 sf. + sfOut = cutlass::float_e4m3_t{sfVal}; + // Cast back to FP32. + sfVal = static_cast(sfOut); + + // The output scale. + // outputScale = reciprocal(fp32(fp8(sfVal * sfScale))) * reciprocal(sfScale)) + // Same as + outputScale = sfVal != 0.f ? reciprocal_approximate_ftz(sfVal * sfScaleInv) : 0.f; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float16 type Tensor to E2m1. +template +inline __device__ void convertFp16ToE2m1(OutT& out, + cutlass::float_e4m3_t& sfOut, + uint32_t const (&in)[NumEltsPerThread / 2], + float sfScale) { + + // This function converts fp16 elements to E2m1. + // Inputs: + // - in: fp16 values. + // - sfScale: The global scaling factor. + // Outputs: + // - return value: The casted E2m1 values. + // - sfOut: The local scaling factor. + + // The number of half2 elements per thread. + int32_t constexpr NumHalf2PerThread = NumEltsPerThread / 2; + // The number of threads per vector of 16 elements. + int32_t constexpr NumThreadsPerVec = 16 / NumEltsPerThread; + + // Cast the input to half2 array. + half2 const(&inH2)[NumHalf2PerThread] = reinterpret_cast(in); + + // Get absolute maximum values among the local 8 values. + auto localAmax = __habs2(inH2[0]); +#pragma unroll + for (int32_t ii = 1; ii < NumHalf2PerThread; ++ii) { + localAmax = __hmax2(localAmax, __habs2(inH2[ii])); + } + + // Perform warp-level reduction to achieve the amax of the vector of 16 elements. + if constexpr (NumThreadsPerVec > 1) { + static_assert(NumThreadsPerVec == 2 || NumThreadsPerVec == 4, "Not supported."); + for (int32_t step = 1; step < NumThreadsPerVec; step *= 2) { + localAmax = __hmax2(__shfl_xor_sync(uint32_t(-1), localAmax, step), localAmax); + } + } + + // Get the final absolute maximum values. + float vecAmax = float(__hmax(localAmax.x, localAmax.y)); + + // Compute the sf and output scale. + float outputScale; + computeSfAndOutputScale(outputScale, sfOut, vecAmax, sfScale); + + // Apply the output scale. + cutlass::Array scaled; +#pragma unroll + for (int32_t ii = 0; ii < NumHalf2PerThread; ++ii) { + float2 tmp = __half22float2(inH2[ii]); + scaled[ii * 2 + 0] = tmp.x * outputScale; + scaled[ii * 2 + 1] = tmp.y * outputScale; + } + + // Array of E2m1. + auto arrFp4 = castArray(scaled); + // Make sure the type size is as expected. + static_assert(sizeof(arrFp4) == NumEltsPerThread / 2 && sizeof(arrFp4) == sizeof(OutT)); + // Cast to E2m1. + out = reinterpret_cast(arrFp4); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float to E2m1. +template +inline __device__ void convertFloatToE2m1(OutT& out, + cutlass::float_e4m3_t& sfOut, + float const (&in)[NumEltsPerThread], + float sfScale) { + + // This function converts float to E2m1. + // Inputs: + // - in: The tensor holding float values. + // - sfScale: The global scaling factor. + // Outputs: + // - return value: The casted E2m1 values. + // - sfOut: The local scaling factor. + + // The number of threads per vector of 16 elements. + int32_t constexpr NumThreadsPerVec = 16 / NumEltsPerThread; + + // Find the loacl amax. + float localAmax = 0; +#pragma unroll + for (int ii = 0; ii < 16; ii++) { + localAmax = fmaxf(localAmax, fabsf(in[ii])); + } + + // Get the absolute maximum among all 16 values. + if constexpr (NumThreadsPerVec > 1) { + static_assert(NumThreadsPerVec == 2, "Not supported."); + localAmax = fmaxf(__shfl_xor_sync(uint32_t(-1), localAmax, 1), localAmax); + } + + // Compute the sf and output scale. + float outputScale; + computeSfAndOutputScale(outputScale, sfOut, localAmax, sfScale); + + // Apply the output scale. + cutlass::Array scaled; +#pragma unroll + for (int ii = 0; ii < 16; ii++) { + scaled[ii] = in[ii] * outputScale; + } + + // Array of E2m1. + auto arrFp4 = castArray(scaled); + // Cast to E2m1. + out = reinterpret_cast(arrFp4); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float to E2m1. +template +inline __device__ void convertFloatToE2m1(OutT& out, float const (&in)[NumEltsPerThread]) { + // Apply the output scale. + auto arrFp32{reinterpret_cast const&>(in[0])}; + + // Array of E2m1. + auto arrFp4 = castArray(arrFp32); + // Cast to E2m1. + out = reinterpret_cast(arrFp4); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert float to E2m1. +inline __device__ uint32_t convertFloat8ToE2m1(float in0, + float in1, + float in2, + float in3, + float in4, + float in5, + float in6, + float in7) { + + cutlass::Array arrFp32{in0, in1, in2, in3, in4, in5, in6, in7}; + + // Array of E2m1. + auto arrFp4 = castArray(arrFp32); + // Cast to uint32_t. + return reinterpret_cast(arrFp4); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Compute the offset that corresponds to (dataRowIdx, dataBlkColIdx) in the SF tensor where +// dataRowIdx and dataBlkColIdx are the respective indices of the row and the block of 16 elts +// from the K dim in the tensor of data. +inline __device__ int64_t getSfOffset(int32_t dataRowIdx, + int32_t dataBlkColIdx, + int32_t numDataBlksPerRow) { + + // The number of rows of SF per block. + static int32_t constexpr NumRowsPerSfBlock = 128; + // The number of cols of SF per block. + static int32_t constexpr NumColsPerSfBlock = 4; + // The size of each SF block. + static int32_t constexpr NumBytesPerSfBlock = NumRowsPerSfBlock * NumColsPerSfBlock; + + // The number of rows of data per SF block. + static int32_t constexpr NumDataRowsPerSfBlock = NumRowsPerSfBlock; + // The number of cols of blocks of data per SF block. + static int32_t constexpr NumDataBlkColsPerSfBlock = NumColsPerSfBlock; + + // The row of the SF block in the SF tensor. + int sfBlkRowIdx = dataRowIdx / NumDataRowsPerSfBlock; + // The col of the SF block in the SF tensor. + int sfBlkColIdx = dataBlkColIdx / NumDataBlkColsPerSfBlock; + // The blocks are stored row-major in the tensor of scaling factors. + int sfBlkIdx = sfBlkRowIdx * numDataBlksPerRow / NumDataBlkColsPerSfBlock + sfBlkColIdx; + + // Find the row in the SF block. + int sfRowIdx = (dataRowIdx % 32) * 4 + (dataRowIdx % NumDataRowsPerSfBlock) / 32; + // Find the col in the SF block. + int sfColIdx = (dataBlkColIdx % 4); + + // Compute the offset in bytes. + return sfBlkIdx * NumBytesPerSfBlock + sfRowIdx * NumColsPerSfBlock + sfColIdx; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Given the GMEM address of an output element, compute the offset of the corresponding scaling +// factor in the SF tensor. Optionally, a startTokenIndex can be provided if the first token is not +// the start token in the SF tensor. This is useful when inflight batching is enabled in TRT-LLM, +// where the context and generation output are stored as one output tensor. In this case, the +// generation output may not start with zero offset in the SF output tensor. +template +inline __device__ int64_t getSfOffset(int64_t gmemOffsetInBytes, + int32_t hiddenDim, + int32_t startTokenIdx = 0) { + // The number of elements per sf. + int32_t constexpr NumEltsPerSf = 16; + // The GMEM offset of the output element. + int64_t gmemOffset = gmemOffsetInBytes * 8 /*bits*/ / NumBitsPerElt; + // The row/col indices of the corresponding SF element. + int32_t sfRowIdx = gmemOffset / hiddenDim + startTokenIdx; + int32_t sfColIdx = (gmemOffset % hiddenDim) / NumEltsPerSf; + // Compute the SF offset. + return getSfOffset(sfRowIdx, sfColIdx, hiddenDim / NumEltsPerSf); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// TODO(tizheng): Refactor to track gmem offset instead of doing pointer subtraction. +template +inline __device__ int64_t getSfOffset(void const* gmemOutPtr, + void const* gmemBasePtr, + int32_t hiddenDim, + int32_t startTokenIdx = 0) { + return getSfOffset(reinterpret_cast(gmemOutPtr) - + reinterpret_cast(gmemBasePtr), + hiddenDim, + startTokenIdx); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Pipeline.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Pipeline.h new file mode 100644 index 000000000000..06b0f782d566 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Pipeline.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template class PipelineState { +public: + // Ctor. + inline __device__ PipelineState() + : mIndex{0} {} + + // Get access to the index. + inline __device__ int index() const { return mIndex; } + + // Increment the state. + inline __device__ PipelineState& operator++() { + mIndex = (mIndex == NumStages - 1) ? 0 : (mIndex + 1); + return *this; + } + +private: + // The state. + int mIndex; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template class Pipeline { + + // Offset to the first full barrier. + static constexpr int FullBarOffset{0}; + // Offset to the first empty barrier. + static constexpr int EmptyBarOffset{NumStages}; + + // The state. + using State = PipelineState; + +public: + // Ctor. + inline explicit __device__ Pipeline(int barId) + : mBarId{barId} {} + + // Consumer release the barrier. + inline __device__ void consumer_release(State const& state) { + barrier_arrive(EmptyBarOffset + mBarId + state.index()); + } + + // Consumer test if they have to wait at the barrier. It does nothing. + [[nodiscard]] inline __device__ int32_t consumer_test_wait(State const&) { return int32_t{0}; } + + // Consumer try to wait at the barrier. It does nothing. + [[nodiscard]] inline __device__ int32_t consumer_try_wait(State const&) { return int32_t{0}; } + + // Consumer wait at the barrier. + inline __device__ void consumer_wait(State const& state, int32_t = int32_t{0}) { + barrier_sync(FullBarOffset + mBarId + state.index()); + } + + // Producer acquire the barrier. + inline __device__ void producer_acquire(State const& state, int32_t t = int32_t{0}) { + if (t != int32_t{1}) { + barrier_sync(EmptyBarOffset + mBarId + state.index()); + } + } + + // Producer arrive at the barrier. + inline __device__ void producer_commit(State const& state) { + barrier_arrive(FullBarOffset + mBarId + state.index()); + } + + // Producer clean the cluster barrier. It does nothing. + inline __device__ void producer_tail(State const&) {} + + // Producer try to acquire the barrier. It does nothing. + [[nodiscard]] inline __device__ int32_t producer_try_acquire(State const&) { return int32_t{0}; } + + // Decrement state index for n positions. + [[nodiscard]] inline __device__ int32_t decr_state_index(State const& state, int32_t n) { + auto index = (state.index() - n) % NumStages; + return index < 0 ? index + NumStages : index; + } + +private: + // Barrier arrive. + inline __device__ void barrier_arrive(int barId) { + asm volatile("barrier.cta.arrive %0, %1;" ::"r"(barId), "n"(NumThreads)); + } + + // Barrier wait. + inline __device__ void barrier_sync(int barId) { + asm volatile("barrier.cta.sync %0, %1;" ::"r"(barId), "n"(NumThreads)); + } + +private: + // The 1st barrier id. This pipeline uses 2 x NumStages named barriers. + int mBarId; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceCol.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceCol.h new file mode 100644 index 000000000000..9dbcb0ed7f68 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceCol.h @@ -0,0 +1,447 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// NOTE: Using a guard here since NVRTC fails if using #pragma once +#ifndef TRTLLM_DEV_REDUCECOL_H +#define TRTLLM_DEV_REDUCECOL_H + +#include +#include "CutlassBarrier.h" + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The following functions are helpers to implement an atomicMax in shared memory for float. +// +// Cutlass implements atomicMax for float using the following method: +// +// if (signbit(x)) { +// atomicMin(smemPtr, reinterpret_cast(x)); +// } else { +// atomicMax(smemPtr, reinterpret_cast(x)); +// } +// +// This code leads to multiple branches and two ATOMS.* per floating-point value. We avoid the +// branching and stick to one ATOMS.MAX per floating-point value using a trick described in +// http://stereopsis.com/radix.html and implemented in CUB's radix sort, for example. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// XOR the sign bit and take two-complement if the sign bit was set. + +inline __device__ uint32_t floatToUInt32ForAtomicMax(float f) { + uint32_t mask = -int32_t(reinterpret_cast(f) >> 31) | 0x80000000; + return reinterpret_cast(f) ^ mask; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Undo the two-complement encoding and reset the sign bit. + +inline __device__ float uint32ToFloatForAtomicMax(uint32_t u) { + uint32_t mask = ((u >> 31) - 1) | 0x80000000; + uint32_t f = (u ^ mask); + return reinterpret_cast(f); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Perform an atomicMax for float using atomicMax for unsigned int32. + +inline __device__ void atomicMaxFloat(float* smemPtr, float val) { + atomicMax((uint32_t*)smemPtr, floatToUInt32ForAtomicMax(val)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The following functions load max values (stored as uint32_t) from shared memory and convert +// those values back to floats (see above conversion code and the link to the trick). + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void loadMaxFromSmem(float (®sMax)[2], uint32_t const* smemMax) { + // Issue the LDS.64 to load from shared memory. + uint2 vals = *reinterpret_cast(smemMax); + // Convert. + regsMax[0] = uint32ToFloatForAtomicMax(vals.x); + regsMax[1] = uint32ToFloatForAtomicMax(vals.y); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void loadMaxFromSmem(float (®sMax)[4], uint32_t const* smemMax) { + // Issue the LDS.128 to load from shared memory. + uint4 vals = *reinterpret_cast(smemMax); + // Convert. + regsMax[0] = uint32ToFloatForAtomicMax(vals.x); + regsMax[1] = uint32ToFloatForAtomicMax(vals.y); + regsMax[2] = uint32ToFloatForAtomicMax(vals.z); + regsMax[3] = uint32ToFloatForAtomicMax(vals.w); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void loadMaxFromSmem(float (®sMax)[8], uint32_t const* smemMax) { + // Issue 2 LDS.128 loads. + for (int ii = 0; ii < 2; ++ii) { + loadMaxFromSmem(reinterpret_cast(regsMax[ii * 4]), smemMax + ii * 4); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void loadMaxFromSmem(float (®sMax)[16], uint32_t const* smemMax) { + // Issue 4 LDS.128 loads. + for (int ii = 0; ii < 4; ++ii) { + loadMaxFromSmem(reinterpret_cast(regsMax[ii * 4]), smemMax + ii * 4); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void loadMaxFromSmem(float (®sMax)[32], uint32_t const* smemMax) { + // Issue 8 LDS.128 loads. + for (int ii = 0; ii < 8; ++ii) { + loadMaxFromSmem(reinterpret_cast(regsMax[ii * 4]), smemMax + ii * 4); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void loadMaxFromSmem(float (®sMax)[64], uint32_t const* smemMax) { + // Issue 16 LDS.128 loads. + for (int ii = 0; ii < 16; ++ii) { + loadMaxFromSmem(reinterpret_cast(regsMax[ii * 4]), smemMax + ii * 4); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This code computes the max for each column of a tile NumRows x NumCols distributed inside a +// warp-group. In this warp-group, there are 4 consecutive threads per row and 4x8 rows of threads. +// That's typically the result of loading the accumulators from TMEM using the 16DP/256b version of +// LDTM (LDTM.16dp256bit). +// +// Distribution of threads: +// +// Row ..0: ..0 ..1 ..2 ..3 +// Row ..1: ..4 ..5 ..6 ..7 +// Row ..2: ..8 ..9 .10 .11 +// Row ..3: .12 .13 .14 .15 +// Row ..4: .16 .17 .18 .19 +// Row ...: ... +// Row ..7: .28 .29 .30 .31 +// Row ..8: .32 .33 .34 .35 +// Row ...: ... +// Row .31: 124 125 126 127 +// +// Distribution of values (even if it does not matter too much). The indices in the following dia- +// gram are the indices of the thread owners. +// +// Row ..0: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..1: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ..2: ..8 ..8 ..9 ..9 .10 .10 .11 .11 +// Row ..3: .12 .12 .13 .13 .14 .14 .15 .15 +// Row ..4: .16 .16 .17 .17 .18 .18 .19 .19 +// Row ...: ... ... +// Row ..7: .28 .28 .29 .29 .30 .30 .31 .31 +// Row ..8: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..9: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .16: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .17: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .24: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .25: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .32: .32 .32 .33 .33 .34 .34 .35 .35 +// Row ...: ... ... +// Row .64: .64 .64 .65 .65 .66 .66 .67 .67 +// Row ...: ... ... +// Row .96: .96 .96 .97 .97 .98 .98 .99 .99 +// Row ...: ... ... +// Row 127: 124 124 125 125 126 126 127 127 + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reduceColMax16dp256bit(float (&dst)[DstN_], + cutlass::Array const& src) { + + // Make sure the number of dst registers is as expected. + static_assert(DstN_ == NumInstsPerRow * NumRepeats * 2); + // Make sure the number of src registers is as expected. + static_assert(SrcN_ == NumInstsPerCol * NumInstsPerRow * NumRepeats * 4); + + for (int ii = 0; ii < NumInstsPerCol; ++ii) { + for (int jj = 0; jj < NumInstsPerRow; ++jj) { + for (int kk = 0; kk < NumRepeats; ++kk) { + // The indices of the columns. + int const dstIdx0 = jj * NumRepeats * 2 + kk * 2 + 0; + int const dstIdx1 = jj * NumRepeats * 2 + kk * 2 + 1; + + // The indices of the source. + int const srcIdx0 = ii * NumInstsPerRow * NumRepeats * 4 + jj * NumRepeats * 4 + kk * 4 + 0; + int const srcIdx1 = ii * NumInstsPerRow * NumRepeats * 4 + jj * NumRepeats * 4 + kk * 4 + 1; + int const srcIdx2 = ii * NumInstsPerRow * NumRepeats * 4 + jj * NumRepeats * 4 + kk * 4 + 2; + int const srcIdx3 = ii * NumInstsPerRow * NumRepeats * 4 + jj * NumRepeats * 4 + kk * 4 + 3; + + // Registers srcIdx + 0 and srcIdx + 2 map to the same column. + dst[dstIdx0] = fmaxf(dst[dstIdx0], AbsoluteMax ? fabsf(src[srcIdx0]) : src[srcIdx0]); + dst[dstIdx0] = fmaxf(dst[dstIdx0], AbsoluteMax ? fabsf(src[srcIdx2]) : src[srcIdx2]); + + // Registers srcIdx + 1 and srcIdx + 3 map to the same column. + dst[dstIdx1] = fmaxf(dst[dstIdx1], AbsoluteMax ? fabsf(src[srcIdx1]) : src[srcIdx1]); + dst[dstIdx1] = fmaxf(dst[dstIdx1], AbsoluteMax ? fabsf(src[srcIdx3]) : src[srcIdx3]); + } + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reduceColMax(float (®sMax)[NumColsPerThread], + float* smemMaxPtr, + int numWarpGrpThreads, + int warpGrpThreadIdx, + int namedBarId) { + + // The number of threads per row. + int constexpr NumThreadsPerRow{4}; + // The number of threads participating in atomicMax. It's an optim between SHFL and ATOMS. + int constexpr NumThreadsPerAtomicMax{8}; + + // Then, reduce maximum values among the threads in the warp. + for (int col = 0; col < NumColsPerThread; ++col) { + for (int laneMask = 16; laneMask >= NumThreadsPerAtomicMax; laneMask /= 2) { + regsMax[col] = + fmaxf(__shfl_xor_sync(uint32_t{0xffffffff}, regsMax[col], laneMask), regsMax[col]); + } + } + + // The lane inside the warp-group. + int const laneIdx{warpGrpThreadIdx % 32}; + // The column inside the warp-group. + int const colIdx{warpGrpThreadIdx % NumThreadsPerRow}; + + // The shared memory location where to perform the atomic max. + float* smemMax = &smemMaxPtr[colIdx * NumColsPerThread]; + + // Compute the warp-group maxes using atomics in shared memory. + for (int col = 0; col < NumColsPerThread; ++col) { + if (laneIdx < NumThreadsPerAtomicMax) { + atomicMaxFloat(&smemMax[col], regsMax[col]); + } + } + + // Sync the threads in the warpgroup. + trtllm::dev::CutlassNamedBarrier::sync(numWarpGrpThreads, namedBarId); + + // Fetch the values from shared memory and populate the output buffer. + loadMaxFromSmem(regsMax, reinterpret_cast(smemMax)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void loadSumFromSmem(float2 (&sum)[NumFloat2s], float const* smem) { + + // The number of float4s to load. + int constexpr NumFloat4s{NumFloat2s / 2}; + + // Load the sums from shared memory. + for (int ii = 0; ii < NumFloat4s; ++ii) { + float4 tmp = reinterpret_cast(smem)[ii]; + sum[ii * 2 + 0].x = tmp.x; + sum[ii * 2 + 0].y = tmp.y; + sum[ii * 2 + 1].x = tmp.z; + sum[ii * 2 + 1].y = tmp.w; + } +} +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline __device__ void loadSumFromSmem(float2 (&sum)[1], float const* smem) { + sum[0] = *reinterpret_cast(smem); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeSumToSmem(float* smem, float2 const (&sum)[NumFloat2s]) { + + // The number of float4s to store. + int constexpr NumFloat4s{NumFloat2s / 2}; + + // Store the sums to shared memory. + for (int ii = 0; ii < NumFloat4s; ++ii) { + float4 tmp; + tmp.x = sum[ii * 2 + 0].x; + tmp.y = sum[ii * 2 + 0].y; + tmp.z = sum[ii * 2 + 1].x; + tmp.w = sum[ii * 2 + 1].y; + reinterpret_cast(smem)[ii] = tmp; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> inline __device__ void storeSumToSmem(float* smem, float2 const (&sum)[1]) { + reinterpret_cast(smem)[0] = sum[0]; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This code computes the sum for each column of a tile NumRows x NumCols distributed inside a +// warp-group. In this warp-group, there are 4 consecutive threads per row and 4x8 rows of threads. +// That's typically the result of loading the accumulators from TMEM using the 16DP/256b version of +// LDTM (LDTM.16dp256bit). +// +// Distribution of threads: +// +// Row ..0: ..0 ..1 ..2 ..3 +// Row ..1: ..4 ..5 ..6 ..7 +// Row ..2: ..8 ..9 .10 .11 +// Row ..3: .12 .13 .14 .15 +// Row ..4: .16 .17 .18 .19 +// Row ...: ... +// Row ..7: .28 .29 .30 .31 +// Row ..8: .32 .33 .34 .35 +// Row ...: ... +// Row .31: 124 125 126 127 +// +// Distribution of values (even if it does not matter too much). The indices in the following dia- +// gram are the indices of the thread owners. +// +// Row ..0: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..1: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ..2: ..8 ..8 ..9 ..9 .10 .10 .11 .11 +// Row ..3: .12 .12 .13 .13 .14 .14 .15 .15 +// Row ..4: .16 .16 .17 .17 .18 .18 .19 .19 +// Row ...: ... ... +// Row ..7: .28 .28 .29 .29 .30 .30 .31 .31 +// Row ..8: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..9: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .16: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .17: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .24: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .25: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .32: .32 .32 .33 .33 .34 .34 .35 .35 +// Row ...: ... ... +// Row .64: .64 .64 .65 .65 .66 .66 .67 .67 +// Row ...: ... ... +// Row .96: .96 .96 .97 .97 .98 .98 .99 .99 +// Row ...: ... ... +// Row 127: 124 124 125 125 126 126 127 127 +// +// The function is "unrolled" to deal with two instances per warp-group (and reduce the number of +// synchronization calls). + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reduceColSum(float* regsSum, + float* smemSumPtr, + int32_t numWarps, + int32_t numWarpGrpThreads, + int32_t warpGrpThreadIdx, + int32_t namedBarId) { + + // Number of threads per row. + int32_t constexpr NumThreadsPerRow{4}; + // The number of columns stored by each warp - the warps work on the same columns. + int32_t constexpr NumColsPerWarp{NumThreadsPerRow * NumColsPerThread}; + + // Declare explicit float2 arrays. + float2 sums[NumColsPerThread / 2]; + + // Issue the copies to populate those float2 arrays (the compiler will remove those copies). + for (int32_t ii = 0; ii < NumColsPerThread / 2; ++ii) { + sums[ii].x = regsSum[2 * ii + 0]; + sums[ii].y = regsSum[2 * ii + 1]; + } + + // Reduce sums across threads in the warp. + for (int32_t laneMask = 16; laneMask >= NumThreadsPerRow; laneMask /= 2) { + for (int32_t ii = 0; ii < NumColsPerThread / 2; ++ii) { + // Shuffle the values + float2 other; + other.x = __shfl_xor_sync(uint32_t{0xffffffff}, sums[ii].x, laneMask); + other.y = __shfl_xor_sync(uint32_t{0xffffffff}, sums[ii].y, laneMask); + + // Perform the summations using explicit FADD2s. + cute::add(sums[ii], sums[ii], other); + } + } + + // The warp inside the warp-group. + int const warpIdx{warpGrpThreadIdx / 32}; + // The lane inside the warp-group. + int const laneIdx{warpGrpThreadIdx % 32}; + // The column inside the warp-group. + int const colIdx{warpGrpThreadIdx % NumThreadsPerRow}; + + // The shared memory location where to store the sums of each warp. + float* smemSumDst = &smemSumPtr[warpIdx * NumColsPerWarp + colIdx * NumColsPerThread]; + + // Store the warp sums to shared memory. Only the first quad of each warp issues STS operations. + if (laneIdx < NumThreadsPerRow) { + storeSumToSmem(&smemSumDst[0], sums); + } + + // Sync the threads in the warpgroup. + trtllm::dev::CutlassNamedBarrier::sync(numWarpGrpThreads, namedBarId); + + // The shared memory locations where to read the sums from. + float const* smemSumSrc = &smemSumPtr[colIdx * NumColsPerThread]; + + // Fetch the sums from the 1st warp. All the threads perform the load. + loadSumFromSmem(sums, smemSumSrc); + + // Iterate over the other warps to fetch the other sums and add them to the existing sums. + for (int ii = 1; ii < numWarps; ++ii) { + float2 other[NumColsPerThread / 2]; + loadSumFromSmem(other, &smemSumSrc[ii * NumColsPerWarp]); + + // Perform the sums - use explicit FADD2. + for (int jj = 0; jj < NumColsPerThread / 2; ++jj) { + cute::add(sums[jj], sums[jj], other[jj]); + } + } + + // Store back to registers. The compiler will remove the MOVs. + for (int ii = 0; ii < NumColsPerThread / 2; ++ii) { + regsSum[2 * ii + 0] = sums[ii].x; + regsSum[2 * ii + 1] = sums[ii].y; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm + +#endif // TRTLLM_DEV_REDUCECOL_H diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceMultiCtasKv.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceMultiCtasKv.h new file mode 100644 index 000000000000..18042c7d2903 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceMultiCtasKv.h @@ -0,0 +1,609 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include + +#include +#include +#include +#include +#include "CutlassPipeline.h" +#include "CutlassBarrier.h" +#include "CutlassUtils.h" +#include "FastMath.h" +#include +#include "StoreGmemO.h" +#include "ReduceMultiCtasKvUtils.h" +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Map the thread's rowIdxO to headIdxO and tokenIdxO. +template +inline __device__ void mapRowToHeadTokenIdx(int32_t rowIdx, + int32_t& headIdxO, + int32_t& tokenIdxO, + int32_t numHeadsQPerKv) { + static_assert(false, "Not implemented."); +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> +inline __device__ void mapRowToHeadTokenIdx(int32_t rowIdx, + int32_t& headIdxO, + int32_t& tokenIdxO, + int32_t) { + // The stats has shape of [numTokensQ, numHeadsQ]. + // Only the tokens are grouped in the row dimension. + tokenIdxO = rowIdx; + headIdxO = 0; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> +inline __device__ void mapRowToHeadTokenIdx(int32_t rowIdx, + int32_t& headIdxO, + int32_t& tokenIdxO, + int32_t) { + // The stats has shape of [numTokensQ, numHeadsQ]. + // Only the heads are grouped in the row dimension. + tokenIdxO = 0; + headIdxO = rowIdx; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> +inline __device__ void mapRowToHeadTokenIdx(int32_t rowIdx, + int32_t& headIdxO, + int32_t& tokenIdxO, + int32_t numHeadsQPerKv) { + // The stats has shape of [numTokensQ, numHeadsQ]. + // If GroupTokensHeadsQ is true, the rowIdx needs to be mapped into tokenIdx and headIdxInGrp. + // The token index. + tokenIdxO = rowIdx / numHeadsQPerKv; + // The head index in the group. + headIdxO = rowIdx % numHeadsQPerKv; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This function updates the number of complete CTAs and return the ctaIdxKv that will do the final +// reduction work. + +inline __device__ int32_t recordCtaCompletion(int32_t* counter, + int32_t* smemPtr, + int32_t warpGrpThreadIdx, + int32_t numCtasKv, + int32_t numCtasKvForReduction, + int32_t numWarpGrpThreads, + int32_t namedBarId) { + // Atomic inc to the counter in order to check if it is the last CtaKv. + cuda::atomic_ref atomicCounter(*counter); + + // Sync the threads in the warp-group to make sure memory stores are moved after the atomic inc. + trtllm::dev::CutlassNamedBarrier::sync(numWarpGrpThreads, namedBarId); + + // The first thread updates the number of CTAs that have completed their work. + int32_t numCompleteCtas{-1}; + if (warpGrpThreadIdx == 0) { + // Use atom.inc to set the counter to zero if it is the last CTA. + asm volatile("atom.acq_rel.gpu.global.inc.u32 %0, [%1], %2;\n" + : "=r"(numCompleteCtas) + : "l"(counter), "r"(numCtasKv - 1)); + + // The ctaIdxKv that will do the final reduction work (which starts from 0). + smemPtr[0] = numCtasKv - 1 - numCompleteCtas; + + // If it is not the last CTA, wait for the last CTA to reset the counter. + if (numCompleteCtas >= (numCtasKv - numCtasKvForReduction) && + numCompleteCtas < (numCtasKv - 1)) { + while (atomicCounter.load() != 0) { + }; + } + } + + // Sync the threads in the warp-group to make sure memory stores are visiable to all threads. + trtllm::dev::CutlassNamedBarrier::sync(numWarpGrpThreads, namedBarId); + + // Return the ctaIdxKv that will do the final reduction work. + return smemPtr[0]; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void storeStatsForAb(float const* maxPtr, + float const* sumPtr, + float* statsPtr, + int32_t statsRowIdx, + int32_t localStatsRowIdx, + bool isValidThread, + int32_t numValidElts) { + // The shape of stats buffer: [numValidElts], where each element is a float2 (max/sum). + + // The layout depends on the instruction used to load from TMEM. When A and B tensors are not + // swapped for Mmas, it is LDTM.32dp32bit/LDTM.16dp32bitx2. + // 1. LDTM.32dp32bit: each thread holds one independent stats values. + // 2. LDTM.16dp32bitx2: each thread holds one independent stats values. + // Only threads with (threadIdx % 32) < 16 will store the stats values. + if (localStatsRowIdx < numValidElts && isValidThread) { + reinterpret_cast(statsPtr)[statsRowIdx] = make_float2(maxPtr[0], sumPtr[0]); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeStatsForAb(float const* maxPtr, + float const* sumPtr, + float* statsPtr, + Barrier* transactionBarrier, + int32_t statsRowIdx, + int32_t remoteSmemCtaRank, + int32_t remoteSmemRowIdx, + bool isValidThread, + int32_t numValidElts) { + // The shape of stats buffer: [numValidElts], where each element is a float2 (max/sum). + + // The layout depends on the instruction used to load from TMEM. When A and B tensors are not + // swapped for Mmas, it is LDTM.32dp32bit/LDTM.16dp32bitx2. + // 1. LDTM.32dp32bit: each thread holds one independent stats values. + // 2. LDTM.16dp32bitx2: each thread holds one independent stats values. + // Only threads with (threadIdx % 32) < 16 will store the stats values. + if (statsRowIdx < numValidElts && isValidThread) { + // The underlying barrier in the smem. + uint64_t* barrier = transactionBarrier->getBarrierPtr(); + // Map the smem address of barrier and max/sum to the remote smem space. + barrier = cuda_ptx::mapa(cuda_ptx::space_cluster_t{}, barrier, remoteSmemCtaRank); + statsPtr = cuda_ptx::mapa(cuda_ptx::space_cluster_t{}, statsPtr, remoteSmemCtaRank); + // Store the max/sum values to the remote smem. + cuda_ptx::st_async(reinterpret_cast(statsPtr) + remoteSmemRowIdx, + make_float2(maxPtr[0], sumPtr[0]), + barrier); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeStatsForSwappedAb(float const* maxPtr, + float const* sumPtr, + float* partialStatsPtr, + Barrier* transactionBarrier, + int32_t numStatsEltsPerCta, + int32_t warpGrpThreadIdx, + int32_t numValidElts) { + // The shape of partialStatsPtr buffer: [TileSizePerCtaQ], where each element is a float2 + // (max/sum). + + // The layout depends on the instruction used to load from TMEM. When A and B tensors are swapped + // for Mmas, it is LDTM.16dp256bit. In this case, the threads are reorganized as 8 x 4 layout, so + // all quads (4 contiguous threads) have the same stats values after reduction. Only the first + // quad needs to write the final max/sum values to global memory. + + // This stores the max/sum values to the remote smem. + // Each CTA has its own smem buffer, and we will split the stats values to different CTA's smem + // buffer in order to parallelize the reduction work. + + // The mapRowToHeadTokenIdx flag. + static_assert(!MapRowToHeadTokenIdx, "MapRowToHeadTokenIdx should be false for this function."); + + // The underlying barrier in the smem. + uint64_t* barrier = transactionBarrier->getBarrierPtr(); + // Store the max/sum values to the remote smem. + if (warpGrpThreadIdx < 4 * NumStatsVals) { + // The max/sum values. + float2 stats{maxPtr[0], sumPtr[0]}; +// Select the max/sum values for the current quad of threads. +#pragma unroll + for (int ii = 1; ii < NumStatsVals; ++ii) { + bool isSelectedQuad = (warpGrpThreadIdx >= 4 * ii) && (warpGrpThreadIdx < 4 * (ii + 1)); + stats.x = isSelectedQuad ? maxPtr[ii] : stats.x; + stats.y = isSelectedQuad ? sumPtr[ii] : stats.y; + } + // The stats value index. + int32_t statsIdx = warpGrpThreadIdx / 4; + // The thread index in the quad. + int32_t quadThreadIdx = warpGrpThreadIdx % 4; + // The offset to store the max/sum values. + int32_t statsOffset = (quadThreadIdx * 2) + (statsIdx / 2) * 8 + (statsIdx % 2); + // The target cta_rank that will process the current stats. + int32_t ctaRank = statsOffset / numStatsEltsPerCta; + // The remote smem rowIdx. + int32_t remoteSmemRowIdx = statsOffset % numStatsEltsPerCta; + // Map the smem address of barrier and max/sum to the remote smem space. + barrier = cuda_ptx::mapa(cuda_ptx::space_cluster_t{}, barrier, ctaRank); + partialStatsPtr = cuda_ptx::mapa(cuda_ptx::space_cluster_t{}, partialStatsPtr, ctaRank); + // Store the valid max/sum values to the remote smem. + if (statsOffset < numValidElts) { + cuda_ptx::st_async(reinterpret_cast(partialStatsPtr) + remoteSmemRowIdx, + stats, + barrier); + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeStatsForSwappedAb(float const* maxPtr, + float const* sumPtr, + float* statsGmemPtr, + int32_t numHeadsQ, + int32_t numHeadsQPerKv, + int32_t warpGrpThreadIdx, + int32_t numValidElts) { + // The shape of stats buffer: [numValidElts], where each element is a float2 (max/sum). + + // The layout depends on the instruction used to load from TMEM. When A and B tensors are swapped + // for Mmas, it is LDTM.16dp256bit. In this case, the threads are reorganized as 8 x 4 layout, so + // all quads (4 contiguous threads) have the same stats values after reduction. Only the first + // quad needs to write the final max/sum values to global memory. + if (warpGrpThreadIdx < 4 * NumStatsVals) { + // The max/sum values. + float2 stats{maxPtr[0], sumPtr[0]}; +// Select the max/sum values for the current quad of threads. +#pragma unroll + for (int ii = 1; ii < NumStatsVals; ++ii) { + bool isSelectedQuad = (warpGrpThreadIdx >= 4 * ii); + stats.x = isSelectedQuad ? maxPtr[ii] : stats.x; + stats.y = isSelectedQuad ? sumPtr[ii] : stats.y; + } + // The stats value index. + int32_t statsIdx = warpGrpThreadIdx / 4; + // The thread index in the quad. + int32_t quadThreadIdx = warpGrpThreadIdx % 4; + // The gmem offset to store the max/sum values. + int32_t statsGmemOffset = (quadThreadIdx * 2) + (statsIdx / 2) * 8 + (statsIdx % 2); + // Is it a valid stats row? + bool isValidStatsRow = statsGmemOffset < numValidElts; + // If grouping both tokens and headsQ, map statsGmemOffset into tokenIdx and headIdxInGrp and + // assume numHeadsQPerKv will be handled in one CTA. + if constexpr (MapRowToHeadTokenIdx) { + int32_t tokenIdx{statsGmemOffset / numHeadsQPerKv}; + int32_t headIdxInGrp{statsGmemOffset % numHeadsQPerKv}; + statsGmemOffset = tokenIdx * numHeadsQ + headIdxInGrp; + } + if (isValidStatsRow) { + reinterpret_cast(statsGmemPtr)[statsGmemOffset] = stats; + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reducePartialO(DtypeO* oPtr, + DtypePartialO const* partialOPtr, + float const* partialStatsPtr, + float const* attentionSinksPtr, + float* softmaxStatsPtr, + float softmaxScaleLog2, + int32_t numCtasKv, + int32_t warpGrpThreadIdx, + int32_t ctaIdxKvForReduction, + int32_t headIdxO, + int32_t numHeadsQ, + trtllm::dev::fast_mod_div numHeadsQPerKvDivisor, + int32_t numValidRows, + bool storesSoftmaxStats, + cutlass::float_e4m3_t* oSfPtr = nullptr, + float sfScale = 0.f, + int32_t sfBaseRowIdx = 0) { + + // clang-format off + // The shape of partialO buffer: [numCtasKv, TileSizePerCtaQ, headDimPerCta]. + // The shape of final O buffer: [numValidRows, numHeadsKv, headDim]. + // The shape of attentionSinks buffer: [numHeadsQ]. + // The shape of partialStats buffer: [numCtasKv, TileSizePerCtaQ], where each element is a float2 (max/sum). + // The shape of softmaxStats buffer: [numValidRows], where each element is a float2 (max/sum). + // The shape of smem buffer: [numCtasKv, NumWarpGrpThreads]. + // Note that numValidRows includes both numValidTokens and numHeadsQPerKv if grouping headsQ. + // clang-format on + + int32_t constexpr NumBytesPerPartialElt{sizeof(DtypePartialO)}; + static_assert(NumBytesPerPartialElt == 2, + "The data type of partialO should be either fp16 or bf16."); + + // The threads in the warp-group should load different values from one partial output + // [numValidRows, headDim], and then iterate over partial outputs from different CTAs. + int32_t constexpr NumEltsPer16BVec{16 / NumBytesPerPartialElt}; + static_assert((HeadDimPerCta * NumBytesPerPartialElt) % 16 == 0, "Not implemented"); + + // The number of unrolled instructions to load partialO and partialStats. + int32_t constexpr UnrollSize{4}; + + // The number of processed rows in one slice. + int32_t constexpr NumBytesPerHeadDim{HeadDimPerCta * NumBytesPerPartialElt}; + int32_t constexpr NumBytePerSlice{NumWarpGrpThreads * 16}; + static_assert(NumBytePerSlice % NumBytesPerHeadDim == 0, "Not implemented"); + int32_t constexpr NumRowsPerSlice{NumBytePerSlice / NumBytesPerHeadDim}; + // The actual number of tensor slices for the reduction. + int32_t numSlices{(numValidRows + NumRowsPerSlice - 1) / NumRowsPerSlice}; + + // The number of slices that each CTA will process. + int32_t numSlicesPerCta{(numSlices + numCtasKv - 1) / numCtasKv}; + // The start slice index for the current CTA. + int32_t startSliceIdx{ctaIdxKvForReduction * numSlicesPerCta}; + // The end slice index for the current CTA. + int32_t endSliceIdx{std::min(startSliceIdx + numSlicesPerCta, numSlices)}; + + // The total number of rows in the partial buffers. + int32_t numRowsInPartialBuffers{TileSizePerCtaQ}; + if constexpr (UsesCgaReduction) { + numRowsInPartialBuffers = numSlicesPerCta * NumRowsPerSlice; + } + + // + // Note: currently we assume TileSizePerCtaQ is relatively small like 8 or 16, so + // duplicate work of reducing max/sum should make minor difference to the performance. + // When TileSizePerCtaQ is larger like 64/128, we might need to consider each thread reducing + // different rows' sum/max values, and make sure they can be reused later when reducing + // partialO values. + // Currently, the second read from partialStatsPtr relies on L1 cache as it is relatively small. + // + + // Iterate over different slices. + // Split the reduction work across multiple CtasKv to reduce the latency. + for (int32_t sliceIdx = startSliceIdx; sliceIdx < endSliceIdx; ++sliceIdx) { + // The base offset that each thread points to. + int32_t const baseOffset{warpGrpThreadIdx * NumEltsPer16BVec}; + // The index in the row dimension. + int32_t const rowIdx{sliceIdx * NumRowsPerSlice + (baseOffset / HeadDimPerCta)}; + // Does this thread point to a valid row ? + bool const isValidRow{rowIdx < numValidRows}; + int32_t validRowIdx{std::min(rowIdx, numValidRows - 1)}; + // If the CGA reduction is used, each CTA has its own smem buffer, and we will split the slices + // to different CTA's smem buffer in order to parallelize the reduction work, which means the + // rowIdx should be mapped to the correct CTA's smem buffer (starts from 0). + int32_t loadRowIdx{validRowIdx}; + if constexpr (UsesCgaReduction) { + // The index in the headDim dimension. + loadRowIdx -= (startSliceIdx * NumRowsPerSlice); + } + // The index in the headDim dimension. + int32_t const headDimIdx{baseOffset % HeadDimPerCta}; + // The memory load offfset (can be from remote shared memory or global memory). + int64_t const destMemOffset{loadRowIdx * HeadDimPerCta + headDimIdx}; + // The memory store offset. + int64_t gmemStoreOffset{validRowIdx * HeadDim + headDimIdx}; + // The local headIdxO. + int32_t localHeadIdxO{headIdxO + validRowIdx}; + // The rowIdx of softmaxStats. + int32_t softmaxStatsRowIdx{validRowIdx}; + // If grouping both tokens and headsQ, map validRowIdx into tokenIdx and headIdxInGrp and + // assume numHeadsQPerKv will be handled in one CTA. + if constexpr (GroupsTokensHeadsQ) { + int32_t tokenIdx{validRowIdx / numHeadsQPerKvDivisor}; + int32_t headIdxInGrp{validRowIdx % numHeadsQPerKvDivisor}; + localHeadIdxO = headIdxO + headIdxInGrp; + softmaxStatsRowIdx = tokenIdx * numHeadsQ + headIdxInGrp; + gmemStoreOffset = int64_t(softmaxStatsRowIdx) * HeadDim + headDimIdx; + } + + // Reduce max, sum and partialO vectors from different CtasKv. + float sumVal{0.f}; + float oldMaxVal{-FLT_MAX}, maxVal{-FLT_MAX}; + float outputVals[NumEltsPer16BVec] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f}; + for (int32_t ii = 0; ii < numCtasKv; ii += UnrollSize) { + // The partialStats array and partialO array. + float2 partialStatsArray[UnrollSize]; + uint4 partialOArray[UnrollSize]; +#pragma unroll + for (int32_t jj = 0; jj < UnrollSize; ++jj) { + int32_t ctaIdxKv = min(ii + jj, numCtasKv - 1); + partialStatsArray[jj] = reinterpret_cast( + partialStatsPtr)[ctaIdxKv * numRowsInPartialBuffers + loadRowIdx]; + partialOArray[jj] = *reinterpret_cast( + partialOPtr + destMemOffset + ctaIdxKv * numRowsInPartialBuffers * HeadDimPerCta); + } +#pragma unroll + for (int32_t jj = 0; jj < UnrollSize; ++jj) { + // Whether the ctaIdxKv is valid. + bool const isValidCtaIdxKv = (ii + jj) < numCtasKv; + // The local max and sum values. + auto partialStats = partialStatsArray[jj]; + float localMax = partialStats.x; + float localSum = partialStats.y; + // Update the max value. + maxVal = fmaxf(maxVal, localMax); + // Compute the correction scales. + float corrScale0 = isValidCtaIdxKv ? exp2f(softmaxScaleLog2 * (oldMaxVal - maxVal)) : 1.f; + float corrScale1 = isValidCtaIdxKv ? exp2f(softmaxScaleLog2 * (localMax - maxVal)) : 0.f; + // Update the old max value. + oldMaxVal = maxVal; + // The partialO value. + uint4 vec = partialOArray[jj]; + // Reduce sum and finalO. + sumVal = sumVal * corrScale0 + localSum * corrScale1; + trtllm::dev::convertToFloatAndAccumulate(outputVals, + vec, + corrScale0, + corrScale1); + } + } + + // Update the sums with the attention sink value. + if (attentionSinksPtr != nullptr) { + float attentionSinkVal = + exp2f(attentionSinksPtr[localHeadIdxO] * CUDART_L2E_F - maxVal * softmaxScaleLog2); + // Multiply the attention sink value by 448.f if the MMA data type is e4m3 as the sum value + // has also included the 448.f quantization scale. + sumVal += IsE4m3Bmm ? attentionSinkVal * 448.f : attentionSinkVal; + } + + // Stores the final softmax stats values to global memory if needed (Helix attention, which + // splits seqLenKv across GPUs). + if (storesSoftmaxStats && isValidRow && headDimIdx == 0) { + // The softmaxScale. + float softmaxScale = (softmaxScaleLog2 * (1.f / CUDART_L2E_F)); + // The sumScale to unscale the 448.f quantization scale from P. + float sumScale = IsE4m3Bmm ? (1.f / 448.f) : 1.f; + // The final max and sum values. + float2 stats{maxVal * softmaxScale, sumVal * sumScale}; + // Store the final max and sum values to global memory. + reinterpret_cast(softmaxStatsPtr)[softmaxStatsRowIdx] = stats; + } + + // The final normalized scale. + // If the output data type is e4m3, make sure that sumVal is divided by the quantization scale + // (448.f), so 1.0f / (sumVal / 448.f) = 448.f / sumVal. + float normalizedScale{IsE4m3Bmm ? (448.f / sumVal) : (1.0f / sumVal)}; + float2 normalizedScale2{normalizedScale, normalizedScale}; + + // Apply the normalized scale to the reduced O values. + for (int ii = 0; ii < NumEltsPer16BVec / 2; ++ii) { + float2& f2 = reinterpret_cast(outputVals)[ii]; + cute::mul(f2, f2, normalizedScale2); + } + + // Convert the float values to DtypeO, and Store it to global memory. + if constexpr (std::is_same_v) { + // The number of E2m1 elements packed in a byte. + int32_t constexpr NumE2m1EltsPerByte = 2; + // The number of elements per sf. + int32_t constexpr NumEltsPerSf = 16; + // The number of cols of SF per block. + int32_t constexpr NumColsPerSfBlock = 4; + // The size of each SF block. + int32_t constexpr NumBytesPerSfBlock = 512; + + // The number of elements per sf. + int32_t constexpr HeadDimSf = HeadDim / NumEltsPerSf; + // The offset to store the SF values. + int64_t storeGmemSfOffset; + + // When grouping tokens and headsQ, each row packs (tokenIdx, headIdxInGrp). + // Use getSfOffset with absolute indices for correct Layout128x4 mapping, + // since different rows map to different SF rows (tokens) and columns (head groups). + if constexpr (GroupsTokensHeadsQ) { + int32_t tokenIdx{validRowIdx / numHeadsQPerKvDivisor}; + int32_t headIdxInGrp{validRowIdx % numHeadsQPerKvDivisor}; + int32_t sfCol = headIdxInGrp * HeadDimSf + headDimIdx / NumEltsPerSf; + int32_t numSfPerRow{numHeadsQ * HeadDimSf}; + storeGmemSfOffset = getSfOffset(sfBaseRowIdx + tokenIdx, sfCol, numSfPerRow); + } else { + // Without GroupsTokensHeadsQ, all rows share the same head and the SF column + // is simply derived from gmemStoreOffset. The oSfPtr already accounts for the + // base head and token offsets. + int32_t sfColIdx = gmemStoreOffset / NumEltsPerSf; + storeGmemSfOffset = + sfColIdx / NumColsPerSfBlock * NumBytesPerSfBlock + sfColIdx % NumColsPerSfBlock; + } + convertAndStoreToGmem( + reinterpret_cast(oPtr + gmemStoreOffset / NumE2m1EltsPerByte), + reinterpret_cast(oSfPtr) + storeGmemSfOffset, + outputVals, + sfScale, + isValidRow); + } else { + if (isValidRow) { + convertAndStoreToGmem(reinterpret_cast(oPtr + gmemStoreOffset), outputVals); + } + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reducePartialO(DtypeO* oPtr, + DtypePartialO const* partialOPtr, + float const* partialStatsPtr, + float const* attentionSinksPtr, + float* softmaxStatsPtr, + Barrier* transactionBarrier, + int32_t completionBytes, + float softmaxScaleLog2, + int32_t numCtasKv, + int32_t warpGrpThreadIdx, + int32_t ctaIdxKvForReduction, + int32_t headIdxO, + int32_t numHeadsQ, + trtllm::dev::fast_mod_div numHeadsQPerKvDivisor, + int32_t numValidRows, + bool storesSoftmaxStats, + cutlass::float_e4m3_t* oSfPtr = nullptr, + float sfScale = 0.f, + int32_t sfBaseRowIdx = 0) { + + // + // If the CGA reduction is used, we need to use the transaction barrier to synchronize the + // reduction. + // + static_assert(UsesCgaReduction, "Not implemented"); + + // Perform the completion of the unused bytes. + if (warpGrpThreadIdx == 0) { + transactionBarrier->complete_transaction(cute::block_rank_in_cluster(), completionBytes); + } + // Wait for all the CTAs in the cluster to complete the remote store. + transactionBarrier->wait(); + + // Perform the reduction on the smem. + reducePartialO(oPtr, + partialOPtr, + partialStatsPtr, + attentionSinksPtr, + softmaxStatsPtr, + softmaxScaleLog2, + numCtasKv, + warpGrpThreadIdx, + ctaIdxKvForReduction, + headIdxO, + numHeadsQ, + numHeadsQPerKvDivisor, + numValidRows, + storesSoftmaxStats, + oSfPtr, + sfScale, + sfBaseRowIdx); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceMultiCtasKvUtils.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceMultiCtasKvUtils.h new file mode 100644 index 000000000000..3574d30131a4 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceMultiCtasKvUtils.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include +#include "CutlassUtils.h" +#include +#include "Fp4Utils.h" + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void convertAndStoreToGmem(char* gmemPtr, float (&input)[NumElts]) { + static_assert(sizeof(Dtype) == 0, "Not implemented."); +} + +template +inline __device__ void convertAndStoreToGmem(char* gmemPtr, + char* oSfPtr, + float (&input)[NumElts], + float sfScale, + bool isValidRow) { + static_assert(sizeof(Dtype) == 0, "Not implemented."); +} + +template <> +inline __device__ void convertAndStoreToGmem(char* gmemPtr, float (&input)[8]) { + uint4 output; + output.x = convert_float2_to_half(input[0], input[1]); + output.y = convert_float2_to_half(input[2], input[3]); + output.z = convert_float2_to_half(input[4], input[5]); + output.w = convert_float2_to_half(input[6], input[7]); + *reinterpret_cast(gmemPtr) = output; +} + +template <> +inline __device__ void convertAndStoreToGmem(char* gmemPtr, + float (&input)[8]) { + uint4 output; + output.x = convert_float2_to_bfloat16(input[0], input[1]); + output.y = convert_float2_to_bfloat16(input[2], input[3]); + output.z = convert_float2_to_bfloat16(input[4], input[5]); + output.w = convert_float2_to_bfloat16(input[6], input[7]); + *reinterpret_cast(gmemPtr) = output; +} + +template <> +inline __device__ void convertAndStoreToGmem(char* gmemPtr, + float (&input)[8]) { + uint2 output; + output.x = convert_float4_to_e4m3(input[0], input[1], input[2], input[3]); + output.y = convert_float4_to_e4m3(input[4], input[5], input[6], input[7]); + *reinterpret_cast(gmemPtr) = output; +} + +template <> +inline __device__ void convertAndStoreToGmem(char* gmemPtr, + char* gmemSfPtr, + float (&input)[8], + float sfScale, + bool isValidRow) { + cutlass::float_e4m3_t sfOut; + uint32_t valOut; + convertFloatToE2m1<8>(valOut, sfOut, input, sfScale); + if (isValidRow) { + *reinterpret_cast(gmemPtr) = valOut; + if (threadIdx.x % 2 == 0) { + *reinterpret_cast(gmemSfPtr) = sfOut; + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void convertToFloatAndAccumulate(float (&output)[NumElts], + uint4 input, + float scale0, + float scale1) { + static_assert(sizeof(Dtype) == 0, "Not implemented."); +} + +template <> +inline __device__ void convertToFloatAndAccumulate(float (&output)[8], + uint4 input, + float scale0, + float scale1) { + float2 scales0 = make_float2(scale0, scale0); + float2 scales1 = make_float2(scale1, scale1); +#pragma unroll + for (int32_t ii = 0; ii < 4; ++ii) { + float2 a = __half22float2(reinterpret_cast<__half2*>(&input)[ii]); + float2& c = reinterpret_cast(output)[ii]; + // FFMA2: output = input * scale1 + output * scale0. + cute::mul(c, c, scales0); + cute::fma(c, a, scales1, c); + } +} + +template <> +inline __device__ void convertToFloatAndAccumulate(float (&output)[8], + uint4 input, + float scale0, + float scale1) { + float2 scales0 = make_float2(scale0, scale0); + float2 scales1 = make_float2(scale1, scale1); +#pragma unroll + for (int32_t ii = 0; ii < 4; ++ii) { + float2 a = __bfloat1622float2(reinterpret_cast<__nv_bfloat162*>(&input)[ii]); + float2& c = reinterpret_cast(output)[ii]; + // FFMA2: output = input * scale1 + output * scale0. + cute::mul(c, c, scales0); + cute::fma(c, a, scales1, c); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceRow.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceRow.h new file mode 100644 index 000000000000..61de813b0e5a --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceRow.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include "ReduceCol.h" +#include "CutlassBarrier.h" + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This code computes the max for each row of a tile NumRows x NumCols distributed inside a +// warp-group. In this warp-group, there are 4 consecutive threads per row and 4x8 rows of threads. +// That's typically the result of loading the accumulators from TMEM using the 16DP/256b version of +// LDTM (LDTM.16dp256bit). +// +// Distribution of threads: +// +// Row ..0: ..0 ..1 ..2 ..3 +// Row ..1: ..4 ..5 ..6 ..7 +// Row ..2: ..8 ..9 .10 .11 +// Row ..3: .12 .13 .14 .15 +// Row ..4: .16 .17 .18 .19 +// Row ...: ... +// Row ..7: .28 .29 .30 .31 +// Row ..8: .32 .33 .34 .35 +// Row ...: ... +// Row .31: 124 125 126 127 +// +// Distribution of values (even if it does not matter too much). The indices in the following dia- +// gram are the indices of the thread owners. +// +// Row ..0: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..1: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ..2: ..8 ..8 ..9 ..9 .10 .10 .11 .11 +// Row ..3: .12 .12 .13 .13 .14 .14 .15 .15 +// Row ..4: .16 .16 .17 .17 .18 .18 .19 .19 +// Row ...: ... ... +// Row ..7: .28 .28 .29 .29 .30 .30 .31 .31 +// Row ..8: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..9: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .16: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .17: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .24: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .25: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .32: .32 .32 .33 .33 .34 .34 .35 .35 +// Row ...: ... ... +// Row .64: .64 .64 .65 .65 .66 .66 .67 .67 +// Row ...: ... ... +// Row .96: .96 .96 .97 .97 .98 .98 .99 .99 +// Row ...: ... ... +// Row 127: 124 124 125 125 126 126 127 127 + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reduceRowMax16dp256bit(float (&dst)[DstN_], + cutlass::Array const& src, + float* smemMaxPtr, + int numThreadsPerWarpGrp, + int warpGrpThreadIdx, + int namedBarId) { + + // Make sure the number of dst registers is as expected. + static_assert(DstN_ == NumInstsPerCol * 2); + // Make sure the number of src registers is as expected. + static_assert(SrcN_ == NumInstsPerCol * NumInstsPerRow * NumRepeats * 4); + + // For each row, each thread computes the abs max amongst its registers. Each LDTM.16dp256bit + // (with repeats) loads elements from two rows in TMEM. Registers 0, 1, 4, 5, 8, 9, ... map to the + // first row when registers 2, 3, 6, 7, 10, 11, ... map to the second row. + + // Iterate over the instructions in the column - produce two max per iteration. + for (int mi = 0; mi < NumInstsPerCol; ++mi) { + + // The indices of the rows. + int const row0 = mi * 2 + 0; + int const row1 = mi * 2 + 1; + + // The number of registers per repeat. LDTM.16dp256bit loads 4 registers per repeat. + int constexpr NumRegsPerRepeat = 4; + // The number of registers per LDTM.16dp256bit with repeats. + int constexpr NumRegsPerInst = NumRepeats * NumRegsPerRepeat; + // The number of registers per row of instructions. + auto constexpr NumRegsPerInstRow = NumInstsPerRow * NumRegsPerInst; + + // Iterate over the instructions in the row. + for (int ni = 0; ni < NumInstsPerRow; ++ni) { + for (int ri = 0; ri < NumRepeats; ++ri) { + + // The indices of the source. + int const src0 = mi * NumRegsPerInstRow + ni * NumRegsPerInst + ri * NumRegsPerRepeat + 0; + int const src1 = mi * NumRegsPerInstRow + ni * NumRegsPerInst + ri * NumRegsPerRepeat + 1; + int const src2 = mi * NumRegsPerInstRow + ni * NumRegsPerInst + ri * NumRegsPerRepeat + 2; + int const src3 = mi * NumRegsPerInstRow + ni * NumRegsPerInst + ri * NumRegsPerRepeat + 3; + + // Within an instruction registers 0 and 1 are for the 1st row. + dst[row0] = fmaxf(dst[row0], AbsoluteMax ? fabsf(src[src0]) : src[src0]); + dst[row0] = fmaxf(dst[row0], AbsoluteMax ? fabsf(src[src1]) : src[src1]); + + // Within an instruction registers 2 and 3 are for the 2nd row. + dst[row1] = fmaxf(dst[row1], AbsoluteMax ? fabsf(src[src2]) : src[src2]); + dst[row1] = fmaxf(dst[row1], AbsoluteMax ? fabsf(src[src3]) : src[src3]); + } + } + } + + // For each row, we have to compute the max accross the 4 lanes of the quad. + for (int mi = 0; mi < DstN_; ++mi) { + for (int laneMask = 2; laneMask >= 1; laneMask /= 2) { + dst[mi] = fmaxf(__shfl_xor_sync(uint32_t{0xffffffff}, dst[mi], laneMask), dst[mi]); + } + } + + // The lane inside the warp-group. + int const laneIdx{warpGrpThreadIdx % 32}; + // The index of the quad in the warp. + int const quadIdx{laneIdx / 4}; + // The index of the warp. + int const warpIdx{warpGrpThreadIdx / 32}; + // Number of rows loaded by a warp. Each quad owns 2 rows per instruction. + // There are NumInstsPerCol instructions. + int const numRowsPerWarp = DstN_ * 8; + // The shared memory location where to perform the atomic max. + float* smemMax = &smemMaxPtr[warpIdx * numRowsPerWarp + quadIdx * DstN_]; + + // Compute the max within warp-groups using atomics in shared memory. + // Only the first thread of the quad writes to smem. + if (warpGrpThreadIdx % 4 == 0) { + for (int ii = 0; ii < DstN_; ++ii) { + atomicMaxFloat(&smemMax[ii], dst[ii]); + } + } + + // Sync the threads in the warpgroup. + trtllm::dev::CutlassNamedBarrier::sync(numThreadsPerWarpGrp, namedBarId); + + // Fetch the values from shared memory and populate the output buffer. + loadMaxFromSmem(dst, reinterpret_cast(smemMax)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The reduce operation. +template struct ReduceOp {}; + +template <> struct ReduceOp { + inline __device__ float operator()(float a, float b) { return fmaxf(a, b); } +}; + +template <> struct ReduceOp { + inline __device__ float operator()(float a, float b) { return a + b; } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The reduce operation for the 2x2 warp-group layout of the M=128 2CTA Utcmma instruction. +template +inline __device__ void reduceWarpGrp2x2(float& val, + float* smem, + int warpGrpThreadIdx, + int namedBarId) { + + // + // The 2x2 warp-group layout. + // Need to reduce the values among the 2 warps (warp0 and warp2, warp1 and warp3). + // + // warp0 warp2 + // warp1 warp3 + // + + // The warpIdx in the warp-group. + int const warpIdx{warpGrpThreadIdx / 32}; + // The smem rowIdx. + int const smemRowIdx{warpGrpThreadIdx % 64}; + // The smem colIdx. + int const smemColIdx{warpGrpThreadIdx / 64}; + + // The named barrier to sync lanes that belong to the same row of warps (warps 0/2 and warps 1/3, + // resp). + int const namedBarrierId{(warpIdx % 2) + namedBarId}; + + // Store to smem. + smem[smemRowIdx * 2 + smemColIdx] = val; + + // Sync the threads among the row of warps. + trtllm::dev::CutlassNamedBarrier::sync(64, namedBarrierId); + + // Load from smem, and perform the reduction with the other warp in the pair. + val = ReduceOp{}(val, smem[smemRowIdx * 2 + (smemColIdx ^ 1)]); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceSliceK.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceSliceK.h new file mode 100644 index 000000000000..25457ece6ce7 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/ReduceSliceK.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Helper functions to do the reduction in the epilogue of the slice-K slices via SMEM. +// A and B matrices are transposed, such that every numSlicesForSliceK of MmaK subtiles +// are mapped along M/N dimension for the MMA. During the epilogue warp `x` has only one +// element `Sxy` for N `y` that is valid. The final result `Sz` is the sum of `Sxz` across all +// warps. +// +// +-----++-----++-----++-----+++-----++-----++-----++-----+ +// | T ileN | +// +-----++-----++-----++-----+++-----++-----++-----++-----+ +// | N0 || N0 || N0 || N0 | | N1 || N2 || N3 || N4 | +// | K0 || K1 || K2 || K3 | | K0 || K1 || K2 || K3 | +// +-----++-----++-----++-----+++-----++-----++-----++-----+ +// +----------------------------+----------------------------+ +// +-------+-------++----+ |+-----+ |+-----+ | +// | | Warp0 || W0 | || S00 | || S10 | | +// | | || K0 | || | || | | +// + +-------++----+ |+-----++-----+ |+-----++-----+ | +// | | Warp1 || W0 | | | S01 | | | S11 | | +// | | || K1 | | | | | | | | +// + TileM +-------++----+ | +-----++-----+ | +-----++-----+ | +// | | Warp2 || W0 | | | S02 | | | S12 | | +// | | || K2 | | | | | | | | +// + +-------++----+ | +-----++-----+| +-----++-----+| +// | | Warp3 || W0 | | | S03 || | S13 || +// | | || K3 | | | || | || +// +-------+-------++----+ | +-----+| +-----+| +// +----------------------------+----------------------------+ +// +// sliceKSaveToSmem writes corresponding whole TMEM to SMEM +// SMEM layout is [NumInstsPerCol * NumInstsPerRow * NumRepeats * 2, 64] +// Each column in SMEM contains 64 float values written by 32 threads -- in 16dp256b thread owns +// 2 elements per row per repeat. Additionally, to minimize bank conflicts, we apply 4 rows swizzle. +// To the written columns. +// Rows in SMEM are mapped as follows: +// +-----------------+-----------------+---------+---------+-------------------------------------+ +// | | | | Repeat0 | t0 | t0 | t1 | t1 | ... | t31 | t31 | +// | | | Row0 | Repeat1 | t1 | t1 | t0 | t0 | ... | t30 | t30 | +// | | | | ....... | ... | +// + + NumInstsPerRow0 +---------+---------+-------------------------------------+ +// | | | | Repeat0 | t0 | t0 | t1 | t1 | ... | t31 | t31 | +// | | | Row8 | Repeat1 | t1 | t1 | t0 | t0 | ... | t30 | t30 | +// | | | | ....... | ... | +// + NumInstsPerCol0 +-----------------+---------+---------+-------------------------------------+ +// | | | | Repeat0 | t0 | t0 | t1 | t1 | ... | t31 | t31 | +// | | | Row0 | Repeat1 | t1 | t1 | t0 | t0 | ... | t30 | t30 | +// | | | | ....... | ... | +// + + NumInstsPerRow1 +---------+---------+-------------------------------------+ +// | | | | Repeat0 | t0 | t0 | t1 | t1 | ... | t31 | t31 | +// | | | Row8 | Repeat1 | t1 | t1 | t0 | t0 | ... | t30 | t30 | +// | | | | ....... | ... | +// +-----------------+-----------------+---------+---------+-------------------------------------+ +// +// In sliceKReduce, warp 0 reduces all subtiles and stores the result to the registers. +// TODO it is inefficient to do it this way -- ideally, we don't need to load whole TMEM and +// do need to store it to SMEM. Only valid elements Sxy must be stored. +// We do that because of 2 reasons: +// - We use 16dp256b, which is not the optimal layout for that problem. We should use 32dp32b with +// proper offset for each warp. This way we read out only valid subtiles Sxy. +// - Index to the valid element in the array of registers is depending on the warp idx +// and can't be figured out at compilation time. Thus, if saving only valid elems +// compiler puts accumulators, the result of the LDTM, to the local memory. +// It turns out to be more efficient to save whole tile and load only valid parts from SMEM. +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void sliceKReduce16dp256bit(int warpIdx, + int laneIdx, + float* smemPtr, + cutlass::Array& acc) { + auto constexpr numRowsPerWarpPerInst = 16; + auto constexpr numThreadsPerCol = 4; + auto constexpr numEltsPerThreadPerInstPerRepeat = 2; + auto constexpr numColsPerInstPerRepeat = numThreadsPerCol * numEltsPerThreadPerInstPerRepeat; + // Number of rows in slice. + auto constexpr numRowsInSlice = NumInstsPerCol * numRowsPerWarpPerInst; + // Number of cols in slices. + auto constexpr numColsInSlice = NumInstsPerRow * NumRepeats * numColsPerInstPerRepeat; + // Number of elements produced by a warp. + auto constexpr numEltsInSlice = numRowsInSlice * numColsInSlice; + // Number of original tile columns per output valid element. + auto constexpr numColsPerValidElem = 4; + // Number of columns in SMEM tile. + auto constexpr numSmemCols = 32 * numEltsPerThreadPerInstPerRepeat; + + // Warp0 reduces all slices + if (warpIdx == 0) { +#pragma unroll + for (int ii = 0; ii < NumInstsPerCol; ++ii) { +#pragma unroll + for (int jj = 0; jj < NumInstsPerRow; ++jj) { +// Number of output elements is 4 times less (as we have 4 slices) +#pragma unroll + for (int kk = 0; kk < NumRepeats / 4; ++kk) { + // Reduced values + cutlass::Array sum[2] = {{0.f, 0.f}, {0.f, 0.f}}; +#pragma unroll + // Loop over slices + for (int si = 0; si < 4; ++si) { + // For warp 0 and 2, we use the 1st element. + // For warp 1 and 3, we use the 2nd element. + auto validElemIndexInCol = si % 2; + // Valid threads are 0 and 2 for warps 0 and 1. + // And threads 1 and 3 are for warps 2 and 3. + auto validElemThreadIdx = si / 2; + + // Row index in the smem. + // Each thread loads 2 rows per instruction (row 0 and row 8). + // Check the layout diagram above to understand the mapping. + auto const srcRowIdx0 = ii * NumInstsPerRow * NumRepeats * 2 + jj * NumRepeats * 2 + + 0 * NumRepeats + ((laneIdx % numThreadsPerCol) + kk * 4); + auto const srcRowIdx1 = ii * NumInstsPerRow * NumRepeats * 2 + jj * NumRepeats * 2 + + 1 * NumRepeats + ((laneIdx % numThreadsPerCol) + kk * 4); + + // Col index in the smem. Each lane loads 2 elements from col k and k + 2 (col width is + // uint64_t). + auto const srcColIdx0 = + (laneIdx / numThreadsPerCol) * numThreadsPerCol + validElemThreadIdx; + auto const srcColIdx1 = + (laneIdx / numThreadsPerCol) * numThreadsPerCol + validElemThreadIdx + 2; + // Swizzle cols to minimize banl conflicts. + auto const swizzledColIdx00 = + (srcColIdx0 ^ (srcRowIdx0 % numThreadsPerCol)) * 2 + validElemIndexInCol; + auto const swizzledColIdx01 = + (srcColIdx1 ^ (srcRowIdx0 % numThreadsPerCol)) * 2 + validElemIndexInCol; + auto const swizzledColIdx10 = + (srcColIdx0 ^ (srcRowIdx1 % numThreadsPerCol)) * 2 + validElemIndexInCol; + auto const swizzledColIdx11 = + (srcColIdx1 ^ (srcRowIdx1 % numThreadsPerCol)) * 2 + validElemIndexInCol; + + // Src indices in the smem to the element in `si`th slice. + int const srcIdx00 = si * numEltsInSlice + srcRowIdx0 * numSmemCols + swizzledColIdx00; + int const srcIdx01 = si * numEltsInSlice + srcRowIdx0 * numSmemCols + swizzledColIdx01; + int const srcIdx10 = si * numEltsInSlice + srcRowIdx1 * numSmemCols + swizzledColIdx10; + int const srcIdx11 = si * numEltsInSlice + srcRowIdx1 * numSmemCols + swizzledColIdx11; + + // Loading elements from SMEM. + auto val00 = smemPtr[srcIdx00]; + auto val01 = smemPtr[srcIdx01]; + auto val10 = smemPtr[srcIdx10]; + auto val11 = smemPtr[srcIdx11]; + + cutlass::Array val0 = {val00, val01}; + cutlass::Array val1 = {val10, val11}; + + // Do the reduction using FFMA2. + cute::add(sum[0], sum[0], val0); + cute::add(sum[1], sum[1], val1); + } + + // Save reduced vals back to accumulators at the "original" positions. + // It is done that way to keep the rest of the epilogue assuming 16dp256b_xR + // structure unmodified and enable more modular code that allows to combine + // slice-k with split-k, AR, etc. + auto accIdx = ii * NumInstsPerRow * NumRepeats * 4 + jj * NumRepeats * 4 + kk * 4; + acc[accIdx + 0] = sum[0][0]; + acc[accIdx + 1] = sum[0][1]; + acc[accIdx + 2] = sum[1][0]; + acc[accIdx + 3] = sum[1][1]; + } + } + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void sliceKSaveToSmem16dp256bit(int warpIdx, + int laneIdx, + float* smemPtr, + cutlass::Array& acc) { + auto constexpr numRowsPerWarpPerInst = 16; + auto constexpr numThreadsPerCol = 4; + auto constexpr numEltsPerThreadPerInstPerRepeat = 2; + auto constexpr numColsPerInstPerRepeat = numThreadsPerCol * numEltsPerThreadPerInstPerRepeat; + // Number of rows in slice. + auto constexpr numRowsInSlice = NumInstsPerCol * numRowsPerWarpPerInst; + // Number of cols in slices. + auto constexpr numColsInSlice = NumInstsPerRow * NumRepeats * numColsPerInstPerRepeat; + // Number of elements produced by a warp. + auto constexpr numEltsInSlice = numRowsInSlice * numColsInSlice; + // Number of columns in SMEM tile. + auto constexpr numSmemCols = 32 * numEltsPerThreadPerInstPerRepeat; + + // Valid threads are 0 and 2 for warps 0 and 1. + // And threads 1 and 3 are for warps 2 and 3. + auto validElemThreadIdx = warpIdx / 2; + +// Write slice to SMEM. +#pragma unroll + for (int ii = 0; ii < NumInstsPerCol; ++ii) { +#pragma unroll + for (int jj = 0; jj < NumInstsPerRow; ++jj) { + if ((laneIdx % 2) == validElemThreadIdx) { +#pragma unroll + for (int kk = 0; kk < NumRepeats; ++kk) { +#pragma unroll + for (int mi = 0; mi < 2; ++mi) { + // Index of the acc in the registers array. + int const srcIdx = + ii * NumInstsPerRow * NumRepeats * 4 + jj * NumRepeats * 4 + kk * 4 + mi * 2; + + // Read elem from accs. + auto const elem = reinterpret_cast(&acc)[srcIdx / 2]; + + // Row index in the dst SMEM. + auto const dstRowIdx = + ii * NumInstsPerRow * NumRepeats * 2 + jj * NumRepeats * 2 + mi * NumRepeats + kk; + // Row index in the dst SMEM. + auto const dstColIdx = laneIdx; + // Swizzle column to avoid bank conflicts. + auto const swizzledCol = (dstColIdx ^ (dstRowIdx % numThreadsPerCol)) * 2; + + // Dst indices in the SMEM. + auto const dstIdx = warpIdx * numEltsInSlice + dstRowIdx * numSmemCols + swizzledCol; + + // Saving elements to SMEM. + reinterpret_cast(smemPtr)[dstIdx / 2] = elem; + } + } + } + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Schedule.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Schedule.h new file mode 100644 index 000000000000..2d3d9d94b484 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Schedule.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Structure with all the members from Cutlass counterpart class, to be interchangable with it +struct WorkTileInfo { + int32_t M_idx; + int32_t N_idx; + int32_t L_idx; + bool is_valid_tile; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This schedule applies a simple euristic to make the load more balanced for workers. +// It relies on the observation that there is frequently a pattern of increasing (or decreasing) +// workload size as the flattened blockIdx increases. +// Assigning (workerId + i * numWorkers) at i-th iteration to a worker with ID workerId +// might result in some workers getting much more work than others, thus increasing kernel runtime. +// What we are doing here is alternating direction of worker assignement at each iteration: +// We assign workTile with this flattened blockIdx: +// ((i % 2 == 0) ? workerId : (numWorkers - 1 - workerId)) + i * numWorkers +class StaticScheduler { +public: + __device__ StaticScheduler(int32_t workerId, + int32_t numWorkers, + int32_t maxM, + int32_t maxN, + int32_t maxL) + : mMaxM(maxM) + , mMaxN(maxN) + , mMaxL(maxL) + , mIsEvenStep(true) { + + int32_t divNL = workerId / mMaxM; + mCurrentWorkTileInfo.M_idx = workerId - divNL * mMaxM; + mCurrentWorkTileInfo.L_idx = divNL / mMaxN; + mCurrentWorkTileInfo.N_idx = divNL - mCurrentWorkTileInfo.L_idx * mMaxN; + mCurrentWorkTileInfo.is_valid_tile = mCurrentWorkTileInfo.L_idx < mMaxL; + + int evenStep = numWorkers * 2 - workerId * 2 - 1; + int32_t divNLEvenStep = evenStep / mMaxM; + mEvenStepM = evenStep - divNLEvenStep * mMaxM; + mEvenStepL = divNLEvenStep / mMaxN; + mEvenStepN = divNLEvenStep - mEvenStepL * mMaxN; + + int oddStep = numWorkers * 2 - evenStep; + int32_t divNLOddStep = oddStep / mMaxM; + mOddStepM = oddStep - divNLOddStep * mMaxM; + mOddStepL = divNLOddStep / mMaxN; + mOddStepN = divNLOddStep - mOddStepL * mMaxN; + } + + // Advance to the next work tile. + __device__ void advance_to_next_work() { + mCurrentWorkTileInfo.M_idx += mIsEvenStep ? mEvenStepM : mOddStepM; + mCurrentWorkTileInfo.N_idx += mIsEvenStep ? mEvenStepN : mOddStepN; + mCurrentWorkTileInfo.L_idx += mIsEvenStep ? mEvenStepL : mOddStepL; + if (mCurrentWorkTileInfo.M_idx >= mMaxM) { + mCurrentWorkTileInfo.M_idx -= mMaxM; + mCurrentWorkTileInfo.N_idx++; + } + if (mCurrentWorkTileInfo.N_idx >= mMaxN) { + mCurrentWorkTileInfo.N_idx -= mMaxN; + mCurrentWorkTileInfo.L_idx++; + } + mCurrentWorkTileInfo.is_valid_tile = mCurrentWorkTileInfo.L_idx < mMaxL; + mIsEvenStep = !mIsEvenStep; + } + + // Return the coordinates of the current work tile. + __device__ cute::tuple fetch_next_work(WorkTileInfo) { + advance_to_next_work(); + return cute::make_tuple(mCurrentWorkTileInfo, true); + } + + // Return the coordinates of the 1st work tile. + __device__ WorkTileInfo initial_work_tile_info() { return mCurrentWorkTileInfo; } + +private: + // Logical grid size + int32_t mMaxM, mMaxN, mMaxL; + // How much we need to change each coordinate when advancing to the next work tile, + // separately for even and odd steps. + // They are precomputed to avoid integer division at each advance_to_next_work + int32_t mEvenStepM, mEvenStepN, mEvenStepL; + int32_t mOddStepM, mOddStepN, mOddStepL; + // Is the current step even or odd? + bool mIsEvenStep; + // Coordinates of the current work tile. + WorkTileInfo mCurrentWorkTileInfo; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/SmemTile.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/SmemTile.h new file mode 100644 index 000000000000..ea380a54c87f --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/SmemTile.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "cuda_runtime_api.h" +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// Helper function to manipulate the Smem descriptors for MMAs. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +union SmemDesc { + uint64_t u64; + uint32_t u32[2]; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ uint64_t createSmemDesc(T* smemPtr, uint32_t lo, uint32_t hi) { + // Convert the SMEM address to uint32_t. + uint32_t mask = 0x3ffffu; + uint32_t smemAddr = (static_cast(__cvta_generic_to_shared(smemPtr)) & mask) >> 4; + // Force the compiler to go down the URF path. + // In some rare cases, the compiler does not think smemAddr is uniform, and generates lots of + // conversion between URF and RF. + smemAddr = __shfl_sync(0xffffffff, smemAddr, 0); + // Pack the values into an uint64_t. + SmemDesc tmp; + tmp.u32[0] = smemAddr | lo; + tmp.u32[1] = hi; + + // Return the uint64_t. + return tmp.u64; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ uint64_t +createSmemDesc(T* smemPtr, T* smemPtrNextBuffer, uint32_t lo, uint32_t hi) { + uint32_t maskFull = 0x3ffffu; + uint32_t maskNoLsb = 0x3fff0u; + uint32_t smemAddr = (static_cast(__cvta_generic_to_shared(smemPtr)) & maskFull) >> 4; + uint32_t smemNextBufferAddr = + (static_cast(__cvta_generic_to_shared(smemPtrNextBuffer)) & maskNoLsb) << (16 - 4); + + // Pack the values into an uint64_t. + SmemDesc tmp; + tmp.u32[0] = smemAddr | smemNextBufferAddr; + tmp.u32[1] = hi; + + // Return the uint64_t. + return tmp.u64; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ uint64_t +createSmemDesc(T* smemPtr, int32_t nextBufferOffsetInBytes, uint32_t lo, uint32_t hi) { + // Get the pointer to the next buffer + T* smemPtrNextBuffer = + reinterpret_cast(reinterpret_cast(smemPtr) + nextBufferOffsetInBytes); + // Get the descriptor + return createSmemDesc(smemPtr, smemPtrNextBuffer, lo, hi); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void decrSmemAddr(uint64_t& smemDesc, uint32_t offset) { + SmemDesc tmp; + tmp.u64 = smemDesc; + tmp.u32[0] -= offset; + smemDesc = tmp.u64; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void incrSmemAddr(uint64_t& smemDesc, uint32_t offset) { + SmemDesc tmp; + tmp.u64 = smemDesc; + tmp.u32[0] += offset; + smemDesc = tmp.u64; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void decrSmemNextBufferAddr(uint64_t& smemDesc, uint32_t offset) { + SmemDesc tmp; + tmp.u64 = smemDesc; + tmp.u32[0] -= (offset << 16); + smemDesc = tmp.u64; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void incrSmemNextBufferAddr(uint64_t& smemDesc, uint32_t offset) { + SmemDesc tmp; + tmp.u64 = smemDesc; + tmp.u32[0] += (offset << 16); + smemDesc = tmp.u64; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/SmemTransposer.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/SmemTransposer.h new file mode 100644 index 000000000000..24031b0a1ac9 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/SmemTransposer.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template struct Rows_per_xor_pattern_ampere_b { + // The size in bits. + enum { NInBits = N * BitsPerElementB }; + // The number of rows. + enum { Value = NInBits <= 256 ? 2 : (NInBits <= 512 ? 4 : 8) }; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +static inline __device__ void ldsmt(uint4& dst, uint32_t ptr) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 730 + asm volatile("ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];\n" + : "=r"(dst.x), "=r"(dst.y), "=r"(dst.z), "=r"(dst.w) + : "r"(ptr)); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +static inline __device__ void swizzleRows(uint32_t& a, uint32_t& b, uint32_t c, uint32_t d) { + asm volatile("prmt.b32 %0, %1, %2, 0x6420;\n" : "=r"(a) : "r"(c), "r"(d)); + asm volatile("prmt.b32 %0, %1, %2, 0x7531;\n" : "=r"(b) : "r"(c), "r"(d)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +static inline __device__ void stsm(uint32_t ptr, const uint4& src) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900 + asm volatile("stmatrix.sync.aligned.m8n8.x4.shared.b16 [%0], {%1, %2, %3, %4};\n" ::"r"(ptr), + "r"(src.x), + "r"(src.y), + "r"(src.z), + "r"(src.w)); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Pass these for BMM2: +// TileSizeN - HeadDim +// TileSizeK - TileSizeKv +template +struct SmemTransposer { + + static_assert(TileSizeK % 128 == 0); + static_assert(4 % WarpCount == 0); + + enum { PassCount = 4 / WarpCount }; + + enum { + WarpsM = 4, + WarpsN = 1, + WarpsK = 1, + }; + + enum { + Warps4x1x1 = (WarpsM == 4 && WarpsN == 1 && WarpsK == 1), + Warps4x1x2 = (WarpsM == 4 && WarpsN == 1 && WarpsK == 2), + }; + + enum { BytesPerLds = 16 }; + enum { BytesPerRow = 128 }; + + // D=64 and 4 warps. + // Per warp we load 32 rows x 16 columns with LDSM.Tx4, 128 rows per CTA. + enum { S = TileSizeK >= 128 ? 128 : TileSizeK }; // The sequence length. + enum { D = TileSizeN >= 128 ? 128 : TileSizeN }; // The head dimension. + + // static_assert(S % 128 == 0); + static_assert(Warps4x1x1 || Warps4x1x2); + static_assert(D % (BytesPerLds * WarpsK) == 0); + + enum { RowsPerLdsmPerCtaWithoutPacking = 128 }; // LDSMx4 + enum { RowPacking = BytesPerRow / (D * ByesPerElementB) }; + enum { RowsPerLdsmPerCta = RowsPerLdsmPerCtaWithoutPacking / RowPacking }; + enum { RowsPerXorPattern = Rows_per_xor_pattern_ampere_b::Value }; + static_assert(RowsPerXorPattern == 8); + + // The number of loads in K dimension. + enum { K = S / RowsPerLdsmPerCtaWithoutPacking }; + // static_assert(K * RowsPerLdsmPerCtaWithoutPacking == S); + // static_assert(K == 3); + // The number of loads in the D dimension. + enum { N = D / (BytesPerLds * WarpsK) }; // 16 bytes per load + static_assert(N * BytesPerLds * WarpsK == D); + + uint4 mRegs[UnrollN][K]; + + uint32_t mReadOffsets[PassCount]; + uint32_t mWriteOffsets[PassCount]; + + inline __device__ SmemTransposer(int threadIdx) { + + for (int pass = 0; pass < PassCount; ++pass) { + int tidx = threadIdx + pass * WarpCount * 32; + int readRow, readCol; + + if (Warps4x1x1 && N == 8) { // D=128, 1 warp in N + readRow = (tidx & 0x7f); + readCol = (tidx & 0x07); + } else if (Warps4x1x1 && N == 4) { // D=64, 1 warp in N + readRow = (tidx & 0xe0) / 2 + (tidx & 0x1e) / 2; + readCol = (tidx & 0x01) * 4 + (tidx & 0x06) / 2; + } else if (Warps4x1x1 && N == 2) { // D=32, 1 warp in N + readRow = (tidx & 0x60) / 4 + (tidx & 0x1c) / 4; + readCol = (tidx & 0x03) * 2; + readCol ^= (readRow & 0x01); + } else if (Warps4x1x2 && N == 4) { // D=128, 2 warps in N + readRow = (tidx & 0x7f); + readCol = (tidx & 0x07); + // For two warpgroups we do two steps in N at once. + readCol ^= (tidx & 0x80) / 128; + } else if (Warps4x1x2 && N == 2) { // D=64, 2 warps in N + readRow = (tidx & 0x60) / 2 + (tidx & 0x1e) / 2; + readCol = (tidx & 0x01) * 4 + (tidx & 0x06) / 2; + // For two warpgroups we do two steps in N at once. + readCol ^= (tidx & 0x80) / 128; + } else if (Warps4x1x2 && N == 1) { // D=32, 2 warps in N + readRow = (tidx & 0x60) / 4 + (tidx & 0x1c) / 4; + readCol = (tidx & 0x03) * 2; + readCol ^= (readRow & 0x01); + // For two warpgroups we do two steps in N at once. + readCol ^= (tidx & 0x80) / 128; + } else { + assert(false); + } + + mReadOffsets[pass] = readRow * BytesPerRow + readCol * BytesPerLds; + + int writeRow, writeCol; + if (Warps4x1x1) { // swizzle_128byte + writeRow = (tidx & 0x10) / 2 + (tidx & 0x07); + writeCol = (tidx & 0x60) / 16 + (tidx & 0x08) / 8; + } else if (Warps4x1x2) { + // Same as above, with second warp group writing next 16 rows. + writeRow = (tidx & 0x80) / 8 + (tidx & 0x10) / 2 + (tidx & 0x07); + writeCol = (tidx & 0x60) / 16 + (tidx & 0x08) / 8; + } else { + assert(false); + } + + writeCol ^= (writeRow & 0x07); + + mWriteOffsets[pass] = writeRow * BytesPerRow + writeCol * BytesPerLds; + } + } + + inline __device__ void transpose(const void* smemSrcPtr, void* smemDstPtr) { + uint32_t smemSrc = static_cast(__cvta_generic_to_shared(smemSrcPtr)); + uint32_t smemDst = static_cast(__cvta_generic_to_shared(smemDstPtr)); +#pragma unroll + for (int pass = 0; pass < PassCount; ++pass) { + uint32_t smemReadLoc; + uint32_t smemWriteLoc; +#pragma unroll + for (int n_begin = 0; n_begin < N; n_begin += UnrollN) { + transposeLdMatrix(n_begin, smemSrc, smemReadLoc, mReadOffsets[pass]); + transposeStMatrix(n_begin, smemDst, smemWriteLoc, mWriteOffsets[pass]); + } + } + } + + inline __device__ void transposeLdMatrix(int n_begin, + uint32_t smemSrc, + uint32_t& smemReadLoc, + uint32_t readOffset) { + static_assert(N % UnrollN == 0, ""); + + uint4 tmp[UnrollN][K]; + if (n_begin == 0) { + smemReadLoc = smemSrc + readOffset; + } + +#pragma unroll + for (int ni = n_begin; ni < n_begin + UnrollN; ni++) { + const int nii = ni - n_begin; +#pragma unroll + for (int ki = 0; ki < K; ki++) { // 2 + ldsmt(tmp[nii][ki], smemReadLoc + ki * RowsPerLdsmPerCta * BytesPerRow); + } + + if (Warps4x1x1 && N == 4) { // D=64, 1 warp in N + smemReadLoc ^= (ni % 2 == 0 ? 1 : 3) * 16; + } else if (Warps4x1x1 && N == 2) { // D=32, 1 warp in N + smemReadLoc ^= 16; + } else if (Warps4x1x2 && N == 2) { // D=64, 2 warps in N + smemReadLoc ^= 32; + } else if (Warps4x1x2 && N == 4) { // D=128, 2 warps in N + smemReadLoc ^= (ni % 2 == 0 ? 1 : 3) * 32; + } else if (Warps4x1x1 && N == 8) { // D=128, 1 warp in N + smemReadLoc ^= ((ni % 4 == 3) ? 7 : (ni % 2 == 1 ? 3 : 1)) * 16; + } else if (N != 1) { + assert(false); + } + } + +#pragma unroll + for (int ni = n_begin; ni < n_begin + UnrollN; ni++) { + const int nii = ni - n_begin; +#pragma unroll + for (int ki = 0; ki < K; ki++) { + swizzleRows(mRegs[nii][ki].x, mRegs[nii][ki].z, tmp[nii][ki].x, tmp[nii][ki].y); // PRMT + // 0+1 + swizzleRows(mRegs[nii][ki].y, mRegs[nii][ki].w, tmp[nii][ki].z, tmp[nii][ki].w); // PRMT + // 2+3 + } + } + } + + inline __device__ void transposeStMatrix(int n_begin, + uint32_t smemDst, + uint32_t& smemWriteLoc, + uint32_t writeOffset) { + + // After LDSM.Tx4 registers hold 2x2 elts: + // [00, 01] + // [10, 11] + // With row offsets + // x: + 0 + // y: + 8 + // z: +16 (g) + // w: +24 (o) + // + // After PRMT 0, the : + // [00, 01] [80, 81] => x: [00, 10, 80, 90], i.e. col 0 + // [10, 11] [90, 91] => z: [01, 11, 81, 91], i.e. col 1 + // + // [g0, g1] [o0, o1] => y: [g0, h0, o0, p0], i.e. col 0 + // [h0, h1] [p0, p1] => w: [g1, h1, o1, p1], i.e. col 1 + // + // Therefore, when looking at the transpose, quad q holds cols 2 * q + [0, 1], i.e. + // - quad 0 holds cols 0, 1 + // - quad 1 holds cols 2, 3 + // - etc. + // + // This fits with the accumulator layout, since N strides in steps of 8 per thread. + + if (n_begin == 0) { + smemWriteLoc = smemDst + writeOffset; + } + +#pragma unroll + for (int ni = n_begin; ni < n_begin + UnrollN; ni++) { + const int nii = ni - n_begin; +#pragma unroll + for (int ki = 0; ki < K; ki++) { + stsm(smemWriteLoc + ki * BytesPerRow * D, mRegs[nii][ki]); + } + if (Warps4x1x1) { // D=64, 1 warp in N. + smemWriteLoc += 16 * BytesPerRow; + } else if (Warps4x1x2) { // D=64, 2 warps in N. + smemWriteLoc += 32 * BytesPerRow; + } else { + assert(false); + } + } + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreGmemO.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreGmemO.h new file mode 100644 index 000000000000..379e77f1bd89 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreGmemO.h @@ -0,0 +1,562 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include + +#include "CutlassBarrier.h" +#include "FastMath.h" +#include "StoreSmemP.h" +#include "Fp4Utils.h" +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void copyFromSmemToGmemAndConvertToE2m1(char const* src, + char* dst, + char* dstSf, + float sfScale, + bool isValidRow) { + static_assert(false, "Not implemented."); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> +inline __device__ void copyFromSmemToGmemAndConvertToE2m1<2>(char const* src, + char* dst, + char* dstSf, + float sfScale, + bool isValidRow) { + // Load from SMEM. + auto in = reinterpret_cast(src)[0]; + + // Convert to E2m1. + cutlass::float_e4m3_t sfOut; + uint16_t valOut; + convertFp16ToE2m1<4>(valOut, sfOut, reinterpret_cast(in), sfScale); + // Each group of 4 threads maps to the same SF. + if (isValidRow) { + // Store the output to GMEM. Each group of 4 threads maps to the same SF. + reinterpret_cast(dst)[0] = valOut; + if (threadIdx.x % 4 == 0) { + reinterpret_cast(dstSf)[0] = sfOut; + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template <> +inline __device__ void copyFromSmemToGmemAndConvertToE2m1<4>(char const* src, + char* dst, + char* dstSf, + float sfScale, + bool isValidRow) { + // Load from SMEM. + auto in = reinterpret_cast(src)[0]; + + // Convert to E2m1. + cutlass::float_e4m3_t sfOut; + uint32_t valOut; + convertFp16ToE2m1<8>(valOut, sfOut, reinterpret_cast(in), sfScale); + // Each pair of threads maps to the same SF. + if (isValidRow) { + // Store the output to GMEM. Each pair of threads maps to the same SF. + reinterpret_cast(dst)[0] = valOut; + if (threadIdx.x % 2 == 0) { + reinterpret_cast(dstSf)[0] = sfOut; + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template struct StoreVec { + static inline __device__ void store(char* dstMemPtr, char* srcMemPtr, uint64_t*, int32_t) { + static_assert(false, "Not implemented."); + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template struct StoreVec { + static inline __device__ void store(char* gmemPtr, char* srcMemPtr, uint64_t*, int32_t) { + // The vectorized store. + using VecType = cutlass::AlignedArray; + reinterpret_cast(gmemPtr)[0] = reinterpret_cast(srcMemPtr)[0]; + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template struct StoreVec { + static inline __device__ void store(char* remoteSmemPtr, + char* srcMemPtr, + uint64_t* barrier, + int32_t targetCtaRank) { + // The vectorized store. + using VecType = cutlass::AlignedArray; + // The srcMem vector. + VecType srcMemVec = reinterpret_cast(srcMemPtr)[0]; + // Map the smem barrier and buffer to the lead CTA (0). + barrier = cuda_ptx::mapa(cuda_ptx::space_cluster_t{}, barrier, targetCtaRank); + remoteSmemPtr = cuda_ptx::mapa(cuda_ptx::space_cluster_t{}, remoteSmemPtr, targetCtaRank); + // Store the vector to remote smem. + static_assert(NumRegs <= 4, "Not implemented."); + cuda_ptx::st_async(reinterpret_cast(remoteSmemPtr), + reinterpret_cast(srcMemVec), + barrier); + } +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Vectorized copy from swizzled shared memory to destination memory (global memory or remote shared +// memory). + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void copyFromSmemToDstMem(char* smemPtr, + char* dstMemPtr, + uint64_t* transactionBarrier, + int32_t baseOffset, + int32_t dstMemRowStrideInBytes, + int32_t numValidRows, + int32_t numReductionRowsPerCta, + int32_t numHeadsQ, + trtllm::dev::fast_mod_div numHeadsQPerKv, + char* dstMemSf = nullptr, + float sfScale = 0.f, + int32_t sfBaseRowIdx = 0) { + // The number of bytes per row in smem. + // The leading dimension of smem will be split into multiple slices if it exceeds 128B. + int32_t constexpr NumBytesPerSmemRow{std::min(NumBytesPerRow, 128)}; + // The number of bytes per row in dstMem. + int32_t constexpr NumBytesPerDstMemRow{NumBytesPerRow}; + // Each thread loads one 16B vector from shared memory, and stores it to global memory. + int32_t constexpr NumBytesPerVec{16}; + // The number of packed rows for swizzling. + int32_t constexpr NumPackedSmemRows{128 / NumBytesPerSmemRow}; + + // Calculate the shared memory offset. + int32_t const smemRowIdx{baseOffset / NumBytesPerSmemRow}; + // There will be 8 swizzle rows considering packed rows. + int64_t const loadSmemOffset{baseOffset ^ + (((smemRowIdx / NumPackedSmemRows) % 8) * NumBytesPerVec)}; + + // The destination memory row index. + int32_t dstMemRowIdx{smemRowIdx}; + // The destination memory column offset. + int32_t dstMemColOffset{(baseOffset % NumBytesPerSmemRow)}; + + // The leading dimension will be split into multiple slices if it exceeds 128B. + // The smem shape [NumLeadingDimSlices, NumRows, NumBytesPerSmemRow]. + if constexpr (NumBytesPerDstMemRow > 128) { + dstMemRowIdx = smemRowIdx % NumRows; + dstMemColOffset = + (smemRowIdx / NumRows) * NumBytesPerSmemRow + (baseOffset % NumBytesPerSmemRow); + } + + // Whether the row is valid. + bool isValidRow = dstMemRowIdx < numValidRows; + + // Copy from shared memory to global memory. + if constexpr (CastToE2m1) { + + // + // Store the SFs in Layout128x4 (see trtllm/gen/DtypeUtils.h for details). + // All elements in the tile [numHeadsQPerKv (row), headDim (col)] are mapped to the col + // dimension of SFs. + // + + // Assume elements are stored in SMEM as FP16. + int32_t constexpr NumBytesPerFp16Elt = 2; + // The number of E2m1 elements packed in a byte. + int32_t constexpr NumE2m1EltsPerByte = 2; + // The number of elements per sf. + int32_t constexpr NumEltsPerSf = 16; + // The number of cols of SF per block. + int32_t constexpr NumColsPerSfBlock = 4; + // The size of each SF block. + int32_t constexpr NumBytesPerSfBlock = 512; + + // The offset to store the SF values. + int64_t dstMemSfOffset; + + // When grouping tokens and headsQ, unpack the row into (tokenIdx, headIdxInGrp) + // and use getSfOffset with absolute indices for correct Layout128x4 mapping. + if constexpr (MapRowToHeadTokenIdx) { + // The token index. + int32_t tokenIdx{dstMemRowIdx / numHeadsQPerKv}; + // The head index in the group. + int32_t headIdxInGrp{dstMemRowIdx % numHeadsQPerKv}; + // The new row index after unpacking. + dstMemRowIdx = headIdxInGrp + tokenIdx * numHeadsQ; + // The local SF column index. + int32_t localSfCol{dstMemColOffset / NumBytesPerFp16Elt / NumEltsPerSf}; + // The SF column index. + int32_t sfHeadCol{headIdxInGrp * NumSfPerHead}; + // The number of SFs per row. + int32_t numSfPerRow{numHeadsQ * NumSfPerHead}; + // The offset to store the SF values. + dstMemSfOffset = getSfOffset(sfBaseRowIdx + tokenIdx, sfHeadCol + localSfCol, numSfPerRow); + } else { + // Without MapRowToHeadTokenIdx, all rows share the same head and the SF column + // is simply derived from the column offset. The dstMemSf pointer already accounts + // for the base head and token offsets. + auto sfColIdx = dstMemColOffset / NumBytesPerFp16Elt / NumEltsPerSf; + dstMemSfOffset = dstMemRowIdx * RowStrideSf + + sfColIdx / NumColsPerSfBlock * NumBytesPerSfBlock + + sfColIdx % NumColsPerSfBlock; + } + + // Compute data destination offset. + int64_t dstMemOffset{dstMemRowIdx * static_cast(dstMemRowStrideInBytes) + + dstMemColOffset}; + dstMemOffset = dstMemOffset / NumBytesPerFp16Elt / NumE2m1EltsPerByte; + + copyFromSmemToGmemAndConvertToE2m1(smemPtr + loadSmemOffset, + dstMemPtr + dstMemOffset, + dstMemSf + dstMemSfOffset, + sfScale, + isValidRow); + } else { + // If it groups both headsQ and tokensQ into one CTA, we need to unpack the row index to the + // valid range if values are stored to finalO. + if constexpr (MapRowToHeadTokenIdx) { + dstMemRowIdx = (dstMemRowIdx % numHeadsQPerKv) + (dstMemRowIdx / numHeadsQPerKv) * numHeadsQ; + } + + // The destination memory offset. + int64_t dstMemOffset{dstMemRowIdx * static_cast(dstMemRowStrideInBytes) + + dstMemColOffset}; + + // If the CGA reduction is used, we store the output to remote smem. + int32_t targetCtaRank = 0; + if constexpr (StoreToRemoteSmem) { + targetCtaRank = dstMemRowIdx / numReductionRowsPerCta; + int32_t remoteSmemRowIdx = dstMemRowIdx % numReductionRowsPerCta; + dstMemOffset = + remoteSmemRowIdx * static_cast(dstMemRowStrideInBytes) + dstMemColOffset; + } + + if (isValidRow) { + // The destination in GMEM/Remote SMEM. + dstMemPtr += dstMemOffset; + // The source in SMEM. + smemPtr += loadSmemOffset; + // Create a vectorized store. + StoreVec::store(dstMemPtr, + smemPtr, + transactionBarrier, + targetCtaRank); + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Vectorized copy from registers to destination memory (global memory or remote shared memory). + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeVec(T* dstMemPtr, uint32_t (&srcVecs)[NumRegs]) { + + // Create a vectorized store. + StoreVec::store(reinterpret_cast(dstMemPtr), + reinterpret_cast(srcVecs), + nullptr, + 0); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeVecToRemoteSmem(T* dstMemPtr, + uint32_t (&srcVecs)[NumRegs], + Barrier* transactionBarrier, + int32_t targetCtaRank) { + + // Create a vectorized store. + StoreVec::store(reinterpret_cast(dstMemPtr), + reinterpret_cast(srcVecs), + transactionBarrier->getBarrierPtr(), + targetCtaRank); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Reorganize data in shared memory for coalesced memory store to global memory. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reorganizeInSmemAndStoreToDstMemImpl_( + DtypeO* smemPtrO, + void* dstMemPtrO, + uint64_t* transactionBarrier, + uint32_t (&arrayO)[NumRegs], + int32_t dstMemRowStride, + int32_t numValidTokens, + int32_t numReductionRowsPerCta, + int32_t numHeadsQ, + trtllm::dev::fast_mod_div numHeadsQPerKv, + int32_t numWarpGrpThreads, + int32_t warpGrpThreadIdx, + int32_t namedBarId, + cutlass::float_e4m3_t* dstMemPtrOSf = nullptr, + float sfScale = 0.f, + int32_t sfBaseRowIdx = 0) { + + static_assert((NumRegs & (NumRegs - 1)) == 0, "Not implemented."); + + // The allowed data types. + static_assert(std::is_same_v || + std::is_same_v || + std::is_same_v, + "Not implemented."); + static_assert(!CastToE2m1 || std::is_same_v, + "DtypeO should be Fp16 if cast to E2M1."); + + // The number of rows and cols after transposing. + int32_t constexpr NumTransRows{NumCols}; + // Assume that each warp in the warpgroup (4 warps in total) stores 16/32 transposed columns. + int32_t constexpr NumTransCols{NumRows}; + // Only 64 or 128 transposed columns are allowed. + static_assert(NumTransCols == 64 || NumTransCols == 128, "Not implemented."); + // The number of transposed rows must be power of 2 and greater than or equal to 8. + static_assert(NumTransRows >= 8 && (NumTransRows & (NumTransRows - 1)) == 0, "Not implemented."); + + // Whether or not to force 16B transactions. + bool constexpr Force16B{true}; + // The maxiumum number of registers per copy per thread. + int32_t constexpr MaxNumRegsPerCopy{4}; + // The required number of registers per copy. + int32_t constexpr RequiredNumRegsPerCopy{std::min(NumRegs, MaxNumRegsPerCopy)}; + // The number of copy calls. + int32_t constexpr NumCopyCalls{NumRegs / RequiredNumRegsPerCopy}; + // The number of registers per copy to actually use. + int32_t constexpr NumRegsPerCopy{Force16B ? MaxNumRegsPerCopy : RequiredNumRegsPerCopy}; + // The number of bytes per copy. + int32_t constexpr NumBytesPerCopy{NumRegsPerCopy * 4}; + // The portion of threads participating in the write + int32_t constexpr ThreadsToUse{NumRegsPerCopy / RequiredNumRegsPerCopy}; + + // The number of bytes per element. + int32_t constexpr NumBytesPerElt{sizeof(DtypeO)}; + + // The base smem/dstMem pointer in char. + char* const baseSmemPtr{reinterpret_cast(smemPtrO)}; + char* const baseDstMemPtr{reinterpret_cast(dstMemPtrO)}; + + // The dstMem row stride in bytes. + int32_t dstMemRowStrideInBytes{dstMemRowStride * NumBytesPerElt}; + + // Store transposed tensor to smem (NumRows = 128). + if constexpr (std::is_same_v) { + storeTransposedSmem8b(smemPtrO, arrayO, warpGrpThreadIdx); + } else if constexpr (NumTransCols == 128) { + storeTransposedSmem128x16b(smemPtrO, arrayO, warpGrpThreadIdx); + } else { + storeTransposedSmem64x16b(smemPtrO, arrayO, warpGrpThreadIdx); + } + // Sync the threads in the warpgroup. + trtllm::dev::CutlassNamedBarrier::sync(numWarpGrpThreads, namedBarId); + + // Multiple copy instructions are needed if there are more than one 16B vec per thread. + for (int32_t ii = 0; ii < NumCopyCalls; ++ii) { + // The base offset for each thread. + // Each thread copies at most 16B. + int32_t const baseOffset{warpGrpThreadIdx * NumBytesPerCopy + + ii * numWarpGrpThreads * NumBytesPerCopy}; + + // Copy from smem to dstMem. + copyFromSmemToDstMem(baseSmemPtr, + baseDstMemPtr, + transactionBarrier, + baseOffset, + dstMemRowStrideInBytes, + numValidTokens, + numReductionRowsPerCta, + numHeadsQ, + numHeadsQPerKv, + reinterpret_cast(dstMemPtrOSf), + sfScale, + sfBaseRowIdx); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reorganizeInSmemAndStoreToDstMem(DtypeO* smemPtrO, + void* dstMemPtrO, + uint32_t (&arrayO)[NumRegs], + int32_t dstMemRowStride, + int32_t numValidTokens, + int32_t numHeadsQ, + trtllm::dev::fast_mod_div numHeadsQPerKv, + int32_t numWarpGrpThreads, + int32_t warpGrpThreadIdx, + int32_t namedBarId) { + reorganizeInSmemAndStoreToDstMemImpl_(smemPtrO, + dstMemPtrO, + nullptr, + arrayO, + dstMemRowStride, + numValidTokens, + numValidTokens, + numHeadsQ, + numHeadsQPerKv, + numWarpGrpThreads, + warpGrpThreadIdx, + namedBarId); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reorganizeInSmemAndStoreToDstMem(DtypeO* smemPtrO, + void* dstMemPtrO, + Barrier* transactionBarrier, + uint32_t (&arrayO)[NumRegs], + int32_t dstMemRowStride, + int32_t numValidTokens, + int32_t numReductionRowsPerCta, + int32_t numHeadsQ, + trtllm::dev::fast_mod_div numHeadsQPerKv, + int32_t numWarpGrpThreads, + int32_t warpGrpThreadIdx, + int32_t namedBarId) { + static_assert(!MapRowToHeadTokenIdx, "MapRowToHeadTokenIdx should be false for this function."); + reorganizeInSmemAndStoreToDstMemImpl_(smemPtrO, + dstMemPtrO, + transactionBarrier->getBarrierPtr(), + arrayO, + dstMemRowStride, + numValidTokens, + numReductionRowsPerCta, + numHeadsQ, + numHeadsQPerKv, + numWarpGrpThreads, + warpGrpThreadIdx, + namedBarId); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void reorganizeInSmemAndStoreToDstMemAsE2m1( + DtypeO* smemPtrO, + void* dstMemPtrO, + uint32_t (&arrayO)[NumRegs], + int32_t dstMemRowStride, + int32_t numValidTokens, + int32_t numHeadsQ, + trtllm::dev::fast_mod_div numHeadsQPerKv, + int32_t numWarpGrpThreads, + int32_t warpGrpThreadIdx, + int32_t namedBarId, + cutlass::float_e4m3_t* dstMemPtrOSf, + float sfScale, + int32_t sfBaseRowIdx = 0) { + + reorganizeInSmemAndStoreToDstMemImpl_(smemPtrO, + dstMemPtrO, + static_cast(nullptr), + arrayO, + dstMemRowStride, + numValidTokens, + numValidTokens, + numHeadsQ, + numHeadsQPerKv, + numWarpGrpThreads, + warpGrpThreadIdx, + namedBarId, + dstMemPtrOSf, + sfScale, + sfBaseRowIdx); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreSmemOut.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreSmemOut.h new file mode 100644 index 000000000000..786ffa78cba9 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreSmemOut.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeToSmemOut(T* smemPtr, + int warpGrpThreadIdx, + uint32_t const (®sOut)[NumRegs]) { + + // The number of regs cannot exceed 32 per thread (a thread writes to at most one 128B SMEM row). + static_assert(NumRegs <= 32, "Too many registers per thread"); + // The number of registers must be a multiple of 4 as we want to use STS.128. + static_assert(NumRegs % 4 == 0, "Must be a multiple of 4"); + // The number of registers must be a power of 2. + static_assert((NumRegs & (NumRegs - 1)) == 0, "Must be a power of 2"); + + // The number of threads per SMEM row (128B per row). + int constexpr NumThreadsPerSmemRow = 32 / NumRegs; + // The number of SMEM rows per swizzle block. + int constexpr NumSmemRowsPerSwizzleBlk = 8 / NumThreadsPerSmemRow; + + // To match CuTe, we apply the XOR on the address (not just the row as in XMMA). + + // The pointer as an UINT32. + uint32_t smemPtrU32 = static_cast(__cvta_generic_to_shared(smemPtr)); + // The offset of the thread. + uint32_t smemOffset = smemPtrU32 + warpGrpThreadIdx * NumRegs * 4 /*numBytesPerReg*/; + // The row. + uint32_t smemRow = smemOffset / 128 /*numBytesPerSmemRow*/; + // The XOR mask. + uint32_t smemXorMask = smemRow % NumSmemRowsPerSwizzleBlk * 16 /*numBytesPerXor*/; + + // Store the elements using STS.128. +#pragma unroll + for (int ii = 0; ii < NumRegs; ii += 4) { + // The destination pointer. + uint32_t dstPtr = (smemOffset + ii * 4 /*numBytesPerReg*/) ^ smemXorMask; + // Write to SMEM using STS.128. + asm volatile("st.shared.v4.u32 [%0], {%1, %2, %3, %4};\n" ::"r"(dstPtr), + "r"(regsOut[ii + 0]), + "r"(regsOut[ii + 1]), + "r"(regsOut[ii + 2]), + "r"(regsOut[ii + 3])); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void loadFromSmemOut(uint32_t (®sOut)[4], T* smemPtr, int warpGrpThreadIdx) { + + // To match CuTe, we apply the XOR on the address (not just the row as in XMMA). + + // The pointer as an UINT32. + uint32_t smemPtrU32 = static_cast(__cvta_generic_to_shared(smemPtr)); + // The position of the 1st element loaded using LDS.128 for each thread. + uint32_t smemOffset = smemPtrU32 + warpGrpThreadIdx * 16 /*numBytesPerLds128*/; + // The row. + uint32_t smemRow = smemOffset / 128 /*numBytesPerSmemRow*/; + // The XOR mask. + uint32_t smemXorMask = smemRow % NumSmemRowsPerSwizzleBlk * 16 /*numBytesPerXor*/; + + // Load from SMEM using LDS.128. + asm volatile("ld.shared.v4.u32 {%0, %1, %2, %3}, [%4];\n" + : "=r"(regsOut[0]), "=r"(regsOut[1]), "=r"(regsOut[2]), "=r"(regsOut[3]) + : "r"(smemOffset ^ smemXorMask)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreSmemP.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreSmemP.h new file mode 100644 index 000000000000..c3cb88f0eadc --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/StoreSmemP.h @@ -0,0 +1,503 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// STSM 8b functions to store transposed 16 (rows) x 8 (cols) to shared memory. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void storeTrans8bMatrix(uint32_t* smemDst, uint32_t const (&src)[1]) { +#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)) + asm volatile("stmatrix.sync.aligned.m16n8.x1.trans.shared.b8 [%0], {%1};\n" ::"l"(smemDst), + "r"(src[0])); +#else + static_assert(false, "Not implemented."); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void storeTrans8bMatrix(uint32_t* smemDst, uint32_t const (&src)[2]) { +#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)) + asm volatile("stmatrix.sync.aligned.m16n8.x2.trans.shared.b8 [%0], {%1, %2};\n" ::"l"(smemDst), + "r"(src[0]), + "r"(src[1])); +#else + assert(false && "Not implemented."); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void storeTrans8bMatrix(uint32_t* smemDst, uint32_t const (&src)[4]) { +#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)) + asm volatile( + "stmatrix.sync.aligned.m16n8.x4.trans.shared.b8 [%0], {%1, %2, %3, %4};\n" ::"l"(smemDst), + "r"(src[0]), + "r"(src[1]), + "r"(src[2]), + "r"(src[3])); +#else + assert(false && "Not implemented."); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This function stores 64/128 rows x 8/16 cols to shared memory with transpose. +// +// The function assumes that the data is distributed amongst the threads after loading from TMEM +// using the LDTM.16dp256bit instructions. +// +// Distribution of threads: +// +// Row ..0: ..0 ..1 ..2 ..3 +// Row ..1: ..4 ..5 ..6 ..7 +// Row ..2: ..8 ..9 .10 .11 +// Row ..3: .12 .13 .14 .15 +// Row ..4: .16 .17 .18 .19 +// Row ...: ... +// Row ..7: .28 .29 .30 .31 +// Row ..8: .32 .33 .34 .35 +// Row ...: ... +// Row .31: 124 125 126 127 +// +// Distribution of values (even if it does not matter too much). The indices in the following dia- +// gram are the indices of the thread owners. +// +// Row ..0: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..1: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ..2: ..8 ..8 ..9 ..9 .10 .10 .11 .11 +// Row ..3: .12 .12 .13 .13 .14 .14 .15 .15 +// Row ..4: .16 .16 .17 .17 .18 .18 .19 .19 +// Row ...: ... ... +// Row ..7: .28 .28 .29 .29 .30 .30 .31 .31 +// Row ..8: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row ..9: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .16: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .17: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .24: ..0 ..0 ..1 ..1 ..2 ..2 ..3 ..3 +// Row .25: ..4 ..4 ..5 ..5 ..6 ..6 ..7 ..7 +// Row ...: ... ... +// Row .32: .32 .32 .33 .33 .34 .34 .35 .35 +// Row ...: ... ... +// Row .64: .64 .64 .65 .65 .66 .66 .67 .67 +// Row ...: ... ... +// Row .96: .96 .96 .97 .97 .98 .98 .99 .99 +// Row ...: ... ... +// Row 127: 124 124 125 125 126 126 127 127 +// +// Distribution of values in each thread. Every 4 contiguous values will be packed as one uint32_t. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeTransposedSmem8b(cutlass::float_e4m3_t* smemPtr, + uint32_t const (®sP)[NumRegs], + int32_t warpGrpThreadIdx) { + + // Make sure NumRows is power of 2 and greater than or equal to 8. + static_assert(NumRows >= 8 && (NumRows & (NumRows - 1)) == 0, "Not implemented."); + // Make sure we have 64 or 128 cols after transposition. + static_assert(NumCols == 64 || NumCols == 128, "Not implemented."); + + // The number of warps per warp-group. + int32_t constexpr NumWarps{4}; + // The number of bytes per row after transposing. + int32_t constexpr NumBytesPerRow{NumCols}; + // The number of rows packed in 128B. + int32_t constexpr NumRowsPer128B{128 / NumBytesPerRow}; + // The number of 16B segments per warp and per row after transposing. + int32_t constexpr NumSegsPerWarpPerRow{NumBytesPerRow / 16 / NumWarps}; + + // The warp in the warp-group. + int32_t const warpIdx{warpGrpThreadIdx / 32}; + // The lane in the warp-group. + int32_t const laneIdx{warpGrpThreadIdx % 32}; + + // Each "repeat" of the STSM instruction stores 8x segments of 16B. For the 1st repeat, the + // threads 0-7 bring the addresses of the first 8 segments (one address per thread). For the 2nd + // repeat, the threads 8-15 are responsible for the addresses of the 8 segments. And so on, ... + + // The number of STSM instructions where each STSM instruction writes at most 16 x 128 fp8 + // elements. + int32_t constexpr NumStsmInsts{std::max(NumRows * NumCols / (16 * 128), 1)}; + // The number of registers per STSM instruction. + static_assert(NumRegs % NumStsmInsts == 0, "Not supported"); + int32_t constexpr NumRegsPerStsm{NumRegs / NumStsmInsts}; + // The number of STSM instructions per row where each STSM instruction processes at most 32 rows. + int32_t constexpr NumStsmPerRow{std::max(NumRows / 32, 1)}; + // The number of transposed STSM.MT168 matrices per col. Each transposed matrix has 8 rows. + int32_t constexpr NumMtxPerCol{NumRows / 8}; + // Each STSM.MT168 matrix is handled by 8 threads. + int32_t const mtxIdx{laneIdx / 8}; + // The position of the matrix in the column. The matrices are stored column-major. + int32_t const mtxRowIdx{mtxIdx % NumMtxPerCol}; + // The position of the matrix in the row. + int32_t const mtxColIdx{mtxIdx / NumMtxPerCol}; + // After transposition, each warp handles all the elements of its "assigned" columns. + int32_t const thrRowIdx{laneIdx % 8}; +// Iterate over the STSM instructions. +// The STSM instruction will process row matrices first and then column matrices in order +// to align with ldtm.16dp256bit instructions. +// When NumRows = 16 NumCols = 128, it will process 2 row x 2 column matrices with one instruction. +// When NumRows >= 32, it will process 4 row x 1 column matrices with one instruction. +#pragma unroll + for (int32_t stsmIdx = 0; stsmIdx < NumStsmInsts; ++stsmIdx) { + + // The STSM instruction will process row matrices first and then column matrices + int32_t const stsmRowIdx = stsmIdx % NumStsmPerRow; + int32_t const stsmColIdx = stsmIdx / NumStsmPerRow; + + // The XOR mask. + int32_t const xorMask = thrRowIdx / NumRowsPer128B; + // Swizzle the offsets based on the swizzle mode. + int32_t const segColIdx = (warpIdx * NumSegsPerWarpPerRow + mtxColIdx + stsmColIdx) ^ xorMask; + + // Assemble the final offset after swizzling. + int smemOffset = + (mtxRowIdx * 8 + thrRowIdx + stsmRowIdx * 32) * NumBytesPerRow + segColIdx * 16; + // Call the STSM instruction. + storeTrans8bMatrix( + reinterpret_cast(smemPtr + smemOffset), + reinterpret_cast(regsP)[stsmIdx]); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// STSM 16b functions to store transposed 8 (rows) x 8 (cols) to shared memory. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void storeTrans16bMatrix(uint32_t* smemDst, uint32_t const (&src)[2]) { +#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900)) + asm volatile("stmatrix.sync.aligned.x2.trans.m8n8.shared.b16 [%0], {%1, %2};\n" ::"l"(smemDst), + "r"(src[0]), + "r"(src[1])); +#else + static_assert(false, "Not implemented."); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void storeTrans16bMatrix(uint32_t* smemDst, uint32_t const (&src)[4]) { +#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900)) + asm volatile( + "stmatrix.sync.aligned.x4.trans.m8n8.shared.b16 [%0], {%1, %2, %3, %4};\n" ::"l"(smemDst), + "r"(src[0]), + "r"(src[1]), + "r"(src[2]), + "r"(src[3])); +#else + static_assert(false, "Not implemented."); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This function stores 64 rows x 8/16 cols to shared memory with transpose. +// +// The function assumes that the data is distributed amongst the threads after loading from TMEM +// using the LDTM.16dp256bit instructions. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeTransposedSmem64x16b(Dtype* smemPtr, + uint32_t const (®sP)[NumRegs], + int32_t warpGrpThreadIdx) { + + // Make sure NumRows is power of 2 and greater than or equal to 8. + static_assert(NumRows >= 8 && (NumRows & (NumRows - 1)) == 0, "Not implemented."); + + + // The number of cols after transposing. + int32_t constexpr NumCols{64}; + + // The number of warps per warp-group. + int32_t constexpr NumWarps{4}; + // The number of bytes per row after transposing. + int32_t constexpr NumBytesPerRow{NumCols * sizeof(uint16_t) /*64*2 = 128B*/}; + + // The warp in the warp-group. + int32_t const warpIdx{warpGrpThreadIdx / 32}; + // The lane in the warp-group. + int32_t const laneIdx{warpGrpThreadIdx % 32}; + + // After each repeat of LDTM.16dp256bit (when copying data from TMEM to registers in TmemS), each + // thread owns two consecutive columns in Reg0 and Reg1 from the same row and two consecutive + // columns in Reg2 and Reg3 from another row (there are 8 rows between those two rows). For exam- + // ple threads 0, 1, 2 and 3 resp. holds columns 0-1, 2-3, 4-5 and 6-7 from rows 0 and 8. Threads + // 4-7 have the same columns from rows 1 and 9. See LDTM documentation for details. The values + // are FP32 values. + // + // In TmemP, the 4x FP32 values (per LDTM repeat) are converted to FP16 and packed into 2 regis- + // ters (Reg0 and Reg1 are converted and packed into a first register - Reg2 and Reg3 go to + // another one). The 1st two STSM repeats will produce 16 columns of the same row in SMEM after + // transposition. Since there are 64 columns and 4 warps. Each warp writes 2 matrices per row. + int32_t constexpr NumMtxPerRow{2}; + + // The number of STSM instructions, where each STSM instruction can at most write 16 rows. + int32_t constexpr NumStsmInsts{std::max(NumRows / 16, 1)}; + // The number of registers per STSM instruction. + static_assert(NumRegs % NumStsmInsts == 0, "Not supported"); + int32_t constexpr NumRegsPerStsm{NumRegs / NumStsmInsts}; + + // Each STSM.MT88 matrix is handled by 8 threads. + int32_t const mtxIdx{laneIdx / 8}; + // The position of the matrix in the col (after transposition). Matrices are stored row-major. + int32_t const mtxRowIdx{mtxIdx / NumMtxPerRow}; + // The position of the matrix in the row. + int32_t const mtxColIdx{mtxIdx % NumMtxPerRow}; + + // After transposition, each warp handles all the elements of its "assigned" columns. + int32_t const thrRowIdx{laneIdx % 8}; + + // The XOR mask (for SWIZZLE_128B). + int32_t const xorMask = thrRowIdx; + // Swizzle the offsets based on the swizzle mode. + int32_t const segColIdx = (warpIdx * NumMtxPerRow + mtxColIdx) ^ xorMask; + + // The base smem pointer in bytes. + char* const smemPtrBytes{reinterpret_cast(smemPtr)}; + +// Iterate over the STSM instructions where each STSM instruction writes at most 16 rows. +#pragma unroll + for (int32_t stsmIdx = 0; stsmIdx < NumStsmInsts; ++stsmIdx) { + // Assemble the final offset after swizzling. + int smemOffset = (mtxRowIdx * 8 + thrRowIdx + stsmIdx * 16) * NumBytesPerRow + segColIdx * 16; + // Call the STSM instruction. + auto regsPArray = reinterpret_cast(®sP[0]); + storeTrans16bMatrix(reinterpret_cast(smemPtrBytes + smemOffset), + regsPArray[stsmIdx]); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// This function stores 128 rows x (8 * numLdtmReps) cols to shared memory with transpose. +// +// The function assumes that the data is distributed amongst the threads after loading from TMEM +// using the LDTM.16dp256bit instructions. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void storeTransposedSmem128x16b(Dtype* smemPtr, + uint32_t const (®sP)[NumRegs], + int32_t warpGrpThreadIdx) { + + // Make sure NumRows is power of 2 and greater than or equal to 8. + static_assert(NumRows >= 8 && (NumRows & (NumRows - 1)) == 0, "Not implemented."); + + + // The number of cols after transposing. + int32_t constexpr NumCols{128}; + + // The warp in the warp-group. + int32_t const warpIdx{warpGrpThreadIdx / 32}; + // The lane in the warp-group. + int32_t const laneIdx{warpGrpThreadIdx % 32}; + + // Since a transposed row has 128 columns of 16-bit elements, it occupies 256B. That's more than + // the 128B per row limit per slice in SMEM. So, a transposed row spans two slices. For that + // reason, we decompose the warp-group into 2 groups of 2 warps. Warps 0-1 write to the 1st slice + // and warps 2-3 write to the 2nd slice. + + // The slice written by the warp. + int32_t const sliceIdx{warpIdx / 2}; + // The warp index in the slice. + int32_t const warpIdxInSlice{warpIdx % 2}; + + // After each repeat of LDTM.16dp256bit (when copying data from TMEM to registers in TmemS), each + // thread owns two consecutive columns in Reg0 and Reg1 from the same row and two consecutive + // columns in Reg2 and Reg3 from another row (there are 8 rows between those two rows). For exam- + // ple threads 0, 1, 2 and 3 resp. holds columns 0-1, 2-3, 4-5 and 6-7 from rows 0 and 8. Threads + // 4-7 have the same columns from rows 1 and 9. See LDTM documentation for details. The values + // are FP32 values. + // + // In TmemP, the 4x FP32 values (per LDTM repeat) are converted to FP16 and packed into 2 regis- + // ters (Reg0 and Reg1 are converted and packed into a first register - Reg2 and Reg3 go to + // another one). The 1st two STSM repeats will produce 16 columns of the same row in SMEM after + // transposition. + // + // Unfortunately, to make things harder, each LDTM repeat is in row-dimension of TMEM. It means + // that when we have more than one LDTM repeat, the next block of 4 registers from LDTM corres- + // ponds to another set of rows in the transposed matrix in SMEM (columns 8-15 in TMEM map to + // rows 8-15 in SMEM after the transposition). It means that if we have 2 LDTM repeats, each + // STSM will write two matrices per column of SMEM (i.e. 16 rows). + // It explains why the below code is a little bit more complicated than we would have liked. + + // The number of LDTM repeats, and each repeat needs one STSM.MT88.x4 instruction. + int32_t constexpr NumLdtmReps{NumRows / 8}; + // The number of rows must be a multiple of 8. + static_assert(NumRows % 8 == 0, "Not supported"); + + // + // Each STSM instruction can write 4 matrices and it will be reshaped differently based on the + // number of LDTM repeats. + // + + // The number of matrices per row in SMEM per STSM (i.e. block of 4 registers). + int32_t constexpr NumMtxPerRowPerStsm{NumLdtmReps == 1 ? 4 : 2}; + // The number of matrices per col in SMEM per STSM (i.e. block of 4 registers). + int32_t constexpr NumMtxPerColPerStsm{NumLdtmReps == 1 ? 1 : 2}; + // Make sure the number of row*col is 4. + static_assert(NumMtxPerRowPerStsm * NumMtxPerColPerStsm == 4); + + // The number of STSM instructions per row after transposition (32 columns per warp, i.e. 4 + // matrices). + int32_t constexpr NumStsmPerRow{4 / NumMtxPerRowPerStsm}; + // The number of STSM instructions per col after transposition. + int32_t constexpr NumStsmPerCol{std::max(NumLdtmReps / NumMtxPerColPerStsm, 1)}; + + // The number of registers per STSM instruction. + static_assert(NumRegs % (NumStsmPerRow * NumStsmPerCol) == 0, "Not supported"); + int32_t constexpr NumRegsPerStsm{NumRegs / (NumStsmPerRow * NumStsmPerCol)}; + + // Each STSM.MT88 matrix is handled by 8 threads. + int32_t const mtxIdx{laneIdx / 8}; + // The position of the matrix in the col (after transposition). + int32_t const mtxRowIdx{mtxIdx / NumMtxPerRowPerStsm}; + // The position of the matrix in the row. Each warp stores 4 matrices per row (4x16 cols/warp). + int32_t const mtxColIdx{(warpIdxInSlice * 4) + (mtxIdx % NumMtxPerRowPerStsm)}; + // After transposition, each warp handles all the elements of its "assigned" columns. + int32_t const thrRowIdx{laneIdx % 8}; + + // The number of bytes per row. + int32_t constexpr NumBytesPerRow{128}; + // The offset to the slice in SMEM. + int32_t const sliceOffset{sliceIdx * NumRows * NumBytesPerRow}; + // The offset to the row in the slice in SMEM. + int32_t const rowOffset{(mtxRowIdx * 8 + thrRowIdx) * NumBytesPerRow}; + +// Each STSM corresponds to one LDTM. +#pragma unroll + for (int32_t ii = 0; ii < NumStsmPerRow; ++ii) { + +#pragma unroll + for (int32_t jj = 0; jj < NumStsmPerCol; ++jj) { + + // The XOR mask (for SWIZZLE_128B). + int32_t const xorMask = thrRowIdx; + // Swizzle the offsets based on the swizzle mode. + int32_t const segColIdx = (mtxColIdx + ii * NumMtxPerRowPerStsm) ^ xorMask; + + // The row offset of the current STSM instruction. + int32_t stsmRowOffset = jj * NumMtxPerColPerStsm * 8 * NumBytesPerRow; + + // The base smem pointer in char. + char* const smemPtrBytes{reinterpret_cast(smemPtr)}; + // Assemble the final offset after swizzling. + int smemOffset{sliceOffset + rowOffset + stsmRowOffset + segColIdx * 16}; + // The dst pointers as UInt32. + auto dstU32 = reinterpret_cast(smemPtrBytes + smemOffset); + // Call the STSM instruction. + auto regsPArray = reinterpret_cast(®sP[0]); + storeTrans16bMatrix(dstU32, regsPArray[ii * NumStsmPerCol + jj]); + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// P is stored in shared memory. Within a warp-group (4 warps), each warp stores 32 rows. For each +// row, the elements are packed into NumU32s uint32s. When the total size per row exceeds 128B, +// multiple SMEM rows are used to store the elements. The usual swizzling is used for storing the +// elements in SMEM. +template +inline __device__ void storeWarpGrp2x2SmemP(uint32_t* smemDst, + uint32_t const (&src)[NumU32s], + int mWarpGrpThreadIdx) { + // + // The 2x2 warp-group layout. + // + // warp0 warp2 + // warp1 warp3 + // + // Note that if we split the K dimension of P into 2 partitions (NumKPartitionsMmaPv = 2), warp2 + // and warp3 naturally store values to the 2nd partition of P. Each partition will swizzle its own + // values based on the size of its K dimension. This is aligned with how we generate the BMM2 + // codes in TmemO.h. + + // NumKPartitionsMmaPv must be 1 or 2. + static_assert(NumKPartitionsMmaPv == 1 || NumKPartitionsMmaPv == 2, + "NumKPartitionsMmaPv must be 1 or 2"); + + // The warpColIdx. + int32_t const warpColIdx{mWarpGrpThreadIdx / 64}; + // The warpRowIdx. + int32_t const warpRowIdx{mWarpGrpThreadIdx % 64}; + // The numUint32s per row. + int32_t const numUint32sPerRow{std::min(NumU32s * (2 / NumKPartitionsMmaPv), 32)}; + + // The base offset of the shared memory. + // There is at most 128B (32 uint32_t) per row considering the swizzling. + int32_t smemBaseOffset{warpRowIdx * numUint32sPerRow}; + // If we split the K dimension of P into 2 partitions, we need to adjust the base offset based on + // the partition. + if constexpr (NumKPartitionsMmaPv == 2) { + smemBaseOffset += warpColIdx * 64 * numUint32sPerRow; + } + + // The number of uint4 elements in the source. + static_assert(NumU32s % 4 == 0, "The number of elements must be a multiple of 4"); + int32_t const numUint4Elts{NumU32s / 4}; + + // The xor factor. + int32_t const xorFactor = std::min(8, numUint32sPerRow / 4); + // The number of packed rows. + int32_t const numPackedRows{8 / xorFactor}; + +#pragma unroll + for (int32_t ii = 0; ii < numUint4Elts; ++ii) { + // The smemColIdx. + int32_t smemColIdx{ii}; + // If we don't split the K dimension of P into 2 partitions, we need to adjust the block index + // based on the warpColIdx. + if constexpr (NumKPartitionsMmaPv == 1) { + smemColIdx += warpColIdx * numUint4Elts; + } + // The smemBlock idx, where each block only contains 128B (32 uint32_t) in the leading + // dimension. + int32_t const smemBlkIdx{smemColIdx / 8}; + // Swizzle the column index. + int32_t swizzledColIdx = (smemColIdx % 8) ^ ((mWarpGrpThreadIdx % 8) / numPackedRows); + // The smem offset in uint32_t. + int32_t const smemOffset{smemBaseOffset + smemBlkIdx * 64 * 32 + swizzledColIdx * 4}; + // Store the data. + *reinterpret_cast(smemDst + smemOffset) = reinterpret_cast(src)[ii]; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/TmemTile.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/TmemTile.h new file mode 100644 index 000000000000..9f4776cff919 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/TmemTile.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// .16dp32bitx2. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline __device__ int ldst16dp32bitTmemColIdx(int tidx) { + // The base is (tidx % 32) / 16) * NumColsBetweenHalfWarps. + return ((tidx & 0x1f) >> 4) * NumColsBetweenHalfWarps; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline __device__ int ldst16dp32bitTmemRowIdx(int tidx) { + // The base is (tidx / 32) * StrideBetweenWarps + (tidx % 16). + return (tidx / 32) * StrideBetweenWarps + (tidx & 0xf); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// Helper function for .16dp128bit and .16dp256bit. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ int ldst16dpTmemRowIdx(int offset) { + + // This code computes "offset / (NumTmemCols * 2) * StrideBetweenWarps". + + // The number of columns multiplied by 2. + auto constexpr NumTmemCols2{NumTmemCols * 2}; + // Extract the index of the instruction (128bit and 256bit span two rows => NumTmemCols * 2). + auto instIdx = offset / NumTmemCols2; + // Compute the stride. + return instIdx * StrideBetweenWarps; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// .16dp256bit. +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ int ldst16dp256bitTmemColIdx(int tidx) { + // The base is (tidx % 4) * 2. + return (tidx & 0x03) * 2; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The col/row functions below have the same template signature to simplify the calling code in +// the generator even if that's a bit awkward below :) + +template +inline __device__ int ldst16dp256bitTmemColIdx(int base, int offset) { + + // The number of columns multiplied by 2. + auto constexpr NumTmemCols2{NumTmemCols * 2}; + // The mask to extract NumTmemCols*2. The right mask excludes 0b11 as we div. by 4 and mul. by 8. + auto constexpr offsetMask{(NumTmemCols2 - 1) & 0xffc}; + // The loop offset is (offset % NumTmemCols2) / 4 * 8 + (offset % NumTmemCols2) % 2. + return base + (offset & offsetMask) * 2 + (offset & 0x01); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline __device__ int ldst16dp256bitTmemRowIdx(int tidx) { + // The base is (tidx / 32) * StrideBetweenWarps + (tidx % 32) / 4. + return (tidx / 32) * StrideBetweenWarps + (tidx & 0x1f) / 4; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ int ldst16dp256bitTmemRowIdx(int base, int offset) { + // The loop offset is (offset / (NumTmemCols * 2)) * StrideBetweenWarps + (offset % 4 / 2) * 8. + return base + ldst16dpTmemRowIdx(offset) + (offset & 0x02) * 4; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ************************************************************************************************* +// M=128 2CTA UTCMMA with 2x2 warpgroup layout. +// +// Warp0 TMEM Row [0 - 31] Col [0 - 31] holds M [0 - 31] N [0 - 31] +// Warp1 TMEM Row [32 - 63] Col [0 - 31] holds M [32 - 63] N [0 - 31] +// Warp2 TMEM Row [64 - 95] Col [0 - 31] holds M [0 - 31] N [32 - 63] +// Warp3 TMEM Row [96 - 127] Col [0 - 31] holds M [32 - 63] N [32 - 63] +// ************************************************************************************************* +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Map tmemD's colIdx to the actual data's colIdx. +template +inline __device__ int warpGrp2x2TmemColIdxToDataColIdx(int warpGrpThreadIdx, int tmemColIdx) { + // The dataD's colIdx = (warpGrpThreadIdx / 64) * (InstN / 2) + tmemColIdx. + return (warpGrpThreadIdx / 64) * (InstN / 2) + tmemColIdx; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Map tmemD's rowIdx to the actual data's rowIdx. +inline __device__ int warpGrp2x2TmemRowIdxToDataRowIdx(int tmemRowIdx) { + // The dataD's rowIdx = tmemRowIdx % 64. + return tmemRowIdx & 0x3f; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Utils.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Utils.h new file mode 100644 index 000000000000..804867abda3e --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/dev/Utils.h @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include +#include +#include + +#include +#include + +namespace trtllm { +namespace dev { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline __device__ T clamp(T x, T lb, T ub) { + return (x < lb) ? lb : (x > ub ? ub : x); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void completeTransaction(uint64_t* barrier, + uint32_t transactionBytes, + uint32_t pred = 1) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900 + asm volatile("{\n\t" + ".reg .pred p;\n\t" + "setp.eq.u32 p, %2, 1;\n\t" + "@p mbarrier.complete_tx.shared::cta.relaxed.cta.b64 [%1], %0;" + "}" + : + : "r"(transactionBytes), + "r"(static_cast(__cvta_generic_to_shared(barrier))), + "r"(pred)); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void cp(T* dst, + T const* src, + int32_t dstOffset = 0, + int64_t srcOffset = 0, + const int cpSize = sizeof(T)) { + if (cpSize == 4) { + uint32_t* dstUInt32 = reinterpret_cast(dst + dstOffset); + uint32_t const* srcUInt32 = reinterpret_cast(src + srcOffset); + *dstUInt32 = *srcUInt32; + } else if (cpSize == 8) { + uint64_t* dstUInt64 = reinterpret_cast(dst + dstOffset); + uint64_t const* srcUInt64 = reinterpret_cast(src + srcOffset); + *dstUInt64 = *srcUInt64; + } else if (cpSize == 16) { + uint4* dstUInt128 = reinterpret_cast(dst + dstOffset); + uint4 const* srcUInt128 = reinterpret_cast(src + srcOffset); + *dstUInt128 = *srcUInt128; + } else { + assert(0 && "cpSize is not supported"); // The compiler will eliminate that code. + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template +inline __device__ void cpAsync(T* dst, + T const* src, + int32_t dstOffset = 0, + int64_t srcOffset = 0, + const int cpSize = sizeof(T)) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 + if (cpSize == 4) { + uint32_t* dstUInt32 = reinterpret_cast(dst + dstOffset); + uint32_t const* srcUInt32 = reinterpret_cast(src + srcOffset); + uint32_t dstU32 = static_cast(__cvta_generic_to_shared(dstUInt32)); + asm volatile("cp.async.ca.shared.global [%0], [%1], 4;\n" ::"r"(dstU32), "l"(srcUInt32)); + } else if (cpSize == 8) { + uint64_t* dstUInt64 = reinterpret_cast(dst + dstOffset); + uint64_t const* srcUInt64 = reinterpret_cast(src + srcOffset); + uint32_t dstU32 = static_cast(__cvta_generic_to_shared(dstUInt64)); + asm volatile("cp.async.ca.shared.global [%0], [%1], 8;\n" ::"r"(dstU32), "l"(srcUInt64)); + } else if (cpSize == 16) { + uint4* dstUInt128 = reinterpret_cast(dst + dstOffset); + uint4 const* srcUInt128 = reinterpret_cast(src + srcOffset); + uint32_t dstU32 = static_cast(__cvta_generic_to_shared(dstUInt128)); + asm volatile("cp.async.ca.shared.global [%0], [%1], 16;\n" ::"r"(dstU32), "l"(srcUInt128)); + } else { + assert(0 && "cpSize is not supported"); // The compiler will eliminate that code. + } +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void ldgInt2(int regs[2], int8_t const* src, int64_t srcOffset) { + int2 i2 = *reinterpret_cast(src + srcOffset); + regs[0] = i2.x; + regs[1] = i2.y; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void ldgInt4(int regs[4], int8_t const* src, int64_t srcOffset) { + int4 i4 = *reinterpret_cast(src + srcOffset); + regs[0] = i4.x; + regs[1] = i4.y; + regs[2] = i4.z; + regs[3] = i4.w; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void ldgInt8(int regs[8], int8_t const* src, int64_t srcOffset) { + asm("ld.ca.global.v8.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8+0];" + : "=r"(regs[0]), + "=r"(regs[1]), + "=r"(regs[2]), + "=r"(regs[3]), + "=r"(regs[4]), + "=r"(regs[5]), + "=r"(regs[6]), + "=r"(regs[7]) + : "l"(src + srcOffset)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void cpAsyncCommitGroup() { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 + asm volatile("cp.async.commit_group;\n"); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline __device__ void cpAsyncWaitGroup() { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 + asm volatile("cp.async.wait_group %0;\n" ::"n"(N)); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +inline __device__ uint32_t mulBf16x2(uint32_t a, uint32_t b) { + uint32_t c; + asm("mul.bf16x2 %0, %1, %2;\n" : "=r"(c) : "r"(a), "r"(b)); + return c; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert packed half2 (represented as uint32_t) to 2xe4m3. +inline __device__ uint16_t convert_half2_to_e4m3(uint32_t packed_h2) { + + // The output bits. + uint16_t output_bits; + // The ptx instruction to convert packed half2 to 2xe4m3. + asm volatile("cvt.rn.satfinite.e4m3x2.f16x2 %0, %1 ;" : "=h"(output_bits) : "r"(packed_h2)); + return output_bits; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert packed half4 (represented as 2xuint32_t) to 4xe4m3 (packed in +// uint32_t). +inline __device__ uint32_t convert_half4_to_e4m3(uint32_t a, uint32_t b) { + + // The output bits. + union { + uint32_t output_bits; + uint16_t output_bits_16[2]; + } output; + // The ptx instruction to convert packed half2 to 2xe4m3. + asm volatile("cvt.rn.satfinite.e4m3x2.f16x2 %0, %2 ;\n" + "cvt.rn.satfinite.e4m3x2.f16x2 %1, %3 ;\n" + : "=h"(output.output_bits_16[0]), "=h"(output.output_bits_16[1]) + : "r"(a), "r"(b)); + return output.output_bits; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert bfloat16x2 to float and add them. +inline __device__ float fadd2_bf16(uint32_t x) { + // BF16 to FP32: shift left by 16 (zero-pad mantissa) + float lo = __int_as_float((x & 0xFFFFu) << 16); + float hi = __int_as_float(x & 0xFFFF0000u); + return lo + hi; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to convert half2 to float and add them. +inline __device__ float fadd2_fp16(uint32_t x) { + float2 result = __half22float2(reinterpret_cast<__half2 const&>(x)); + return result.x + result.y; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ float phi(float x) { + return 0.5f * (1.0f + tanhf(0.7978845608028654f * (x + 0.044715f * x * x * x))); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ float gelu(float x) { + return x * phi(x); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to add bfloat16x2 values (reinterpreted as uint32_t). +inline __device__ uint32_t hadd2_bf16(uint32_t inA, uint32_t inB) { + uint32_t output; + asm volatile("{\n" + "add.rn.bf16x2 %0, %1, %2;\n" + "}\n" + : "=r"(output) + : "r"(inA), "r"(inB)); + return output; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Helper function to add half2 values (reinterpreted as uint32_t). +inline __device__ uint32_t hadd2_fp16(uint32_t inA, uint32_t inB) { + uint32_t output; + asm volatile("{\n" + "add.rn.f16x2 %0, %1, %2;\n" + "}\n" + : "=r"(output) + : "r"(inA), "r"(inB)); + return output; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline __device__ void prmt(uint32_t& out, T hi, T lo, uint32_t selectCode) { + out = __byte_perm(reinterpret_cast(lo), reinterpret_cast(hi), selectCode); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ float relu(float x) { + return fmaxf(0.0f, x); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ float sigmoid(float x) { + return 1.0f / (1.0f + expf(-x)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ float sigmoid_base2(float x) { + return 1.0f / (1.0f + exp2f(-x)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ float silu(float x) { + return x * sigmoid(x); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void prefetchTensorMap(void const* ptr) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900 + asm volatile("prefetch.tensormap [%0];" : : "l"(reinterpret_cast(ptr)) : "memory"); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void prefetchTensor3dL2(void const* desc_ptr, + int32_t crd0, + int32_t crd1, + int32_t crd2) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900 + // The .tile prefetch variant performed better for BatchedGemm prefetchB tuning. + uint64_t gmem_int_desc = reinterpret_cast(desc_ptr); + asm volatile("cp.async.bulk.prefetch.tensor.3d.L2.global.tile [%0, {%1, %2, %3}];" + : + : "l"(gmem_int_desc), "r"(crd0), "r"(crd1), "r"(crd2) + : "memory"); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline __device__ void prefetchTensor4dL2(void const* desc_ptr, + int32_t crd0, + int32_t crd1, + int32_t crd2, + int32_t crd3) { +#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900 + // The .tile prefetch variant performed better for BatchedGemm prefetchB tuning. + uint64_t gmem_int_desc = reinterpret_cast(desc_ptr); + asm volatile("cp.async.bulk.prefetch.tensor.4d.L2.global.tile [%0, {%1, %2, %3, %4}];" + : + : "l"(gmem_int_desc), "r"(crd0), "r"(crd1), "r"(crd2), "r"(crd3) + : "memory"); +#endif +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Initialize PersistentTileSchedulerSm90::Params on device for StaticPersistent scheduler. +// +// Note: This function is called on device during resource initialization. Basically copied from +// PersistentTileSchedulerSm90Params::initialize() but modified to become a device function and +// pinned raster/swizzle configuration to AlongM/Disabled only. +// +// TODO: overload the function with gemm::KernelParams and batchedGemm::KernelParams. +template +inline __device__ cutlass::gemm::kernel::detail::PersistentTileSchedulerSm90Params +initPersistentSchedulerSm90Params(KernelParams const& kernelParams, + ClusterShape clusterShape, + TileShape /* tileShape */) { + // BatchM and RasterAlongNonBatchDim implies RasterAlongN + // BatchM and !RasterAlongNonBatchDim implies RasterAlongM + // !BatchM and RasterAlongNonBatchDim implies RasterAlongM + // !BatchM and !RasterAlongNonBatchDim implies RasterAlongN + bool constexpr RasterAlongM{true}; + using Params = cutlass::gemm::kernel::detail::PersistentTileSchedulerSm90Params; + using RasterOrder = typename Params::RasterOrder; + Params schedulerParams{}; + + int32_t const clusterM = cute::get<0>(clusterShape); + int32_t const clusterN = cute::get<1>(clusterShape); + + // Calculate number of tiles based on batch mode. + // - nm is the non-batched dimension: N if batchM, M if batchN. + // - tileStridePerBatch is: N/TileN if batchM, M/TileM if batchN. + // - ptrNumNonExitingCtas[0] gives the max number of tiles in the batched dimension. + // + // Note: For StaticPersistent scheduler, ptrNumNonExitingCtas MUST be set because we cannot + // compute the tile count for the batched dimension from nm alone (nm is the OTHER dimension). + int32_t numTilesM; + int32_t numTilesN; + if constexpr (BatchM) { + // Batching along M: nm = N (fixed), numTilesN is known, numTilesM from early exit info + numTilesN = kernelParams.tileStridePerBatch; // N / TileN + // ptrNumNonExitingCtas[0] gives the max number of M tiles across all batches + numTilesM = kernelParams.ptrNumNonExitingCtas[int32_t{0}]; + } else { + // Batching along N: nm = M (fixed), numTilesM is known, numTilesN from early exit info + numTilesM = kernelParams.tileStridePerBatch; // M / TileM + // ptrNumNonExitingCtas[0] gives the max number of N tiles across all batches + numTilesN = kernelParams.ptrNumNonExitingCtas[int32_t{0}]; + } + + // We map the ragged batch dim to M if BatchM==true else N. Hence always 1 in classic BMM sense. + int32_t const numBatches = 1; + + schedulerParams.problem_tiles_m_ = numTilesM; + schedulerParams.problem_tiles_n_ = numTilesN; + schedulerParams.problem_tiles_l_ = numBatches; + schedulerParams.cluster_shape_m_ = clusterM; + schedulerParams.cluster_shape_n_ = clusterN; + schedulerParams.log_swizzle_size_ = 0; + // Raster order: AlongM if transposeMmaOutput==true, else AlongN. + // TODO: check if raster order is compatible with how TRTLLM-Gen sets grid shape in x or y. + schedulerParams.raster_order_ = RasterAlongM ? RasterOrder::AlongM : RasterOrder::AlongN; + + uint64_t const blocksPerProblem = + uint64_t(numTilesM) * uint64_t(numTilesN) * uint64_t(numBatches); + schedulerParams.blocks_per_problem_ = blocksPerProblem; + + // Use power of 2 variant for cluster shapes since they are typically 1, 2, or 4 + if constexpr (RasterAlongM) { + schedulerParams.divmod_cluster_shape_major_ = cutlass::FastDivmodU64Pow2(clusterM); + schedulerParams.divmod_cluster_shape_minor_ = cutlass::FastDivmodU64Pow2(clusterN); + } else { + schedulerParams.divmod_cluster_shape_major_ = cutlass::FastDivmodU64Pow2(clusterN); + schedulerParams.divmod_cluster_shape_minor_ = cutlass::FastDivmodU64Pow2(clusterM); + } + + uint64_t const tilesPerBatch = uint64_t(numTilesM) * uint64_t(numTilesN); + schedulerParams.divmod_batch_ = cutlass::FastDivmodU64(tilesPerBatch); + + if constexpr (RasterAlongM) { + uint64_t const clustersAlongMajor = (numTilesM + clusterM - 1) / clusterM; + schedulerParams.divmod_cluster_blk_major_ = cutlass::FastDivmodU64(clustersAlongMajor); + } else { + uint64_t const clustersAlongMajor = (numTilesN + clusterN - 1) / clusterN; + schedulerParams.divmod_cluster_blk_major_ = cutlass::FastDivmodU64(clustersAlongMajor); + } + + return schedulerParams; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace dev +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CommonUtils.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CommonUtils.h new file mode 100644 index 000000000000..fdae1d1d7cff --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CommonUtils.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +namespace trtllm { +namespace gen { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// +// TMA OOB optimization constants. +// +// CUDA Programming Guide states that "globalDim must be non-zero and less than or equal to 2^32". +// In practice, the kernel acts funny with TMA shape of 2^32 so we use 2^31. +constexpr unsigned long TmaDimMax = 1UL << 31; +// Chosen so that LargeN * XLargeN * sizeof(dtype) >= 2^64 which causes overflow and effectively +// becomes 0. As sizeof(dtype) can be as small as 0.5B, we choose LargeN = 2^30 and XLargeN = 2^35 +// so overflow can happen. +constexpr unsigned long LargeN = 1UL << 30; +// Used in TMA stride. Should be less than 2^40. +constexpr unsigned long XLargeN = 1UL << 35; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline T ceilDiv(T m, T n) { + return (m + n - T(1)) / n; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline T roundUp(T m, T n) { + return ceilDiv(m, n) * n; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace gen +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CudaArchDecl.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CudaArchDecl.h new file mode 100644 index 000000000000..1f3f8506f932 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CudaArchDecl.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Be careful when modifying this file as it is included by the generated kernels. For example, do +// not add TLLM_CHECK_* constructs in this file. Thanks! +// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace trtllm { +namespace gen { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +enum class CudaArch { + // Hopper + Sm90a = 0, + // Blackwell + Sm100a, + // Blackwell-family + Sm100f, + // Blackwell Ultra + Sm103a, +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline bool isArchHopper(CudaArch cudaArch) { + return cudaArch == CudaArch::Sm90a; +} + + +inline bool isArchBlackwell(CudaArch cudaArch) { + return cudaArch == CudaArch::Sm100a || cudaArch == CudaArch::Sm100f || + cudaArch == CudaArch::Sm103a; +} + +inline bool isArchBlackwellUltra(CudaArch cudaArch) { + return cudaArch == CudaArch::Sm103a; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline std::string cudaArchToString(CudaArch cudaArch, bool isFull = true) { + switch (cudaArch) { + case CudaArch::Sm90a: + return isFull ? "90a" : "90"; + case CudaArch::Sm100a: + return isFull ? "100a" : "100"; + case CudaArch::Sm100f: + return isFull ? "100f" : "100"; + case CudaArch::Sm103a: + return isFull ? "103a" : "103"; + default: + assert(false); + return ""; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline CudaArch stringToCudaArch(std::string const& str) { + if (str == "90a") { + return CudaArch::Sm90a; + } else if (str == "100a") { + return CudaArch::Sm100a; + } else if (str == "100f") { + return CudaArch::Sm100f; + } else if (str == "103a") { + return CudaArch::Sm103a; + } else { + assert(false); + return CudaArch::Sm100a; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace gen +} // namespace trtllm \ No newline at end of file diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CudaRunner.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CudaRunner.h new file mode 100644 index 000000000000..9d6aa1c83112 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/CudaRunner.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#ifndef TLLM_GEN_EXPORT_INTERFACE +#include +#else +#include +#include +class Kernel; +#endif // TLLM_GEN_EXPORT_INTERFACE + +namespace trtllm { +namespace gen { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +class CudaRunnerImpl; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +class CudaRunner { +public: + // Ctor. + CudaRunner(Kernel* kernel); + // Dtor. + ~CudaRunner(); + + // The options to compile the kernel. + using Options = std::vector; + // Compile the kernel. + void compile(Options options = Options{}, + bool loadFromCubin = false, + bool exportCubin = false, + int32_t numInstances = 1); + + // Get the kernel. + Kernel const* getKernel() const; + + // The dimensions of the grid. It will be determined automatically if Grid{} is used. + using Grid = std::vector; + // The dimension of the cluster during the runtime. + using Cluster = std::vector; + + // Run the kernel. + void run(void* kernelParams, + void* cudaStream, + Grid grid = Grid{}, + Cluster cluster = Cluster{}, + int32_t instanceId = 0); + + // Set the kernel. + void setKernel(Kernel const* kernel); + +private: + // The only instance of the implementation. + CudaRunnerImpl* mImpl; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace gen +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/DtypeDecl.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/DtypeDecl.h new file mode 100644 index 000000000000..3c57da62cc26 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/DtypeDecl.h @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include +#include +#ifndef TLLM_GEN_EXPORT_INTERFACE +#include +#else +#include "MmaDecl.h" +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Be careful when modifying this file as it is included by the generated kernels. For example, do +// not add TLLM_CHECK_* constructs in this file. Thanks! +// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace trtllm { +namespace gen { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +enum class Dtype : uint32_t { + +// We use the following encoding for the types: +// +// Byte 0: Identifier for the type (going from 0 to the number of data types - 1, +// Byte 1: Number of bits in the type, +// Byte 2: Bit 0: Is it an integer? 0x1 if true, 0x0 otherwise; +// Bit 4: is it signed? 0x1 if true, 0x0 otherwise. +// Byte 3: Is it a block format? 0x1 if true, 0x0 otherwise. + +#define TLLM_ENCODE_DTYPE(BlockFormatBit, SignedBit, IntegerBit, NumBits, Uid) \ + uint32_t { \ + (BlockFormatBit << 24) | (SignedBit << 20) | (IntegerBit << 16) | (NumBits << 8) | (Uid) \ + } + + // clang-format off + Bfloat16 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 16u, /*uid*/ 0u), + Bool = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 0u, /*int*/ 1u, /*bits*/ 1u, /*uid*/ 1u), + E2m1 = TLLM_ENCODE_DTYPE(/*block*/ 1u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 4u, /*uid*/ 2u), + E2m3 = TLLM_ENCODE_DTYPE(/*block*/ 1u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 6u, /*uid*/ 3u), + E3m2 = TLLM_ENCODE_DTYPE(/*block*/ 1u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 6u, /*uid*/ 4u), + E4m3 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 8u, /*uid*/ 5u), + E5m2 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 8u, /*uid*/ 6u), + Fp16 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 16u, /*uid*/ 7u), + Fp32 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 32u, /*uid*/ 8u), + Int8 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 1u, /*bits*/ 8u, /*uid*/ 9u), + Int32 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 1u, /*bits*/ 32u, /*uid*/ 10u), + Int64 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 1u, /*bits*/ 64u, /*uid*/ 11u), + MxE2m1 = TLLM_ENCODE_DTYPE(/*block*/ 1u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 4u, /*uid*/ 12u), + MxE4m3 = TLLM_ENCODE_DTYPE(/*block*/ 1u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 8u, /*uid*/ 13u), + MxInt4 = TLLM_ENCODE_DTYPE(/*block*/ 1u, /*signed*/ 1u, /*int*/ 1u, /*bits*/ 4u, /*uid*/ 14u), + UE8m0 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 0u, /*int*/ 0u, /*bits*/ 8u, /*uid*/ 15u), + UInt8 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 0u, /*int*/ 1u, /*bits*/ 8u, /*uid*/ 16u), + UInt16 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 0u, /*int*/ 1u, /*bits*/ 16u, /*uid*/ 17u), + UInt32 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 0u, /*int*/ 1u, /*bits*/ 32u, /*uid*/ 18u), + UInt64 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 0u, /*int*/ 1u, /*bits*/ 64u, /*uid*/ 19u), + UInt128 = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 0u, /*int*/ 1u, /*bits*/ 128u, /*uid*/ 20u), + Void = TLLM_ENCODE_DTYPE(/*block*/ 0u, /*signed*/ 1u, /*int*/ 0u, /*bits*/ 0u, /*uid*/ 21u), +// clang-format on + +#undef TLLM_ENCODE_DTYPE +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The number of bits in a data type? +inline int dtypeGetNumBits(Dtype dtype) { + constexpr uint32_t kMask = 0xffu << 8; + return static_cast((static_cast(dtype) & kMask) >> 8); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Does the format use block scaling? +inline bool dtypeIsBlockFmt(Dtype dtype) { + constexpr uint32_t kMask = 0xffu << 24; + return static_cast((static_cast(dtype) & kMask) >> 24); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Is a given data type a floating-point type? +inline bool dtypeIsFloat(Dtype dtype) { + constexpr uint32_t kMask = 0x1u << 16; + return dtype != Dtype::Void && 0 == (static_cast(dtype) & kMask); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Is a given data type an 8-bit floating-point type? +inline bool dtypeIsFp8(Dtype dtype) { + return dtype == Dtype::E4m3 || dtype == Dtype::E5m2; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Is a given data type an integer type? +inline bool dtypeIsInt(Dtype dtype) { + constexpr uint32_t kMask = 0x1u << 16; + return (dtype != Dtype::Bool) && (0 != (static_cast(dtype) & kMask)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Is a given data type signed? +inline bool dtypeIsSigned(Dtype dtype) { + constexpr uint32_t kMask = 0x1u << 20; + return (0 != (static_cast(dtype) & kMask)); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// For logging and error reporting +inline std::string dtypeToString(Dtype dtype) { + switch (dtype) { + case Dtype::Bfloat16: + return "Bfloat16"; + case Dtype::Bool: + return "Bool"; + case Dtype::E2m1: + return "E2m1"; + case Dtype::E2m3: + return "E2m3"; + case Dtype::E3m2: + return "E3m2"; + case Dtype::E4m3: + return "E4m3"; + case Dtype::E5m2: + return "E5m2"; + case Dtype::Fp16: + return "Fp16"; + case Dtype::Fp32: + return "Fp32"; + case Dtype::Int8: + return "Int8"; + case Dtype::Int32: + return "Int32"; + case Dtype::Int64: + return "Int64"; + case Dtype::MxE4m3: + return "MxE4m3"; + case Dtype::MxE2m1: + return "MxE2m1"; + case Dtype::MxInt4: + return "MxInt4"; + case Dtype::UE8m0: + return "UE8m0"; + case Dtype::UInt8: + return "UInt8"; + case Dtype::UInt16: + return "UInt16"; + case Dtype::UInt32: + return "UInt32"; + case Dtype::UInt64: + return "UInt64"; + case Dtype::UInt128: + return "UInt128"; + case Dtype::Void: + return "Void"; + default: + assert(false); + return "Unsupported type"; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline Dtype dtypeEltType(Dtype dtype) { + switch (dtype) { + case Dtype::MxE2m1: + return Dtype::E2m1; + case Dtype::MxE4m3: + return Dtype::E4m3; + default: + return dtype; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Note: the block size from the options should be used instead. +// TODO: remove this function? +inline int dtypeNumEltsPerSf(Dtype dtype, bool useSparsity = false) { + switch (dtype) { + case Dtype::E2m1: + return useSparsity ? 32 : 16; + case Dtype::MxE2m1: + case Dtype::MxE4m3: + case Dtype::MxInt4: + return useSparsity ? 64 : 32; + default: + assert(false); + return -1; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Returns the dtype of scaling factors, if applicable. +inline Dtype dtypeGetBlockSfType(Dtype dtype) { + switch (dtype) { + case Dtype::E2m1: + return Dtype::E4m3; + case Dtype::MxE2m1: + case Dtype::MxE4m3: + return Dtype::UE8m0; + case Dtype::MxInt4: + return Dtype::Bfloat16; + default: + assert(false); + return Dtype::Void; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline MmaKind dtypeGetMmaKind(Dtype dtypeA, Dtype dtypeB) { + auto dtypeEltA = dtypeEltType(dtypeA); + auto dtypeEltB = dtypeEltType(dtypeB); + + // Note: the order of the conditions is important here. + if ((dtypeA == Dtype::Fp16 && dtypeB == Dtype::Fp16) || + (dtypeA == Dtype::Bfloat16 && dtypeB == Dtype::Bfloat16)) { + return MmaKind::Fp16; + } + + if ((dtypeA == Dtype::Int8 || dtypeA == Dtype::UInt8) && + (dtypeB == Dtype::Int8 || dtypeB == Dtype::UInt8)) { + return MmaKind::Int8; + } + + // This statement captures both MxE2m1 and E2m1. + if (dtypeEltA == Dtype::E2m1 && dtypeEltB == Dtype::E2m1) { + return MmaKind::MxFp4NvFp4; + } + + if ((dtypeA == Dtype::E4m3 || dtypeA == Dtype::E5m2 || dtypeA == Dtype::E2m3 || + dtypeA == Dtype::E3m2 || dtypeA == Dtype::E2m1) && + (dtypeB == Dtype::E4m3 || dtypeB == Dtype::E5m2 || dtypeB == Dtype::E2m3 || + dtypeB == Dtype::E3m2 || dtypeB == Dtype::E2m1)) { + return MmaKind::Fp8Fp6Fp4; + } + + // At this point we know that both dtypes are Mx types and not both MxE2m1 at the same time. + if ((dtypeEltA == Dtype::E4m3 || dtypeEltA == Dtype::E5m2 || dtypeEltA == Dtype::E2m3 || + dtypeEltA == Dtype::E3m2 || dtypeEltA == Dtype::E2m1) && + (dtypeEltB == Dtype::E4m3 || dtypeEltB == Dtype::E5m2 || dtypeEltB == Dtype::E2m3 || + dtypeEltB == Dtype::E3m2 || dtypeEltB == Dtype::E2m1)) { + return MmaKind::MxFp8Fp6Fp4; + } + return MmaKind::Tf32; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline bool dtypeNeedsPadding(Dtype dtype, + MmaKind mmaKind, + [[maybe_unused]] int mmaK, + [[maybe_unused]] bool isSparseA) { + bool needsPadding = mmaKind == MmaKind::MxFp8Fp6Fp4 && dtype == Dtype::MxE2m1; + return needsPadding; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace gen +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/MmaDecl.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/MmaDecl.h new file mode 100644 index 000000000000..ffb651787d70 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllm/gen/MmaDecl.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2011-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#include +#ifndef TLLM_GEN_EXPORT_INTERFACE +#include +#else // TLLM_GEN_EXPORT_INTERFACE +#include "CommonUtils.h" +#endif // TLLM_GEN_EXPORT_INTERFACE + +namespace trtllm { +namespace gen { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// The kind of the MMA instruction +enum class MmaKind : uint32_t { + // For Blackwell this follows the PTX ISA description of the MMA instructions. + // https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-kind-shapes + + // The MMA type is auto-detected from the dtypes of the input tensors + Auto = 0, + // Supports dtypeA = dtypeB = Fp16 and dtypeD = [Fp16, Fp32] + // or dtypeA = dtypeB = Bfloat16 and dtypeD = [Fp32] + // Corresponds to the kind::f16 of tcgen05.mma. + Fp16 = 1, + // Supports dtypeA/B = [E4m3, E5m2, E2m3, E3m2, E2m1] and dtypeD = [Fp16, Fp32] + // Corresponds to the kind::f8f6f4 of tcgen05.mma. + Fp8Fp6Fp4 = 2, + // Supports dtypeA = dtypeB = [Int8, Uint8] and dtypeD = [Int32] + // Corresponds to the kind::i8 of tcgen05.mma. + Int8 = 3, + // Supports dtypeA = dtypeB = [MxE2m1, E2m1] with block scale [UM8e0, UEm4e3] + // and dtypeD = [Fp32] + // Corresponds to the kind::mxf4nvf4 of tcgen05.mma. + MxFp4NvFp4 = 4, + // Supports dtype dtypeA = dtypeB = [MxE4m3, MxE2m1] with block scale [UM8e0] + // and dtypeD = [Fp32] + // Corresponds to the kind::mxf8f6f4 of tcgen05.mma. + MxFp8Fp6Fp4 = 5, + // Supports dtypeA = dtypeB = Tf32 with dtypeD = [Fp32] + // Corresponds to the kind::tf32 of tcgen05.mma. + Tf32 = 6 +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +inline bool mmaKindIsBlockFmt(MmaKind mmaKind) { + return mmaKind == MmaKind::MxFp8Fp6Fp4 || mmaKind == MmaKind::MxFp4NvFp4; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// For logging and error reporting +inline std::string mmaKindToString(MmaKind mmaKind) { + switch (mmaKind) { + case MmaKind::Auto: + return "Auto"; + case MmaKind::Fp16: + return "Fp16"; + case MmaKind::Fp8Fp6Fp4: + return "Fp8Fp6Fp4"; + case MmaKind::Int8: + return "Int8"; + case MmaKind::MxFp4NvFp4: + return "MxFp4NvFp4"; + case MmaKind::MxFp8Fp6Fp4: + return "MxFp8Fp6Fp4"; + case MmaKind::Tf32: + return "Tf32"; + default: + assert(false); + return "Unsupported type"; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +// Get the TMEM column stride per group. +// A group is one or more MMA instructions that share the same TMEM columns. +inline int32_t getTmemColStridePerGroup(int32_t mmaMn, + int32_t mmaK, + [[maybe_unused]] int32_t kGroupSize) { + int32_t colStride = 2 * ceilDiv(mmaMn, 64); + if (mmaK == 96) { + colStride = std::max(4, colStride); + } + return colStride; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace gen +} // namespace trtllm diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenExportCompat.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenExportCompat.h new file mode 100644 index 000000000000..ff8bbca527e8 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenExportCompat.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +// Compatibility header for building trtllm-gen FMHA export headers inside TensorRT-LLM. +// Provides type aliases, toString specializations, check macros, and utility functions +// that bridge the gap between trtllm-gen's native types and TRT-LLM's kernel types. +// +// This header is included by export headers (e.g., KernelTraits.h) when +// TLLM_GEN_EXPORT_INTERFACE is defined, replacing trtllm-gen-internal headers +// like KernelConfigBase.h, GenCtx.h, TmemTile.h, etc. + +#include "../fmhaRunnerParams.h" +#include "tensorrt_llm/common/assert.h" +#include "tensorrt_llm/common/logger.h" +#include "trtllm/gen/CommonUtils.h" +#include "trtllm/gen/CudaArchDecl.h" +#include "trtllm/gen/DtypeDecl.h" +#include +#include +#include + +namespace fmha { + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace { +namespace tk = tensorrt_llm::kernels; +namespace tg = trtllm::gen; +} // namespace + +// Type aliases: map fmha:: names to TRT-LLM kernel enum types. +using AttentionMaskType = tk::TrtllmGenAttentionMaskType; +using FmhaKernelType = tk::FmhaKernelType; +using MultiCtasKvMode = tk::MultiCtasKvMode; +using QkvLayout = tk::QkvLayout; +using TileScheduler = tk::TileScheduler; + +using trtllm::gen::ceilDiv; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Check macros: streaming-style (matching trtllm-gen calling convention). +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace detail { +template +inline std::string checkErrorStr(Args const&... args) { + std::ostringstream oss; + ((oss << args), ...); + return oss.str(); +} +} // namespace detail + +#ifndef TLLM_CHECK_ERROR +#define TLLM_CHECK_ERROR(cond, ...) \ + do { \ + if (!static_cast(cond)) { \ + tensorrt_llm::common::throwRuntimeError( \ + __FILE__, __LINE__, ::fmha::detail::checkErrorStr(__VA_ARGS__).c_str()); \ + } \ + } while (0) +#endif + +#ifndef TLLM_CHECK_INFO +#define TLLM_CHECK_INFO(cond, ...) \ + do { \ + if (!static_cast(cond)) { \ + TLLM_LOG_INFO("[FMHA] %s", ::fmha::detail::checkErrorStr(__VA_ARGS__).c_str()); \ + } \ + } while (0) +#endif + +// Printf-style check macro (used by KernelTraits.h). +#ifndef TLLM_CHECK_ERROR_FMT +#define TLLM_CHECK_ERROR_FMT(cond, fmt, ...) \ + do { \ + if (!static_cast(cond)) { \ + tensorrt_llm::common::throwRuntimeError( \ + __FILE__, __LINE__, \ + tensorrt_llm::common::fmtstr(fmt, __VA_ARGS__).c_str()); \ + } \ + } while (0) +#endif + +// Helper functions (isPagedKv, isContextKernel, etc.) are NOT defined here +// because fmhaRunnerParams.h already provides them in namespace tensorrt_llm::kernels. +// The using-aliases above make fmha:: types the same as tk:: types, so no ambiguity. + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// MmaOrder enum (not in fmhaRunnerParams.h, defined natively here). +//////////////////////////////////////////////////////////////////////////////////////////////////// + +enum class MmaOrder { + Pv0_Qk0_Pv1_Qk1 = 0, + Qk0_Pv0_Qk1_Pv1, + Qk0_Qk1_Pv0_Pv1, +}; + +inline std::string mmaOrderToString(MmaOrder mmaOrder) { + switch (mmaOrder) { + case MmaOrder::Pv0_Qk0_Pv1_Qk1: + return "Pv0_Qk0_Pv1_Qk1"; + case MmaOrder::Qk0_Pv0_Qk1_Pv1: + return "Qk0_Pv0_Qk1_Pv1"; + case MmaOrder::Qk0_Qk1_Pv0_Pv1: + return "Qk0_Qk1_Pv0_Pv1"; + default: + assert(false); + return "Invalid MmaOrder"; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Serialization helpers (toString specializations). +//////////////////////////////////////////////////////////////////////////////////////////////////// + +template inline std::string toString(T e) { + return std::to_string(e); +} + +template <> inline std::string toString(bool flag) { + return (flag ? "true" : "false"); +} + +template <> inline std::string toString(AttentionMaskType e) { + switch (e) { + case AttentionMaskType::Dense: + return "Dense"; + case AttentionMaskType::Causal: + return "Causal"; + case AttentionMaskType::SlidingOrChunkedCausal: + return "SlidingOrChunkedCausal"; + case AttentionMaskType::Custom: + return "Custom"; + default: + return ""; + } +} + +template <> inline std::string toString(tg::CudaArch arch) { + return tg::cudaArchToString(arch); +} + +template <> inline std::string toString(FmhaKernelType e) { + switch (e) { + case FmhaKernelType::Context: + return "Context"; + case FmhaKernelType::Generation: + return "Gen"; + case FmhaKernelType::SwapsMmaAbForGeneration: + return "SwapsAbForGen"; + case FmhaKernelType::KeepsMmaAbForGeneration: + return "KeepsAbForGen"; + default: + return ""; + } +} + +template <> inline std::string toString(MultiCtasKvMode mode) { + switch (mode) { + case MultiCtasKvMode::Disabled: + return "Disabled"; + case MultiCtasKvMode::GmemReduction: + return "GmemReduction"; + case MultiCtasKvMode::GmemReductionWithSeparateKernel: + return "GmemReductionWithSeparateKernel"; + case MultiCtasKvMode::CgaSmemReduction: + return "CgaSmemReduction"; + default: + return ""; + } +} + +inline std::string multiCtasKvModeToString(MultiCtasKvMode mode) { + return toString(mode); +} + +template <> inline std::string toString(TileScheduler scheduler) { + switch (scheduler) { + case TileScheduler::Static: + return "Static"; + case TileScheduler::Persistent: + return "Persistent"; + default: + return ""; + } +} + +template <> inline std::string toString(QkvLayout qkvLayout) { + switch (qkvLayout) { + case QkvLayout::SeparateQkv: + return "SeparateQkv"; + case QkvLayout::PackedQkv: + return "PackedQkv"; + case QkvLayout::PagedKv: + return "PagedKv"; + case QkvLayout::ContiguousKv: + return "ContiguousKv"; + default: + return ""; + } +} + +template <> inline std::string toString(tg::Dtype e) { + return tg::dtypeToString(e); +} + +template <> inline std::string toString(MmaOrder e) { + return mmaOrderToString(e); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// JSON serialization macro (matching KernelConfigBase.h). +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TO_JSON +#define TO_JSON(field) j[#field] = toString(field); +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// TmemTile constant (replaces tg::TmemTile::TmemRowScale from TmemTile.h). +//////////////////////////////////////////////////////////////////////////////////////////////////// + +namespace tg_compat { +static constexpr int TmemRowScale = 1 << 16; +} // namespace tg_compat + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace fmha + +// Provide stubs for trtllm-gen types not available in TRT-LLM. +namespace trtllm { +namespace gen { +struct TmemTile { + static int constexpr TmemRowScale = ::fmha::tg_compat::TmemRowScale; +}; +class GenCfg; +} // namespace gen +} // namespace trtllm + +// Include KernelConfigBase.h for the KernelConfigBase struct definition. +// The enum/toString sections are skipped via #ifndef TLLM_FMHA_TRTLLM_COMPAT +// (already provided above as TRT-LLM type aliases). +#include "KernelConfigBase.h" diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenLogCompat.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenLogCompat.h new file mode 100644 index 000000000000..76fd6de9d1f1 --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenLogCompat.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +// Compatibility layer: trtllm-gen export headers use streaming-style log macros +// (e.g., TLLM_LOG_TRACE("val=", x)) while TensorRT-LLM's logger.h uses printf-style +// (e.g., TLLM_LOG_TRACE("val=%d", x)). This header saves the original definitions +// and replaces them with streaming-compatible versions. +// +// Usage in fmhaKernels.h: +// #include "tensorrt_llm/common/logger.h" // TRT-LLM printf-style +// #include "trtllmGen_fmha_export/trtllmGenLogCompat.h" // switch to streaming +// #include "trtllmGen_fmha_export/FmhaOptions.h" // export headers (streaming) +// #include "trtllmGen_fmha_export/trtllmGenLogCompatEnd.h" // restore printf-style + +#include +#include "tensorrt_llm/common/logger.h" + +namespace trtllm_gen_log_compat +{ + +template +inline void logStreaming(tensorrt_llm::common::Logger::Level level, Args const&... args) +{ + auto* const logger = tensorrt_llm::common::Logger::getLogger(); + if (logger->isEnabled(level)) + { + std::ostringstream oss; + (oss << ... << args); + logger->log(level, "%s", oss.str().c_str()); + } +} + +} // namespace trtllm_gen_log_compat + +// Save the original TRT-LLM log macro definitions and replace with streaming-compatible versions. +#pragma push_macro("TLLM_LOG_TRACE") +#pragma push_macro("TLLM_LOG_INFO") +#pragma push_macro("TLLM_LOG_WARNING") +#pragma push_macro("TLLM_LOG_ERROR") + +#undef TLLM_LOG_TRACE +#undef TLLM_LOG_INFO +#undef TLLM_LOG_WARNING +#undef TLLM_LOG_ERROR + +#define TLLM_LOG_TRACE(...) \ + trtllm_gen_log_compat::logStreaming(tensorrt_llm::common::Logger::TRACE, __VA_ARGS__) +#define TLLM_LOG_INFO(...) \ + trtllm_gen_log_compat::logStreaming(tensorrt_llm::common::Logger::INFO, __VA_ARGS__) +#define TLLM_LOG_WARNING(...) \ + trtllm_gen_log_compat::logStreaming(tensorrt_llm::common::Logger::WARNING, __VA_ARGS__) +#define TLLM_LOG_ERROR(...) \ + trtllm_gen_log_compat::logStreaming(tensorrt_llm::common::Logger::ERROR, __VA_ARGS__) diff --git a/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenLogCompatEnd.h b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenLogCompatEnd.h new file mode 100644 index 000000000000..1024c754b43c --- /dev/null +++ b/cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllmGen_fmha_export/trtllmGenLogCompatEnd.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Restore the original TRT-LLM printf-style log macros saved by trtllmGenLogCompat.h. +#pragma pop_macro("TLLM_LOG_TRACE") +#pragma pop_macro("TLLM_LOG_INFO") +#pragma pop_macro("TLLM_LOG_WARNING") +#pragma pop_macro("TLLM_LOG_ERROR") diff --git a/cpp/tensorrt_llm/kernels/xqaDispatcher.cpp b/cpp/tensorrt_llm/kernels/xqaDispatcher.cpp index 41aab02d3043..5f11514db8b6 100644 --- a/cpp/tensorrt_llm/kernels/xqaDispatcher.cpp +++ b/cpp/tensorrt_llm/kernels/xqaDispatcher.cpp @@ -291,11 +291,19 @@ bool XqaDispatcher::isSupported() tllmRunnerParams.mNumHeadsQ = mFixedParams.numQHeads; tllmRunnerParams.mNumHeadsKv = mFixedParams.numKvHeads; tllmRunnerParams.mNumHeadsQPerKv = mFixedParams.numQHeads / mFixedParams.numKvHeads; - tllmRunnerParams.mNumTokensPerPage = mFixedParams.numTokensPerBlock; + // Align with ExportCubin: only PagedKv kernels are built with numTokensPerPage > 0. + // ContiguousKv must use 0 so hash matches registered cubins. + tllmRunnerParams.mNumTokensPerPage = mFixedParams.isPagedKv ? mFixedParams.numTokensPerBlock : 0; // Set the chunked attention size and sliding window size to INT_MAX to disable them when checking if // the kernel is supported. tllmRunnerParams.mChunkedAttentionSize = INT_MAX; tllmRunnerParams.mAttentionWindowSize = INT_MAX; + // Problem size fields used by FMHA kernel selection (computeNumCtas). Must be non-zero to avoid + // integer divide-by-zero when mMultiCtasKvMode is true. Actual launch uses real sizes from runImpl. + tllmRunnerParams.mBatchSize = 1; + tllmRunnerParams.mMaxSeqLenQ = 1; + tllmRunnerParams.mMaxSeqLenKv = 1; + tllmRunnerParams.mMultiProcessorCount = mMultiProcessorCount; // Check if it is supported or not. auto [isSupported, info] = mTllmGenFMHARunner->isSupportedWithInfo(tllmRunnerParams); @@ -489,7 +497,7 @@ void XqaDispatcher::runImpl( tllmRunnerParams.mMaskType = tllmRunnerParams.mIsSpecDecTree ? TrtllmGenAttentionMaskType::Custom : TrtllmGenAttentionMaskType::Causal; tllmRunnerParams.mLayerIdx = params.layer_idx; - tllmRunnerParams.seqlensQPtr = params.spec_decoding_generation_lengths; + tllmRunnerParams.seqLensQPtr = params.spec_decoding_generation_lengths; tllmRunnerParams.generalPackedCustoMaskPtr = params.spec_decoding_packed_mask; tllmRunnerParams.customMaskPtr = params.spec_decoding_bl_tree_mask; tllmRunnerParams.customMaskOffsetsPtr = params.spec_decoding_bl_tree_mask_offset; diff --git a/cpp/tensorrt_llm/thop/CMakeLists.txt b/cpp/tensorrt_llm/thop/CMakeLists.txt index 28f468960b90..a4ca98821c32 100644 --- a/cpp/tensorrt_llm/thop/CMakeLists.txt +++ b/cpp/tensorrt_llm/thop/CMakeLists.txt @@ -120,7 +120,6 @@ target_link_libraries( if(USING_OSS_CUTLASS_LOW_LATENCY_GEMM) target_compile_definitions(th_common PUBLIC "USING_OSS_CUTLASS_LOW_LATENCY_GEMM") - message(STATUS "Enable open source Cutlass low latency gemm kernel") endif() if(USING_OSS_CUTLASS_FP4_GEMM) diff --git a/cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp b/cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp index 116013de2ffe..61722e9953fc 100644 --- a/cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp +++ b/cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp @@ -36,7 +36,6 @@ namespace using tensorrt_llm::kernels::FmhaKernelType; using tensorrt_llm::kernels::runPrepareCustomMask; -using tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo; using tensorrt_llm::kernels::TllmGenFmhaRunnerParams; using tensorrt_llm::runtime::BufferManager; using tensorrt_llm::runtime::CudaStream; @@ -302,14 +301,6 @@ class PrepareCustomMaskTest : public ::testing::Test cudaMemsetAsync(bufferCast(*customMaskDevice), 0, totalMaskSize * sizeof(int32_t), mStream->get()); cudaStreamSynchronize(mStream->get()); - // Setup kernel parameters - TllmGenFmhaKernelMetaInfo kernelMeta{}; - kernelMeta.mTileSizeQ = tileSizeQ; - kernelMeta.mTileSizeKv = tileSizeKv; - kernelMeta.mStepQ = tileSizeQ * numInstsQ; - kernelMeta.mStepKv = tileSizeKv * numInstsKv; - kernelMeta.mKernelType = static_cast(FmhaKernelType::KeepsMmaAbForGeneration); - TllmGenFmhaRunnerParams runnerParams; runnerParams.mBatchSize = batchSize; runnerParams.mNumHeadsQPerKv = numHeadsQPerKv; @@ -317,13 +308,16 @@ class PrepareCustomMaskTest : public ::testing::Test runnerParams.mMaxSeqLenKv = *std::max_element(seqLensKv.begin(), seqLensKv.end()); runnerParams.seqLensKvPtr = bufferCast(*seqLensKvDevice); runnerParams.cumSeqLensQPtr = bufferCast(*cumSeqLensQDevice); - runnerParams.seqlensQPtr = bufferCast(*specDecodingGenerationLengthsDevice); + runnerParams.seqLensQPtr = bufferCast(*specDecodingGenerationLengthsDevice); runnerParams.firstSparseMaskOffsetsKvPtr = bufferCast(*firstSparseMaskOffsetsKvDevice); runnerParams.generalPackedCustoMaskPtr = bufferCast(*inputPackedMaskDevice); runnerParams.customMaskOffsetsPtr = bufferCast(*customMaskOffsetsDevice); runnerParams.customMaskPtr = reinterpret_cast(bufferCast(*customMaskDevice)); - runPrepareCustomMask(kernelMeta, runnerParams, mStream->get()); + int32_t const stepQ = tileSizeQ * numInstsQ; + int32_t const stepKv = tileSizeKv * numInstsKv; + runPrepareCustomMask(runnerParams, FmhaKernelType::KeepsMmaAbForGeneration, stepQ, stepKv, tileSizeQ, + tileSizeKv, mStream->get()); cudaError_t cudaErr = cudaStreamSynchronize(mStream->get()); if (cudaErr != cudaSuccess) { diff --git a/jenkins/Build.groovy b/jenkins/Build.groovy index face171493c3..12e606de1a9c 100644 --- a/jenkins/Build.groovy +++ b/jenkins/Build.groovy @@ -432,6 +432,14 @@ def runLLMBuild(pipeline, buildFlags, tarName, is_linux_x86_64) sh "cp ${LLM_ROOT}/cpp/build/attribution/import_payload.json TensorRT-LLM/attribution/ || true" sh "cp ${LLM_ROOT}/cpp/build/attribution/file_mappings.json TensorRT-LLM/attribution/ || true" + sh "mkdir -p TensorRT-LLM/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/" + sh "cp -r ${LLM_ROOT}/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/cuda_ptx TensorRT-LLM/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/" + sh "cp -r ${LLM_ROOT}/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/cutlass TensorRT-LLM/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/" + sh "cp -r ${LLM_ROOT}/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/trtllm TensorRT-LLM/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/" + sh "cp -r ${LLM_ROOT}/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/cuda TensorRT-LLM/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/" + sh "cp ${LLM_ROOT}/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/KernelParams.h TensorRT-LLM/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/" + sh "cp ${LLM_ROOT}/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/KernelParamsDecl.h TensorRT-LLM/cpp/build/tensorrt_llm/kernels/trtllmGenKernels/fmha/" + if (is_linux_x86_64) { sh "rm -rf ${tarName}" sh "pigz --version || true" diff --git a/jenkins/L0_MergeRequest.groovy b/jenkins/L0_MergeRequest.groovy index 1b8355dd6d56..05860cf1f095 100644 --- a/jenkins/L0_MergeRequest.groovy +++ b/jenkins/L0_MergeRequest.groovy @@ -998,7 +998,11 @@ def triggerJob(jobName, parameters, jenkinsUrl = "", credentials = "") def launchJob(jobName, reuseBuild, enableFailFast, globalVars, platform="x86_64", additionalParameters = [:]) { def parameters = getCommonParameters() - String globalVarsJson = writeJSON returnText: true, json: globalVars + // Build a local copy to avoid racey growth from shared parallel mutations. + // In particular, CACHED_CHANGED_FILE_LIST can become very large and may + // trigger "Argument list too long" when passed to downstream jobs. + def globalVarsToPass = globalVars.findAll { key, value -> key != CACHED_CHANGED_FILE_LIST } + String globalVarsJson = writeJSON returnText: true, json: globalVarsToPass parameters += [ 'enableFailFast': enableFailFast, 'globalVars': globalVarsJson, @@ -1398,8 +1402,8 @@ pipeline { } } else { // globalVars[CACHED_CHANGED_FILE_LIST] is only used in setupPipelineEnvironment - // Reset it to null to workaround the "Argument list too long" error - globalVars[CACHED_CHANGED_FILE_LIST] = null + // Remove it to workaround the "Argument list too long" error + globalVars.remove(CACHED_CHANGED_FILE_LIST) launchStages(this, reuseBuild, testFilter, enableFailFast, globalVars) } } diff --git a/scripts/build_wheel.py b/scripts/build_wheel.py index db8931c3e621..7d2e34aeae44 100755 --- a/scripts/build_wheel.py +++ b/scripts/build_wheel.py @@ -728,7 +728,20 @@ def main(*, clear_folder(cache_dir) install_file = copy - install_tree = copytree + + # Wrapper for copytree that checks if source and destination are the same + def safe_copytree(src, dst, dirs_exist_ok=True): + """Copy tree, but skip if source and destination resolve to the same directory.""" + src_path = Path(src).resolve() + dst_path = Path(dst).resolve() + if src_path == dst_path: + # Source and destination are the same, skip copying + return + if dst_path.exists() and dirs_exist_ok: + rmtree(dst_path) + copytree(src_path, dst_path, dirs_exist_ok=dirs_exist_ok) + + install_tree = safe_copytree if skip_building_wheel and linking_install_binary: def symlink_remove_dst(src, dst): @@ -756,6 +769,63 @@ def symlink_remove_dst_tree(src, dst, dirs_exist_ok=True): install_tree(get_source_dir() / "include" / "tensorrt_llm" / "deep_gemm", include_dir / "deep_gemm", dirs_exist_ok=True) + + # Copy FMHA kernel generation headers for JIT compilation + fmha_build_dir = build_dir / "tensorrt_llm" / "kernels" / "trtllmGenKernels" / "fmha" + fmha_include_dir = include_dir / "trtllm_gen_kernels" / "fmha" + if fmha_build_dir.exists(): + fmha_include_dir.mkdir(parents=True, exist_ok=True) + + # Helper function to resolve symlinks and copy actual content + def copy_resolving_symlink(src_path, dst_path): + """Copy file or directory, resolving symlinks to copy actual content.""" + if src_path.is_symlink(): + resolved_src = src_path.resolve() + else: + resolved_src = src_path + + if resolved_src.is_dir(): + if dst_path.exists(): + rmtree(dst_path) + # Use symlinks=False (default) to follow symlinks and copy actual content + # This ensures nested symlinks are also resolved + copytree(resolved_src, dst_path, symlinks=False) + else: + if dst_path.is_dir(): + dst_path = dst_path / src_path.name + copy(resolved_src, dst_path) + + # Copy cuda_ptx directory (actual directory, not symlink) + cuda_ptx_src = fmha_build_dir / "cuda_ptx" + if cuda_ptx_src.exists(): + copy_resolving_symlink(cuda_ptx_src, fmha_include_dir / "cuda_ptx") + + # Copy cutlass (symlink, need to resolve) + cutlass_src = fmha_build_dir / "cutlass" + if cutlass_src.exists(): + copy_resolving_symlink(cutlass_src, fmha_include_dir / "cutlass") + + # Copy trtllm directory (contains dev symlink) + trtllm_src = fmha_build_dir / "trtllm" + if trtllm_src.exists(): + copy_resolving_symlink(trtllm_src, fmha_include_dir / "trtllm") + + # Copy cuda (symlink, need to resolve) + cuda_src = fmha_build_dir / "cuda" + if cuda_src.exists(): + copy_resolving_symlink(cuda_src, fmha_include_dir / "cuda") + + # Copy KernelParams.h (actual file) + kernel_params_src = fmha_build_dir / "KernelParams.h" + if kernel_params_src.exists(): + copy(kernel_params_src, fmha_include_dir / "KernelParams.h") + + # Copy KernelParamsDecl.h (actual file) + kernel_params_decl_src = fmha_build_dir / "KernelParamsDecl.h" + if kernel_params_decl_src.exists(): + copy(kernel_params_decl_src, + fmha_include_dir / "KernelParamsDecl.h") + required_cuda_headers = [ "cuda_fp16.h", "cuda_fp16.hpp", "cuda_bf16.h", "cuda_bf16.hpp", "cuda_fp8.h", "cuda_fp8.hpp"