[None][feat] bias for FP4 TRT-LLM Gen MoE (#9220)

Signed-off-by: Nikita Korobov <[email protected]>

Author: nekorobov

cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/GemmOptions.h

@@ -1623,8 +1623,8 @@ inline CUresult loadCubinData(CUmodule* module, Config const& config)
     // Trtllm links the cubin into the executable while Flashinfer loads the cubin from storage.
 #ifdef TLLM_GEN_EXPORT_FLASHINFER
 #ifdef TLLM_GEN_GEMM_CUBIN_PATH
-    static const std::string tllm_gen_gemm_cubin_path = std::string(TLLM_GEN_GEMM_CUBIN_PATH);
-    const std::string sha256 = config.mHash ? config.mHash : "";
+    static std::string const tllm_gen_gemm_cubin_path = std::string(TLLM_GEN_GEMM_CUBIN_PATH);
+    std::string const sha256 = config.mHash ? config.mHash : "";
     std::string fileName = config.mFunctionName;
     if (!fileName.empty())
     {

cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/KernelMetaInfo.h

@@ -224,7 +224,7 @@ static auto makeTmaShapeStrideAbc(GemmOptions const& options, int sizeM, int siz
 
 // Create the TMA shape/stride for A/B block scaling factors.
 static auto makeTmaShapeStrideSfAb(int mM, int mN, int mK, MatrixType matrixType, int tileM, int tileN, int tileK,
-    tg::SfLayout layout, int sfReshapeFactor, const int32_t numEltsPerSf)
+    tg::SfLayout layout, int sfReshapeFactor, int32_t const numEltsPerSf)
 {
 
     // The outer dimension.

cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/KernelParams.h

@@ -39,7 +39,8 @@
             "dtypeA": "e2m1",
             "dtypeC": "e2m1",
             "mmaK": 64,
-            "tileK": 512
+            "tileK": 512,
+            "biasType": "m"
         },
         "BatchedGemmFp4LowLatency": {
             "_template": "BatchedGemmFp4Base",
@@ -53,8 +54,7 @@
             "mmaM": 256,
             "clusterDimX": 2,
             "sfLayoutB": "128x4",
-            "sfLayoutC": "128x4",
-            "biasType": "m"
+            "sfLayoutC": "128x4"
         },
 
         "BatchedGemmPerTensorScalingFp8Base": {
@@ -156,7 +156,6 @@
             "dtypeB": "e4m3",
             "dtypeMmaA": "e4m3",
             "sfBlockSizeA": 32,
-            "biasType": "m",
             "act": "swiglu"
         }
     },

cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/config.json

@@ -1,3 +1,3 @@
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-size 636234
+oid sha256:576f67d83e31ec7ffc09187a24c64f60159793502f4e14a1badbb1fa0ea03f23
+size 591981

cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/cubins/Bmm_Bfloat16_E2m1E2m1_Fp32_t128x128x256_s6_et128x128_m256x128x64_cga2x1x1_16dp256b_rM_TN_transOut_schedP2x1x2x3_biasM_bN_tmaOpt_clmp_dynBatch_sm100f_cubin.cpp

@@ -1,3 +1,3 @@
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cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/cubins/Bmm_Bfloat16_E2m1E2m1_Fp32_t128x128x256u2_s6_et128x128_m256x128x64_cga2x1x1_16dp256b_rM_TN_transOut_schedP2x1x2x3_biasM_bN_tmaOpt_clmp_dynBatch_sm100f_cubin.cpp

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/cubins/Bmm_Bfloat16_E2m1E2m1_Fp32_t128x16x256_s9_et128x16_m128x16x64_cga1x1x1_16dp256b_rM_TN_transOut_schedP2x1x2x3_bN_tmaOpt_clmp_dynBatch_sm100f_cubin.cpp

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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