remove github actions we can't run

disable unneeded github actions for this repo

remove broken submodules

disable unneeded github actions for this repo

remove broken submodules

cores/fround/hdl/jt00778x.v: either none or all wires need to be init…

cores/fround/hdl/jt00778x.v: either none or all wires need to be init…

cores/fround/hdl/jt00778x.v: fix missing init for vivado

cores/fround/hdl/jt00778x.v: fix missing init for vivado

cores/fround/hdl/jt00778x.v: fix missing init for vivado

cores/fround/hdl/jt00778x.v: fix missing init for vivado

cores/fround/hdl/jt00778x.v: fix missing init for vivado

use ODDR for 180 degree SDRAM phase shift

use ODDR for 180 degree SDRAM phase shift

fix missing begin/end in verilog functions for vivado

fix missing begin/end in verilog functions for vivado

mistex remove JTFRAME_MR_DDRLOAD for cps2

updates macros.def for mistex target

fix vivado compatibility of cores/1942/hdl/jt1942_sound.v

fix vivado compatibility of cores/1942/hdl/jt1942_sound.v

implement mistex target, many thanks to @somhi for porting it

implement mistex target

Merge branch 'merge-master'

mistex - update cyclone iv plls, remove jtframe_emu

jtframe_pll6671_0002-xilinx7.v: fix CLKOUT1/2 divisors

jtframe_pll6671_0002-xilinx7.v: fix DIVCLK_DIVIDE

jtframe_pll6671_0002-xilinx7.v: Use a second PLL to generate output 4…

arrays are used zero based, then they need to be declared as zero based

fix xilinx jotego PLLs

mistex target pll update for quartus and changes for Vivado