diff --git a/deploy/packaging/debian/htsdevices.noarch b/deploy/packaging/debian/htsdevices.noarch index 552515a0e4..d759d2c483 100644 --- a/deploy/packaging/debian/htsdevices.noarch +++ b/deploy/packaging/debian/htsdevices.noarch @@ -1,7 +1,7 @@ ./usr/local/mdsplus/pydevices/HtsDevices/_version.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_423st.py -./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435sc.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_423tr.py +./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435sc.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435st.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435tr.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_WRPG.py diff --git a/deploy/packaging/debian/rfxdevices.noarch b/deploy/packaging/debian/rfxdevices.noarch index 27f5fc35ab..a8d29340d7 100644 --- a/deploy/packaging/debian/rfxdevices.noarch +++ b/deploy/packaging/debian/rfxdevices.noarch @@ -108,6 +108,7 @@ ./usr/local/mdsplus/pydevices/RfxDevices/RFXWAVESETUP.py ./usr/local/mdsplus/pydevices/RfxDevices/RFX_PROTECTIONS.py ./usr/local/mdsplus/pydevices/RfxDevices/RFX_RPADC.py +./usr/local/mdsplus/pydevices/RfxDevices/RFX_RPDAC.py ./usr/local/mdsplus/pydevices/RfxDevices/SIG_SNAPSHOT.py ./usr/local/mdsplus/pydevices/RfxDevices/SIS3820.py ./usr/local/mdsplus/pydevices/RfxDevices/SOFT_TRIGGER.py diff --git a/deploy/packaging/redhat/htsdevices.noarch b/deploy/packaging/redhat/htsdevices.noarch index 3817d60015..614814bb2a 100644 --- a/deploy/packaging/redhat/htsdevices.noarch +++ b/deploy/packaging/redhat/htsdevices.noarch @@ -1,8 +1,8 @@ ./usr/local/mdsplus/pydevices/HtsDevices ./usr/local/mdsplus/pydevices/HtsDevices/_version.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_423st.py -./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435sc.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_423tr.py +./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435sc.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435st.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_435tr.py ./usr/local/mdsplus/pydevices/HtsDevices/acq2106_WRPG.py diff --git a/deploy/packaging/redhat/rfxdevices.noarch b/deploy/packaging/redhat/rfxdevices.noarch index cf3c3ef3df..0a6ae2dc79 100644 --- a/deploy/packaging/redhat/rfxdevices.noarch +++ b/deploy/packaging/redhat/rfxdevices.noarch @@ -109,6 +109,7 @@ ./usr/local/mdsplus/pydevices/RfxDevices/RFXWAVESETUP.py ./usr/local/mdsplus/pydevices/RfxDevices/RFX_PROTECTIONS.py ./usr/local/mdsplus/pydevices/RfxDevices/RFX_RPADC.py +./usr/local/mdsplus/pydevices/RfxDevices/RFX_RPDAC.py ./usr/local/mdsplus/pydevices/RfxDevices/SIG_SNAPSHOT.py ./usr/local/mdsplus/pydevices/RfxDevices/SIS3820.py ./usr/local/mdsplus/pydevices/RfxDevices/SOFT_TRIGGER.py diff --git a/device_support/redpitaya/Makefile b/device_support/redpitaya/Makefile index 4b6e68d0e9..37461390c1 100755 --- a/device_support/redpitaya/Makefile +++ b/device_support/redpitaya/Makefile @@ -5,7 +5,7 @@ CFLAGS = -fPIC -std=c++11 -o2 -Wall -DLINUX -I${MDSPLUS_DIR}/include -I. LDFLAGS = -L${MDSPLUS_DIR}/lib -lpthread -lMdsObjectsCppShr -SOURCES=redpitaya.cpp AsyncStoreManager.cpp +SOURCES=redpitaya.cpp AsyncStoreManager.cpp redpitaya_dac.cpp OBJECTS=$(SOURCES:.cpp=.o) SHAREDLIB=libredpitaya.so EXE=test diff --git a/device_support/redpitaya/redpitaya.cpp b/device_support/redpitaya/redpitaya.cpp index f808f31883..42050d88d5 100644 --- a/device_support/redpitaya/redpitaya.cpp +++ b/device_support/redpitaya/redpitaya.cpp @@ -97,8 +97,6 @@ static void writeConfig(int fd, struct rpadc_configuration *config) regs.post_register_enable = 1; regs.post_register = config->post_samples; - regs.trig_event_code_enable = 1; - regs.trig_event_code = config->event_code; regs.decimator_register_enable = 1; @@ -184,7 +182,6 @@ static void readConfig(int fd, struct rpadc_configuration *config) config->post_samples = regs.post_register; config->pre_samples = regs.pre_register; config->decimation = regs.decimator_register + 1; - config->event_code = regs.trig_event_code; } static void fifoFlush(int fd) { ioctl(fd, RFX_STREAM_FIFO_FLUSH, NULL); } diff --git a/device_support/redpitaya/redpitaya_dac.cpp b/device_support/redpitaya/redpitaya_dac.cpp new file mode 100644 index 0000000000..20e83b5ae4 --- /dev/null +++ b/device_support/redpitaya/redpitaya_dac.cpp @@ -0,0 +1,255 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern "C" { + int rpdacInit(int useExtClk, int useExtTrig, double clockFreq, int numPoints1, double *Y1, double *X1, int numPoints2, double *Y2, double *X2); + void rpdacTrigger(); + void rpdacStop(); +} + + +static int fd; + +//Prepare arrays to be enqueued in FPGA FIFO. It is assumed that both inTimes1 and inTimes2 start with time 0 +static int convertInputs(double clockPeriod, int numPoints1, double *inValues1, double *inTimes1, int numPoints2, double *inValues2, double *inTimes2, + double *outStart1, double *outStart2, double *stepVals1, double *stepVals2, int *outSteps) +{ + int outIdx = 0, inIdx1 = 0, inIdx2 = 0, numOutPoints, i; + double outTimes[numPoints1 + numPoints2]; + + while(inIdx1 < numPoints1 || inIdx2 < numPoints2) + { + if(inIdx1 < numPoints1 && inIdx2 < numPoints2) + { + if(inTimes1[inIdx1] == inTimes2[inIdx2]) + { + outStart1[outIdx] = inValues1[inIdx1]; + outStart2[outIdx] = inValues2[inIdx2]; + outTimes[outIdx] = inTimes1[inIdx1]; + inIdx1++; + inIdx2++; + } + else if (inTimes1[inIdx1] < inTimes2[inIdx2]) + { + outStart1[outIdx] = inValues1[inIdx1]; + outStart2[outIdx] = inValues2[inIdx2-1] + (inTimes1[inIdx1] - inTimes2[inIdx2 - 1])*(inValues2[inIdx2] - inValues2[inIdx2-1])/(inTimes2[inIdx2] - inTimes2[inIdx2-1]); + outTimes[outIdx] = inTimes1[inIdx1]; + inIdx1++; + } + else //(inTimes1[inIdx1] > inTimes2[inIdx2]) + { + outStart2[outIdx] = inValues2[inIdx2]; + outStart1[outIdx] = inValues1[inIdx1-1] + (inTimes2[inIdx2] - inTimes1[inIdx2 - 1])*(inValues1[inIdx1] - inValues1[inIdx1-1])/(inTimes1[inIdx1] - inTimes1[inIdx1-1]); + outTimes[outIdx] = inTimes2[inIdx2]; + inIdx2++; + } + } + else if(inIdx1 < numPoints1) + { + outStart1[outIdx] = inValues1[inIdx1]; + outStart2[outIdx] = outStart2[outIdx - 1]; + outTimes[outIdx] = inTimes1[inIdx1]; + inIdx1++; + } + else //(inIdx2 < numPoints2) + { + outStart2[outIdx] = inValues2[inIdx2]; + outStart1[outIdx] = outStart1[outIdx - 1]; + outTimes[outIdx] = inTimes2[inIdx2]; + inIdx2++; + } + outIdx++; + } + + + numOutPoints = outIdx; + for(outIdx = 0; outIdx < numOutPoints - 1; outIdx++) + { + outSteps[outIdx] = (int)((outTimes[outIdx + 1] - outTimes[outIdx])/clockPeriod); + if(outSteps[outIdx] < 1) + outSteps[outIdx] = 1; + stepVals1[outIdx] = (outStart1[outIdx + 1] - outStart1[outIdx]); + stepVals2[outIdx] = (outStart2[outIdx + 1] - outStart2[outIdx]); + } + outSteps[numOutPoints - 1] = 2; //Just two clock perios to force last value + stepVals1[numOutPoints - 1] = 0; + stepVals2[numOutPoints - 1] = 0; + for(outIdx = 0; outIdx < numOutPoints; outIdx++) + { + outStart1[outIdx] = 8192 - (outStart1[outIdx] * 8192); + outStart2[outIdx] = 8192 - (outStart2[outIdx] * 8192); + if(outStart1[outIdx] < 0) + outStart1[outIdx] = 0; + if(outStart2[outIdx] < 0) + outStart2[outIdx] = 0; + if(outStart1[outIdx] > 16383) + outStart1[outIdx] = 16383; + if(outStart2[outIdx] > 16383) + outStart2[outIdx] = 16383; + stepVals1[outIdx] = -stepVals1[outIdx] * 8192; + stepVals2[outIdx] = -stepVals2[outIdx] * 8192; + } + return numOutPoints; +} + +int rpdacInit(int useExtClk, int useExtTrig, double clockFreq, int numPoints1, double *Y1, double *X1, int numPoints2, double *Y2, double *X2) +{ + //Make sure that time 0 is included in X1 and X1. If not add point at 0 with the same value of the first point + double intY1[numPoints1+1], intY2[numPoints2+1], intX1[numPoints1 + 1], intX2[numPoints2 + 1]; + int actPoints1, actPoints2; + unsigned int clockDivReg = 0, modeReg = 0, commandReg = 0, reg, i; + unsigned long long currLongVal; + + double stepVals1[numPoints1+numPoints2 + 2], stepVals2[numPoints1+numPoints2 + 2], startVals1[numPoints1+numPoints2 + 2], startVals2[numPoints1+numPoints2 + 2]; + int steps[numPoints1+numPoints2 + 2]; + int numSteps; + + if(X1[0] == 0) + { + actPoints1 = numPoints1; + memcpy(intX1, X1, numPoints1 * sizeof(double)); + memcpy(intY1, Y1, numPoints1 * sizeof(double)); + } + else + { + actPoints1 = numPoints1 + 1; + intX1[0] = 0; + intY1[0] = Y1[0]; + memcpy(&intX1[1], X1, numPoints1 * sizeof(double)); + memcpy(&intY1[1], Y1, numPoints1 * sizeof(double)); + } + if(X2[0] == 0) + { + actPoints2 = numPoints2; + memcpy(intX2, X2, numPoints2 * sizeof(double)); + memcpy(intY2, Y2, numPoints2 * sizeof(double)); + } + else + { + actPoints2 = numPoints2 + 1; + intX2[0] = 0; + intY2[0] = Y2[0]; + memcpy(&intX2[1], X2, numPoints2 * sizeof(double)); + memcpy(&intY2[1], Y2, numPoints2 * sizeof(double)); + } + fd = open("/dev/rfx_dac", O_RDWR | O_SYNC); + if(fd < 0) + { + printf("Cannot open device!\n"); + return fd; + } + printf("Device Open %d\n", fd); + + modeReg = 0; + if(useExtClk) + { + modeReg |= 0x2; + clockDivReg = 1; + } + else + { + clockDivReg = (int)(125E6/clockFreq + 0.5); + printf("clockDivReg: %d\n", clockDivReg); + } + if(useExtTrig) + { + modeReg |= 0x1; + } + printf("Mode Reg.: %d\n", modeReg); + + //clear fifo + ioctl(fd, RFX_DAC_CLEAR_AXI_FIFO_MM_S_0, 0); + usleep(10000); + ioctl(fd, RFX_DAC_SET_CLOCK_DIVIDE_REG, &clockDivReg); + usleep(1000); + // trigger software mode + ioctl(fd, RFX_DAC_SET_MODE_REG, &modeReg); + usleep(1000); + + //stop + commandReg = 2; + ioctl(fd, RFX_DAC_SET_CMD_REG, &commandReg); + usleep(1000); + + //Arm + commandReg = 4; + ioctl(fd, RFX_DAC_SET_CMD_REG, &commandReg); + usleep(1000); + + + + numSteps = convertInputs(1./clockFreq, actPoints1, intY1, intX1, actPoints2, intY2, intX2, startVals1, startVals2, stepVals1, stepVals2, steps); + + + printf("NUM STEPS: %d\n", numSteps); + for(i = 0; i < numSteps; i++) + { + printf("startVal1 = %f\tstartVal2 = %f\tstepVal1 = %f\tstepVal2 = %f\tstep = %d\n", startVals1[i], startVals2[i], stepVals1[i], stepVals2[i], steps[i]); + } + + + + + //prepare FIFO + for(i = 0; i < numSteps; i++) + { + //Start ch 1-2 + reg = (int)(startVals2[i])&0x0000FFFF; + reg |= ((int)(startVals1[i])<<16)&0xFFFF0000; + ioctl(fd, RFX_DAC_SET_AXI_FIFO_MM_S_0_VAL, ®); + usleep(1000); + + //Num Steps + reg = (unsigned int)(steps[i]); + // reg = (unsigned int)(0x0FFFFFFF); + ioctl(fd, RFX_DAC_SET_AXI_FIFO_MM_S_0_VAL, ®); + usleep(1000); + + //Step ch 1 + currLongVal = (long long)((stepVals2[i]/steps[i])*pow(2,50)); + reg = (unsigned int)(currLongVal & 0x00000000FFFFFFFF); + ioctl(fd, RFX_DAC_SET_AXI_FIFO_MM_S_0_VAL, ®); + usleep(1000); + reg = (unsigned int)((currLongVal & 0xFFFFFFFF00000000)>> 32); + ioctl(fd, RFX_DAC_SET_AXI_FIFO_MM_S_0_VAL, ®); + usleep(1000); + + //Step ch 2 + currLongVal = (long long)((stepVals1[i]/steps[i])*pow(2,50)); + reg = (unsigned int)(currLongVal & 0x00000000FFFFFFFF); + ioctl(fd, RFX_DAC_SET_AXI_FIFO_MM_S_0_VAL, ®); + usleep(1000); + reg = (unsigned int)((currLongVal & 0xFFFFFFFF00000000)>> 32); + ioctl(fd, RFX_DAC_SET_AXI_FIFO_MM_S_0_VAL, ®); + usleep(1000); + } + + return fd; +} + + +void rpdacTrigger() +{ + unsigned int commandReg = 1; + ioctl(fd, RFX_DAC_SET_CMD_REG, &commandReg); + usleep(1000); +} + +void rpdacStop() +{ + unsigned int commandReg = 2; + ioctl(fd, RFX_DAC_SET_CMD_REG, &commandReg); + usleep(1000); +} + + diff --git a/device_support/redpitaya/rfx_dac.h b/device_support/redpitaya/rfx_dac.h new file mode 100644 index 0000000000..a9150c793e --- /dev/null +++ b/device_support/redpitaya/rfx_dac.h @@ -0,0 +1,129 @@ +#ifndef RFX_DAC_H +#define RFX_DAC_H + + +#include +#include + + + +#ifdef __cplusplus +extern "C" { +#endif + +//Temporaneo +#define DMA_SOURCE 1 +//////////////// + + +#define DEVICE_NAME "rfx_dac" /* Dev name as it appears in /proc/devices */ +#define MODULE_NAME "rfx_dac" + +//Generic IOCTL commands + +#define RFX_DAC_IOCTL_BASE 'W' +#define RFX_DAC_ARM_DMA _IO(RFX_DAC_IOCTL_BASE, 1) +#define RFX_DAC_START_DMA _IO(RFX_DAC_IOCTL_BASE, 2) +#define RFX_DAC_STOP_DMA _IO(RFX_DAC_IOCTL_BASE, 3) +#define RFX_DAC_SET_DMA_BUFLEN _IO(RFX_DAC_IOCTL_BASE, 4) +#define RFX_DAC_GET_DMA_BUFLEN _IO(RFX_DAC_IOCTL_BASE, 5) +#define RFX_DAC_IS_DMA_RUNNING _IO(RFX_DAC_IOCTL_BASE, 6) +#define RFX_DAC_GET_DMA_DATA _IO(RFX_DAC_IOCTL_BASE, 7) +#define RFX_DAC_SET_DRIVER_BUFLEN _IO(RFX_DAC_IOCTL_BASE, 8) +#define RFX_DAC_GET_DRIVER_BUFLEN _IO(RFX_DAC_IOCTL_BASE, 9) +#define RFX_DAC_GET_REGISTERS _IO(RFX_DAC_IOCTL_BASE, 10) +#define RFX_DAC_SET_REGISTERS _IO(RFX_DAC_IOCTL_BASE, 11) +#define RFX_DAC_FIFO_INT_HALF_SIZE _IO(RFX_DAC_IOCTL_BASE, 12) +#define RFX_DAC_FIFO_INT_FIRST_SAMPLE _IO(RFX_DAC_IOCTL_BASE, 13) +#define RFX_DAC_FIFO_FLUSH _IO(RFX_DAC_IOCTL_BASE, 14) +#define RFX_DAC_START_READ _IO(RFX_DAC_IOCTL_BASE, 15) +#define RFX_DAC_STOP_READ _IO(RFX_DAC_IOCTL_BASE, 16) +#define RFX_DAC_GET_AXI_CFG_REGISTER_0 _IO(RFX_DAC_IOCTL_BASE, 20) +#define RFX_DAC_SET_AXI_CFG_REGISTER_0 _IO(RFX_DAC_IOCTL_BASE, 21) +#define RFX_DAC_GET_CLOCK_DIVIDE_REG _IO(RFX_DAC_IOCTL_BASE, 22) +#define RFX_DAC_SET_CLOCK_DIVIDE_REG _IO(RFX_DAC_IOCTL_BASE, 23) +#define RFX_DAC_GET_CMD_REG _IO(RFX_DAC_IOCTL_BASE, 24) +#define RFX_DAC_SET_CMD_REG _IO(RFX_DAC_IOCTL_BASE, 25) +#define RFX_DAC_GET_MODE_REG _IO(RFX_DAC_IOCTL_BASE, 26) +#define RFX_DAC_SET_MODE_REG _IO(RFX_DAC_IOCTL_BASE, 27) +#define RFX_DAC_GET_AXI_FIFO_MM_S_0_LEN _IO(RFX_DAC_IOCTL_BASE, 28) +#define RFX_DAC_GET_AXI_FIFO_MM_S_0_VAL _IO(RFX_DAC_IOCTL_BASE, 29) +#define RFX_DAC_SET_AXI_FIFO_MM_S_0_VAL _IO(RFX_DAC_IOCTL_BASE, 30) +#define RFX_DAC_CLEAR_AXI_FIFO_MM_S_0 _IO(RFX_DAC_IOCTL_BASE, 31) + + +#ifndef AXI_ENUMS_DEFINED +#define AXI_ENUMS_DEFINED +enum AxiStreamFifo_Register { + ISR = 0x00, ///< Interrupt Status Register (ISR) + IER = 0x04, ///< Interrupt Enable Register (IER) + TDFR = 0x08, ///< Transmit Data FIFO Reset (TDFR) + TDFV = 0x0c, ///< Transmit Data FIFO Vacancy (TDFV) + TDFD = 0x10, ///< Transmit Data FIFO 32-bit Wide Data Write Port + TDFD4 = 0x1000, ///< Transmit Data FIFO for AXI4 Data Write Port + TLR = 0x14, ///< Transmit Length Register (TLR) + RDFR = 0x18, ///< Receive Data FIFO reset (RDFR) + RDFO = 0x1c, ///< Receive Data FIFO Occupancy (RDFO) + RDFD = 0x20, ///< Receive Data FIFO 32-bit Wide Data Read Port (RDFD) + RDFD4 = 0x1000, ///< Receive Data FIFO for AXI4 Data Read Port (RDFD) + RLR = 0x24, ///< Receive Length Register (RLR) + SRR = 0x28, ///< AXI4-Stream Reset (SRR) + TDR = 0x2c, ///< Transmit Destination Register (TDR) + RDR = 0x30, ///< Receive Destination Register (RDR) + /// not supported yet .. /// + TID = 0x34, ///< Transmit ID Register + TUSER = 0x38, ///< Transmit USER Register + RID = 0x3c, ///< Receive ID Register + RUSER = 0x40 ///< Receive USER Register +}; + +enum AxiStreamFifo_ISREnum { + ISR_RFPE = 1 << 19, ///< Receive FIFO Programmable Empty + ISR_RFPF = 1 << 20, ///< Receive FIFO Programmable Full + ISR_TFPE = 1 << 21, ///< Transmit FIFO Programmable Empty + ISR_TFPF = 1 << 22, ///< Transmit FIFO Programmable Full + ISR_RRC = 1 << 23, ///< Receive Reset Complete + ISR_TRC = 1 << 24, ///< Transmit Reset Complete + ISR_TSE = 1 << 25, ///< Transmit Size Error + ISR_RC = 1 << 26, ///< Receive Complete + ISR_TC = 1 << 27, ///< Transmit Complete + ISR_TPOE = 1 << 28, ///< Transmit Packet Overrun Error + ISR_RPUE = 1 << 29, ///< Receive Packet Underrun Error + ISR_RPORE = 1 << 30, ///< Receive Packet Overrun Read Error + ISR_RPURE = 1 << 31, ///< Receive Packet Underrun Read Error +}; + +enum RegisterIdx { + FIFO_00_IDX = 0, + FIFO_01_IDX = 1, + FIFO_10_IDX = 2, + FIFO11_IDX = 3, + COMMAND_REG_IDX = 4, + PRE_POST_REG_IDX = 5, + DEC_REG_IDX = 6, + MODE_REG_IDX = 8 +}; +#endif + +#pragma pack(1) + +struct rfx_dac_registers +{ + char axi_cfg_register_0_enable; + unsigned int axi_cfg_register_0; + char clock_divide_reg_enable; + unsigned int clock_divide_reg; + char cmd_reg_enable; + unsigned int cmd_reg; + char mode_reg_enable; + unsigned int mode_reg; + +}; + + + +#ifdef __cplusplus +} +#endif + +#endif // RFX_DAC_H diff --git a/device_support/redpitaya/rfx_stream.h b/device_support/redpitaya/rfx_stream.h index 785c55f2e6..224c5b4d92 100644 --- a/device_support/redpitaya/rfx_stream.h +++ b/device_support/redpitaya/rfx_stream.h @@ -1,93 +1,110 @@ #ifndef RFX_STREAM_H #define RFX_STREAM_H + #include #include + + #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif //Temporaneo #define DMA_SOURCE 1 - //////////////// +//////////////// + -#define DEVICE_NAME "rfx_stream" /* Dev name as it appears in /proc/devices */ +#define DEVICE_NAME "rfx_stream" /* Dev name as it appears in /proc/devices */ #define MODULE_NAME "rfx_stream" - //Generic IOCTL commands - -#define RFX_STREAM_IOCTL_BASE 'W' -#define RFX_STREAM_ARM_DMA _IO(RFX_STREAM_IOCTL_BASE, 1) -#define RFX_STREAM_START_DMA _IO(RFX_STREAM_IOCTL_BASE, 2) -#define RFX_STREAM_STOP_DMA _IO(RFX_STREAM_IOCTL_BASE, 3) -#define RFX_STREAM_SET_DMA_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 4) -#define RFX_STREAM_GET_DMA_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 5) -#define RFX_STREAM_IS_DMA_RUNNING _IO(RFX_STREAM_IOCTL_BASE, 6) -#define RFX_STREAM_GET_DMA_DATA _IO(RFX_STREAM_IOCTL_BASE, 7) -#define RFX_STREAM_SET_DRIVER_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 8) -#define RFX_STREAM_GET_DRIVER_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 9) -#define RFX_STREAM_GET_REGISTERS _IO(RFX_STREAM_IOCTL_BASE, 10) -#define RFX_STREAM_SET_REGISTERS _IO(RFX_STREAM_IOCTL_BASE, 11) -#define RFX_STREAM_FIFO_INT_HALF_SIZE _IO(RFX_STREAM_IOCTL_BASE, 12) -#define RFX_STREAM_FIFO_INT_FIRST_SAMPLE _IO(RFX_STREAM_IOCTL_BASE, 13) -#define RFX_STREAM_FIFO_FLUSH _IO(RFX_STREAM_IOCTL_BASE, 14) -#define RFX_STREAM_START_READ _IO(RFX_STREAM_IOCTL_BASE, 15) -#define RFX_STREAM_STOP_READ _IO(RFX_STREAM_IOCTL_BASE, 16) -#define RFX_STREAM_GET_COMMAND_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 20) -#define RFX_STREAM_SET_COMMAND_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 21) -#define RFX_STREAM_GET_DECIMATOR_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 22) -#define RFX_STREAM_SET_DECIMATOR_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 23) -#define RFX_STREAM_GET_LEV_TRIG_COUNT _IO(RFX_STREAM_IOCTL_BASE, 24) -#define RFX_STREAM_SET_LEV_TRIG_COUNT _IO(RFX_STREAM_IOCTL_BASE, 25) -#define RFX_STREAM_GET_MODE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 26) -#define RFX_STREAM_SET_MODE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 27) -#define RFX_STREAM_GET_PACKETIZER _IO(RFX_STREAM_IOCTL_BASE, 28) -#define RFX_STREAM_SET_PACKETIZER _IO(RFX_STREAM_IOCTL_BASE, 29) -#define RFX_STREAM_GET_POST_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 30) -#define RFX_STREAM_SET_POST_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 31) -#define RFX_STREAM_GET_PRE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 32) -#define RFX_STREAM_SET_PRE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 33) -#define RFX_STREAM_GET_TRIG_EVENT_CODE _IO(RFX_STREAM_IOCTL_BASE, 34) -#define RFX_STREAM_SET_TRIG_EVENT_CODE _IO(RFX_STREAM_IOCTL_BASE, 35) -#define RFX_STREAM_GET_EVENT_CODE _IO(RFX_STREAM_IOCTL_BASE, 36) -#define RFX_STREAM_SET_EVENT_CODE _IO(RFX_STREAM_IOCTL_BASE, 37) -#define RFX_STREAM_GET_DATA_FIFO_LEN _IO(RFX_STREAM_IOCTL_BASE, 38) -#define RFX_STREAM_GET_DATA_FIFO_VAL _IO(RFX_STREAM_IOCTL_BASE, 39) -#define RFX_STREAM_CLEAR_DATA_FIFO _IO(RFX_STREAM_IOCTL_BASE, 40) -#define RFX_STREAM_GET_TIME_FIFO_LEN _IO(RFX_STREAM_IOCTL_BASE, 41) -#define RFX_STREAM_GET_TIME_FIFO_VAL _IO(RFX_STREAM_IOCTL_BASE, 42) -#define RFX_STREAM_CLEAR_TIME_FIFO _IO(RFX_STREAM_IOCTL_BASE, 43) +//Generic IOCTL commands + +#define RFX_STREAM_IOCTL_BASE 'W' +#define RFX_STREAM_ARM_DMA _IO(RFX_STREAM_IOCTL_BASE, 1) +#define RFX_STREAM_START_DMA _IO(RFX_STREAM_IOCTL_BASE, 2) +#define RFX_STREAM_STOP_DMA _IO(RFX_STREAM_IOCTL_BASE, 3) +#define RFX_STREAM_SET_DMA_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 4) +#define RFX_STREAM_GET_DMA_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 5) +#define RFX_STREAM_IS_DMA_RUNNING _IO(RFX_STREAM_IOCTL_BASE, 6) +#define RFX_STREAM_GET_DMA_DATA _IO(RFX_STREAM_IOCTL_BASE, 7) +#define RFX_STREAM_SET_DRIVER_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 8) +#define RFX_STREAM_GET_DRIVER_BUFLEN _IO(RFX_STREAM_IOCTL_BASE, 9) +#define RFX_STREAM_GET_REGISTERS _IO(RFX_STREAM_IOCTL_BASE, 10) +#define RFX_STREAM_SET_REGISTERS _IO(RFX_STREAM_IOCTL_BASE, 11) +#define RFX_STREAM_FIFO_INT_HALF_SIZE _IO(RFX_STREAM_IOCTL_BASE, 12) +#define RFX_STREAM_FIFO_INT_FIRST_SAMPLE _IO(RFX_STREAM_IOCTL_BASE, 13) +#define RFX_STREAM_FIFO_FLUSH _IO(RFX_STREAM_IOCTL_BASE, 14) +#define RFX_STREAM_START_READ _IO(RFX_STREAM_IOCTL_BASE, 15) +#define RFX_STREAM_STOP_READ _IO(RFX_STREAM_IOCTL_BASE, 16) +#define RFX_STREAM_GET_AUX_CFG_REG _IO(RFX_STREAM_IOCTL_BASE, 20) +#define RFX_STREAM_SET_AUX_CFG_REG _IO(RFX_STREAM_IOCTL_BASE, 21) +#define RFX_STREAM_GET_COMMAND_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 22) +#define RFX_STREAM_SET_COMMAND_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 23) +#define RFX_STREAM_GET_DECIMATOR_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 24) +#define RFX_STREAM_SET_DECIMATOR_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 25) +#define RFX_STREAM_GET_K1_REG _IO(RFX_STREAM_IOCTL_BASE, 26) +#define RFX_STREAM_SET_K1_REG _IO(RFX_STREAM_IOCTL_BASE, 27) +#define RFX_STREAM_GET_K2_REG _IO(RFX_STREAM_IOCTL_BASE, 28) +#define RFX_STREAM_SET_K2_REG _IO(RFX_STREAM_IOCTL_BASE, 29) +#define RFX_STREAM_GET_LEV_TRIG_COUNT _IO(RFX_STREAM_IOCTL_BASE, 30) +#define RFX_STREAM_SET_LEV_TRIG_COUNT _IO(RFX_STREAM_IOCTL_BASE, 31) +#define RFX_STREAM_GET_MODE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 32) +#define RFX_STREAM_SET_MODE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 33) +#define RFX_STREAM_GET_PACKETIZER _IO(RFX_STREAM_IOCTL_BASE, 34) +#define RFX_STREAM_SET_PACKETIZER _IO(RFX_STREAM_IOCTL_BASE, 35) +#define RFX_STREAM_GET_POST_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 36) +#define RFX_STREAM_SET_POST_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 37) +#define RFX_STREAM_GET_PRE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 38) +#define RFX_STREAM_SET_PRE_REGISTER _IO(RFX_STREAM_IOCTL_BASE, 39) +#define RFX_STREAM_GET_STEP_HI_REG _IO(RFX_STREAM_IOCTL_BASE, 40) +#define RFX_STREAM_SET_STEP_HI_REG _IO(RFX_STREAM_IOCTL_BASE, 41) +#define RFX_STREAM_GET_STEP_LO_REG _IO(RFX_STREAM_IOCTL_BASE, 42) +#define RFX_STREAM_SET_STEP_LO_REG _IO(RFX_STREAM_IOCTL_BASE, 43) +#define RFX_STREAM_GET_TIME_COMMAND_REG _IO(RFX_STREAM_IOCTL_BASE, 44) +#define RFX_STREAM_SET_TIME_COMMAND_REG _IO(RFX_STREAM_IOCTL_BASE, 45) +#define RFX_STREAM_GET_TIME_OFFSET_HI_REG _IO(RFX_STREAM_IOCTL_BASE, 46) +#define RFX_STREAM_SET_TIME_OFFSET_HI_REG _IO(RFX_STREAM_IOCTL_BASE, 47) +#define RFX_STREAM_GET_TIME_OFFSET_LO_REG _IO(RFX_STREAM_IOCTL_BASE, 48) +#define RFX_STREAM_SET_TIME_OFFSET_LO_REG _IO(RFX_STREAM_IOCTL_BASE, 49) +#define RFX_STREAM_GET_DATA_FIFO_LEN _IO(RFX_STREAM_IOCTL_BASE, 50) +#define RFX_STREAM_GET_DATA_FIFO_VAL _IO(RFX_STREAM_IOCTL_BASE, 51) +#define RFX_STREAM_CLEAR_DATA_FIFO _IO(RFX_STREAM_IOCTL_BASE, 52) +#define RFX_STREAM_GET_SYNC_FIFO_LEN _IO(RFX_STREAM_IOCTL_BASE, 53) +#define RFX_STREAM_GET_SYNC_FIFO_VAL _IO(RFX_STREAM_IOCTL_BASE, 54) +#define RFX_STREAM_CLEAR_SYNC_FIFO _IO(RFX_STREAM_IOCTL_BASE, 55) +#define RFX_STREAM_GET_TIME_FIFO_LEN _IO(RFX_STREAM_IOCTL_BASE, 56) +#define RFX_STREAM_GET_TIME_FIFO_VAL _IO(RFX_STREAM_IOCTL_BASE, 57) +#define RFX_STREAM_CLEAR_TIME_FIFO _IO(RFX_STREAM_IOCTL_BASE, 58) + #ifndef AXI_ENUMS_DEFINED #define AXI_ENUMS_DEFINED - enum AxiStreamFifo_Register - { - ISR = 0x00, ///< Interrupt Status Register (ISR) - IER = 0x04, ///< Interrupt Enable Register (IER) - TDFR = 0x08, ///< Transmit Data FIFO Reset (TDFR) - TDFV = 0x0c, ///< Transmit Data FIFO Vacancy (TDFV) - TDFD = 0x10, ///< Transmit Data FIFO 32-bit Wide Data Write Port +enum AxiStreamFifo_Register { + ISR = 0x00, ///< Interrupt Status Register (ISR) + IER = 0x04, ///< Interrupt Enable Register (IER) + TDFR = 0x08, ///< Transmit Data FIFO Reset (TDFR) + TDFV = 0x0c, ///< Transmit Data FIFO Vacancy (TDFV) + TDFD = 0x10, ///< Transmit Data FIFO 32-bit Wide Data Write Port TDFD4 = 0x1000, ///< Transmit Data FIFO for AXI4 Data Write Port - TLR = 0x14, ///< Transmit Length Register (TLR) - RDFR = 0x18, ///< Receive Data FIFO reset (RDFR) - RDFO = 0x1c, ///< Receive Data FIFO Occupancy (RDFO) - RDFD = 0x20, ///< Receive Data FIFO 32-bit Wide Data Read Port (RDFD) + TLR = 0x14, ///< Transmit Length Register (TLR) + RDFR = 0x18, ///< Receive Data FIFO reset (RDFR) + RDFO = 0x1c, ///< Receive Data FIFO Occupancy (RDFO) + RDFD = 0x20, ///< Receive Data FIFO 32-bit Wide Data Read Port (RDFD) RDFD4 = 0x1000, ///< Receive Data FIFO for AXI4 Data Read Port (RDFD) - RLR = 0x24, ///< Receive Length Register (RLR) - SRR = 0x28, ///< AXI4-Stream Reset (SRR) - TDR = 0x2c, ///< Transmit Destination Register (TDR) - RDR = 0x30, ///< Receive Destination Register (RDR) + RLR = 0x24, ///< Receive Length Register (RLR) + SRR = 0x28, ///< AXI4-Stream Reset (SRR) + TDR = 0x2c, ///< Transmit Destination Register (TDR) + RDR = 0x30, ///< Receive Destination Register (RDR) /// not supported yet .. /// - TID = 0x34, ///< Transmit ID Register - TUSER = 0x38, ///< Transmit USER Register - RID = 0x3c, ///< Receive ID Register - RUSER = 0x40 ///< Receive USER Register - }; - - enum AxiStreamFifo_ISREnum - { + TID = 0x34, ///< Transmit ID Register + TUSER = 0x38, ///< Transmit USER Register + RID = 0x3c, ///< Receive ID Register + RUSER = 0x40 ///< Receive USER Register +}; + +enum AxiStreamFifo_ISREnum { ISR_RFPE = 1 << 19, ///< Receive FIFO Programmable Empty ISR_RFPF = 1 << 20, ///< Receive FIFO Programmable Full ISR_TFPE = 1 << 21, ///< Transmit FIFO Programmable Empty @@ -101,10 +118,9 @@ extern "C" ISR_RPUE = 1 << 29, ///< Receive Packet Underrun Error ISR_RPORE = 1 << 30, ///< Receive Packet Overrun Read Error ISR_RPURE = 1 << 31, ///< Receive Packet Underrun Read Error - }; +}; - enum RegisterIdx - { +enum RegisterIdx { FIFO_00_IDX = 0, FIFO_01_IDX = 1, FIFO_10_IDX = 2, @@ -113,32 +129,47 @@ extern "C" PRE_POST_REG_IDX = 5, DEC_REG_IDX = 6, MODE_REG_IDX = 8 - }; +}; #endif #pragma pack(1) - struct rfx_stream_registers - { - char command_register_enable; - unsigned int command_register; - char decimator_register_enable; - unsigned int decimator_register; - char lev_trig_count_enable; - unsigned int lev_trig_count; - char mode_register_enable; - unsigned int mode_register; - char packetizer_enable; - unsigned int packetizer; - char post_register_enable; - unsigned int post_register; - char pre_register_enable; - unsigned int pre_register; - char trig_event_code_enable; - unsigned int trig_event_code; - char event_code_enable; - unsigned int event_code; - }; +struct rfx_stream_registers +{ + char aux_cfg_reg_enable; + unsigned int aux_cfg_reg; + char command_register_enable; + unsigned int command_register; + char decimator_register_enable; + unsigned int decimator_register; + char k1_reg_enable; + unsigned int k1_reg; + char k2_reg_enable; + unsigned int k2_reg; + char lev_trig_count_enable; + unsigned int lev_trig_count; + char mode_register_enable; + unsigned int mode_register; + char packetizer_enable; + unsigned int packetizer; + char post_register_enable; + unsigned int post_register; + char pre_register_enable; + unsigned int pre_register; + char step_hi_reg_enable; + unsigned int step_hi_reg; + char step_lo_reg_enable; + unsigned int step_lo_reg; + char time_command_reg_enable; + unsigned int time_command_reg; + char time_offset_hi_reg_enable; + unsigned int time_offset_hi_reg; + char time_offset_lo_reg_enable; + unsigned int time_offset_lo_reg; + +}; + + #ifdef __cplusplus } diff --git a/java/jdevices/src/main/java/RFX_RPDACSetup.java b/java/jdevices/src/main/java/RFX_RPDACSetup.java new file mode 100644 index 0000000000..bb5e4914ee --- /dev/null +++ b/java/jdevices/src/main/java/RFX_RPDACSetup.java @@ -0,0 +1,176 @@ +/* + * To change this license header, choose License Headers in Project Properties. + * To change this template file, choose Tools | Templates + * and open the template in the editor. + */ + +/** + * + * @author mdsplus + */ +public class RFX_RPDACSetup extends DeviceSetup { + + /** + * Creates new form RFX_RPDACSetup + */ + public RFX_RPDACSetup() { + initComponents(); + } + + /** + * This method is called from within the constructor to initialize the form. + * WARNING: Do NOT modify this code. The content of this method is always + * regenerated by the Form Editor. + */ + @SuppressWarnings("unchecked") + // //GEN-BEGIN:initComponents + private void initComponents() { + + deviceButtons1 = new DeviceButtons(); + jPanel2 = new javax.swing.JPanel(); + jPanel4 = new javax.swing.JPanel(); + deviceField6 = new DeviceField(); + deviceDispatch1 = new DeviceDispatch(); + jPanel6 = new javax.swing.JPanel(); + deviceChoice1 = new DeviceChoice(); + deviceChoice2 = new DeviceChoice(); + jPanel5 = new javax.swing.JPanel(); + deviceField1 = new DeviceField(); + deviceField7 = new DeviceField(); + jPanel1 = new javax.swing.JPanel(); + jPanel3 = new javax.swing.JPanel(); + jPanel7 = new javax.swing.JPanel(); + deviceField2 = new DeviceField(); + jPanel8 = new javax.swing.JPanel(); + deviceField3 = new DeviceField(); + jPanel9 = new javax.swing.JPanel(); + jPanel10 = new javax.swing.JPanel(); + deviceField4 = new DeviceField(); + jPanel11 = new javax.swing.JPanel(); + deviceField5 = new DeviceField(); + + setDeviceProvider("localhost:8100"); + setDeviceTitle("RedPitaya DAC"); + setDeviceType("RFX_RPDAC"); + setHeight(400); + setWidth(600); + getContentPane().add(deviceButtons1, java.awt.BorderLayout.PAGE_END); + + jPanel2.setLayout(new java.awt.GridLayout(3, 1)); + + deviceField6.setIdentifier(""); + deviceField6.setLabelString("Comment: "); + deviceField6.setNumCols(20); + deviceField6.setOffsetNid(1); + jPanel4.add(deviceField6); + jPanel4.add(deviceDispatch1); + + jPanel2.add(jPanel4); + + deviceChoice1.setChoiceItems(new String[] {"INTERNAL", "EXTERNAL"}); + deviceChoice1.setIdentifier(""); + deviceChoice1.setLabelString("Clock Mode"); + deviceChoice1.setOffsetNid(3); + deviceChoice1.setUpdateIdentifier(""); + jPanel6.add(deviceChoice1); + + deviceChoice2.setChoiceItems(new String[] {"INTERNAL", "EXTERNAL"}); + deviceChoice2.setIdentifier(""); + deviceChoice2.setLabelString("Trig. Mode: "); + deviceChoice2.setOffsetNid(4); + deviceChoice2.setUpdateIdentifier(""); + jPanel6.add(deviceChoice2); + + jPanel2.add(jPanel6); + + deviceField1.setIdentifier(""); + deviceField1.setLabelString("Clock Freq."); + deviceField1.setNumCols(15); + deviceField1.setOffsetNid(2); + jPanel5.add(deviceField1); + + deviceField7.setIdentifier(""); + deviceField7.setLabelString("Trig. Time"); + deviceField7.setNumCols(15); + deviceField7.setOffsetNid(5); + jPanel5.add(deviceField7); + + jPanel2.add(jPanel5); + + getContentPane().add(jPanel2, java.awt.BorderLayout.PAGE_START); + + jPanel1.setLayout(new java.awt.GridLayout(2, 1)); + + jPanel3.setBorder(javax.swing.BorderFactory.createTitledBorder("Channnel 1")); + jPanel3.setLayout(new java.awt.GridLayout(2, 1)); + + deviceField2.setIdentifier(""); + deviceField2.setLabelString("X Values"); + deviceField2.setNumCols(30); + deviceField2.setOffsetNid(6); + jPanel7.add(deviceField2); + + jPanel3.add(jPanel7); + + deviceField3.setIdentifier(""); + deviceField3.setLabelString("Y Values: "); + deviceField3.setNumCols(30); + deviceField3.setOffsetNid(7); + jPanel8.add(deviceField3); + + jPanel3.add(jPanel8); + + jPanel1.add(jPanel3); + + jPanel9.setBorder(javax.swing.BorderFactory.createTitledBorder("Channnel 2")); + jPanel9.setLayout(new java.awt.GridLayout(2, 1)); + + deviceField4.setIdentifier(""); + deviceField4.setLabelString("X Values"); + deviceField4.setNumCols(30); + deviceField4.setOffsetNid(8); + jPanel10.add(deviceField4); + + jPanel9.add(jPanel10); + + deviceField5.setIdentifier(""); + deviceField5.setLabelString("Y Values: "); + deviceField5.setNumCols(30); + deviceField5.setOffsetNid(9); + jPanel11.add(deviceField5); + + jPanel9.add(jPanel11); + + jPanel1.add(jPanel9); + + getContentPane().add(jPanel1, java.awt.BorderLayout.CENTER); + + getAccessibleContext().setAccessibleName(""); + }// //GEN-END:initComponents + + + // Variables declaration - do not modify//GEN-BEGIN:variables + private DeviceButtons deviceButtons1; + private DeviceChoice deviceChoice1; + private DeviceChoice deviceChoice2; + private DeviceDispatch deviceDispatch1; + private DeviceField deviceField1; + private DeviceField deviceField2; + private DeviceField deviceField3; + private DeviceField deviceField4; + private DeviceField deviceField5; + private DeviceField deviceField6; + private DeviceField deviceField7; + private javax.swing.JPanel jPanel1; + private javax.swing.JPanel jPanel10; + private javax.swing.JPanel jPanel11; + private javax.swing.JPanel jPanel2; + private javax.swing.JPanel jPanel3; + private javax.swing.JPanel jPanel4; + private javax.swing.JPanel jPanel5; + private javax.swing.JPanel jPanel6; + private javax.swing.JPanel jPanel7; + private javax.swing.JPanel jPanel8; + private javax.swing.JPanel jPanel9; + // End of variables declaration//GEN-END:variables +} diff --git a/java/jdevices/src/main/resources/RFX_RPDACSetup.form b/java/jdevices/src/main/resources/RFX_RPDACSetup.form new file mode 100644 index 0000000000..353c64f49b --- /dev/null +++ b/java/jdevices/src/main/resources/RFX_RPDACSetup.form @@ -0,0 +1,228 @@ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pydevices/RfxDevices/RFX_RPDAC.py b/pydevices/RfxDevices/RFX_RPDAC.py new file mode 100644 index 0000000000..746d4af894 --- /dev/null +++ b/pydevices/RfxDevices/RFX_RPDAC.py @@ -0,0 +1,127 @@ + +from MDSplus import mdsExceptions, Device, Data, Event +from threading import Thread +from ctypes import CDLL, c_int, c_double, c_char_p, byref + + +class RFX_RPDAC(Device): + parts = [{'path': ':COMMENT', 'type': 'text'}, + {'path': ':CLOCK_FREQ', 'type': 'numeric', 'value': 1000}, + {'path': ':CLOCK_MODE', 'type': 'text', 'value': 'INTERNAL'}, + {'path': ':TRIG_MODE', 'type': 'text', 'value': 'INTERNAL'}, + {'path': ':TRIG_TIME', 'type': 'numeric', 'value': 0}, + {'path': ':CHAN1_X', 'type': 'numeric'}, + {'path': ':CHAN1_Y', 'type': 'numeric'}, + {'path': ':CHAN2_X', 'type': 'numeric'}, + {'path': ':CHAN2_Y', 'type': 'numeric'}, + {'path': ':INIT_ACTION', 'type': 'action', + 'valueExpr': "Action(Dispatch('RP_SERVER','PULSE_PREPARATION',50,None),Method(None,'init',head))", + 'options': ('no_write_shot',)}, + {'path': ':TRIG_ACTION', 'type': 'action', + 'valueExpr': "Action(Dispatch('RP_SERVER','INIT',60,None),Method(None,'trigger',head))", + 'options': ('no_write_shot',)}, + {'path': ':STOP_ACTION', 'type': 'action', + 'valueExpr': "Action(Dispatch('RP_SERVER','STORE',50,None),Method(None,'stop',head))", + 'options': ('no_write_shot',)}] + + + def init(self): + print('================= RPDAC Init ===============') + try: + self.lib = CDLL("libredpitaya.so") + print('library loaded') + except: + print('Cannot load redpitaya.so') + raise mdsExceptions.TclFAILED_ESSENTIAL + try: + if (self.clock_mode.data().upper() == 'INTERNAL'): + useExtClock = 0 + else: + useExtClock = 1 + except: + print('Cannot get clock_mode') + raise mdsExceptions.TclFAILED_ESSENTIAL + try: + if (self.trig_mode.data().upper() == 'INTERNAL'): + useExtTrigger = 0 + else: + useExtTrigger = 1 + except: + print('Cannot get trigger mode') + raise mdsExceptions.TclFAILED_ESSENTIAL + + try: + freq = self.clock_freq.data() + except: + print('Cannot get clock frequency') + raise mdsExceptions.TclFAILED_ESSENTIAL + try: + trigTime = self.trig_time.data() + except: + print('Cannot get trigger time') + raise mdsExceptions.TclFAILED_ESSENTIAL + try: + x1 = self.chan1_x.data().astype('float64') + x1 = x1 - trigTime + numX1 = len(x1) + except: + print('Cannot read Chan 1 X array') + raise mdsExceptions.TclFAILED_ESSENTIAL + try: + y1 = self.chan1_y.data().astype('float64') + numY1 = len(y1) + except: + print('Cannot read Chan 1 Y array') + raise mdsExceptions.TclFAILED_ESSENTIAL + if numX1 != numY1: + print('Different size for Chan 1 arrays') + raise mdsExceptions.TclFAILED_ESSENTIAL + try: + x2 = self.chan2_x.data().astype('float64') + x2 = x2 - trigTime + numX2 = len(x2) + except: + print('Cannot read Chan 2 X array') + raise mdsExceptions.TclFAILED_ESSENTIAL + try: + y2 = self.chan2_y.data().astype('float64') + numY2 = len(y2) + except: + print('Cannot read Chan 2 Y array') + raise mdsExceptions.TclFAILED_ESSENTIAL + if numX2 != numY2: + print('Different size for Chan 2 arrays') + raise mdsExceptions.TclFAILED_ESSENTIAL + + self.fd = self.lib.rpdacInit(c_int(useExtClock), c_int(useExtTrigger), + c_double(freq), + c_int(numX1), + (c_double * numX1)(*y1), + (c_double * numX1)(*x1), + c_int(numX2), + (c_double * numX2)(*y2), + (c_double * numX2)(*x2)) + + return + + + def trigger(self): + print('================= RPDAC Trigger ===============') + try: + self.lib = CDLL("libredpitaya.so") + print('library loaded') + except: + print('Cannot load redpitaya.so') + raise mdsExceptions.TclFAILED_ESSENTIAL + self.lib.rpdacTrigger(); + + def stop(self): + print('================= RPDAC Trigger ===============') + try: + self.lib = CDLL("libredpitaya.so") + print('library loaded') + except: + print('Cannot load redpitaya.so') + raise mdsExceptions.TclFAILED_ESSENTIAL + self.lib.rpdacStop(); +