From 98856b3e17c509d38c934d75c0d68801c97b39a7 Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Thu, 24 Jun 2021 20:03:26 -0400 Subject: [PATCH 1/7] Fix: Set the WRTD_TICKNS from loaded clock plan --- pydevices/HtsDevices/acq2106_WRTD.py | 58 +++++++++++++++++++++------- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/pydevices/HtsDevices/acq2106_WRTD.py b/pydevices/HtsDevices/acq2106_WRTD.py index 91cf6003ea..43a5d40d98 100644 --- a/pydevices/HtsDevices/acq2106_WRTD.py +++ b/pydevices/HtsDevices/acq2106_WRTD.py @@ -197,7 +197,29 @@ def init(self): uut = self.getUUT() # Sets WRTD TICKNS in nsecs: defined by 1/MBCLK - uut.cC.WRTD_TICKNS = self.wr_init_wrtd_tickns.data() + # We can take MBCLK from the name of the clock plan that is going to be used when + # the desired sample rate is set by the acq2106 device's INIT function. + # Quering sync_role() will give us the clock plan name (FIN): + # sync_role_query = uut.s0.sync_role + # clk_plan = sync_role_query.split('\n')[4] + # MBCLK = clk_plan.split(' ')[1] + + sys_clk_plan = uut.s0.SYS_CLK_CONFIG + MBCLK = sys_clk_plan.split(' ')[1] + + tonano = 1E9 + allowed_plans = {'31M25-5M12':(1./51200000)*tonano, '31M25-10M24':(1./10240000)*tonano, '31M25-20M48':(1./20480000)*tonano, + '31M25-32M768':(1./32768000)*tonano, '31M25-40M':25.0000, '31M25-20M':50.0000} + + # In TIGA systems the clock plan is 31M25-40M, but MBCLK = 10 MHz, and is set to WRTD_TICKNS = 100. + + if not self.is_tiga(): + if MBCLK in allowed_plans: + uut.cC.WRTD_TICKNS = allowed_plans.get(MBCLK) + self.wr_init_wrtd_tickns.record = allowed_plans.get(MBCLK) + else: + raise MDSplus.DevBAD_PARAMETER( + "MBCLK must be 5M12, 10M24, 20M48, 32M768, 31M25-40M or 31M25-20M; not %d" % (MBCLK,)) # Sets WR "safe time for broadcasts" the message, i.e. WRTT_TAI = TAI_TIME_NOW + WRTD_DELTA_NS uut.cC.WRTD_DELTA_NS = self.wr_init_wrtd_dns.data() @@ -228,20 +250,7 @@ def trig(self, msg=''): uut = self.getUUT() pg_slot = self.getDioSlot() - # Is the System a TIGA system? - # In embedded software there is also a command: - # /usr/local/bin/is_tiga - # - # it's not a knob and it's totally silent, it contains the following: - # #!/bin/sh - # [ -e /dev/acq400.0.knobs/wr_tai_trg_s1 ] && exit 0 - # exit 1 - # - # We can emulate that in HAPI the following way: - try: - is_tiga = uut.s0.wr_tai_trg_s1 is not None - except: - is_tiga = False + is_tiga = self.is_tiga() message = str(msg) @@ -284,6 +293,25 @@ def trig(self, msg=''): TRIG = trig + def is_tiga(self): + uut = self.getUUT() + # Is the System a TIGA system? + # In embedded software there is also a command: + # /usr/local/bin/is_tiga + # + # it's not a knob and it's totally silent, it contains the following: + # #!/bin/sh + # [ -e /dev/acq400.0.knobs/wr_tai_trg_s1 ] && exit 0 + # exit 1 + # + # We can emulate that in HAPI the following way: + try: + tiga = uut.s0.wr_tai_trg_s1 is not None + except: + tiga = False + + return tiga + def getUUT(self): import acq400_hapi uut = acq400_hapi.Acq2106(self.node.data(), has_wr=True) From c4c49b6df115741220973aeac4a59d8310857e2a Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Thu, 24 Jun 2021 20:21:38 -0400 Subject: [PATCH 2/7] Fix the value of the 5M12 frequency --- pydevices/HtsDevices/acq2106_WRTD.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/pydevices/HtsDevices/acq2106_WRTD.py b/pydevices/HtsDevices/acq2106_WRTD.py index 43a5d40d98..84b6301a43 100644 --- a/pydevices/HtsDevices/acq2106_WRTD.py +++ b/pydevices/HtsDevices/acq2106_WRTD.py @@ -100,7 +100,7 @@ class ACQ2106_WRTD(MDSplus.Device): { 'path': ':WR_INIT:WRTD_TICKNS', 'type': 'numeric', - 'value': 50, + 'value': 50.0, 'options': ('no_write_shot',) }, # 50msec - our "safe time for broadcast". From uut.cC.WRTD_DELTA_NS @@ -204,11 +204,12 @@ def init(self): # clk_plan = sync_role_query.split('\n')[4] # MBCLK = clk_plan.split(' ')[1] + # Or, it can be query by: sys_clk_plan = uut.s0.SYS_CLK_CONFIG MBCLK = sys_clk_plan.split(' ')[1] tonano = 1E9 - allowed_plans = {'31M25-5M12':(1./51200000)*tonano, '31M25-10M24':(1./10240000)*tonano, '31M25-20M48':(1./20480000)*tonano, + allowed_plans = {'31M25-5M12':(1./5120000)*tonano, '31M25-10M24':(1./10240000)*tonano, '31M25-20M48':(1./20480000)*tonano, '31M25-32M768':(1./32768000)*tonano, '31M25-40M':25.0000, '31M25-20M':50.0000} # In TIGA systems the clock plan is 31M25-40M, but MBCLK = 10 MHz, and is set to WRTD_TICKNS = 100. From 6871b9b414ed3f15196b0fc7a7a8e81bbc373da0 Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Fri, 25 Jun 2021 10:41:43 -0400 Subject: [PATCH 3/7] Improve some comments --- pydevices/HtsDevices/acq2106_WRTD.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/pydevices/HtsDevices/acq2106_WRTD.py b/pydevices/HtsDevices/acq2106_WRTD.py index 84b6301a43..d19697c0fb 100644 --- a/pydevices/HtsDevices/acq2106_WRTD.py +++ b/pydevices/HtsDevices/acq2106_WRTD.py @@ -199,18 +199,19 @@ def init(self): # Sets WRTD TICKNS in nsecs: defined by 1/MBCLK # We can take MBCLK from the name of the clock plan that is going to be used when # the desired sample rate is set by the acq2106 device's INIT function. - # Quering sync_role() will give us the clock plan name (FIN): + # + # 1- Quering sync_role() will give us the clock plan name (FIN): # sync_role_query = uut.s0.sync_role # clk_plan = sync_role_query.split('\n')[4] # MBCLK = clk_plan.split(' ')[1] - # Or, it can be query by: + # 2- Quering SYS:CLK:CONFIG will also give us the clock plan's name: sys_clk_plan = uut.s0.SYS_CLK_CONFIG MBCLK = sys_clk_plan.split(' ')[1] - tonano = 1E9 - allowed_plans = {'31M25-5M12':(1./5120000)*tonano, '31M25-10M24':(1./10240000)*tonano, '31M25-20M48':(1./20480000)*tonano, - '31M25-32M768':(1./32768000)*tonano, '31M25-40M':25.0000, '31M25-20M':50.0000} + to_nano = 1E9 + allowed_plans = {'31M25-5M12':(1./5120000)*to_nano, '31M25-10M24':(1./10240000)*to_nano, '31M25-20M48':(1./20480000)*to_nano, + '31M25-32M768':(1./32768000)*to_nano, '31M25-40M':25.0000, '31M25-20M':50.0000} # In TIGA systems the clock plan is 31M25-40M, but MBCLK = 10 MHz, and is set to WRTD_TICKNS = 100. @@ -220,7 +221,7 @@ def init(self): self.wr_init_wrtd_tickns.record = allowed_plans.get(MBCLK) else: raise MDSplus.DevBAD_PARAMETER( - "MBCLK must be 5M12, 10M24, 20M48, 32M768, 31M25-40M or 31M25-20M; not %d" % (MBCLK,)) + "MBCLK must be 31M25-5M12, 31M25-10M24, 31M25-20M48, 31M25-32M768, 31M25-40M or 31M25-20M; not %d" % (MBCLK,)) # Sets WR "safe time for broadcasts" the message, i.e. WRTT_TAI = TAI_TIME_NOW + WRTD_DELTA_NS uut.cC.WRTD_DELTA_NS = self.wr_init_wrtd_dns.data() From dac14b88c7e7857583c6d6ec68f4d0521e34341d Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Wed, 30 Jun 2021 02:01:31 -0400 Subject: [PATCH 4/7] Improve error handling --- pydevices/HtsDevices/acq2106_WRTD.py | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/pydevices/HtsDevices/acq2106_WRTD.py b/pydevices/HtsDevices/acq2106_WRTD.py index d19697c0fb..bf1044d9de 100644 --- a/pydevices/HtsDevices/acq2106_WRTD.py +++ b/pydevices/HtsDevices/acq2106_WRTD.py @@ -202,8 +202,10 @@ def init(self): # # 1- Quering sync_role() will give us the clock plan name (FIN): # sync_role_query = uut.s0.sync_role - # clk_plan = sync_role_query.split('\n')[4] - # MBCLK = clk_plan.split(' ')[1] + # if 'FIN=' in sync_role_query: + # MBCLK = sync_role_query.split('FIN=')[1] + # else: + # MBCK = '' # 2- Quering SYS:CLK:CONFIG will also give us the clock plan's name: sys_clk_plan = uut.s0.SYS_CLK_CONFIG @@ -213,15 +215,18 @@ def init(self): allowed_plans = {'31M25-5M12':(1./5120000)*to_nano, '31M25-10M24':(1./10240000)*to_nano, '31M25-20M48':(1./20480000)*to_nano, '31M25-32M768':(1./32768000)*to_nano, '31M25-40M':25.0000, '31M25-20M':50.0000} - # In TIGA systems the clock plan is 31M25-40M, but MBCLK = 10 MHz, and is set to WRTD_TICKNS = 100. + # In TIGA systems the clock plan is 31M25-40M, but MBCLK = 10 MHz, and is set at boot-time to WRTD_TICKNS = 100. if not self.is_tiga(): - if MBCLK in allowed_plans: - uut.cC.WRTD_TICKNS = allowed_plans.get(MBCLK) - self.wr_init_wrtd_tickns.record = allowed_plans.get(MBCLK) + if MBCLK: + if MBCLK in allowed_plans: + uut.cC.WRTD_TICKNS = allowed_plans.get(MBCLK) + self.wr_init_wrtd_tickns.record = allowed_plans.get(MBCLK) + else: + raise MDSplus.DevBAD_PARAMETER( + "MBCLK must be 31M25-5M12, 31M25-10M24, 31M25-20M48, 31M25-32M768, 31M25-40M or 31M25-20M; not %d" % (MBCLK,)) else: - raise MDSplus.DevBAD_PARAMETER( - "MBCLK must be 31M25-5M12, 31M25-10M24, 31M25-20M48, 31M25-32M768, 31M25-40M or 31M25-20M; not %d" % (MBCLK,)) + raise MDSplus.DevBAD_PARAMETER("MBCLK plan name is empty") # Sets WR "safe time for broadcasts" the message, i.e. WRTT_TAI = TAI_TIME_NOW + WRTD_DELTA_NS uut.cC.WRTD_DELTA_NS = self.wr_init_wrtd_dns.data() From fc8d985affd2cac8873abaa80f880369e4f8ca4e Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Wed, 7 Jul 2021 09:13:55 -0400 Subject: [PATCH 5/7] Remove 2 unused nodes --- pydevices/HtsDevices/acq2106_WRTD.py | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/pydevices/HtsDevices/acq2106_WRTD.py b/pydevices/HtsDevices/acq2106_WRTD.py index bf1044d9de..6e1b343e63 100644 --- a/pydevices/HtsDevices/acq2106_WRTD.py +++ b/pydevices/HtsDevices/acq2106_WRTD.py @@ -44,11 +44,6 @@ class ACQ2106_WRTD(MDSplus.Device): 'value': '192.168.0.254', 'options': ('no_write_shot',) }, - { - 'path': ':HOSTNAME', - 'type': 'text', - 'options': ('no_write_shot',) - }, { 'path': ':COMMENT', 'type': 'text', @@ -71,12 +66,6 @@ class ACQ2106_WRTD(MDSplus.Device): 'value': 0., 'options': ('write_shot',) }, - { - 'path': ':T0', - 'type': 'numeric', - 'value': 0., - 'options': ('write_shot',) - }, # If DIO-PG is present: { 'path': ':DIO_SITE', @@ -101,7 +90,7 @@ class ACQ2106_WRTD(MDSplus.Device): 'path': ':WR_INIT:WRTD_TICKNS', 'type': 'numeric', 'value': 50.0, - 'options': ('no_write_shot',) + 'options': ('write_shot',) }, # 50msec - our "safe time for broadcast". From uut.cC.WRTD_DELTA_NS { From 5152a59b5f859fa92b1ad079b23b91b016a596e9 Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Thu, 8 Jul 2021 01:02:28 -0400 Subject: [PATCH 6/7] Remove un-necessary check logic and use sync_role query to check plan --- pydevices/HtsDevices/acq2106_WRTD.py | 36 ++++++++++------------------ 1 file changed, 13 insertions(+), 23 deletions(-) diff --git a/pydevices/HtsDevices/acq2106_WRTD.py b/pydevices/HtsDevices/acq2106_WRTD.py index 6e1b343e63..d7ad80116f 100644 --- a/pydevices/HtsDevices/acq2106_WRTD.py +++ b/pydevices/HtsDevices/acq2106_WRTD.py @@ -190,15 +190,15 @@ def init(self): # the desired sample rate is set by the acq2106 device's INIT function. # # 1- Quering sync_role() will give us the clock plan name (FIN): - # sync_role_query = uut.s0.sync_role - # if 'FIN=' in sync_role_query: - # MBCLK = sync_role_query.split('FIN=')[1] - # else: - # MBCK = '' + sync_role_query = uut.s0.sync_role + if 'FIN_DEF=' in sync_role_query: + mbclk_plan = sync_role_query.split('FIN_DEF=')[1] + else: + mbclk_plan = '' # 2- Quering SYS:CLK:CONFIG will also give us the clock plan's name: - sys_clk_plan = uut.s0.SYS_CLK_CONFIG - MBCLK = sys_clk_plan.split(' ')[1] + # sys_clk_plan = uut.s0.SYS_CLK_CONFIG + # mbclk_plan = sys_clk_plan.split(' ')[1] to_nano = 1E9 allowed_plans = {'31M25-5M12':(1./5120000)*to_nano, '31M25-10M24':(1./10240000)*to_nano, '31M25-20M48':(1./20480000)*to_nano, @@ -207,15 +207,15 @@ def init(self): # In TIGA systems the clock plan is 31M25-40M, but MBCLK = 10 MHz, and is set at boot-time to WRTD_TICKNS = 100. if not self.is_tiga(): - if MBCLK: - if MBCLK in allowed_plans: - uut.cC.WRTD_TICKNS = allowed_plans.get(MBCLK) - self.wr_init_wrtd_tickns.record = allowed_plans.get(MBCLK) + if mbclk_plan: + if mbclk_plan in allowed_plans: + uut.cC.WRTD_TICKNS = allowed_plans.get(mbclk_plan) + self.wr_init_wrtd_tickns.record = allowed_plans.get(mbclk_plan) else: raise MDSplus.DevBAD_PARAMETER( - "MBCLK must be 31M25-5M12, 31M25-10M24, 31M25-20M48, 31M25-32M768, 31M25-40M or 31M25-20M; not %d" % (MBCLK,)) + "MBCLK plan must be 31M25-5M12, 31M25-10M24, 31M25-20M48, 31M25-32M768, 31M25-40M or 31M25-20M; not %d" % (mbclk_plan,)) else: - raise MDSplus.DevBAD_PARAMETER("MBCLK plan name is empty") + raise MDSplus.DevBAD_PARAMETER("MBCLK plan name is missing from the query uut.s0.sync_role") # Sets WR "safe time for broadcasts" the message, i.e. WRTT_TAI = TAI_TIME_NOW + WRTD_DELTA_NS uut.cC.WRTD_DELTA_NS = self.wr_init_wrtd_dns.data() @@ -252,16 +252,6 @@ def trig(self, msg=''): self.TRIG_MSG.record = message - if message in uut.cC.WRTD_RX_MATCHES: - # To be sure that the EVENT bus is set to TRG - uut.s0.SIG_EVENT_SRC_0 = 'TRG' - elif message in uut.cC.WRTD_RX_MATCHES1: - # To be sure that the EVENT bus is set to TRG - uut.s0.SIG_EVENT_SRC_1 = 'TRG' - else: - print('Message does not match either of the WRTTs available') - self.running.on = False - if not message.strip(): # Set WRTD_ID: message to be transmitted from this device if FTTRG or HDMI is used to trigger. print("Waiting for external trigger ({})...".format( From 96b44a4af8d1e0393d758713cc58182005e138b7 Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Thu, 8 Jul 2021 01:24:16 -0400 Subject: [PATCH 7/7] Remove a small bug when building the plan string --- pydevices/HtsDevices/acq2106_WRTD.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pydevices/HtsDevices/acq2106_WRTD.py b/pydevices/HtsDevices/acq2106_WRTD.py index d7ad80116f..cb48318421 100644 --- a/pydevices/HtsDevices/acq2106_WRTD.py +++ b/pydevices/HtsDevices/acq2106_WRTD.py @@ -192,7 +192,7 @@ def init(self): # 1- Quering sync_role() will give us the clock plan name (FIN): sync_role_query = uut.s0.sync_role if 'FIN_DEF=' in sync_role_query: - mbclk_plan = sync_role_query.split('FIN_DEF=')[1] + mbclk_plan = '31M25-' + sync_role_query.split('FIN_DEF=')[1] else: mbclk_plan = ''