From d716e2c8994dd929eed0d0937904b51d014d6429 Mon Sep 17 00:00:00 2001 From: Stephen Lane-Walsh Date: Tue, 4 May 2021 12:26:50 -0400 Subject: [PATCH 1/2] Use the FREQ node to generate the CLKDIV --- pydevices/HtsDevices/acq2106_435sc.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/pydevices/HtsDevices/acq2106_435sc.py b/pydevices/HtsDevices/acq2106_435sc.py index 5bf5669a04..619c60decd 100644 --- a/pydevices/HtsDevices/acq2106_435sc.py +++ b/pydevices/HtsDevices/acq2106_435sc.py @@ -72,6 +72,24 @@ class _ACQ2106_435SC(acq2106_435st._ACQ2106_435ST): ] def init(self): + uut = self.getUUT() + + freq = int(self.freq.data()) + + clock_div = 0 + if freq == 40000: + clock_div = 1 + elif freq == 20000: + clock_div = 2 + elif freq == 10000: + clock_div = 4 + + # For now, the frequency must be a clean division of 40000 + # This could change when peter works out his arbitrary frequency 'plan' files + if clock_div == 0: + raise MDSplus.DevBAD_PARAMETER( + "FREQ must be 40000, 20000, or 10000, not %d" % (freq,)) + self.slots = super(_ACQ2106_435SC, self).getSlots() for card in self.slots: @@ -103,6 +121,10 @@ def init(self): # - init(True) => use resampling function: # makeSegmentResampled(begin, end, dim, b, resampled, res_factor) super(_ACQ2106_435SC, self).init(resampling=True) + + # Set the clock division in order to generate the desired frequency + # The computed frequency will be (40000 / CLKDIV) + uut.s1.CLKDIV = clock_div INIT=init From 0afbd89b1a0bd0a57a693142e6c2bbbced1e02e0 Mon Sep 17 00:00:00 2001 From: Fernando Santoro Date: Tue, 4 May 2021 15:24:48 -0400 Subject: [PATCH 2/2] Moved setting of CLKDIV before calling super-class's init() --- pydevices/HtsDevices/acq2106_435sc.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/pydevices/HtsDevices/acq2106_435sc.py b/pydevices/HtsDevices/acq2106_435sc.py index 619c60decd..255cf425c0 100644 --- a/pydevices/HtsDevices/acq2106_435sc.py +++ b/pydevices/HtsDevices/acq2106_435sc.py @@ -85,7 +85,7 @@ def init(self): clock_div = 4 # For now, the frequency must be a clean division of 40000 - # This could change when peter works out his arbitrary frequency 'plan' files + # This could change when D-Taqc's Peter Milne works out his arbitrary frequency 'plan' files if clock_div == 0: raise MDSplus.DevBAD_PARAMETER( "FREQ must be 40000, 20000, or 10000, not %d" % (freq,)) @@ -116,16 +116,16 @@ def init(self): if self.debug: print("GAINs Committed for site %s" % (card,)) - - # Here, the argument to the init of the superclass: - # - init(True) => use resampling function: - # makeSegmentResampled(begin, end, dim, b, resampled, res_factor) - super(_ACQ2106_435SC, self).init(resampling=True) # Set the clock division in order to generate the desired frequency # The computed frequency will be (40000 / CLKDIV) uut.s1.CLKDIV = clock_div + # Here, the argument to the init of the superclass: + # - init(True) => use resampling function: + # makeSegmentResampled(begin, end, dim, b, resampled, res_factor) + super(_ACQ2106_435SC, self).init(resampling=True) + INIT=init def getUUT(self):