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add rocm sdot4 TIR intrin
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python/tvm/tir/tensor_intrin/__init__.py

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from .x86 import *
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from .arm_cpu import *
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from .dot_product_common import *
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from .rocm import *
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# Licensed to the Apache Software Foundation (ASF) under one
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# or more contributor license agreements. See the NOTICE file
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# distributed with this work for additional information
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# regarding copyright ownership. The ASF licenses this file
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# to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance
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# with the License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing,
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# software distributed under the License is distributed on an
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# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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# KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations
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# under the License.
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# pylint: disable=invalid-name,missing-function-docstring
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"""Intrinsics for AMDGPU tensorization."""
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from tvm.script import tir as T
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from .. import TensorIntrin
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from .dot_product_common import dp4a_desc
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@T.prim_func
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def sdot4(
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A: T.Buffer((4,), "int8", offset_factor=1, align=4, scope="shared"),
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B: T.Buffer((4,), "int8", offset_factor=1, align=4, scope="shared"),
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C: T.Buffer((1,), "int32", offset_factor=1, align=4, scope="local"),
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) -> None:
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with T.block("root"):
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T.reads(C[0], A[0:4], B[0:4])
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T.writes(C[0])
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C[0] += T.call_llvm_pure_intrin(
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T.llvm_lookup_intrinsic_id("llvm.amdgcn.sdot4"),
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T.uint32(4),
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T.reinterpret(A.vload([0], "int8x4"), dtype="int32"),
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T.reinterpret(B.vload([0], "int8x4"), dtype="int32"),
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T.int32(0),
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T.bool(1),
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dtype="int32"
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)
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AMDGPU_SDOT4_INTRIN = "sdot4"
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TensorIntrin.register(AMDGPU_SDOT4_INTRIN, dp4a_desc, sdot4)

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