diff --git a/README.md b/README.md
index ab77c7d..9f95d3e 100644
--- a/README.md
+++ b/README.md
@@ -17,6 +17,7 @@ The FPGA architecture runs at 100 MHz and embeds many peripherals:
- 2 x UART,
- I2C (master),
- ISO7816 (master),
+- ISO14443-A (NFC daughterboard)
- SPI (master),
- Power supply controllers for each evaluation socket,
- 4 x Delay and pulse generators with 10 ns resolution
diff --git a/api/scaffold/__init__.py b/api/scaffold/__init__.py
index 1272427..2aa00b5 100644
--- a/api/scaffold/__init__.py
+++ b/api/scaffold/__init__.py
@@ -1010,7 +1010,7 @@ def trigger_long(self):
@trigger_long.setter
def trigger_long(self, value):
- # We want until transmission is ready to avoid triggering on a pending
+ # We wait until transmission is ready to avoid triggering on a pending
# one.
self.reg_config.set_bit(
self.__REG_CONFIG_TRIGGER_LONG,
@@ -1605,6 +1605,244 @@ def glitch_count(self, value):
self.reg_count.set(value)
+class ISO14443Trigger(int, Enum):
+ """Triggering modes for ISO-14443 peripheral."""
+ NONE = 0,
+ START = 1,
+ END = 2,
+ RX = 4,
+ START_LONG = 9
+ END_LONG = 10
+
+
+class ISO14443(Module):
+ """
+ ISO 14443-A module of Scaffold.
+ """
+
+ __REG_STATUS_CONTROL_BIT_BUSY = 0
+ __REG_STATUS_CONTROL_BIT_START = 0
+ __REG_STATUS_CONTROL_BIT_POWER_ON = 1
+ __REG_STATUS_CONTROL_BIT_POWER_OFF = 2
+ __REG_CONFIG_BIT_USE_SYNC = 6
+ __REG_CONFIG_BIT_POLARITY = 7
+ __REG_CONFIG_BIT_TRIGGER_TX_START_EN = 0
+ __REG_CONFIG_BIT_TRIGGER_TX_END_EN = 1
+ __REG_CONFIG_BIT_TRIGGER_RX_START_EN = 2
+ __REG_CONFIG_BIT_TRIGGER_LONG_EN = 3
+
+ def __init__(self, parent):
+ super().__init__(parent, "/iso14443")
+ # Declare the signals
+ self.add_signals("tx", "trigger", "rx", "clock_13_56", "tearing")
+ # Declare the registers
+ self.__addr_base = base = 0x0b00
+ self.add_register("status_control", "rwv", base)
+ self.add_register("config", "w", base + 1, reset=0)
+ self.add_register("data", "rwv", base + 2)
+ self.add_register("timeout", "w", base + 3, wideness=3, reset=0x2faf08)
+ self.add_register("demod_delay", "w", base + 4, wideness=4, reset=0)
+
+ def reset(self):
+ self.reg_config.set(
+ (1 << self.__REG_CONFIG_BIT_POLARITY)
+ | (1 << self.__REG_CONFIG_BIT_USE_SYNC))
+
+ def power_on(self):
+ self.reg_status_control.write(1 << self.__REG_STATUS_CONTROL_BIT_POWER_ON)
+
+ def power_off(self):
+ self.reg_status_control.write(1 << self.__REG_STATUS_CONTROL_BIT_POWER_OFF)
+
+ def start(self):
+ self.reg_status_control.write(1 << self.__REG_STATUS_CONTROL_BIT_START)
+
+ def transmit_bits(self, bits: bytes):
+ """
+ Transmits a frame.
+
+ :param bits: Bits to be transmitted. Does not include start and stop bits. Must
+ includes parity bits. Each element of this bytes object must be 0 or 1.
+ """
+ patterns = bytearray()
+ # Symbols "X", "Y" and "Z" for type A according to ISO 14443-2
+ seq_x = 0b10
+ seq_y = 0b11
+ seq_z = 0b01
+ # Append start bit
+ patterns.append(seq_z)
+ previous_bit = 0
+ # Append symbols for all bits following the miller encoding.
+ for bit in bits:
+ assert bit in (0, 1)
+ if bit == 1:
+ seq = seq_x
+ elif previous_bit == 0:
+ seq = seq_z
+ else:
+ seq = seq_y
+ patterns.append(seq)
+ previous_bit = bit
+ # Append end of communication
+ if previous_bit == 0:
+ seq = seq_z
+ else:
+ seq = seq_y
+ patterns.append(seq)
+ patterns.append(seq_y)
+ # Send patterns to Scaffold board and trigger transmission.
+ # Flush RX fifo as well.
+ self.reg_data.write(patterns)
+ self.start()
+
+ def receive_bits(self, bit_size_hint: Optional[int] = None):
+ """
+ Reads all bits received in the reception FIFO.
+
+ :param bit_size_hint: If the number of expected bits in the response is known,
+ it can be indicated as a hint to improve response readout performance. This
+ number includes start and parity bits. If response has more bits than
+ expected, it will still be read completely.
+ """
+ # We don't know yet how many bits are available in the FIFO, and we
+ # want to read them all as fast as possible. Reading the data register
+ # returns one received bit and other informations that will help us to
+ # have low latency:
+ # - bit 1 is 1 if the FIFO is empty,
+ # - bits 7 to 2 hints how many bytes are still in the FIFO (value gives
+ # a range in multiple of 64).
+ # Therefore a good strategy is:
+ # - Read a first chunk and estimate how many bytes are still in the
+ # FIFO.
+ # - If there are other bits in the FIFO, read all the rest with a
+ # single read command.
+ # - Discard all bits that are invalid using the fifo emptyness flag.
+
+ # Read 255 bits from the FIFO.
+ # We wait for the reception hardware to say it has finished receiving.
+ if bit_size_hint is None:
+ # 255 is the max possible with a single Scaffold bus request.
+ size = 255
+ else:
+ size = bit_size_hint + 1
+ data = self.reg_data.read(
+ size,
+ self.reg_status_control.poll(
+ mask=(1 << self.__REG_STATUS_CONTROL_BIT_BUSY), value=0
+ ),
+ )
+ # Look at last received byte to know if there are more, and how many
+ # about.
+ if (data[-1] & 2) == 0:
+ count = (data[-1] >> 2) * 64 + 63
+ # Fetch the remaining
+ data += self.reg_data.read(count)
+
+ # Strip invalid bits
+ count = 0
+ end = False
+ for (i, b) in enumerate(data):
+ if not end:
+ if b & 2 == 2:
+ end = True
+ else:
+ count = i + 1
+ else:
+ assert b & 2 == 2
+ data = data[:count]
+ bits = bytes(b & 1 for b in data)
+ return bits
+
+ def receive(self, bit_size_hint: Optional[int] = None) -> bytes:
+ """
+ Reads all bytes received in the reception FIFO.
+
+ :param bit_size_hint: If the number of expected bits in the response is known,
+ it can be indicated as a hint to improve response readout performance. This
+ number includes start and parity bits. If response has more bits than
+ expected, it will still be read completely.
+ """
+ # 1 start bit, 9 bits per byte with parity
+ bits = self.receive_bits(bit_size_hint = bit_size_hint)
+ if len(bits) == 0:
+ # No response
+ return b''
+ # Response always starts with a 1. The Scaffold hardware peripheral is
+ # not able to receive something else anyways, so if we have a 0 here we
+ # have a bug.
+ assert bits[0] == 1
+ bits = bits[1:]
+ result = bytearray()
+ while len(bits) > 0:
+ b = 0
+ p = 1
+ for i in range(8):
+ b += bits[i] << i
+ p ^= bits[i]
+ assert p == bits[8] # Check parity bit
+ bits = bits[9:]
+ result.append(b)
+ return bytes(result)
+
+ def transmit(self, data: bytes):
+ """
+ Transmits a frame.
+ """
+ bits = bytearray()
+ for byte in data:
+ parity_bit = 1
+ for i in range(8):
+ bit = (byte >> i & 1)
+ parity_bit ^= bit
+ bits.append(bit)
+ bits.append(parity_bit)
+ self.transmit_bits(bits)
+
+ def transmit_short(self, byte: int):
+ """Transmits a short frame (7-bits)."""
+ assert byte < 128
+ bits = bytes((byte >> i) & 1 for i in range(7))
+ self.transmit_bits(bits)
+
+ @property
+ def trigger_mode(self) -> ISO14443Trigger:
+ return ISO14443Trigger(self.reg_config.get() & 0xf)
+
+ @trigger_mode.setter
+ def trigger_mode(self, value: ISO14443Trigger):
+ self.reg_config.set_mask(value, 0xf)
+
+ @property
+ def timeout(self) -> float:
+ ticks = self.reg_timeout.get()
+ return ticks * (2**6) / self.parent.sys_freq
+
+ @timeout.setter
+ def timeout(self, t: float):
+ if t < 0:
+ raise ValueError("Timeout cannot be negative")
+ ticks = round((t * self.parent.sys_freq) / 2**6)
+ if ticks > 0xffffff:
+ raise ValueError("Timeout is too long")
+ if ticks < 1:
+ raise ValueError("Timeout is too short")
+ self.reg_timeout.set(ticks)
+
+ @property
+ def demod_delay(self) -> float:
+ ticks = self.reg_demod_delay.get()
+ return ticks / self.parent.sys_freq
+
+ @demod_delay.setter
+ def demod_delay(self, t: float):
+ if t < 0:
+ raise ValueError("Demodulation delay cannot be negative")
+ ticks = round(t * self.parent.sys_freq)
+ if ticks >= 2**28:
+ raise ValueError("Demodulation delay is too long")
+ self.reg_demod_delay.set(ticks)
+
+
class IOMode(Enum):
AUTO = 0
OPEN_DRAIN = 1
@@ -2098,6 +2336,7 @@ def __init__(
"0.7.2",
"0.8",
"0.9",
+ "0.10"
)
],
)
@@ -2205,6 +2444,12 @@ def connect(
# Create the ISO7816 module
self.iso7816 = ISO7816(self)
+ # Create the ISO 14443-A module
+ if self.version >= parse_version("0.10"):
+ self.iso14443 = ISO14443(self)
+ else:
+ self.iso14443 = None
+
# FPGA left matrix input signals
self.add_mtxl_in("0")
self.add_mtxl_in("1")
@@ -2238,6 +2483,8 @@ def connect(
self.add_mtxl_in(f"/pgen{i}/out")
for i in range(len(self.chains)):
self.add_mtxl_in(f"/chain{i}/trigger")
+ if self.iso14443 is not None:
+ self.add_mtxl_in("/iso14443/trigger")
# FPGA left matrix output signals
# Update this section when adding new modules with inputs
@@ -2259,6 +2506,10 @@ def connect(
self.add_mtxl_out(f"/chain{i}/event{j}")
for i in range(len(self.clocks)):
self.add_mtxl_out(f"/clock{i}/glitch")
+ if self.iso14443 is not None:
+ self.add_mtxl_out("/iso14443/rx")
+ self.add_mtxl_out("/iso14443/clock_13_56")
+ self.add_mtxl_out("/iso14443/tearing")
# FPGA right matrix input signals
# Update this section when adding new modules with outpus
@@ -2290,6 +2541,9 @@ def connect(
self.add_mtxr_in(f"/chain{i}/trigger")
for i in range(len(self.clocks)):
self.add_mtxr_in(f"/clock{i}/out")
+ if self.version >= parse_version("0.10"):
+ self.add_mtxr_in("/iso14443/tx")
+ self.add_mtxr_in("/iso14443/trigger")
# FPGA right matrix output signals
self.add_mtxr_out("/io/a0")
@@ -2355,3 +2609,5 @@ def reset_config(self, init_ios=False):
i2c.reset_config()
for spi in self.spis:
spi.reset_registers()
+ if self.iso14443 is not None:
+ self.iso14443.reset()
diff --git a/api/scaffold/bus.py b/api/scaffold/bus.py
index bdd4f18..849a5a7 100644
--- a/api/scaffold/bus.py
+++ b/api/scaffold/bus.py
@@ -318,7 +318,7 @@ class ScaffoldBus:
"""
MAX_CHUNK = 255
- FIFO_SIZE = 512
+ FIFO_SIZE = 2048
def __init__(self, sys_freq, baudrate):
"""
diff --git a/api/scaffold/iso14443.py b/api/scaffold/iso14443.py
new file mode 100644
index 0000000..00fecbf
--- /dev/null
+++ b/api/scaffold/iso14443.py
@@ -0,0 +1,414 @@
+# This file is part of Scaffold
+#
+# Scaffold is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with this program. If not, see .
+#
+#
+# Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+from . import Scaffold, Pull
+from time import sleep
+from enum import Enum
+from typing import Optional
+import crcmod
+import colorama
+import time
+
+
+class CRCError(Exception):
+ """Thrown when CRC of response is invalid"""
+
+ def __init__(self, got: bytes, expected: bytes):
+ self.got = got
+ self.expected = expected
+
+ def __str__(self):
+ return f"Bad CRC: expected {self.expected.hex()}, got {self.got.hex()}."
+
+
+class TRF7970ACommand(int, Enum):
+ """TRF7970A command code, as defined in the datasheet."""
+
+ IDLE = 0x00
+ SOFTWARE_INIT = 0x03
+ RF_COLLISION_AVOIDANCE = 0x04
+ RESPONSE_RF_COLLISION_AVOIDANCE_1 = 0x05
+ RESPONSE_RF_COLLISION_AVOIDANCE_2 = 0x06
+ RESET_FIFO = 0x0F
+ TRANSMISSION_WITHOUT_CRC = 0x10
+ TRANSMISSION_WITH_CRC = 0x11
+ DELAYED_TRANSMISSION_WITHOUT_CRC = 0x12
+ DELAYED_TRANSMISSION_WITH_CRC = 0x13
+ END_OF_FRAME_AND_TRANSMIT_NEXT_TIME_SLOT = 0x14
+ BLOCK_RECEIVER = 0x16
+ ENABLE_RECEIVER = 0x17
+ TEST_INTERNAL_RF = 0x18
+ TEST_EXTERNAL_RF = 0x19
+
+
+class TRF7970ARegister(int, Enum):
+ """TRF7970A register addresses, as defined in the datasheet."""
+
+ CHIP_STATUS_CONTROL = 0x00
+ ISO_CONTROL = 0x01
+ ISO_IEC_14443B_TX_OPTIONS = 0x02
+ ISO_IEC_14443A_HIGH_BIT_RATE_OPTIONS = 0x03
+ TX_TIMER_CONTROL_HIGH = 0x04
+ TX_TIMER_CONTROL_LOW = 0x05
+ TX_PULSE_LENGTH_CONTROL = 0x06
+ RX_NO_RESPONSE_WAIT_TIME = 0x07
+ RX_WAIT_TIME = 0x08
+ MODULATOR_AND_SYS_CLK_CONTROL = 0x09
+ RX_SPECIAL_SETTING = 0x0A
+ REGULATOR_AND_IO_CONTROL = 0x0B
+ SPECIAL_FUNCTION_1 = 0x10
+ SPECIAL_FUNCTION_2 = 0x11
+ ADJUSTABLE_FIFO_IRQ_LEVELS = 0x14
+ NFC_LOW_FIELD_LEVEL = 0x16
+ NFCID1_NUMBER = 0x17
+ NFC_TARGET_DETECTION_LEVEL = 0x18
+ NFC_TARGET_PROTOCOL = 0x19
+ IRQ_STATUS = 0x0C
+ COLLISION_POSITION_AND_INTERRUPT_MASK = 0x0D
+ COLLISION_POSITION = 0x0E
+ RSSI_LEVELS_AND_OSCILLATOR_STATUS = 0x0F
+ RAM_1 = 0x12
+ RAM_2 = 0x13
+ TEST_1 = 0x1A
+ TEST_2 = 0x1B
+ FIFO_STATUS = 0x1C
+ TX_LENGTH_BYTE_1 = 0x1D
+ TX_LENGTH_BUTE_2 = 0x1E
+ FIFO_IO = 0x1F
+
+
+class NFC:
+ """
+ NFC daughterboard driver to enable ISO 14443 communication with contactless
+ cards.
+
+ Uses a special scaffold daughterboard with the Texas Instruments TRF7970A
+ RFID chip as a RF front-end. The chip is controlled via SPI using Scaffold
+ SPI peripheral.
+
+ The daughterboard has the following pinout:
+
+ - D0: MOD modulation input
+ - D1: SPI MISO
+ - D2: Serial clock out
+ - D6: IO0
+ - D7: IO1
+ - D8: IO2
+ - D9: IO3
+ - D10: SPI SS
+ - D11: SPI MOSI
+ - D12: SPI SCK
+ - D13: ASK/OOK
+ - D14: EN
+ - D15: SYS_CLK
+ """
+
+ def __init__(self, scaffold: Scaffold, platform_socket: bool = False):
+ self.scaffold = scaffold
+ if not platform_socket:
+ scaffold.power.dut = 0
+ else:
+ scaffold.power.platform = 0
+ self.trigger = scaffold.iso14443.trigger
+ self.spi = scaffold.spi0
+ self.iso14443 = scaffold.iso14443
+ self.platform_socket = platform_socket
+ if not platform_socket:
+ self.pin_mosi = scaffold.d11
+ self.pin_miso = scaffold.d1
+ self.pin_sck = scaffold.d12
+ self.pin_ss = scaffold.d10
+ self.pin_en = scaffold.d14
+ self.pin_io0 = scaffold.d6
+ self.pin_io1 = scaffold.d7
+ self.pin_io2 = scaffold.d8
+ self.pin_clock_13_56 = scaffold.d15
+ scaffold.d0 << self.iso14443.tx
+ scaffold.d1 >> self.iso14443.rx
+ else:
+ self.pin_mosi = scaffold.p11
+ self.pin_miso = scaffold.p1
+ self.pin_sck = scaffold.p12
+ self.pin_ss = scaffold.p10
+ self.pin_en = scaffold.p14
+ self.pin_io0 = scaffold.p6
+ self.pin_io1 = scaffold.p7
+ self.pin_io2 = scaffold.p8
+ self.pin_clock_13_56 = scaffold.p15
+ scaffold.p0 << self.iso14443.tx
+ scaffold.p1 >> self.iso14443.rx
+ self.pin_clock_13_56 >> self.iso14443.clock_13_56
+
+ self.pin_en << 0
+ self.pin_ss << 0
+
+ # According to the datasheet IO0, IO1 and IO2 must be tied to the
+ # following values to select SPI communication with Slave Select.
+ self.pin_io0 << 0
+ self.pin_io1 << 1
+ self.pin_io2 << 1
+
+ self.spi.mosi >> self.pin_mosi
+ self.spi.miso << self.pin_miso
+ self.spi.sck >> self.pin_sck
+ self.spi.phase = 1
+ self.spi.frequency = 1000000
+
+ #self.pin_miso.pull = Pull.UP
+ self.crc_a = crcmod.mkCrcFun(0x11021, 0x6363, rev=True)
+
+ # Used for I-block encapsulation
+ self.block_number = 0
+
+ self.verbose = False
+ self.log_t_start = None
+
+ def startup(self):
+ """Power-on the NFC daughterboard and initialize the TRF7970A front-end."""
+ if not self.platform_socket:
+ self.scaffold.power.dut = 1
+ else:
+ self.scaffold.power.platform = 1
+ sleep(2e-3)
+ self.pin_ss << 1
+ sleep(4e-3)
+ self.pin_en << 1
+ # Wait for the TRF7970A to be ready.
+ # Below 2 ms sometimes it fails.
+ sleep(4e-3)
+ # Software reset
+ self.command(TRF7970ACommand.SOFTWARE_INIT)
+ self.command(TRF7970ACommand.IDLE)
+ sleep(1e-3)
+ # Read some registers and check their value after reset, as a sanity check.
+ regs = (
+ (TRF7970ARegister.CHIP_STATUS_CONTROL, 0x01),
+ (TRF7970ARegister.ISO_CONTROL, 0x21),
+ (TRF7970ARegister.ISO_IEC_14443B_TX_OPTIONS, 0x00),
+ (TRF7970ARegister.ISO_IEC_14443A_HIGH_BIT_RATE_OPTIONS, 0x00),
+ (TRF7970ARegister.TX_TIMER_CONTROL_HIGH, 0xC1),
+ # We could read more, but this seems good enough to be confident.
+ )
+ for reg, value in regs:
+ if self.register_read(reg) != value:
+ print(f"DEBUG {reg} {value}")
+ raise RuntimeError("TRF7970A not recognized")
+ # Disable 27.12 MHz crystal, our crystal is 13.56 MHz.
+ # Select OOK 100% modulation depth
+ self.register_write(TRF7970ARegister.MODULATOR_AND_SYS_CLK_CONTROL, 0b00110001)
+ self.register_write(TRF7970ARegister.ISO_CONTROL, 0b00001000)
+ # Direct mode, RF ON, full output power
+ # TODO bit 0 to 0
+ self.register_write(TRF7970ARegister.CHIP_STATUS_CONTROL, 0b00100001)
+ self.register_write(
+ TRF7970ARegister.CHIP_STATUS_CONTROL, 0b01100001, keep_ss_low=True
+ )
+ self.spi.transmit(0)
+ # Reset the block number
+ self.block_number = 0
+ self.iso14443.power_on()
+
+ def register_read(self, address: int) -> int:
+ """
+ Read a register of the TRF7970A front-end.
+
+ :param address: 5-bit address.
+ """
+ assert address in range(32)
+ self.pin_ss << 0
+ self.spi.transmit(0b01000000 | address)
+ result = self.spi.transmit(0)
+ self.pin_ss << 1
+ return result
+
+ def register_write(self, address: int, value: int, keep_ss_low: bool = False):
+ """
+ Write a register of the TRF7970A front-end.
+
+ :param address: 5-bit address.
+ :param value: Byte to be written.
+ """
+ assert address in range(32)
+ assert value in range(256)
+ self.pin_ss << 0
+ self.spi.transmit(address, read=False)
+ self.spi.transmit(value, read=False)
+ if not keep_ss_low:
+ self.pin_ss << 1
+
+ def command(self, value: TRF7970ACommand):
+ """
+ Sends a command to the TRF7970A front-end.
+
+ :param value: 5-bit command index.
+ """
+ assert value in range(32)
+ self.pin_ss << 0
+ self.spi.transmit(0x80 | value, read=False)
+ self.pin_ss << 1
+
+ def reqa(self, read=True) -> bytes:
+ """Sends REQA frame. Returns ATQA response bytes."""
+ data = 0x26
+ if self.verbose:
+ self.log(True, "REQA", bytes((data,)))
+ self.iso14443.transmit_short(data)
+ result = self.iso14443.receive(bit_size_hint=19)
+ if self.verbose:
+ self.log(False, "ATQA", result)
+ assert len(result) == 2
+ return result
+
+ def log(self, rw: bool, what: str, data: bytes):
+ """
+ Print log line in standard output.
+
+ :param rw: True if data is sent to the card, card if data is read from the card.
+ :param str: Frame type indication ("REQA", "ATQA", etc.).
+ :param data: Data read/written from/to the card.
+ """
+ if rw:
+ print(colorama.Fore.YELLOW, end="")
+ else:
+ print(colorama.Fore.CYAN, end="")
+ sep = "│"
+ rw_str = {False: "←", True: "→"}[rw]
+ desc_lines = []
+ while len(data) > 0:
+ desc_lines.append(data[:32].hex())
+ data = data[32:]
+ if len(desc_lines) == 0:
+ desc_lines.append("")
+ t = time.time()
+ if self.log_t_start is None:
+ self.log_t_start = t
+ dt = t - self.log_t_start
+ print(
+ f"{dt * 1000.0:>9.3f} ms {sep} Scaffold {rw_str} Card {sep} {what:<4} "
+ f"{sep} {desc_lines[0]}"
+ )
+ for line in desc_lines[1:]:
+ print(" " * 13 + sep + " " * 17 + sep + " " * 6 + sep + f" {line}")
+ print(colorama.Fore.RESET, end="")
+
+ def transmit(
+ self,
+ data: bytes,
+ what_tx: str = "",
+ what_rx: str = "",
+ bit_size_hint: Optional[int] = None,
+ ) -> bytes:
+ """
+ Transmits data to the card and reads the response. If card does not respond an
+ empty byte string is returned.
+
+ :param data: Bytes to be transmitted.
+ :param what_tx: Transmitted frame type indication ("REQA" for instance).
+ used when verbose is True.
+ :param what_rx: Received frame type indication ("ATQA" for instance).
+ used when verbose is True.
+ :param bit_size_hint: If the number of expected bits in the response is known,
+ it can be indicated as a hint to improve response readout performance. This
+ number includes start and parity bits. If response has more bits than
+ expected, it will still be read completely.
+ """
+ if self.verbose:
+ self.log(True, what_tx, data)
+ self.iso14443.transmit(data)
+ response = self.iso14443.receive(bit_size_hint=bit_size_hint)
+ if self.verbose:
+ self.log(False, what_rx, response)
+ return response
+
+ def transmit_with_crc(
+ self,
+ data: bytes,
+ what_tx: str = "",
+ what_rx: str = "",
+ bit_size_hint: int = None,
+ ) -> bytes:
+ """
+ Transmits data, with CRC appended, reads the response and checks the received
+ CRC validity.
+
+ :param data: Bytes to be transmitted.
+ :param what_tx: Transmitted frame type indication ("SEL" for instance).
+ used when verbose is True.
+ :param what_rx: Received frame type indication ("SAK" for instance).
+ used when verbose is True.
+ :param bit_size_hint: If the number of expected bits in the response is known,
+ it can be indicated as a hint to improve response readout performance. This
+ number includes start and parity bits. If response has more bits than
+ expected, it will still be read completely.
+ :raises CRCError: If received CRC is invalid.
+ """
+ frame = data + self.crc_a(data).to_bytes(2, "little")
+ response = self.transmit(
+ frame, what_tx=what_tx, what_rx=what_rx, bit_size_hint=bit_size_hint
+ )
+ assert len(response) >= 2
+ got_crc = response[-2:]
+ expected_crc = self.crc_a(response[:-2]).to_bytes(2, "little")
+ if got_crc != expected_crc:
+ raise CRCError(got_crc, expected_crc)
+ return response[:-2]
+
+ def sel(self, level: int) -> bytes:
+ """
+ Performs selection. This sends a SEL frame, reads the returned UID by the card
+ and selects it with another SEL frame. Returns the UID returned during
+ selection.
+ Note: the returned UID can be partial, only the bytes corresponding to the
+ selected cascade level are returned.
+
+ :param level: Cascade level. Must be 1, 2 or 3.
+ """
+ sel = 0x93 + 2 * (level - 1)
+ uid = self.transmit(
+ bytes((sel, 0x20)), what_tx="SEL", what_rx="UID", bit_size_hint=46
+ )
+ self.transmit_with_crc(
+ bytes((sel, 0x70)) + uid, what_tx="SEL", what_rx="SAK", bit_size_hint=28
+ )
+ return uid
+
+ def rats(self) -> bytes:
+ """
+ Sends RATS (Request for Answer To Select) frame and returns PICC
+ response.
+
+ FSDI is set to 256 bytes. This value is the highest possible and is
+ supported by Scaffold. CID is set to 0.
+ """
+ return self.transmit_with_crc(b"\xe0\x80", what_tx="RATS", what_rx="ATS")
+
+ def apdu(self, apdu: bytes) -> bytes:
+ """
+ Sends an APDU and returns the response. Exchange is performed using I-blocks,
+ and waiting time extension requests are handled transparently.
+
+ :param apdu: APDU to be transmitted. Does not include I-block header or CRC.
+ """
+ iblock = bytes((0x02 + self.block_number,)) + apdu
+ self.block_number = (self.block_number + 1) % 2
+ response = self.transmit_with_crc(iblock)
+ while response[0] & 0xC0 == 0xC0:
+ # S-block with waiting time extension request
+ response = self.transmit_with_crc(b"\xf2" + bytes((response[1],)))
+ return response[1:]
diff --git a/daughter-boards/nfc/fp-lib-table b/daughter-boards/nfc/fp-lib-table
new file mode 100644
index 0000000..a04d910
--- /dev/null
+++ b/daughter-boards/nfc/fp-lib-table
@@ -0,0 +1,4 @@
+(fp_lib_table
+ (version 7)
+ (lib (name "library")(type "KiCad")(uri "${KIPRJMOD}/library.pretty")(options "")(descr ""))
+)
diff --git a/daughter-boards/nfc/gerber/nfc-B_Cu.gbr b/daughter-boards/nfc/gerber/nfc-B_Cu.gbr
new file mode 100644
index 0000000..d96600b
--- /dev/null
+++ b/daughter-boards/nfc/gerber/nfc-B_Cu.gbr
@@ -0,0 +1,1621 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,9.99.0-unknown-d5f02ba7bc~182~ubuntu22.04.1*
+G04 #@! TF.CreationDate,2025-03-17T15:10:36+01:00*
+G04 #@! TF.ProjectId,rfid-reader,72666964-2d72-4656-9164-65722e6b6963,rev?*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Copper,L2,Bot*
+G04 #@! TF.FilePolarity,Positive*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 9.99.0-unknown-d5f02ba7bc~182~ubuntu22.04.1) date 2025-03-17 15:10:36*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 #@! TA.AperFunction,ComponentPad*
+%ADD10R,1.700000X1.700000*%
+G04 #@! TD*
+G04 #@! TA.AperFunction,ComponentPad*
+%ADD11O,1.700000X1.700000*%
+G04 #@! TD*
+G04 #@! TA.AperFunction,ViaPad*
+%ADD12C,0.600000*%
+G04 #@! TD*
+G04 #@! TA.AperFunction,Conductor*
+%ADD13C,0.200000*%
+G04 #@! TD*
+G04 APERTURE END LIST*
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diff --git a/daughter-boards/nfc/gerber/nfc-B_Mask.gbr b/daughter-boards/nfc/gerber/nfc-B_Mask.gbr
new file mode 100644
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diff --git a/daughter-boards/nfc/gerber/nfc-B_Paste.gbr b/daughter-boards/nfc/gerber/nfc-B_Paste.gbr
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diff --git a/daughter-boards/nfc/gerber/nfc-B_Silkscreen.gbr b/daughter-boards/nfc/gerber/nfc-B_Silkscreen.gbr
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diff --git a/daughter-boards/nfc/gerber/nfc-Edge_Cuts.gbr b/daughter-boards/nfc/gerber/nfc-Edge_Cuts.gbr
new file mode 100644
index 0000000..6e138f2
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+++ b/daughter-boards/nfc/gerber/nfc-Edge_Cuts.gbr
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diff --git a/daughter-boards/nfc/gerber/nfc-F_Cu.gbr b/daughter-boards/nfc/gerber/nfc-F_Cu.gbr
new file mode 100644
index 0000000..e38d753
--- /dev/null
+++ b/daughter-boards/nfc/gerber/nfc-F_Cu.gbr
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+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
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+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
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+G04 Aperture macros list end*
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+G04 #@! TA.AperFunction,SMDPad,CuDef*
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diff --git a/daughter-boards/nfc/gerber/nfc-F_Mask.gbr b/daughter-boards/nfc/gerber/nfc-F_Mask.gbr
new file mode 100644
index 0000000..1471960
--- /dev/null
+++ b/daughter-boards/nfc/gerber/nfc-F_Mask.gbr
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diff --git a/daughter-boards/nfc/gerber/nfc-F_Paste.gbr b/daughter-boards/nfc/gerber/nfc-F_Paste.gbr
new file mode 100644
index 0000000..b4f5cdd
--- /dev/null
+++ b/daughter-boards/nfc/gerber/nfc-F_Paste.gbr
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+G04 #@! TF.CreationDate,2025-03-17T15:10:36+01:00*
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+G04 APERTURE LIST*
+G04 Aperture macros list*
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new file mode 100644
index 0000000..b158111
--- /dev/null
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diff --git a/daughter-boards/nfc/library.pretty/ANTENNA.kicad_mod b/daughter-boards/nfc/library.pretty/ANTENNA.kicad_mod
new file mode 100644
index 0000000..b3013d0
--- /dev/null
+++ b/daughter-boards/nfc/library.pretty/ANTENNA.kicad_mod
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diff --git a/daughter-boards/nfc/nfc.kicad_pcb b/daughter-boards/nfc/nfc.kicad_pcb
new file mode 100644
index 0000000..3f0639b
--- /dev/null
+++ b/daughter-boards/nfc/nfc.kicad_pcb
@@ -0,0 +1,15231 @@
+(kicad_pcb
+ (version 20250302)
+ (generator "pcbnew")
+ (generator_version "9.99")
+ (general
+ (thickness 1.6)
+ (legacy_teardrops no)
+ )
+ (paper "A4")
+ (title_block
+ (title "Scaffold daughterboard")
+ (date "2021-09-14")
+ (comment 1 "Under LGPL v3 license")
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+ (33 "B.Fab" user)
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+ (layer "F.Mask"
+ (type "Top Solder Mask")
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+ )
+ (layer "F.Cu"
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+ (layer "dielectric 1"
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+ (thickness 1.51)
+ (material "FR4")
+ (epsilon_r 4.5)
+ (loss_tangent 0.02)
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+ (layer "B.Mask"
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+ (thickness 0.01)
+ )
+ (layer "B.Paste"
+ (type "Bottom Solder Paste")
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+ (layer "B.SilkS"
+ (type "Bottom Silk Screen")
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+ (copper_finish "None")
+ (dielectric_constraints no)
+ )
+ (pad_to_mask_clearance 0)
+ (allow_soldermask_bridges_in_footprints no)
+ (tenting
+ (front yes)
+ (back yes)
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+ (covering
+ (front no)
+ (back no)
+ )
+ (plugging
+ (front no)
+ (back no)
+ )
+ (capping no)
+ (filling no)
+ (grid_origin 81.28 147.32)
+ (pcbplotparams
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+ (mode 1)
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+ (net 6 "unconnected-(J1-D15-Pad15)")
+ (net 7 "unconnected-(J2-X9-Pad9)")
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+ (net 10 "unconnected-(J2-X7-Pad7)")
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diff --git a/daughter-boards/nfc/nfc.kicad_prl b/daughter-boards/nfc/nfc.kicad_prl
new file mode 100644
index 0000000..2e15320
--- /dev/null
+++ b/daughter-boards/nfc/nfc.kicad_prl
@@ -0,0 +1,131 @@
+{
+ "board": {
+ "active_layer": 0,
+ "active_layer_preset": "",
+ "auto_track_width": true,
+ "hidden_netclasses": [],
+ "hidden_nets": [],
+ "high_contrast_mode": 0,
+ "net_color_mode": 1,
+ "opacity": {
+ "images": 0.6,
+ "pads": 1.0,
+ "shapes": 1.0,
+ "tracks": 1.0,
+ "vias": 1.0,
+ "zones": 0.6
+ },
+ "prototype_zone_fills": false,
+ "selection_filter": {
+ "dimensions": true,
+ "footprints": true,
+ "graphics": true,
+ "keepouts": true,
+ "lockedItems": false,
+ "otherItems": true,
+ "pads": true,
+ "text": true,
+ "tracks": true,
+ "vias": true,
+ "zones": true
+ },
+ "visible_items": [
+ "vias",
+ "footprint_text",
+ "footprint_anchors",
+ "ratsnest",
+ "grid",
+ "footprints_front",
+ "footprints_back",
+ "footprint_values",
+ "footprint_references",
+ "tracks",
+ "drc_errors",
+ "drawing_sheet",
+ "bitmaps",
+ "pads",
+ "zones",
+ "drc_warnings",
+ "locked_item_shadows",
+ "conflict_shadows",
+ "shapes"
+ ],
+ "visible_layers": "ffffffff_ffffffff_fffffff7_ffffffff",
+ "zone_display_mode": 0
+ },
+ "git": {
+ "repo_type": "",
+ "repo_username": "",
+ "ssh_key": ""
+ },
+ "meta": {
+ "filename": "rfid-reader.kicad_prl",
+ "version": 5
+ },
+ "net_inspector_panel": {
+ "col_hidden": [
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+ false,
+ false,
+ false,
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+ ],
+ "custom_group_rules": [],
+ "expanded_rows": [],
+ "filter_by_net_name": true,
+ "filter_by_netclass": true,
+ "filter_text": "",
+ "group_by_constraint": false,
+ "group_by_netclass": false,
+ "show_unconnected_nets": false,
+ "show_zero_pad_nets": false,
+ "sort_ascending": true,
+ "sorting_column": 0
+ },
+ "open_jobsets": [],
+ "project": {
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+ },
+ "schematic": {
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+ "labels": true,
+ "lockedItems": false,
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+ "pins": true,
+ "symbols": true,
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+ "wires": true
+ }
+ }
+}
diff --git a/daughter-boards/nfc/nfc.kicad_pro b/daughter-boards/nfc/nfc.kicad_pro
new file mode 100644
index 0000000..f6c1686
--- /dev/null
+++ b/daughter-boards/nfc/nfc.kicad_pro
@@ -0,0 +1,678 @@
+{
+ "board": {
+ "3dviewports": [],
+ "design_settings": {
+ "defaults": {
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+ "apply_defaults_to_fp_shapes": false,
+ "apply_defaults_to_fp_text": false,
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+ "copper_line_width": 0.2,
+ "copper_text_italic": false,
+ "copper_text_size_h": 1.5,
+ "copper_text_size_v": 1.5,
+ "copper_text_thickness": 0.3,
+ "copper_text_upright": false,
+ "courtyard_line_width": 0.05,
+ "dimension_precision": 4,
+ "dimension_units": 3,
+ "dimensions": {
+ "arrow_length": 1270000,
+ "extension_offset": 500000,
+ "keep_text_aligned": true,
+ "suppress_zeroes": true,
+ "text_position": 0,
+ "units_format": 0
+ },
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+ "fab_text_italic": false,
+ "fab_text_size_h": 1.0,
+ "fab_text_size_v": 1.0,
+ "fab_text_thickness": 0.15,
+ "fab_text_upright": false,
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+ "other_text_italic": false,
+ "other_text_size_h": 1.0,
+ "other_text_size_v": 1.0,
+ "other_text_thickness": 0.15,
+ "other_text_upright": false,
+ "pads": {
+ "drill": 0.8,
+ "height": 1.27,
+ "width": 2.54
+ },
+ "silk_line_width": 0.1,
+ "silk_text_italic": false,
+ "silk_text_size_h": 1.0,
+ "silk_text_size_v": 1.0,
+ "silk_text_thickness": 0.1,
+ "silk_text_upright": false,
+ "zones": {
+ "min_clearance": 0.2
+ }
+ },
+ "diff_pair_dimensions": [
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+ "via_gap": 0.0,
+ "width": 0.0
+ }
+ ],
+ "drc_exclusions": [
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+ ""
+ ]
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+ },
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+ "connection_width": "warning",
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+ "copper_sliver": "warning",
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+ "diff_pair_uncoupled_length_too_long": "error",
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+ "footprint": "error",
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+ "footprint_type_mismatch": "ignore",
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+ "invalid_outline": "error",
+ "isolated_copper": "warning",
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+ "items_not_allowed": "error",
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+ "lib_footprint_mismatch": "warning",
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+ "microvia_drill_out_of_range": "error",
+ "mirrored_text_on_front_layer": "warning",
+ "missing_courtyard": "ignore",
+ "missing_footprint": "warning",
+ "net_conflict": "warning",
+ "nonmirrored_text_on_back_layer": "warning",
+ "npth_inside_courtyard": "ignore",
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+ "pth_inside_courtyard": "ignore",
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+ "via_dangling": "warning",
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diff --git a/daughter-boards/nfc/nfc.kicad_sch b/daughter-boards/nfc/nfc.kicad_sch
new file mode 100644
index 0000000..065ef52
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diff --git a/daughter-boards/nfc/sym-lib-table b/daughter-boards/nfc/sym-lib-table
new file mode 100644
index 0000000..63d7c9e
--- /dev/null
+++ b/daughter-boards/nfc/sym-lib-table
@@ -0,0 +1,4 @@
+(sym_lib_table
+ (version 7)
+ (lib (name "library")(type "KiCad")(uri "${KIPRJMOD}/library.kicad_sym")(options "")(descr ""))
+)
diff --git a/docs/api.rst b/docs/api.rst
index 0643205..fb934ae 100644
--- a/docs/api.rst
+++ b/docs/api.rst
@@ -6,3 +6,4 @@ Python API
Scaffold
STM32
ISO7816
+ ISO14443
diff --git a/docs/api_iso14443.rst b/docs/api_iso14443.rst
new file mode 100644
index 0000000..4d78aa3
--- /dev/null
+++ b/docs/api_iso14443.rst
@@ -0,0 +1,18 @@
+ISO7816 API
+===========
+
+This API provides support for ISO7816 support with Scaffold.
+
+.. automodule:: scaffold.iso14443
+
+.. autoclass:: NFC
+ :special-members: __init__
+ :members:
+
+.. autoclass:: TRF7970ACommand
+ :members:
+ :undoc-members:
+
+.. autoclass:: TRF7970ARegister
+ :members:
+ :undoc-members:
diff --git a/docs/exts/modbox.py b/docs/exts/modbox.py
index e3c25f1..7517781 100755
--- a/docs/exts/modbox.py
+++ b/docs/exts/modbox.py
@@ -50,7 +50,7 @@ def make_fig(path, inputs, outputs):
# Head length and head width for arrows
hl = 0.25
hw = hl * 0.75
- box_w = 6
+ box_w = 8
box_left = -box_w//2
box_right = -box_left
top = 1
diff --git a/docs/iso14443_module.rst b/docs/iso14443_module.rst
new file mode 100644
index 0000000..9570f5b
--- /dev/null
+++ b/docs/iso14443_module.rst
@@ -0,0 +1,166 @@
+ISO-14443 module
+================
+
+The ISO-14443 module is a reader interface allowing communication with any
+ISO-14443 contactless card.
+
+This peripheral only handles frames transmission and decoding, and it must be
+used with the dedicated NFC daughterboard which is responsible for the radio
+modulation and demodulation. More precisely, this daughterboard embeds a
+TRF7970A integrated circuit which acts as the RF front-end.
+
+.. warning::
+ Only ISO-14443 type A is supported at the moment.
+
+Python API example
+------------------
+
+The following example shows how to select a card and send an APDU.
+
+.. code-block:: python
+
+ from scaffold import Scaffold, ISO14443Trigger
+ from scaffold.iso14443 import NFC
+
+ s = Scaffold()
+ nfc = NFC(s)
+ nfc.startup()
+ s.d5 << nfc.trigger
+ nfc.iso14443.trigger_mode = ISO14443Trigger.START
+
+ print(nfc.reqa().hex())
+
+ uid = nfc.transmit(b"\x93\x20")
+ print(uid.hex())
+
+ result = nfc.transmit_with_crc(b"\x93\x70" + uid)
+ print(result.hex())
+
+ # Send RATS
+ result = nfc.transmit_with_crc(b"\xe0\x80")
+ print(result.hex())
+
+
+Signals
+-------
+
+.. modbox::
+ :inputs: rx, clock_13_56, tearing
+ :outputs: tx, trigger*
+
+Internal registers
+------------------
+
++--------+----------------+-----+
+| 0x0500 | status/control | R/W |
++--------+----------------+-----+
+| 0x0501 | config | W |
++--------+----------------+-----+
+| 0x0502 | data | R/W |
++--------+----------------+-----+
+| 0x0503 | timeout | W |
++--------+----------------+-----+
+
+status and control register
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
++-------+---+---+---+---+---+-----------+----------+-------+
+| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
++-------+---+---+---+---+---+-----------+----------+-------+
+| read | *reserved* | busy |
++-------+-------------------+-----------+----------+-------+
+| write | *reserved* | power_off | power_on | start |
++-------+-------------------+-----------+----------+-------+
+
+busy
+ Reading this bit returns 1 when a transmission is ongoing.
+start
+ Writing 1 to this bit will start the transmission of patterns pushed in the
+ FIFO.
+power_on
+ Writing to 1 enables RF power.
+power_off
+ Writing to 1 disables RF power by constant modulation.
+ Works only for ISO-14443 type A.
+
+Note: Starting a transmission automatically flushes the reception FIFO.
+
+config register
+^^^^^^^^^^^^^^^
+
++----------+----------+---+--------+--------------+------------+----------------+------------------+
+| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
++----------+----------+------------+--------------+------------+----------------+------------------+
+| polarity | use_sync | *reserved* | trigger_long | trigger_rx | trigger_tx_end | trigger_tx_start |
++----------+----------+------------+--------------+------------+----------------+------------------+
+
+trigger_start
+ When set to 1, trigger signal will be asserted at the beginning of
+ transmission, for one clock cycle long. Can be combined with trigger_end and
+ trigger_rx.
+trigger_end
+ When set to 1, trigger signal will be asserted at the end of transmission,
+ for one clock cycle long. Can be combined with trigger_start and trigger_rx.
+trigger_rx
+ When set to 1, trigger signal will be asserted when the card starts to
+ respond. Can be combined with trigger_start and trigger_end. Ignored if
+ trigger_long is set.
+trigger_long
+ When set to 1, start or end signals will raise the trigger and keep it high
+ until the card starts to respond, or the response timeout expires.
+use_sync
+ When set to 1, the transmitter will synchronize the transmission to the 13.56
+ MHz clock issued from the daughterboard. This option reduces the jitter.
+polarity
+ Can be modified to set tx modulation signal polarity. Use value 1 for the
+ reference Scaffold NFC daughterboard. May be changed if RF front-end is
+ different.
+
+data register
+^^^^^^^^^^^^^
+
++-------+---+---+---+---+---+---+---+------------+
+| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
++-------+---+---+---+---+---+---+---+------+-----+
+| read | size_hint | rx_empty | bit |
++-------+-----------------------+----------+-----+
+| write | *reserved* | pattern |
++-------+-----------------------+----------------+
+
+Writing to this register pushes in the FIFO a pattern to be transmitted. The
+pattern field is encoded as this:
+
+- 10: Miller sequence X (type A)
+- 11: Miller sequence Y (type A) or NRZ bit 1 symbol (type B)
+- 01: Miller sequence Z (type A)
+- 00: NRZ bit 0 symbol (type B)
+
+Up to 2048 patterns can be pushed in the FIFO. When all patterns have been
+loaded, transmission can start by writting to the control register.
+
+Reading this register pops the lastest bit stored in the reception FIFO and
+returns the following information:
+
+bit:
+ Oldest received bit.
+rx_empty:
+ True if the FIFO is empty. False if it contains bits (before the actual
+ read).
+size_hint:
+ Hints how many bits are stored in the FIFO. 0 means FIFO has from 0 to 63
+ elements, 1 means FIFO has from 64 to 127 elements, etc. Maximum value is
+ 63, which means FIFO has from 4032 to 4095 elements.
+
+The rx_empty and size_hint fields helps the software to read the correct amount
+of received data with minimizing the number of requests to the board and
+therefore reducing the response reading latency.
+
+timeout register
+^^^^^^^^^^^^^^^^
+
+This 24-bit register defines how long the reader can awaits for a response from
+the contactless card. After transmission and once the timeout expires, the
+ISO-14443 peripheral returns to idle state.
+
+Write three bytes, MSB first, to set the timeout. Each unit corresponds to
+9.44 µs. The default setting is 2 seconds.
diff --git a/docs/iso7816_module.rst b/docs/iso7816_module.rst
index 30bac6a..0c5f48c 100644
--- a/docs/iso7816_module.rst
+++ b/docs/iso7816_module.rst
@@ -84,7 +84,7 @@ control register
| *reserved* | flush |
+---------------------------+-------+
-clear
+flush
Write this bit to 1 to flush the reception FIFO memory.
config register
diff --git a/docs/peripherals.rst b/docs/peripherals.rst
index 446851c..8a5d62b 100644
--- a/docs/peripherals.rst
+++ b/docs/peripherals.rst
@@ -22,12 +22,13 @@ the signal `output_c` in the example above.
I/Os
UART
- Power
- LEDs
- ISO7816
I2C
SPI
+ ISO7816 (contact smartcards)
+ ISO14443 (contactless smartcards)
Pulse generator
Clock generator
+ Power
Chain triggers
+ LEDs
Version
diff --git a/examples/iso14443.py b/examples/iso14443.py
new file mode 100755
index 0000000..0a14d13
--- /dev/null
+++ b/examples/iso14443.py
@@ -0,0 +1,42 @@
+#!/usr/bin/python3
+#
+# This file is part of Scaffold
+#
+# Scaffold is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with this program. If not, see .
+#
+#
+# Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+from scaffold import Scaffold, ISO14443Trigger
+from scaffold.iso14443 import NFC
+
+s = Scaffold()
+nfc = NFC(s)
+s.d5 << nfc.trigger
+nfc.startup()
+nfc.iso14443.trigger_mode = ISO14443Trigger.START
+nfc.iso14443.timeout = 1
+nfc.verbose = True
+
+# REQA
+atqa = nfc.reqa()
+uid_size = ((atqa[0] >> 6) & 3) + 1
+# Selection
+for i in range(uid_size):
+ nfc.sel(i + 1)
+# Send Request Answer To Select
+result = nfc.rats()
+# Send APDU
+response = nfc.apdu(bytes.fromhex("00a404000e315041592e5359532e4444463031"))
diff --git a/fpga-arch/buffered_uart_rx.vhd b/fpga-arch/buffered_uart_rx.vhd
index 0e1dea2..e03776d 100644
--- a/fpga-arch/buffered_uart_rx.vhd
+++ b/fpga-arch/buffered_uart_rx.vhd
@@ -49,7 +49,7 @@ port (
-- read_request has been asserted.
data: out std_logic_vector(7 downto 0);
-- Number of bytes in the FIFO.
- size: out std_logic_vector(8 downto 0) );
+ size: out std_logic_vector(10 downto 0) );
end;
@@ -62,7 +62,7 @@ architecture behavior of buffered_uart_rx is
signal light_uart_has_data: std_logic;
begin
-- Reading a byte from the FIFO takes one clock cycle (no read-ahead).
- e_fifo512: entity work.fifo512
+ e_fifo2048: entity work.fifo2048
port map (
aclr => not reset_n,
sclr => '0',
diff --git a/fpga-arch/bus_bridge.vhd b/fpga-arch/bus_bridge.vhd
index 7ad5cd6..9c41a6b 100644
--- a/fpga-arch/bus_bridge.vhd
+++ b/fpga-arch/bus_bridge.vhd
@@ -109,7 +109,7 @@ architecture behavior of bus_bridge is
-- cycle.
signal fifo_rdreq: std_logic;
-- Size of the FIFO
- signal fifo_use: std_logic_vector(8 downto 0);
+ signal fifo_use: std_logic_vector(10 downto 0);
-- When high, the FSM is waiting from a byte to be available from the FIFO.
-- This signal is used to perform read requests.
signal need_byte: std_logic;
@@ -170,7 +170,7 @@ architecture behavior of bus_bridge is
signal delay_counter: std_logic_vector(23 downto 0);
-- Expected size of the command buffer when a wait buffer operation is
-- performed. This is configured during st_buf_wait_conf_x states.
- signal buf_wait_size: std_logic_vector(8 downto 0);
+ signal buf_wait_size: std_logic_vector(10 downto 0);
-- Register for pipelining the incoming data from the bus.
signal bus_read_data_pipelined: byte_t;
@@ -836,7 +836,7 @@ begin
when st_buf_wait_conf_1 | st_buf_wait_conf_2 =>
if byte_available = '1' then
-- Shift-load from the right
- buf_wait_size <= buf_wait_size(0) & uart_data_rx;
+ buf_wait_size <= buf_wait_size(2 downto 0) & uart_data_rx;
else
buf_wait_size <= buf_wait_size;
end if;
diff --git a/fpga-arch/confware-0.10.pof b/fpga-arch/confware-0.10.pof
new file mode 100644
index 0000000..5fa55b9
Binary files /dev/null and b/fpga-arch/confware-0.10.pof differ
diff --git a/fpga-arch/iso14443_clock_sync.vhd b/fpga-arch/iso14443_clock_sync.vhd
new file mode 100644
index 0000000..2f7d5f0
--- /dev/null
+++ b/fpga-arch/iso14443_clock_sync.vhd
@@ -0,0 +1,70 @@
+-- This file is part of Scaffold
+--
+-- Scaffold is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see .
+--
+--
+-- Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity iso14443_clock_sync is
+port (
+ -- System clock.
+ clock: in std_logic;
+ -- System reset, active low.
+ reset_n: in std_logic;
+ -- 13.56 MHz clock input
+ clock_13_56: in std_logic;
+ -- Resynchronization result
+ go: out std_logic );
+end;
+
+
+architecture behavior of iso14443_clock_sync is
+ -- Synchronization register chain
+ signal sync_chain: std_logic_vector(3 downto 0);
+ -- Sampled clock used for detection.
+ signal samples: std_logic_vector(3 downto 0);
+begin
+ -- This chain helps preventing metastability issues.
+ -- See Altera White Paper WP-01082-1.2
+ -- https://cdrdv2-public.intel.com/650346/wp-01082-quartus-ii-metastability.pdf
+ p_sync_chain: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ sync_chain <= (others => '0');
+ elsif rising_edge(clock) then
+ sync_chain <= sync_chain(sync_chain'high - 1 downto 0) & clock_13_56;
+ end if;
+ end process;
+
+ p_samples: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ samples <= (others => '0');
+ go <= '0';
+ elsif rising_edge(clock) then
+ samples <= samples(samples'high - 1 downto 0) & sync_chain(sync_chain'high);
+ if samples = "0111" then
+ go <= '1';
+ else
+ go <= '0';
+ end if;
+ end if;
+ end process;
+end;
diff --git a/fpga-arch/iso14443_demod.vhd b/fpga-arch/iso14443_demod.vhd
new file mode 100644
index 0000000..b8f4dcf
--- /dev/null
+++ b/fpga-arch/iso14443_demod.vhd
@@ -0,0 +1,99 @@
+-- This file is part of Scaffold
+--
+-- Scaffold is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see .
+--
+--
+-- Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity iso14443_demod is
+port (
+ -- System clock.
+ clock: in std_logic;
+ -- System reset, active low.
+ reset_n: in std_logic;
+ -- Subcarrier input.
+ rx: in std_logic;
+ -- High to enable demodulator.
+ enable: in std_logic;
+ -- Demodulated output.
+ result: out std_logic );
+end;
+
+
+architecture behavior of iso14443_demod is
+ signal rx_z: std_logic;
+ signal edge: std_logic;
+ signal level: unsigned(1 downto 0);
+ signal counter: unsigned(7 downto 0);
+begin
+ p_rx: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ rx_z <= '0';
+ edge <= '0';
+ elsif rising_edge(clock) then
+ rx_z <= rx and enable;
+ edge <= rx xor rx_z;
+ end if;
+ end process;
+
+ p_counter: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ counter <= (others => '0');
+ elsif rising_edge(clock) then
+ if edge = '1' then
+ -- 176 = 59 * 3 - 1
+ -- With this value, for perfect modulated input we have a pulse
+ -- of exactly half the duration of one bit.
+ counter <= to_unsigned(176, counter'length);
+ else
+ if counter = 0 then
+ counter <= counter;
+ else
+ counter <= counter - 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_level: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ level <= (others => '0');
+ result <= '0';
+ elsif rising_edge(clock) then
+ if (counter = 0) or (enable = '0') then
+ level <= (others => '0');
+ else
+ if (edge = '1') and (level /= 3) then
+ level <= level + 1;
+ else
+ level <= level;
+ end if;
+ end if;
+ if (enable = '1') and (level = 3) then
+ result <= '1';
+ else
+ result <= '0';
+ end if;
+ end if;
+ end process;
+end;
diff --git a/fpga-arch/iso14443_module.vhd b/fpga-arch/iso14443_module.vhd
new file mode 100644
index 0000000..8f1f3ca
--- /dev/null
+++ b/fpga-arch/iso14443_module.vhd
@@ -0,0 +1,231 @@
+-- This file is part of Scaffold
+--
+-- Scaffold is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see .
+--
+--
+-- Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.common_pkg.all;
+
+
+--
+-- Configurable ISO14443 module.
+--
+-- Generates a modulation signal which is fed to an analog front-end (most
+-- likely the TRF7970A) and decodes received demodulated sub-carrier signal.
+-- Configurable triggers can be generated to synchronize experiments with the RF
+-- communication.
+--
+entity iso14443_module is
+port (
+ -- System clock.
+ clock: in std_logic;
+ -- System reset, active low.
+ reset_n: in std_logic;
+ -- Bus signals
+ bus_in: in bus_in_t;
+
+ -- Registers selection signals, from address decoder.
+ en_status_control: in std_logic;
+ en_config: in std_logic;
+ en_data: in std_logic;
+ en_timeout: in std_logic;
+ en_demod_delay: in std_logic;
+
+ -- Output registers
+ reg_status: out byte_t;
+ reg_data: out byte_t;
+
+ -- 13.56 MHz clock source used for synchronization.
+ clock_13_56: in std_logic;
+ -- If high, cut RF power (by modulating all the time).
+ -- Works for ISO-14443 type A only (requires OOK modulation).
+ tearing: in std_logic;
+
+ -- ISO14443 signals
+ tx: out std_logic;
+ rx: in std_logic;
+ trigger: out std_logic );
+end;
+
+
+architecture behavior of iso14443_module is
+ -- Status register.
+ signal status: byte_t;
+ signal busy: std_logic;
+ -- Configuration register.
+ signal config: byte_t;
+ signal trigger_tx_start_en: std_logic;
+ signal trigger_tx_end_en: std_logic;
+ signal trigger_rx_start_en: std_logic;
+ signal trigger_long_en: std_logic;
+ signal polarity: std_logic;
+ signal use_sync: std_logic;
+ -- Timeout register
+ signal reg_timeout: std_logic_vector(23 downto 0);
+ -- Demodulation delay register.
+ -- Only 29 bits are used, MSB will be ignored.
+ signal reg_demod_delay: std_logic_vector(31 downto 0);
+
+ -- When high, pushes a byte in the FIFO.
+ signal push: std_logic;
+ -- When high, starts transmitting what has been stored in the FIFO.
+ signal start: std_logic;
+ -- Triggers generated by the transmit module
+ signal trigger_tx_start: std_logic;
+ signal trigger_tx_end: std_logic;
+ signal trigger_rx_start: std_logic;
+ signal trigger_long: std_logic;
+ -- Trigger asserted when reception begin.
+ signal trigger_rx: std_logic;
+ -- High during one clock cycle when a bit has been received.
+ signal rx_bit_valid: std_logic;
+ -- Received bit value. Valid only if rx_bit_valid is high.
+ signal rx_bit_out: std_logic;
+ -- Enables RF power, used for tearing.
+ signal power_enable: std_logic;
+
+ -- FIFO control signals
+ signal rx_fifo_q: std_logic;
+ signal rx_fifo_empty: std_logic;
+ signal rx_fifo_empty_z: std_logic;
+ signal rx_fifo_rdreq: std_logic;
+ signal rx_fifo_usedw: std_logic_vector(11 downto 0);
+ signal rx_fifo_usedw_z: std_logic_vector(11 downto 0);
+ signal trigger_reg: std_logic;
+begin
+ -- Timeout register
+ -- Default value to 2 seconds.
+ e_timeout_reg: entity work.module_wide_reg
+ generic map (wideness => 3, reset => x"2faf08")
+ port map (clock => clock, reset_n => reset_n, en => en_timeout,
+ bus_in => bus_in, value => reg_timeout);
+
+ -- Demodulation delay counter.
+ e_reg_demod_delay: entity work.module_wide_reg
+ generic map (wideness => 4, reset => x"00000000")
+ port map (clock => clock, reset_n => reset_n, en => en_demod_delay,
+ bus_in => bus_in, value => reg_demod_delay);
+
+ e_iso14443_tx: entity work.iso14443_tx
+ port map (
+ clock => clock,
+ reset_n => reset_n,
+ pattern => bus_in.write_data(1 downto 0),
+ power_enable => power_enable,
+ polarity => polarity,
+ push => push,
+ start => start,
+ busy => busy,
+ use_sync => use_sync,
+ clock_13_56 => clock_13_56,
+ timeout => reg_timeout,
+ demod_delay => reg_demod_delay(28 downto 0),
+ rx_fifo_q => rx_fifo_q,
+ rx_fifo_empty => rx_fifo_empty,
+ rx_fifo_rdreq => rx_fifo_rdreq,
+ rx_fifo_usedw => rx_fifo_usedw,
+ trigger_tx_start => trigger_tx_start,
+ trigger_tx_end => trigger_tx_end,
+ trigger_rx_start => trigger_rx_start,
+ rx => rx,
+ tx => tx );
+
+ push <= en_data and bus_in.write;
+ start <= en_status_control and bus_in.write and bus_in.write_data(0);
+
+ p_power_enable: process (clock, reset_n)
+ begin
+ if reset_n = '0' then
+ power_enable <= '0';
+ elsif rising_edge(clock) then
+ if (en_status_control = '1') and (bus_in.write = '1') then
+ power_enable <= (power_enable or bus_in.write_data(1)) and (not bus_in.write_data(2));
+ else
+ power_enable <= power_enable and (not tearing);
+ end if;
+ end if;
+ end process;
+
+ -- Transmission trigger
+ p_trigger: process (clock, reset_n)
+ begin
+ if reset_n = '0' then
+ trigger_reg <= '0';
+ trigger_long <= '0';
+ elsif rising_edge(clock) then
+ -- Trigger long is also reset if push is asserted. This is usefull
+ -- when no response is received from the card.
+ -- We also need to reset the trigger when there is no response: we
+ -- AND with busy for that purpose.
+ trigger_long <= (trigger_long and busy and (not push)
+ and (not trigger_rx_start))
+ or (trigger_tx_start and trigger_tx_start_en)
+ or (trigger_tx_end and trigger_tx_end_en);
+ trigger_reg <= (trigger_long and trigger_long_en)
+ or (trigger_tx_start and trigger_tx_start_en)
+ or (trigger_tx_end and trigger_tx_end_en)
+ or (trigger_rx_start and trigger_rx_start_en);
+ end if;
+ end process;
+
+ trigger <= trigger_reg;
+
+ e_config: entity work.module_reg
+ generic map (reset => x"00")
+ port map (
+ clock => clock,
+ reset_n => reset_n,
+ en => en_config,
+ bus_in => bus_in,
+ value => config );
+
+ trigger_tx_start_en <= config(0);
+ trigger_tx_end_en <= config(1);
+ trigger_rx_start_en <= config(2);
+ trigger_long_en <= config(3);
+ use_sync <= config(6);
+ polarity <= config(7);
+
+ status <= "0000000" & busy;
+ reg_status <= status;
+
+ rx_fifo_rdreq <= en_data and bus_in.read;
+
+ -- Reading data register pops the FIFO. We want the usedw and empty signals
+ -- of the FIFO before the pop operation, so we save them in registers when
+ -- data register is read.
+ p_fifo_z: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ rx_fifo_usedw_z <= (others => '0');
+ rx_fifo_empty_z <= '0';
+ elsif rising_edge(clock) then
+ if rx_fifo_rdreq then
+ rx_fifo_usedw_z <= rx_fifo_usedw;
+ rx_fifo_empty_z <= rx_fifo_empty;
+ else
+ rx_fifo_usedw_z <= rx_fifo_usedw_z;
+ rx_fifo_empty_z <= rx_fifo_empty_z;
+ end if;
+ end if;
+ end process;
+
+ reg_data <= rx_fifo_usedw_z(rx_fifo_usedw_z'high
+ downto rx_fifo_usedw_z'high - 5) & rx_fifo_empty_z & rx_fifo_q;
+end;
diff --git a/fpga-arch/iso14443_rx_fifo.vhd b/fpga-arch/iso14443_rx_fifo.vhd
new file mode 100644
index 0000000..9b2f375
--- /dev/null
+++ b/fpga-arch/iso14443_rx_fifo.vhd
@@ -0,0 +1,97 @@
+-- This file is part of Scaffold
+--
+-- Scaffold is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see .
+--
+--
+-- Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+library altera_mf;
+use altera_mf.all;
+
+
+entity iso14443_rx_fifo is
+port (
+ clock: in std_logic;
+ aclr: in std_logic;
+ data: in std_logic;
+ rdreq: in std_logic;
+ sclr: in std_logic;
+ wrreq: in std_logic;
+ empty: out std_logic;
+ full: out std_logic;
+ q: out std_logic;
+ usedw: out std_logic_vector(11 downto 0) );
+end;
+
+
+architecture behavior of iso14443_rx_fifo is
+ component scfifo
+ generic (
+ lpm_type: string;
+ intended_device_family: string;
+ add_ram_output_register: string;
+ lpm_numwords: integer;
+ lpm_showahead: string;
+ lpm_width: integer;
+ lpm_widthu: integer;
+ overflow_checking: string;
+ underflow_checking: string;
+ use_eab: string );
+ port (
+ clock: in std_logic;
+ aclr: in std_logic;
+ data: in std_logic_vector(0 downto 0);
+ rdreq: in std_logic;
+ sclr: in std_logic;
+ wrreq: in std_logic;
+ empty: out std_logic;
+ full: out std_logic;
+ q: out std_logic_vector(0 downto 0);
+ usedw: out std_logic_vector(11 downto 0) );
+ end component;
+
+ signal data_vec: std_logic_vector(0 downto 0);
+ signal q_vec: std_logic_vector(0 downto 0);
+begin
+ s_fifo: scfifo
+ generic map (
+ lpm_type => "scfifo",
+ intended_device_family => "Cyclone IV E",
+ add_ram_output_register => "ON",
+ lpm_numwords => 4095,
+ -- Disable showahead for more performance
+ lpm_showahead => "OFF",
+ lpm_width => 1,
+ lpm_widthu => 12,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON" )
+ port map (
+ clock => clock,
+ aclr => aclr,
+ data => data_vec,
+ rdreq => rdreq,
+ sclr => sclr,
+ wrreq => wrreq,
+ empty => empty,
+ full => full,
+ q => q_vec,
+ usedw => usedw );
+
+ q <= q_vec(0);
+ data_vec(0) <= data;
+end;
diff --git a/fpga-arch/iso14443_tx.vhd b/fpga-arch/iso14443_tx.vhd
new file mode 100644
index 0000000..6e1e9bc
--- /dev/null
+++ b/fpga-arch/iso14443_tx.vhd
@@ -0,0 +1,497 @@
+-- This file is part of Scaffold
+--
+-- Scaffold is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see .
+--
+--
+-- Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity iso14443_tx is
+port (
+ -- System clock.
+ clock: in std_logic;
+ -- System reset, active low.
+ reset_n: in std_logic;
+ -- Polarity bit to negate the output if necessary, depending on the radio
+ -- front-end.
+ polarity: std_logic;
+ -- High to resynchronize to external 13.56 MHz clock.
+ use_sync: in std_logic;
+ -- External 13.56 MHz clock.
+ -- Use to synchronize transmission with the RF front-end clock if use_sync
+ -- is enabled.
+ clock_13_56: in std_logic;
+ -- When low, forces modulation to cut power (valid only in OOK).
+ power_enable: in std_logic;
+ -- Maximum timeout value.
+ timeout: in std_logic_vector(23 downto 0);
+ -- Time to wait before starting RX decoding after transmission.
+ -- This can help to avoid demodulator noise.
+ demod_delay: in std_logic_vector(28 downto 0);
+ -- Input pattern to be pushed.
+ pattern: in std_logic_vector(1 downto 0);
+ -- When high, push pattern in the FIFO.
+ push: in std_logic;
+ -- When high, start transmission.
+ start: in std_logic;
+ -- Number of bits stored in the FIFO.
+ rx_fifo_usedw: out std_logic_vector(11 downto 0);
+ -- High when reception FIFO is empty.
+ rx_fifo_empty: out std_logic;
+ -- RX FIFO output bit.
+ rx_fifo_q: out std_logic;
+ -- RX FIFO read request.
+ rx_fifo_rdreq: in std_logic;
+ -- High when transmission or reception is ongoing.
+ busy: out std_logic;
+ -- Output trigger asserted when transmission starts.
+ trigger_tx_start: out std_logic;
+ -- Output trigger asserted when transmission ends.
+ trigger_tx_end: out std_logic;
+ -- Output trigger asserted when the card starts to respond.
+ trigger_rx_start: out std_logic;
+ -- Sub-carrier input.
+ rx: in std_logic;
+ -- Modulation output.
+ tx: out std_logic );
+end;
+
+
+architecture behavior of iso14443_tx is
+ -- FSM states
+ type state_t is (
+ st_idle,
+ st_sync,
+ st_trigger_start,
+ st_tx_fetch,
+ st_tx_copy,
+ st_tx,
+ st_trigger_tx_end,
+ st_rx_delay,
+ st_rx_wait,
+ st_rx_a,
+ st_rx_a_sample,
+ st_rx_dummy,
+ st_rx_b,
+ st_rx_b_sample,
+ st_rx_decode,
+ st_end );
+ -- Current FSM state
+ signal state: state_t;
+ -- Start signal from the 13.56 MHz clock synchronizer.
+ signal clock_sync_go: std_logic;
+ -- Symbol being transmitted.
+ signal tx_buffer: std_logic_vector(3 downto 0);
+ -- Counter used for the transmission, to generate 1/4 symbol period.
+ -- One ETU is 128/fc, which is approximatively 1/944 clock cycles.
+ -- One period is then 944 / 4 = 236, which corresponds the pause time of
+ -- 2.5 µs.
+ -- Maximum counter value will therefore be 235 for transmission.
+ -- This counter is also used for reception, with a maximum value of 469
+ -- (about half bit period).
+ signal time_counter: unsigned(8 downto 0);
+ -- Counts the number of moments during transmission of symbol.
+ signal tx_symbol_counter: unsigned(1 downto 0);
+ -- Transmission FIFO signals
+ signal tx_fifo_q: std_logic_vector(1 downto 0);
+ signal tx_fifo_empty: std_logic;
+ signal tx_fifo_full: std_logic;
+ signal tx_fifo_rdreq: std_logic;
+ -- Samples come from the output of the demoulator.
+ -- Two samples per bit are taken.
+ signal samples: std_logic_vector(1 downto 0);
+ -- High when samples is "01" or "10", corresponding to a valid Manchester
+ -- symbol.
+ signal samples_valid: std_logic;
+ -- Reception FIFO signals
+ signal rx_fifo_full: std_logic;
+ signal rx_fifo_wreq: std_logic;
+ -- Timeout counter.
+ signal timeout_counter: unsigned(29 downto 0);
+ -- Demodulation start delay counter.
+ signal demod_delay_counter: unsigned(28 downto 0);
+ -- Demodulator output.
+ signal demod_result: std_logic;
+ -- High to enable demodulator block. This help reducing power consumption
+ -- and noise: we don't need to always have it running.
+ signal demod_enable: std_logic;
+begin
+ p_state: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ state <= st_idle;
+ elsif rising_edge(clock) then
+ case state is
+ -- Nothing is happening.
+ -- Wait for the order to start transmission.
+ when st_idle =>
+ if start = '1' then
+ state <= st_sync;
+ else
+ state <= st_idle;
+ end if;
+
+ -- Transmission has been requested, we are in clock
+ -- synchronization state. Synchronization is bypassed if
+ -- use_sync is disabled.
+ when st_sync =>
+ if (clock_sync_go = '1') or (use_sync = '0') then
+ state <= st_trigger_start;
+ else
+ state <= st_sync;
+ end if;
+
+ -- One clock cycle to generate trigger.
+ when st_trigger_start =>
+ state <= st_tx_fetch;
+
+ -- One clock cycle to request FIFO pop.
+ when st_tx_fetch =>
+ state <= st_tx_copy;
+
+ -- One clock cycle to load transmission buffer from FIFO output.
+ when st_tx_copy =>
+ state <= st_tx;
+
+ -- We are transmitting bits.
+ when st_tx =>
+ if tx_symbol_counter = 0 then
+ -- We are transmitting the last moment of the current
+ -- symbol.
+ if (time_counter = 2) and (tx_fifo_empty = '0') then
+ -- We still have symbols to transmit, fetch it from
+ -- the FIFO.
+ state <= st_tx_fetch;
+ elsif time_counter = 0 then
+ -- Done transmitting all symbols.
+ state <= st_trigger_tx_end;
+ else
+ state <= st_tx;
+ end if;
+ else
+ state <= st_tx;
+ end if;
+
+ -- One clock cycle used to generate end of transmission trigger.
+ when st_trigger_tx_end =>
+ state <= st_rx_delay;
+
+ when st_rx_delay =>
+ if demod_delay_counter = 0 then
+ state <= st_rx_wait;
+ else
+ state <= st_rx_delay;
+ end if;
+
+ -- Waiting for the beginning of the response.
+ -- Goes to reception when modulation is detected, or end
+ -- reception if timeout occurs.
+ when st_rx_wait =>
+ if timeout_counter = 0 then
+ state <= st_end;
+ else
+ if demod_result = '1' then
+ state <= st_rx_a;
+ else
+ state <= st_rx_wait;
+ end if;
+ end if;
+
+ -- Waiting to be at the middle of first bit half.
+ when st_rx_a =>
+ if time_counter = 0 then
+ state <= st_rx_a_sample;
+ else
+ state <= st_rx_a;
+ end if;
+
+ -- One clock cycle to sample first bit half.
+ when st_rx_a_sample =>
+ state <= st_rx_dummy;
+
+ -- One clock dummy cycle to have same timing as second bit half
+ -- where there is a cycle for decoding. This way the time
+ -- counter is reloaded to the same value for both bit halves.
+ when st_rx_dummy =>
+ state <= st_rx_b;
+
+ -- Waiting to be at the middle of second bit half.
+ when st_rx_b =>
+ if time_counter = 0 then
+ state <= st_rx_b_sample;
+ else
+ state <= st_rx_b;
+ end if;
+
+ -- One clock cycle to sample second bit half.
+ when st_rx_b_sample =>
+ state <= st_rx_decode;
+
+ -- We took two samples for the current bit, we now have one
+ -- clock cycle to decode bit and push it in the RX FIFO. If bit
+ -- has no valid encoding, end reception.
+ when st_rx_decode =>
+ if samples_valid = '1' then
+ -- Bit has valid Manchester encoding, continue reception.
+ state <= st_rx_a;
+ else
+ -- Bit is not valid, end of transmission
+ state <= st_end;
+ end if;
+
+ when st_end =>
+ state <= st_idle;
+
+ end case;
+ end if;
+ end process;
+
+ busy <= '1' when state /= st_idle else '0';
+
+ -- Time counter to generate the correct baudrates for transmission and
+ -- reception.
+ p_time_counter: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ time_counter <= (others => '0');
+ elsif rising_edge(clock) then
+ case state is
+ -- Decrement the counter during all transmission, which includes
+ -- st_tx_fetch.
+ -- Exception: before starting transmission, when the first
+ -- symbol is fetched from the FIFO the counter will be
+ -- decremented once. This is not a problem, no need to add logic
+ -- to avoid that.
+ when st_tx | st_tx_fetch =>
+ if time_counter = 0 then
+ time_counter <= to_unsigned(235, time_counter'length);
+ else
+ time_counter <= time_counter - 1;
+ end if;
+ when st_rx_wait | st_tx_copy =>
+ -- 235 = 944 / 4 - 1 - 2
+ -- Quarter bit duration, minus one because 0 is included,
+ -- minus 2 to take into account the dummy cycle and sampling
+ -- cycle.
+ time_counter <= to_unsigned(235, time_counter'length);
+ when st_rx_a | st_rx_b =>
+ time_counter <= time_counter - 1;
+ when st_rx_a_sample | st_rx_dummy | st_rx_b_sample | st_rx_decode =>
+ -- 469 = 944 / 2 - 1 - 2
+ -- Half bit duration, minus one because 0 is included,
+ -- minus 2 to take into account the sampling cycle and
+ -- decoding cycle.
+ time_counter <= to_unsigned(469, time_counter'length);
+ when others =>
+ time_counter <= time_counter;
+ end case;
+ end if;
+ end process;
+
+ -- Symbol counting for transmission.
+ -- Counts the number of moments to be transmitted. Loaded to value 3
+ -- (4 moments) for each symbol to be transmitted.
+ p_tx_symbol_counter: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ tx_symbol_counter <= (others => '0');
+ elsif rising_edge(clock) then
+ case state is
+ when st_tx =>
+ if time_counter = 0 then
+ tx_symbol_counter <= tx_symbol_counter - 1;
+ else
+ tx_symbol_counter <= tx_symbol_counter;
+ end if;
+ when others =>
+ tx_symbol_counter <= to_unsigned(3, tx_symbol_counter'length);
+ end case;
+ end if;
+ end process;
+
+ -- Timout counter management.
+ p_timeout_counter: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ timeout_counter <= (others => '1');
+ elsif rising_edge(clock) then
+ case state is
+ when st_idle =>
+ timeout_counter <= unsigned(timeout & "000000");
+ when st_rx_wait =>
+ timeout_counter <= timeout_counter - 1;
+ when others =>
+ timeout_counter <= timeout_counter;
+ end case;
+ end if;
+ end process;
+
+ -- Transmission buffer management.
+ p_tx_buffer: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ tx_buffer <= "1111";
+ elsif rising_edge(clock) then
+ case state is
+ -- Load tx_buffer with the symbol to be transmitted right
+ -- after. Symbol is stored on 2 bits in the FIFO, so there is
+ -- some kind of decompression here.
+ when st_tx_copy =>
+ case tx_fifo_q is
+ when "00" => tx_buffer <= "0000";
+ when "11" => tx_buffer <= "1111";
+ when "01" => tx_buffer <= "0111";
+ when "10" => tx_buffer <= "1101";
+ when others => tx_buffer <= "1111";
+ end case;
+ when st_tx =>
+ if time_counter = 0 then
+ tx_buffer <= tx_buffer(2 downto 0) & "1";
+ else
+ tx_buffer <= tx_buffer;
+ end if;
+ when others =>
+ tx_buffer <= tx_buffer;
+ end case;
+ end if;
+ end process;
+
+ -- Transmission patterns storage FIFO.
+ e_tx_fifo: entity work.iso14443_tx_fifo
+ port map (
+ clock => clock,
+ aclr => not reset_n,
+ sclr => '0',
+ data => pattern,
+ wrreq => push,
+ q => tx_fifo_q,
+ full => tx_fifo_full,
+ empty => tx_fifo_empty,
+ rdreq => tx_fifo_rdreq );
+
+ tx_fifo_rdreq <= '1' when state = st_tx_fetch else '0';
+
+ -- 13.56 MHz clock synchronization block
+ e_clock_sync: entity work.iso14443_clock_sync
+ port map (
+ clock => clock,
+ reset_n => reset_n,
+ clock_13_56 => clock_13_56,
+ go => clock_sync_go );
+
+ tx <= (tx_buffer(3) and power_enable) xor polarity;
+
+ p_samples: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ samples <= "00";
+ elsif rising_edge(clock) then
+ case state is
+ when st_rx_a_sample | st_rx_b_sample =>
+ samples <= samples(0) & demod_result;
+ when others =>
+ samples <= samples;
+ end case;
+ end if;
+ end process;
+
+ samples_valid <= samples(0) xor samples(1);
+
+ p_demod_delay_counter: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ demod_delay_counter <= to_unsigned(0, demod_delay_counter'length);
+ elsif rising_edge(clock) then
+ case state is
+ when st_idle =>
+ if start = '1' then
+ demod_delay_counter <= unsigned(demod_delay);
+ else
+ demod_delay_counter <= demod_delay_counter;
+ end if;
+ when st_rx_delay =>
+ demod_delay_counter <= demod_delay_counter - 1;
+ when others =>
+ demod_delay_counter <= demod_delay_counter;
+ end case;
+ end if;
+ end process;
+
+ e_demod: entity work.iso14443_demod
+ port map (
+ clock => clock,
+ reset_n => reset_n,
+ enable => demod_enable,
+ rx => rx,
+ result => demod_result );
+
+ p_demo_enable: process (state) is
+ begin
+ case state is
+ when st_rx_wait | st_rx_a | st_rx_a_sample | st_rx_dummy | st_rx_b
+ | st_rx_b_sample | st_rx_decode =>
+ demod_enable <= '1';
+ when others =>
+ demod_enable <= '0';
+ end case;
+ end process;
+
+ -- Received bits are stored in the following FIFO.
+ -- FIFO is automatically flushed when a new transmission is requested.
+ e_rx_fifo: entity work.iso14443_rx_fifo
+ port map (
+ clock => clock,
+ aclr => not reset_n,
+ sclr => start,
+ data => samples(1),
+ wrreq => rx_fifo_wreq,
+ q => rx_fifo_q,
+ full => rx_fifo_full,
+ empty => rx_fifo_empty,
+ rdreq => rx_fifo_rdreq,
+ usedw => rx_fifo_usedw );
+
+ rx_fifo_wreq <= '1' when ((state = st_rx_decode) and (samples_valid = '1'))
+ else '0';
+
+ p_triggers: process (clock, reset_n) is
+ begin
+ if reset_n = '0' then
+ trigger_tx_start <= '0';
+ trigger_tx_end <= '0';
+ trigger_rx_start <= '0';
+ elsif rising_edge(clock) then
+ if state = st_trigger_start then
+ trigger_tx_start <= '1';
+ else
+ trigger_tx_start <= '0';
+ end if;
+ if state = st_trigger_tx_end then
+ trigger_tx_end <= '1';
+ else
+ trigger_tx_end <= '0';
+ end if;
+ if (state = st_rx_wait) and (demod_result = '1') then
+ trigger_rx_start <= '1';
+ else
+ trigger_rx_start <= '0';
+ end if;
+ end if;
+ end process;
+end;
diff --git a/fpga-arch/iso14443_tx_fifo.vhd b/fpga-arch/iso14443_tx_fifo.vhd
new file mode 100644
index 0000000..1128e2b
--- /dev/null
+++ b/fpga-arch/iso14443_tx_fifo.vhd
@@ -0,0 +1,91 @@
+-- This file is part of Scaffold
+--
+-- Scaffold is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see .
+--
+--
+-- Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+library altera_mf;
+use altera_mf.all;
+
+
+entity iso14443_tx_fifo is
+port (
+ clock: in std_logic;
+ aclr: in std_logic;
+ data: in std_logic_vector(1 downto 0);
+ rdreq: in std_logic;
+ sclr: in std_logic;
+ wrreq: in std_logic;
+ empty: out std_logic;
+ full: out std_logic;
+ q: out std_logic_vector(1 downto 0);
+ usedw: out std_logic_vector(10 downto 0) );
+end;
+
+
+architecture behavior of iso14443_tx_fifo is
+ component scfifo
+ generic (
+ lpm_type: string;
+ intended_device_family: string;
+ add_ram_output_register: string;
+ lpm_numwords: integer;
+ lpm_showahead: string;
+ lpm_width: integer;
+ lpm_widthu: integer;
+ overflow_checking: string;
+ underflow_checking: string;
+ use_eab: string );
+ port (
+ clock: in std_logic;
+ aclr: in std_logic;
+ data: in std_logic_vector(1 downto 0);
+ rdreq: in std_logic;
+ sclr: in std_logic;
+ wrreq: in std_logic;
+ empty: out std_logic;
+ full: out std_logic;
+ q: out std_logic_vector(1 downto 0);
+ usedw: out std_logic_vector(10 downto 0) );
+ end component;
+begin
+ s_fifo: scfifo
+ generic map (
+ lpm_type => "scfifo",
+ intended_device_family => "Cyclone IV E",
+ add_ram_output_register => "ON",
+ lpm_numwords => 2048,
+ -- Disable showahead for more performance
+ lpm_showahead => "OFF",
+ lpm_width => 2,
+ lpm_widthu => 11,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON" )
+ port map (
+ clock => clock,
+ aclr => aclr,
+ data => data,
+ rdreq => rdreq,
+ sclr => sclr,
+ wrreq => wrreq,
+ empty => empty,
+ full => full,
+ q => q,
+ usedw => usedw );
+end;
diff --git a/fpga-arch/scaffold.qsf b/fpga-arch/scaffold.qsf
index 80a45e7..a6bc652 100644
--- a/fpga-arch/scaffold.qsf
+++ b/fpga-arch/scaffold.qsf
@@ -88,10 +88,21 @@ set_location_assignment PIN_113 -to io[32]
set_location_assignment PIN_115 -to io[33]
set_location_assignment PIN_125 -to io[34]
set_location_assignment PIN_120 -to io[35]
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VHDL_FILE fifo2048.vhd
+set_global_assignment -name VHDL_FILE iso14443_demod.vhd
+set_global_assignment -name VHDL_FILE iso14443_clock_sync.vhd
+set_global_assignment -name VHDL_FILE iso14443_rx_fifo.vhd
+set_global_assignment -name VHDL_FILE iso14443_tx_fifo.vhd
+set_global_assignment -name VHDL_FILE iso14443_tx.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE iso14443_module.vhd
set_global_assignment -name VHDL_FILE buffered_uart_rx.vhd
set_global_assignment -name VHDL_FILE buffered_uart_tx.vhd
set_global_assignment -name VHDL_FILE spi_slave.vhd
@@ -134,8 +145,4 @@ set_global_assignment -name VHDL_FILE uart_module.vhd
set_global_assignment -name VHDL_FILE uart_rx.vhd
set_global_assignment -name VHDL_FILE uart_tx.vhd
set_global_assignment -name VHDL_FILE version_module.vhd
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/fpga-arch/system.vhd b/fpga-arch/system.vhd
index 4047acb..0fbca45 100644
--- a/fpga-arch/system.vhd
+++ b/fpga-arch/system.vhd
@@ -151,7 +151,8 @@ architecture behavior of system is
+ 1 -- I2C trigger
+ 1 -- SPI trigger
+ pulse_gen_count -- Pulse generator outputs
- + chain_count; -- Chain trigger
+ + chain_count -- Chain trigger
+ + 1; -- ISO 14443-A trigger
signal mtxl_in: std_logic_vector(mtxl_in_count-1 downto 0);
-- Left matrix outputs. Inputs of modules.
@@ -161,7 +162,8 @@ architecture behavior of system is
+ 2 -- I2C
+ 1 -- SPI
+ 2 -- SPI slave
- + 1; -- Clock
+ + 1 -- Clock
+ + 3; -- ISO14443
signal mtxl_out: std_logic_vector(mtxl_out_count-1 downto 0);
signal mtxl_out_uart_rx: std_logic_vector(uart_count-1 downto 0);
signal mtxl_out_pulse_gen_start: std_logic_vector(pulse_gen_count-1 downto 0);
@@ -174,6 +176,9 @@ architecture behavior of system is
signal mtxl_out_clock_glitch_start: std_logic;
signal mtxl_out_chain_events:
std_logic_vector_array_t(chain_count-1 downto 0)(chain_size-1 downto 0);
+ signal mtxl_out_iso14443_rx: std_logic;
+ signal mtxl_out_iso14443_clock_13_56: std_logic;
+ signal mtxl_out_iso14443_tearing: std_logic;
-- Right matrix inputs. Output of modules.
-- Each output wire has two signals: a value and an output enable.
@@ -184,7 +189,8 @@ architecture behavior of system is
+ 3 -- I2C module
+ 4 -- SPI module
+ 1 -- SPI slave module
- + 1; -- Clock
+ + 1 -- Clock
+ + 2; -- ISO 14443-A
signal mtxr_in: tristate_array_t(mtxr_in_count-1 downto 0);
signal mtxr_in_uart_tx: std_logic_vector(uart_count-1 downto 0);
signal mtxr_in_uart_trigger: std_logic_vector(uart_count-1 downto 0);
@@ -204,6 +210,8 @@ architecture behavior of system is
signal mtxr_in_spi_slave_miso: std_logic;
signal mtxr_in_clock_out: std_logic;
signal mtxr_in_chain_out: std_logic_vector(chain_count-1 downto 0);
+ signal mtxr_in_iso14443_tx: std_logic;
+ signal mtxr_in_iso14443_trigger: std_logic;
-- Output signals of the output matrix
constant mtxr_out_count: positive := io_count;
@@ -258,6 +266,11 @@ architecture behavior of system is
constant addr_clock_divisor_a: address_t := x"0a01";
constant addr_clock_divisor_b: address_t := x"0a02";
constant addr_clock_count: address_t := x"0a03";
+ constant addr_iso14443_status_control: address_t := x"0b00";
+ constant addr_iso14443_config: address_t := x"0b01";
+ constant addr_iso14443_data: address_t := x"0b02";
+ constant addr_iso14443_timeout: address_t := x"0b03";
+ constant addr_iso14443_demod_delay: address_t := x"0b04";
constant addr_io_value_base: address_t := x"e000";
constant addr_io_config_base: address_t := x"e001";
constant addr_mtxl_base: address_t := x"f000";
@@ -307,6 +320,11 @@ architecture behavior of system is
signal en_clock_divisor_a: std_logic;
signal en_clock_divisor_b: std_logic;
signal en_clock_count: std_logic;
+ signal en_iso14443_status_control: std_logic;
+ signal en_iso14443_config: std_logic;
+ signal en_iso14443_data: std_logic;
+ signal en_iso14443_timeout: std_logic;
+ signal en_iso14443_demod_delay: std_logic;
signal en_io_value: std_logic_vector(io_count-1 downto 0);
signal en_io_config: std_logic_vector(io_count-1 downto 0);
signal en_mtxl_sel: std_logic_vector(mtxl_out_count-1 downto 0);
@@ -323,7 +341,8 @@ architecture behavior of system is
+ 1 -- Power control
+ 2 -- ISO7816 status and data
+ 4 -- I2C
- + 2; -- SPI
+ + 2 -- SPI
+ + 2; -- ISO14443
signal reg_io_value: std_logic_vector_array_t(io_count-1 downto 0)
(7 downto 0);
signal reg_version_data: byte_t;
@@ -335,6 +354,7 @@ architecture behavior of system is
signal reg_power_control: byte_t;
signal reg_i2c_status, reg_i2c_data, reg_i2c_size_h, reg_i2c_size_l: byte_t;
signal reg_spi_status, reg_spi_data: byte_t;
+ signal reg_iso14443_status, reg_iso14443_data: byte_t;
-- State of the LEDs (when override is disabled in LEDs module).
signal leds: std_logic_vector(23 downto 0);
@@ -434,6 +454,11 @@ begin
en_clock_divisor_a <= addr_en(bus_in, addr_clock_divisor_a);
en_clock_divisor_b <= addr_en(bus_in, addr_clock_divisor_b);
en_clock_count <= addr_en(bus_in, addr_clock_count);
+ en_iso14443_status_control <= addr_en(bus_in, addr_iso14443_status_control);
+ en_iso14443_config <= addr_en(bus_in, addr_iso14443_config);
+ en_iso14443_data <= addr_en(bus_in, addr_iso14443_data);
+ en_iso14443_timeout <= addr_en(bus_in, addr_iso14443_timeout);
+ en_iso14443_demod_delay <= addr_en(bus_in, addr_iso14443_demod_delay);
en_io_value <= addr_en_loop(bus_in, addr_io_value_base, x"0010", io_count);
en_io_config <=
addr_en_loop(bus_in, addr_io_config_base, x"0010", io_count);
@@ -461,7 +486,9 @@ begin
reg_iso7816_status &
reg_iso7816_data &
reg_spi_status &
- reg_spi_data,
+ reg_spi_data &
+ reg_iso14443_status &
+ reg_iso14443_data,
enables =>
en_io_value &
en_pulse_gen_status &
@@ -476,7 +503,9 @@ begin
en_iso7816_status &
en_iso7816_data &
en_spi_status &
- en_spi_data,
+ en_spi_data &
+ en_iso14443_status_control &
+ en_iso14443_data,
value => bus_out.read_data );
-- I/O modules
@@ -520,7 +549,7 @@ begin
-- Version module
e_version_module: entity work.version_module
- generic map (version => "scaffold-0.9")
+ generic map (version => "scaffold-0.10")
port map (
clock => clock,
reset_n => reset_n,
@@ -694,6 +723,25 @@ begin
output => mtxr_in_clock_out,
glitch_start => mtxl_out_clock_glitch_start );
+ -- ISO 14443-A module
+ e_iso14443: entity work.iso14443_module
+ port map (
+ clock => clock,
+ reset_n => reset_n,
+ bus_in => bus_in,
+ en_status_control => en_iso14443_status_control,
+ en_config => en_iso14443_config,
+ en_data => en_iso14443_data,
+ en_timeout => en_iso14443_timeout,
+ en_demod_delay => en_iso14443_demod_delay,
+ reg_status => reg_iso14443_status,
+ reg_data => reg_iso14443_data,
+ tx => mtxr_in_iso14443_tx,
+ rx => mtxl_out_iso14443_rx,
+ clock_13_56 => mtxl_out_iso14443_clock_13_56,
+ tearing => mtxl_out_iso14443_tearing,
+ trigger => mtxr_in_iso14443_trigger );
+
-- Left matrix module
e_left_matrix_module: entity work.left_matrix_module
generic map (
@@ -733,6 +781,12 @@ begin
end loop;
mtxl_out_clock_glitch_start <= mtxl_out(i);
i := i + 1;
+ mtxl_out_iso14443_rx <= mtxl_out(i);
+ i := i + 1;
+ mtxl_out_iso14443_clock_13_56 <= mtxl_out(i);
+ i := i + 1;
+ mtxl_out_iso14443_tearing <= mtxl_out(i);
+ i := i + 1;
assert i = mtxl_out_count;
end process;
@@ -740,6 +794,7 @@ begin
-- mtxr signals are feedback outputs of modules.
-- Warning: signals order is inversed regarding Python API code.
mtxl_in <=
+ mtxr_in_iso14443_trigger &
mtxr_in_chain_out &
mtxr_in_pulse_gen_out &
mtxr_in_spi_trigger &
@@ -783,7 +838,9 @@ begin
mtxr_in_spi_trigger,
mtxr_in_spi_slave_miso,
mtxr_in_chain_out,
- mtxr_in_clock_out )
+ mtxr_in_clock_out,
+ mtxr_in_iso14443_tx,
+ mtxr_in_iso14443_trigger )
variable i: integer;
begin
mtxr_in(0) <= "00"; -- Z
@@ -831,6 +888,10 @@ begin
-- Clock module
mtxr_in(i) <= "1" & mtxr_in_clock_out;
i := i + 1;
+ -- ISO 14443-A module
+ mtxr_in(i) <= "1" & mtxr_in_iso14443_tx;
+ mtxr_in(i+1) <= "1" & mtxr_in_iso14443_trigger;
+ i := i + 2;
-- If you add other signals, please dont forget to update the sensivity
-- list for simulation support.
assert i = mtxr_in_count;
diff --git a/fpga-sim/sim_iso14443_tx.vhd b/fpga-sim/sim_iso14443_tx.vhd
new file mode 100644
index 0000000..6f52325
--- /dev/null
+++ b/fpga-sim/sim_iso14443_tx.vhd
@@ -0,0 +1,205 @@
+-- This file is part of Scaffold
+--
+-- Scaffold is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see .
+--
+--
+-- Copyright 2025 Ledger SAS, written by Olivier Hériveaux
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.common_pkg.all;
+
+
+entity sim_iso14443_tx is end;
+
+
+architecture behavior of sim_iso14443_tx is
+ constant clock_frequency: integer := 100000000;
+ constant clock_period: time := (1 sec) / clock_frequency;
+ constant bit_period: time := 9.4395 us;
+ constant mod_half_period: time := bit_period / 16;
+
+ -- External clock
+ signal clock: std_logic;
+ -- Reset
+ signal reset_n: std_logic;
+
+ -- Input signals
+ signal polarity: std_logic;
+ signal push: std_logic;
+ signal start: std_logic;
+ signal pattern: std_logic_vector(1 downto 0);
+ signal rx: std_logic;
+
+ -- Output signals
+ signal busy: std_logic;
+ signal tx: std_logic;
+ signal trigger_tx_start: std_logic;
+ signal trigger_tx_end: std_logic;
+
+begin
+
+ e_iso14443: entity work.iso14443_tx
+ port map (
+ clock => clock,
+ reset_n => reset_n,
+ polarity => polarity,
+ use_sync => '0',
+ clock_13_56 => '0',
+ power_enable => '1',
+ pattern => pattern,
+ push => push,
+ start => start,
+ --busy => busy,
+ tx => tx,
+ rx => rx,
+ timeout => x"ffffff",
+ demod_delay => x"000050",
+ trigger_tx_start => trigger_tx_start,
+ trigger_tx_end => trigger_tx_end,
+ rx_fifo_rdreq => '0' );
+
+ -- External clock generation
+ p_clock: process
+ begin
+ clock <= '0';
+ wait for clock_period / 2;
+ clock <= '1';
+ wait for clock_period / 2;
+ end process;
+
+ -- Reset signal
+ p_reset: process
+ begin
+ reset_n <= '0';
+ wait for clock_period * 4;
+ reset_n <= '1';
+ wait;
+ end process;
+
+ p_0: process is
+ begin
+ polarity <= '0';
+ push <= '0';
+ start <= '0';
+ pattern <= "11";
+ rx <= '0';
+ wait for clock_period * 100;
+
+ pattern <= "01";
+ push <= '1';
+ wait for clock_period;
+ push <= '0';
+ pattern <= "01";
+ push <= '1';
+ wait for clock_period;
+ push <= '0';
+ pattern <= "01";
+ push <= '1';
+ wait for clock_period;
+ push <= '0';
+
+ wait for clock_period;
+ start <= '1';
+ wait for clock_period;
+ start <= '0';
+
+ wait for bit_period * 5;
+
+ rx <= '1';
+ wait for mod_half_period;
+
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ wait for mod_half_period * 8;
+
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ wait for mod_half_period * 8;
+
+ wait for mod_half_period * 8;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+ rx <= '0';
+ wait for mod_half_period;
+ rx <= '1';
+ wait for mod_half_period;
+
+ wait for bit_period * 5;
+
+ pattern <= "01";
+ push <= '1';
+ wait for clock_period;
+ push <= '0';
+ pattern <= "01";
+ push <= '1';
+ wait for clock_period;
+ push <= '0';
+ pattern <= "01";
+ push <= '1';
+ wait for clock_period;
+ push <= '0';
+
+ wait for clock_period;
+ start <= '1';
+ wait for clock_period;
+ start <= '0';
+
+ wait for bit_period * 5;
+
+
+ wait;
+ end process;
+
+end;