diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc index ecf31f72cc..96d9afac9d 100644 --- a/include/LLVMSPIRVExtensions.inc +++ b/include/LLVMSPIRVExtensions.inc @@ -22,3 +22,4 @@ EXT(SPV_INTEL_optimization_hints) EXT(SPV_INTEL_float_controls2) EXT(SPV_INTEL_vector_compute) EXT(SPV_INTEL_usm_storage_classes) +EXT(SPV_INTEL_arbitrary_precision_fixed_point) diff --git a/lib/SPIRV/OCLUtil.h b/lib/SPIRV/OCLUtil.h index b6409f874d..e2291af4df 100644 --- a/lib/SPIRV/OCLUtil.h +++ b/lib/SPIRV/OCLUtil.h @@ -183,6 +183,17 @@ const static char Clamp[] = "clamp"; const static char ConvertPrefix[] = "convert_"; const static char Dot[] = "dot"; const static char EnqueueKernel[] = "enqueue_kernel"; +const static char FixedSqrtINTEL[] = "intel_arbitrary_fixed_sqrt"; +const static char FixedRecipINTEL[] = "intel_arbitrary_fixed_recip"; +const static char FixedRsqrtINTEL[] = "intel_arbitrary_fixed_rsqrt"; +const static char FixedSinINTEL[] = "intel_arbitrary_fixed_sin"; +const static char FixedCosINTEL[] = "intel_arbitrary_fixed_cos"; +const static char FixedSinCosINTEL[] = "intel_arbitrary_fixed_sincos"; +const static char FixedSinPiINTEL[] = "intel_arbitrary_fixed_sinpi"; +const static char FixedCosPiINTEL[] = "intel_arbitrary_fixed_cospi"; +const static char FixedSinCosPiINTEL[] = "intel_arbitrary_fixed_sincospi"; +const static char FixedLogINTEL[] = "intel_arbitrary_fixed_log"; +const static char FixedExpINTEL[] = "intel_arbitrary_fixed_exp"; const static char FMax[] = "fmax"; const static char FMin[] = "fmin"; const static char FPGARegIntel[] = "__builtin_intel_fpga_reg"; @@ -1109,6 +1120,26 @@ template <> inline void LLVMSPIRVAtomicRmwOpCodeMap::init() { add(llvm::AtomicRMWInst::UMin, OpAtomicUMin); } +class SPIRVFixedPointIntelInst; +template <> +inline void SPIRVMap::init() { +#define _SPIRV_OP(x, y) add("intel_arbitrary_fixed_" #x, OpFixed##y##INTEL); + _SPIRV_OP(sqrt, Sqrt) + _SPIRV_OP(recip, Recip) + _SPIRV_OP(rsqrt, Rsqrt) + _SPIRV_OP(sin, Sin) + _SPIRV_OP(cos, Cos) + _SPIRV_OP(sincos, SinCos) + _SPIRV_OP(sinpi, SinPi) + _SPIRV_OP(cospi, CosPi) + _SPIRV_OP(sincospi, SinCosPi) + _SPIRV_OP(log, Log) + _SPIRV_OP(exp, Exp) +#undef _SPIRV_OP +} +typedef SPIRVMap + SPIRVFixedPointIntelMap; + } // namespace SPIRV #endif // SPIRV_OCLUTIL_H diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp index 972beb7c66..ee87d1ad7a 100644 --- a/lib/SPIRV/SPIRVReader.cpp +++ b/lib/SPIRV/SPIRVReader.cpp @@ -2375,6 +2375,19 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F, auto *IntrinsicCall = Builder.CreateIntrinsic(IID, RetTy, Args); return mapValue(BV, IntrinsicCall); } + case OpFixedSqrtINTEL: + case OpFixedRecipINTEL: + case OpFixedRsqrtINTEL: + case OpFixedSinINTEL: + case OpFixedCosINTEL: + case OpFixedSinCosINTEL: + case OpFixedSinPiINTEL: + case OpFixedCosPiINTEL: + case OpFixedSinCosPiINTEL: + case OpFixedLogINTEL: + case OpFixedExpINTEL: + return mapValue( + BV, transFixedPointInst(static_cast(BV), BB)); default: { auto OC = BV->getOpCode(); if (isSPIRVCmpInstTransToLLVMInst(static_cast(BV))) { @@ -2399,6 +2412,64 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F, } } +CallInst *SPIRVToLLVM::transFixedPointInst(SPIRVInstruction *BI, + BasicBlock *BB) { + // LLVM fixed point functions return value: + // iN + // Arguments: + // A(iN), S(i1), I(i32), rI(i32), Quantization(i32), Overflow(i32) + + // SPIR-V fixed point instruction contains: + // ResTy Res InTy In \ + // Literal S Literal I Literal rI Literal Q Literal O + + Type *RetTy = transType(BI->getType()); + + auto Inst = static_cast(BI); + Type *InTy = transType(Inst->getOperand(1)->getType()); + + IntegerType *Int32Ty = IntegerType::get(*Context, 32); + IntegerType *Int1Ty = IntegerType::get(*Context, 1); + + SmallVector ArgTys = {InTy, Int1Ty, Int32Ty, + Int32Ty, Int32Ty, Int32Ty}; + FunctionType *FT = FunctionType::get(RetTy, ArgTys, false); + + // Add meaningful suffix at the end of the function name to avoid ascending + // numerical suffixes. It is useful in situations, where the same function is + // called twice or more in one basic block. So, the function name is formed in + // the following way: [FuncName].[ReturnTy].[InputTy] + std::stringstream Suffix; + Suffix << ".i" << RetTy->getIntegerBitWidth() << ".i" + << InTy->getIntegerBitWidth(); + + Op OpCode = Inst->getOpCode(); + std::string FuncName = SPIRVFixedPointIntelMap::rmap(OpCode) + Suffix.str(); + + FunctionCallee FCallee = M->getOrInsertFunction(FuncName, FT); + + if (Function *Fn = dyn_cast(FCallee.getCallee())) { + Fn->setCallingConv(CallingConv::SPIR_FUNC); + if (isFuncNoUnwind()) + Fn->addFnAttr(Attribute::NoUnwind); + } + + // Words contain: + // InTy In Literal S Literal I Literal rI Literal Q Literal O + auto Words = Inst->getOpWords(); + std::vector Args = { + transValue(Inst->getOperand(1), BB->getParent(), BB) /* A - input */, + ConstantInt::get(Int1Ty, Words[2]) /* S - indicator of signedness */, + ConstantInt::get(Int32Ty, + Words[3]) /* I - fixed-point location of the input */, + ConstantInt::get(Int32Ty, + Words[4]) /* rI - fixed-point location of the result*/, + ConstantInt::get(Int32Ty, Words[5]) /* Quantization mode */, + ConstantInt::get(Int32Ty, Words[6]) /* Overflow mode */}; + + return CallInst::Create(FCallee, Args, "", BB); +} + template bool SPIRVToLLVM::foreachFuncCtlMask(SourceTy Source, FuncTy Func) { SPIRVWord FCM = Source->getFuncCtlMask(); diff --git a/lib/SPIRV/SPIRVReader.h b/lib/SPIRV/SPIRVReader.h index e33ce316d6..41b3173d7f 100644 --- a/lib/SPIRV/SPIRVReader.h +++ b/lib/SPIRV/SPIRVReader.h @@ -108,6 +108,7 @@ class SPIRVToLLVM { Value *transAsmINTEL(SPIRVAsmINTEL *BA); CallInst *transAsmCallINTEL(SPIRVAsmCallINTEL *BI, Function *F, BasicBlock *BB); + CallInst *transFixedPointInst(SPIRVInstruction *BI, BasicBlock *BB); bool transNonTemporalMetadata(Instruction *I); bool transSourceLanguage(); bool transSourceExtension(); diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp index a7617ac8e1..7b1d34f460 100644 --- a/lib/SPIRV/SPIRVWriter.cpp +++ b/lib/SPIRV/SPIRVWriter.cpp @@ -2570,6 +2570,11 @@ SPIRVInstruction *LLVMToSPIRV::transBuiltinToInst(StringRef DemangledName, !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_blocking_pipes)) return nullptr; + if (OpFixedSqrtINTEL <= OC && OC <= OpFixedExpINTEL && + !BM->isAllowedToUseExtension( + ExtensionID::SPV_INTEL_arbitrary_precision_fixed_point)) + return nullptr; + auto Inst = transBuiltinToInstWithoutDecoration(OC, CI, BB); addDecorations(Inst, Dec); return Inst; @@ -2867,6 +2872,45 @@ LLVMToSPIRV::transBuiltinToInstWithoutDecoration(Op OC, CallInst *CI, transValue(Image, BB), transValue(Sampler, BB), BB); } + case OpFixedSqrtINTEL: + case OpFixedRecipINTEL: + case OpFixedRsqrtINTEL: + case OpFixedSinINTEL: + case OpFixedCosINTEL: + case OpFixedSinCosINTEL: + case OpFixedSinPiINTEL: + case OpFixedCosPiINTEL: + case OpFixedSinCosPiINTEL: + case OpFixedLogINTEL: + case OpFixedExpINTEL: { + // LLVM fixed point functions return value: + // iN + // Arguments: + // A(iN), S(i1), I(i32), rI(i32), Quantization(i32), Overflow(i32) + // where A - integer input of any width. + + // SPIR-V fixed point instruction contains: + // ResTy Res InTy In \ + // Literal S Literal I Literal rI Literal Q Literal O + + Type *ResTy = CI->getType(); + SPIRVValue *Input = + transValue(CI->getOperand(0) /* A - integer input of any width */, BB); + + std::vector Operands = { + CI->getOperand(1) /* S - bool value, indicator of signedness */, + CI->getOperand(2) /* I - location of the fixed-point of the input */, + CI->getOperand(3) /* rI - location of the fixed-point of the result*/, + CI->getOperand(4) /* Quantization mode */, + CI->getOperand(5) /* Overflow mode */}; + std::vector Literals; + for (auto *O : Operands) { + Literals.push_back(cast(O)->getZExtValue()); + } + + return BM->addFixedPointIntelInst(OC, transType(ResTy), Input, Literals, + BB); + } default: { if (isCvtOpCode(OC) && OC != OpGenericCastToPtrExplicit) { return BM->addUnaryInst(OC, transType(CI->getType()), diff --git a/lib/SPIRV/libSPIRV/SPIRVInstruction.h b/lib/SPIRV/libSPIRV/SPIRVInstruction.h index 4ea5036138..f0694cbc0f 100644 --- a/lib/SPIRV/libSPIRV/SPIRVInstruction.h +++ b/lib/SPIRV/libSPIRV/SPIRVInstruction.h @@ -2660,6 +2660,33 @@ _SPIRV_OP(ReadPipeBlockingINTEL, false, 5) _SPIRV_OP(WritePipeBlockingINTEL, false, 5) #undef _SPIRV_OP +class SPIRVFixedPointIntelInst : public SPIRVInstTemplateBase { +protected: + SPIRVCapVec getRequiredCapability() const override { + return getVec(CapabilityArbitraryPrecisionFixedPointINTEL); + } + + SPIRVExtSet getRequiredExtensions() const override { + return getSet(ExtensionID::SPV_INTEL_arbitrary_precision_fixed_point); + } +}; + +#define _SPIRV_OP(x, ...) \ + typedef SPIRVInstTemplate \ + SPIRV##x; +_SPIRV_OP(FixedSqrtINTEL, true, 10) +_SPIRV_OP(FixedRecipINTEL, true, 10) +_SPIRV_OP(FixedRsqrtINTEL, true, 10) +_SPIRV_OP(FixedSinINTEL, true, 10) +_SPIRV_OP(FixedCosINTEL, true, 10) +_SPIRV_OP(FixedSinCosINTEL, true, 10) +_SPIRV_OP(FixedSinPiINTEL, true, 10) +_SPIRV_OP(FixedCosPiINTEL, true, 10) +_SPIRV_OP(FixedSinCosPiINTEL, true, 10) +_SPIRV_OP(FixedLogINTEL, true, 10) +_SPIRV_OP(FixedExpINTEL, true, 10) +#undef _SPIRV_OP + class SPIRVAtomicInstBase : public SPIRVInstTemplateBase { public: SPIRVCapVec getRequiredCapability() const override { diff --git a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h index 2b6b0bc3d0..00391d600b 100644 --- a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h @@ -609,6 +609,7 @@ inline bool isValid(spv::Capability V) { case CapabilityUnstructuredLoopControlsINTEL: case CapabilityKernelAttributesINTEL: case CapabilityFPGAKernelAttributesINTEL: + case CapabilityArbitraryPrecisionFixedPointINTEL: return true; default: return false; @@ -870,6 +871,17 @@ inline bool isValid(spv::Op V) { case OpGroupSMax: case OpReadPipe: case OpWritePipe: + case OpFixedSqrtINTEL: + case OpFixedRecipINTEL: + case OpFixedRsqrtINTEL: + case OpFixedSinINTEL: + case OpFixedCosINTEL: + case OpFixedSinCosINTEL: + case OpFixedSinPiINTEL: + case OpFixedCosPiINTEL: + case OpFixedSinCosPiINTEL: + case OpFixedLogINTEL: + case OpFixedExpINTEL: case OpReadPipeBlockingINTEL: case OpWritePipeBlockingINTEL: case OpReservedReadPipe: diff --git a/lib/SPIRV/libSPIRV/SPIRVModule.cpp b/lib/SPIRV/libSPIRV/SPIRVModule.cpp index de2f3b5746..e0a740d44b 100644 --- a/lib/SPIRV/libSPIRV/SPIRVModule.cpp +++ b/lib/SPIRV/libSPIRV/SPIRVModule.cpp @@ -364,6 +364,10 @@ class SPIRVModuleImpl : public SPIRVModule { addLoopControlINTELInst(SPIRVWord LoopControl, std::vector LoopControlParameters, SPIRVBasicBlock *BB) override; + SPIRVInstruction *addFixedPointIntelInst(Op OC, SPIRVType *ResTy, + SPIRVValue *Input, + const std::vector &Ops, + SPIRVBasicBlock *BB) override; SPIRVInstruction *addSelectionMergeInst(SPIRVId MergeBlock, SPIRVWord SelectionControl, SPIRVBasicBlock *BB) override; @@ -1410,6 +1414,15 @@ SPIRVInstruction *SPIRVModuleImpl::addLoopControlINTELInst( const_cast(BB->getTerminateInstr())); } +SPIRVInstruction *SPIRVModuleImpl::addFixedPointIntelInst( + Op OC, SPIRVType *ResTy, SPIRVValue *Input, + const std::vector &Ops, SPIRVBasicBlock *BB) { + std::vector TheOps = + getVec(Input->getType()->getId(), getVec(Input->getId(), Ops)); + return addInstruction( + SPIRVInstTemplateBase::create(OC, ResTy, getId(), TheOps, BB, this), BB); +} + SPIRVInstruction * SPIRVModuleImpl::addPtrAccessChainInst(SPIRVType *Type, SPIRVValue *Base, std::vector Indices, diff --git a/lib/SPIRV/libSPIRV/SPIRVModule.h b/lib/SPIRV/libSPIRV/SPIRVModule.h index a4ec3ef3b7..208fd814f6 100644 --- a/lib/SPIRV/libSPIRV/SPIRVModule.h +++ b/lib/SPIRV/libSPIRV/SPIRVModule.h @@ -372,6 +372,10 @@ class SPIRVModule { addLoopControlINTELInst(SPIRVWord LoopControl, std::vector LoopControlParameters, SPIRVBasicBlock *BB) = 0; + virtual SPIRVInstruction * + addFixedPointIntelInst(Op OC, SPIRVType *ResTy, SPIRVValue *Input, + const std::vector &Ops, + SPIRVBasicBlock *BB) = 0; virtual SPIRVInstruction *addStoreInst(SPIRVValue *, SPIRVValue *, const std::vector &, SPIRVBasicBlock *) = 0; diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index a1a1d194c4..40fd0869f3 100644 --- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -541,6 +541,8 @@ template <> inline void SPIRVMap::init() { add(CapabilityIndirectReferencesINTEL, "IndirectReferencesINTEL"); add(CapabilityKernelAttributesINTEL, "KernelAttributesINTEL"); add(CapabilityFPGAKernelAttributesINTEL, "FPGAKernelAttributesINTEL"); + add(CapabilityArbitraryPrecisionFixedPointINTEL, + "ArbitraryPrecisionFixedPointINTEL"); add(CapabilityIOPipeINTEL, "IOPipeINTEL"); add(CapabilityOptimizationHintsINTEL, "OptimizationHintsINTEL"); add(CapabilityGroupNonUniform, "GroupNonUniform"); diff --git a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h index ceaad8ec5a..d34bc5333d 100644 --- a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h @@ -469,6 +469,17 @@ _SPIRV_OP(SubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL, 5814) _SPIRV_OP(SubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL, 5815) _SPIRV_OP(SubgroupAvcSicGetInterRawSadsINTEL, 5816) _SPIRV_OP(LoopControlINTEL, 5887) +_SPIRV_OP(FixedSqrtINTEL, 5923) +_SPIRV_OP(FixedRecipINTEL, 5924) +_SPIRV_OP(FixedRsqrtINTEL, 5925) +_SPIRV_OP(FixedSinINTEL, 5926) +_SPIRV_OP(FixedCosINTEL, 5927) +_SPIRV_OP(FixedSinCosINTEL, 5928) +_SPIRV_OP(FixedSinPiINTEL, 5929) +_SPIRV_OP(FixedCosPiINTEL, 5930) +_SPIRV_OP(FixedSinCosPiINTEL, 5931) +_SPIRV_OP(FixedLogINTEL, 5932) +_SPIRV_OP(FixedExpINTEL, 5933) _SPIRV_OP(PtrCastToCrossWorkgroupINTEL, 5934) _SPIRV_OP(CrossWorkgroupCastToPtrINTEL, 5938) _SPIRV_OP(ReadPipeBlockingINTEL, 5946) diff --git a/lib/SPIRV/libSPIRV/spirv.hpp b/lib/SPIRV/libSPIRV/spirv.hpp index bb2f1f3161..607d5f1479 100644 --- a/lib/SPIRV/libSPIRV/spirv.hpp +++ b/lib/SPIRV/libSPIRV/spirv.hpp @@ -955,6 +955,7 @@ enum Capability { CapabilityFPGARegINTEL = 5948, CapabilityKernelAttributesINTEL = 5892, CapabilityFPGAKernelAttributesINTEL = 5897, + CapabilityArbitraryPrecisionFixedPointINTEL = 5922, CapabilityUSMStorageClassesINTEL = 5935, CapabilityIOPipeINTEL = 5943, CapabilityMax = 0x7fffffff, @@ -1496,6 +1497,17 @@ enum Op { OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815, OpSubgroupAvcSicGetInterRawSadsINTEL = 5816, OpLoopControlINTEL = 5887, + OpFixedSqrtINTEL = 5923, + OpFixedRecipINTEL = 5924, + OpFixedRsqrtINTEL = 5925, + OpFixedSinINTEL = 5926, + OpFixedCosINTEL = 5927, + OpFixedSinCosINTEL = 5928, + OpFixedSinPiINTEL = 5929, + OpFixedCosPiINTEL = 5930, + OpFixedSinCosPiINTEL = 5931, + OpFixedLogINTEL = 5932, + OpFixedExpINTEL = 5933, OpPtrCastToCrossWorkgroupINTEL = 5934, OpCrossWorkgroupCastToPtrINTEL = 5938, OpReadPipeBlockingINTEL = 5946, diff --git a/test/capability-arbitrary-precision-fixed-point-numbers.ll b/test/capability-arbitrary-precision-fixed-point-numbers.ll new file mode 100644 index 0000000000..ef68f70dec --- /dev/null +++ b/test/capability-arbitrary-precision-fixed-point-numbers.ll @@ -0,0 +1,583 @@ +; SYCL source (compiled with -S -emit-llvm -fsycl-device-only): +; template +; void sqrt() { +; ap_int a; +; auto ap_fixed_Sqrt = __spirv_FixedSqrtINTEL(a, S, I, rI); +; ap_int b; +; auto ap_fixed_Sqrt_b = __spirv_FixedSqrtINTEL(b, S, I, rI); +; ap_int c; +; auto ap_fixed_Sqrt_c = __spirv_FixedSqrtINTEL(c, S, I, rI); +; } + +; template +; void recip() { +; ap_int a; +; auto ap_fixed_Recip = __spirv_FixedRecipINTEL(a, S, I, rI); +; } + +; template +; void rsqrt() { +; ap_int a; +; auto ap_fixed_Rsqrt = __spirv_FixedRsqrtINTEL(a, S, I, rI); +; } + +; template +; void sin() { +; ap_int a; +; auto ap_fixed_Sin = __spirv_FixedSinINTEL(a, S, I, rI); +; } + +; template +; void cos() { +; ap_int a; +; auto ap_fixed_Cos = __spirv_FixedCosINTEL(a, S, I, rI); +; } + +; template +; void sin_cos() { +; ap_int a; +; auto ap_fixed_SinCos = __spirv_FixedSinCosINTEL(a, S, I, rI); +; } + +; template +; void sin_pi() { +; ap_int a; +; auto ap_fixed_SinPi = __spirv_FixedSinPiINTEL(a, S, I, rI); +; } + +; template +; void cos_pi() { +; ap_int a; +; auto ap_fixed_CosPi = __spirv_FixedCosPiINTEL(a, S, I, rI); +; } + +; template +; void sin_cos_pi() { +; ap_int a; +; auto ap_fixed_SinCosPi = __spirv_FixedSinCosPiINTEL(a, S, I, rI); +; } + +; template +; void log() { +; ap_int a; +; auto ap_fixed_Log = __spirv_FixedLogINTEL(a, S, I, rI); +; } + +; template +; void exp() { +; ap_int a; +; auto ap_fixed_Exp = __spirv_FixedExpINTEL(a, S, I, rI); +; } + +; template +; __attribute__((sycl_kernel)) void kernel_single_task(Func kernelFunc) { +; kernelFunc(); +; } + +; int main() { +; kernel_single_task([]() { +; sqrt<13, 5, false, 2, 2>(); +; recip<3, 8, true, 4, 4>(); +; rsqrt<11, 10, false, 8, 6>(); +; sin<17, 11, true, 7, 5>(); +; cos<35, 28, false, 9, 3>(); +; sin_cos<31, 20, true, 10, 12>(); +; sin_pi<60, 5, false, 2, 2>(); +; cos_pi<28, 16, false, 8, 5>(); +; sin_cos_pi<13, 5, false, 2, 2>(); +; log<64, 44, true, 24, 22>(); +; exp<44, 34, false, 20, 20>(); +; }); +; return 0; +; } + +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_arbitrary_precision_integers,+SPV_INTEL_arbitrary_precision_fixed_point -o %t.spv +; RUN: llvm-spirv %t.spv -to-text -o - | FileCheck %s --check-prefix=CHECK-SPIRV + +; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_arbitrary_precision_integers -spirv-text -o - | FileCheck %s --check-prefix=CHECK-SPIRV-NEGATIVE + +; RUN: llvm-spirv -r %t.spv -o %t.bc +; RUN: llvm-dis < %t.bc | FileCheck %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV: 2 Capability ArbitraryPrecisionIntegersINTEL +; CHECK-SPIRV: 2 Capability ArbitraryPrecisionFixedPointINTEL +; CHECK-SPIRV: 12 Extension "SPV_INTEL_arbitrary_precision_fixed_point" +; CHECK-SPIRV: 11 Extension "SPV_INTEL_arbitrary_precision_integers" + +; CHECK-SPIRV-NEGATIVE-NOT: 2 Capability ArbitraryPrecisionFixedPointINTEL +; CHECK-SPIRV-NEGATIVE-NOT: 12 Extension "SPV_INTEL_arbitrary_precision_fixed_point" + +; CHECK-SPIRV: 4 TypeInt [[Ty_8:[0-9]+]] 8 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_13:[0-9]+]] 13 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_5:[0-9]+]] 5 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_3:[0-9]+]] 3 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_11:[0-9]+]] 11 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_10:[0-9]+]] 10 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_17:[0-9]+]] 17 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_35:[0-9]+]] 35 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_28:[0-9]+]] 28 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_31:[0-9]+]] 31 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_40:[0-9]+]] 40 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_60:[0-9]+]] 60 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_16:[0-9]+]] 16 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_64:[0-9]+]] 64 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_44:[0-9]+]] 44 0 +; CHECK-SPIRV: 4 TypeInt [[Ty_34:[0-9]+]] 34 0 + +; CHECK-SPIRV: 6 Load [[Ty_13]] [[Sqrt_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedSqrtINTEL [[Ty_5]] [[#]] [[Ty_13]] [[Sqrt_InId]] 0 2 2 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedSqrtINTEL +; CHECK-SPIRV: 6 Load [[Ty_5]] [[Sqrt_InId_B:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedSqrtINTEL [[Ty_13]] [[#]] [[Ty_5]] [[Sqrt_InId_B]] 0 2 2 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedSqrtINTEL +; CHECK-SPIRV: 6 Load [[Ty_5]] [[Sqrt_InId_C:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedSqrtINTEL [[Ty_13]] [[#]] [[Ty_5]] [[Sqrt_InId_C]] 0 2 2 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedSqrtINTEL + +; CHECK-SPIRV: 6 Load [[Ty_3]] [[Recip_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedRecipINTEL [[Ty_8]] [[#]] [[Ty_3]] [[Recip_InId]] 1 4 4 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedRecipINTEL + +; CHECK-SPIRV: 6 Load [[Ty_11]] [[Rsqrt_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedRsqrtINTEL [[Ty_10]] [[#]] [[Ty_11]] [[Rsqrt_InId]] 0 8 6 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedRsqrtINTEL + +; CHECK-SPIRV: 6 Load [[Ty_17]] [[Sin_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedSinINTEL [[Ty_11]] [[#]] [[Ty_17]] [[Sin_InId]] 1 7 5 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedSinINTEL + +; CHECK-SPIRV: 6 Load [[Ty_35]] [[Cos_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedCosINTEL [[Ty_28]] [[#]] [[Ty_35]] [[Cos_InId]] 0 9 3 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedCosINTEL + +; CHECK-SPIRV: 6 Load [[Ty_31]] [[SinCos_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedSinCosINTEL [[Ty_40]] [[#]] [[Ty_31]] [[SinCos_InId]] 1 10 12 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedSinCosINTEL + +; CHECK-SPIRV: 6 Load [[Ty_60]] [[SinPi_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedSinPiINTEL [[Ty_5]] [[#]] [[Ty_60]] [[SinPi_InId]] 0 2 2 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedSinPiINTEL + +; CHECK-SPIRV: 6 Load [[Ty_28]] [[CosPi_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedCosPiINTEL [[Ty_16]] [[#]] [[Ty_28]] [[CosPi_InId]] 0 8 5 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedCosPiINTEL + +; CHECK-SPIRV: 6 Load [[Ty_13]] [[SinCosPi_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedSinCosPiINTEL [[Ty_10]] [[#]] [[Ty_13]] [[SinCosPi_InId]] 0 2 2 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedSinCosPiINTEL + +; CHECK-SPIRV: 6 Load [[Ty_64]] [[Log_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedLogINTEL [[Ty_44]] [[#]] [[Ty_64]] [[Log_InId]] 1 24 22 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedLogINTEL + +; CHECK-SPIRV: 6 Load [[Ty_44]] [[Exp_InId:[0-9]+]] +; CHECK-SPIRV-NEXT: 10 FixedExpINTEL [[Ty_34]] [[#]] [[Ty_44]] [[Exp_InId]] 0 20 20 0 0 +; CHECK-SPIRV-NEGATIVE-NOT: 10 FixedExpINTEL + +; CHECK-LLVM: call i5 @intel_arbitrary_fixed_sqrt.i5.i13(i13 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0) +; CHECK-LLVM: call i13 @intel_arbitrary_fixed_sqrt.i13.i5(i5 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0) +; CHECK-LLVM: call i13 @intel_arbitrary_fixed_sqrt.i13.i5(i5 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0) +; CHECK-LLVM: call i8 @intel_arbitrary_fixed_recip.i8.i3(i3 %[[#]], i1 true, i32 4, i32 4, i32 0, i32 0) +; CHECK-LLVM: call i10 @intel_arbitrary_fixed_rsqrt.i10.i11(i11 %[[#]], i1 false, i32 8, i32 6, i32 0, i32 0) +; CHECK-LLVM: call i11 @intel_arbitrary_fixed_sin.i11.i17(i17 %[[#]], i1 true, i32 7, i32 5, i32 0, i32 0) +; CHECK-LLVM: call i28 @intel_arbitrary_fixed_cos.i28.i35(i35 %[[#]], i1 false, i32 9, i32 3, i32 0, i32 0) +; CHECK-LLVM: call i40 @intel_arbitrary_fixed_sincos.i40.i31(i31 %[[#]], i1 true, i32 10, i32 12, i32 0, i32 0) +; CHECK-LLVM: call i5 @intel_arbitrary_fixed_sinpi.i5.i60(i60 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0) +; CHECK-LLVM: call i16 @intel_arbitrary_fixed_cospi.i16.i28(i28 %[[#]], i1 false, i32 8, i32 5, i32 0, i32 0) +; CHECK-LLVM: call i10 @intel_arbitrary_fixed_sincospi.i10.i13(i13 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0) +; CHECK-LLVM: call i44 @intel_arbitrary_fixed_log.i44.i64(i64 %[[#]], i1 true, i32 24, i32 22, i32 0, i32 0) +; CHECK-LLVM: call i34 @intel_arbitrary_fixed_exp.i34.i44(i44 %[[#]], i1 false, i32 20, i32 20, i32 0, i32 0) + +; ModuleID = 'ap_fixed.cpp' +source_filename = "ap_fixed.cpp" +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" +target triple = "spir64-unknown-linux-sycldevice" + +%"class._ZTSZ4mainE3$_0.anon" = type { i8 } + +$_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv = comdat any + +$_Z5recipILi3ELi8ELb1ELi4ELi4EEvv = comdat any + +$_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv = comdat any + +$_Z3sinILi17ELi11ELb1ELi7ELi5EEvv = comdat any + +$_Z3cosILi35ELi28ELb0ELi9ELi3EEvv = comdat any + +$_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv = comdat any + +$_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv = comdat any + +$_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv = comdat any + +$_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv = comdat any + +$_Z3logILi64ELi44ELb1ELi24ELi22EEvv = comdat any + +$_Z3expILi44ELi34ELb0ELi20ELi20EEvv = comdat any + +; Function Attrs: norecurse +define dso_local spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 !kernel_arg_host_accessible !3 !kernel_arg_pipe_depth !3 !kernel_arg_pipe_io !3 !kernel_arg_buffer_location !3 { +entry: + %0 = alloca %"class._ZTSZ4mainE3$_0.anon", align 1 + %1 = bitcast %"class._ZTSZ4mainE3$_0.anon"* %0 to i8* + call void @llvm.lifetime.start.p0i8(i64 1, i8* %1) #5 + %2 = addrspacecast %"class._ZTSZ4mainE3$_0.anon"* %0 to %"class._ZTSZ4mainE3$_0.anon" addrspace(4)* + call spir_func void @"_ZZ4mainENK3$_0clEv"(%"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %2) + %3 = bitcast %"class._ZTSZ4mainE3$_0.anon"* %0 to i8* + call void @llvm.lifetime.end.p0i8(i64 1, i8* %3) #5 + ret void +} + +; Function Attrs: argmemonly nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: inlinehint norecurse +define internal spir_func void @"_ZZ4mainENK3$_0clEv"(%"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %this) #2 align 2 { +entry: + %this.addr = alloca %"class._ZTSZ4mainE3$_0.anon" addrspace(4)*, align 8 + store %"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %this, %"class._ZTSZ4mainE3$_0.anon" addrspace(4)** %this.addr, align 8, !tbaa !5 + call spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv() + call spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv() + call spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv() + call spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv() + call spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv() + call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv() + call spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv() + call spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv() + call spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv() + call spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv() + call spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv() + ret void +} + +; Function Attrs: argmemonly nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv() #3 comdat { +entry: + %a = alloca i13, align 2 + %ap_fixed_Sqrt = alloca i5, align 1 + %b = alloca i5, align 1 + %ap_fixed_Sqrt_b = alloca i13, align 2 + %c = alloca i5, align 1 + %ap_fixed_Sqrt_c = alloca i13, align 2 + %0 = bitcast i13* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %0) #5 + %1 = bitcast i5* %ap_fixed_Sqrt to i8* + call void @llvm.lifetime.start.p0i8(i64 1, i8* %1) #5 + %2 = load i13, i13* %a, align 2, !tbaa !9 + %call = call spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %2, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5 + store i5 %call, i5* %ap_fixed_Sqrt, align 1, !tbaa !11 + %3 = bitcast i5* %b to i8* + call void @llvm.lifetime.start.p0i8(i64 1, i8* %3) #5 + %4 = bitcast i13* %ap_fixed_Sqrt_b to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %4) #5 + %5 = load i5, i5* %b, align 1, !tbaa !11 + %call1 = call spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext %5, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5 + store i13 %call1, i13* %ap_fixed_Sqrt_b, align 2, !tbaa !9 + %6 = bitcast i5* %c to i8* + call void @llvm.lifetime.start.p0i8(i64 1, i8* %6) #5 + %7 = bitcast i13* %ap_fixed_Sqrt_c to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %7) #5 + %8 = load i5, i5* %c, align 1, !tbaa !11 + %call2 = call spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext %8, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5 + store i13 %call2, i13* %ap_fixed_Sqrt_c, align 2, !tbaa !9 + %9 = bitcast i13* %ap_fixed_Sqrt_c to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %9) #5 + %10 = bitcast i5* %c to i8* + call void @llvm.lifetime.end.p0i8(i64 1, i8* %10) #5 + %11 = bitcast i13* %ap_fixed_Sqrt_b to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %11) #5 + %12 = bitcast i5* %b to i8* + call void @llvm.lifetime.end.p0i8(i64 1, i8* %12) #5 + %13 = bitcast i5* %ap_fixed_Sqrt to i8* + call void @llvm.lifetime.end.p0i8(i64 1, i8* %13) #5 + %14 = bitcast i13* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %14) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv() #3 comdat { +entry: + %a = alloca i3, align 1 + %ap_fixed_Recip = alloca i8, align 1 + %0 = bitcast i3* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 1, i8* %0) #5 + call void @llvm.lifetime.start.p0i8(i64 1, i8* %ap_fixed_Recip) #5 + %1 = load i3, i3* %a, align 1, !tbaa !13 + %call = call spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext %1, i1 zeroext true, i32 4, i32 4, i32 0, i32 0) #5 + store i8 %call, i8* %ap_fixed_Recip, align 1, !tbaa !15 + call void @llvm.lifetime.end.p0i8(i64 1, i8* %ap_fixed_Recip) #5 + %2 = bitcast i3* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 1, i8* %2) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv() #3 comdat { +entry: + %a = alloca i11, align 2 + %ap_fixed_Rsqrt = alloca i10, align 2 + %0 = bitcast i11* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %0) #5 + %1 = bitcast i10* %ap_fixed_Rsqrt to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %1) #5 + %2 = load i11, i11* %a, align 2, !tbaa !17 + %call = call spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext %2, i1 zeroext false, i32 8, i32 6, i32 0, i32 0) #5 + store i10 %call, i10* %ap_fixed_Rsqrt, align 2, !tbaa !19 + %3 = bitcast i10* %ap_fixed_Rsqrt to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %3) #5 + %4 = bitcast i11* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv() #3 comdat { +entry: + %a = alloca i17, align 4 + %ap_fixed_Sin = alloca i11, align 2 + %0 = bitcast i17* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 + %1 = bitcast i11* %ap_fixed_Sin to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %1) #5 + %2 = load i17, i17* %a, align 4, !tbaa !21 + %call = call spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext %2, i1 zeroext true, i32 7, i32 5, i32 0, i32 0) #5 + store i11 %call, i11* %ap_fixed_Sin, align 2, !tbaa !17 + %3 = bitcast i11* %ap_fixed_Sin to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %3) #5 + %4 = bitcast i17* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv() #3 comdat { +entry: + %a = alloca i35, align 8 + %ap_fixed_Cos = alloca i28, align 4 + %0 = bitcast i35* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %0) #5 + %1 = bitcast i28* %ap_fixed_Cos to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %1) #5 + %2 = load i35, i35* %a, align 8, !tbaa !23 + %call = call spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35 %2, i1 zeroext false, i32 9, i32 3, i32 0, i32 0) #5 + store i28 %call, i28* %ap_fixed_Cos, align 4, !tbaa !25 + %3 = bitcast i28* %ap_fixed_Cos to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %3) #5 + %4 = bitcast i35* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv() #3 comdat { +entry: + %a = alloca i31, align 4 + %ap_fixed_SinCos = alloca i40, align 8 + %0 = bitcast i31* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 + %1 = bitcast i40* %ap_fixed_SinCos to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %1) #5 + %2 = load i31, i31* %a, align 4, !tbaa !27 + %call = call spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext %2, i1 zeroext true, i32 10, i32 12, i32 0, i32 0) #5 + store i40 %call, i40* %ap_fixed_SinCos, align 8, !tbaa !29 + %3 = bitcast i40* %ap_fixed_SinCos to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %3) #5 + %4 = bitcast i31* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv() #3 comdat { +entry: + %a = alloca i60, align 8 + %ap_fixed_SinPi = alloca i5, align 1 + %0 = bitcast i60* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %0) #5 + %1 = bitcast i5* %ap_fixed_SinPi to i8* + call void @llvm.lifetime.start.p0i8(i64 1, i8* %1) #5 + %2 = load i60, i60* %a, align 8, !tbaa !31 + %call = call spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60 %2, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5 + store i5 %call, i5* %ap_fixed_SinPi, align 1, !tbaa !11 + %3 = bitcast i5* %ap_fixed_SinPi to i8* + call void @llvm.lifetime.end.p0i8(i64 1, i8* %3) #5 + %4 = bitcast i60* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv() #3 comdat { +entry: + %a = alloca i28, align 4 + %ap_fixed_CosPi = alloca i16, align 2 + %0 = bitcast i28* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 + %1 = bitcast i16* %ap_fixed_CosPi to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %1) #5 + %2 = load i28, i28* %a, align 4, !tbaa !25 + %call = call spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext %2, i1 zeroext false, i32 8, i32 5, i32 0, i32 0) #5 + store i16 %call, i16* %ap_fixed_CosPi, align 2, !tbaa !33 + %3 = bitcast i16* %ap_fixed_CosPi to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %3) #5 + %4 = bitcast i28* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv() #3 comdat { +entry: + %a = alloca i13, align 2 + %ap_fixed_SinCosPi = alloca i10, align 2 + %0 = bitcast i13* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %0) #5 + %1 = bitcast i10* %ap_fixed_SinCosPi to i8* + call void @llvm.lifetime.start.p0i8(i64 2, i8* %1) #5 + %2 = load i13, i13* %a, align 2, !tbaa !9 + %call = call spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %2, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5 + store i10 %call, i10* %ap_fixed_SinCosPi, align 2, !tbaa !19 + %3 = bitcast i10* %ap_fixed_SinCosPi to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %3) #5 + %4 = bitcast i13* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 2, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv() #3 comdat { +entry: + %a = alloca i64, align 8 + %ap_fixed_Log = alloca i44, align 8 + %0 = bitcast i64* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %0) #5 + %1 = bitcast i44* %ap_fixed_Log to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %1) #5 + %2 = load i64, i64* %a, align 8, !tbaa !35 + %call = call spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64 %2, i1 zeroext true, i32 24, i32 22, i32 0, i32 0) #5 + store i44 %call, i44* %ap_fixed_Log, align 8, !tbaa !37 + %3 = bitcast i44* %ap_fixed_Log to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %3) #5 + %4 = bitcast i64* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %4) #5 + ret void +} + +; Function Attrs: norecurse nounwind +define linkonce_odr dso_local spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv() #3 comdat { +entry: + %a = alloca i44, align 8 + %ap_fixed_Exp = alloca i34, align 8 + %0 = bitcast i44* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %0) #5 + %1 = bitcast i34* %ap_fixed_Exp to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %1) #5 + %2 = load i44, i44* %a, align 8, !tbaa !37 + %call = call spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44 %2, i1 zeroext false, i32 20, i32 20, i32 0, i32 0) #5 + store i34 %call, i34* %ap_fixed_Exp, align 8, !tbaa !39 + %3 = bitcast i34* %ap_fixed_Exp to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %3) #5 + %4 = bitcast i44* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %4) #5 + ret void +} + +; Function Attrs: nounwind +declare dso_local spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64, i1 zeroext, i32, i32, i32, i32) #4 + +; Function Attrs: nounwind +declare dso_local spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44, i1 zeroext, i32, i32, i32, i32) #4 + +attributes #0 = { norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "sycl-module-id"="ap_fixed.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nounwind willreturn } +attributes #2 = { inlinehint norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #4 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #5 = { nounwind } + +!llvm.module.flags = !{!0} +!opencl.spir.version = !{!1} +!spirv.Source = !{!2} +!opencl.used.extensions = !{!3} +!opencl.used.optional.core.features = !{!3} +!opencl.compiler.options = !{!3} +!llvm.ident = !{!4} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, i32 2} +!2 = !{i32 4, i32 100000} +!3 = !{} +!4 = !{!"Intel(R) oneAPI DPC++ Compiler 2021.1 (YYYY.x.0.MMDD)"} +!5 = !{!6, !6, i64 0} +!6 = !{!"any pointer", !7, i64 0} +!7 = !{!"omnipotent char", !8, i64 0} +!8 = !{!"Simple C++ TBAA"} +!9 = !{!10, !10, i64 0} +!10 = !{!"_ExtInt(13)", !7, i64 0} +!11 = !{!12, !12, i64 0} +!12 = !{!"_ExtInt(5)", !7, i64 0} +!13 = !{!14, !14, i64 0} +!14 = !{!"_ExtInt(3)", !7, i64 0} +!15 = !{!16, !16, i64 0} +!16 = !{!"_ExtInt(8)", !7, i64 0} +!17 = !{!18, !18, i64 0} +!18 = !{!"_ExtInt(11)", !7, i64 0} +!19 = !{!20, !20, i64 0} +!20 = !{!"_ExtInt(10)", !7, i64 0} +!21 = !{!22, !22, i64 0} +!22 = !{!"_ExtInt(17)", !7, i64 0} +!23 = !{!24, !24, i64 0} +!24 = !{!"_ExtInt(35)", !7, i64 0} +!25 = !{!26, !26, i64 0} +!26 = !{!"_ExtInt(28)", !7, i64 0} +!27 = !{!28, !28, i64 0} +!28 = !{!"_ExtInt(31)", !7, i64 0} +!29 = !{!30, !30, i64 0} +!30 = !{!"_ExtInt(40)", !7, i64 0} +!31 = !{!32, !32, i64 0} +!32 = !{!"_ExtInt(60)", !7, i64 0} +!33 = !{!34, !34, i64 0} +!34 = !{!"_ExtInt(16)", !7, i64 0} +!35 = !{!36, !36, i64 0} +!36 = !{!"_ExtInt(64)", !7, i64 0} +!37 = !{!38, !38, i64 0} +!38 = !{!"_ExtInt(44)", !7, i64 0} +!39 = !{!40, !40, i64 0} +!40 = !{!"_ExtInt(34)", !7, i64 0}