diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc index 2c2cd52b0d..8bdcfb0cea 100644 --- a/include/LLVMSPIRVExtensions.inc +++ b/include/LLVMSPIRVExtensions.inc @@ -48,6 +48,7 @@ EXT(SPV_INTEL_arithmetic_fence) EXT(SPV_INTEL_bfloat16_conversion) EXT(SPV_INTEL_split_barrier) EXT(SPV_INTEL_masked_gather_scatter) -EXT(SPV_INTEL_tensor_float32_conversion) +EXT(SPV_INTEL_tensor_float32_conversion) // TODO: to remove old extension +EXT(SPV_INTEL_tensor_float32_rounding) EXT(SPV_INTEL_hw_thread_queries) EXT(SPV_EXT_relaxed_printf_string_address_space) diff --git a/lib/SPIRV/libSPIRV/SPIRVInstruction.h b/lib/SPIRV/libSPIRV/SPIRVInstruction.h index 17b2c3f545..4b0e2a28ac 100644 --- a/lib/SPIRV/libSPIRV/SPIRVInstruction.h +++ b/lib/SPIRV/libSPIRV/SPIRVInstruction.h @@ -3437,10 +3437,10 @@ _SPIRV_OP(MaskedScatter, false, 5) #undef _SPIRV_OP template -class SPIRVTensorFloat32ConversionINTELInstBase : public SPIRVUnaryInst { +class SPIRVTensorFloat32RoundingINTELInstBase : public SPIRVUnaryInst { protected: SPIRVCapVec getRequiredCapability() const override { - return getVec(internal::CapabilityTensorFloat32ConversionINTEL); + return getVec(internal::CapabilityTensorFloat32RoundingINTEL); } llvm::Optional getRequiredExtension() const override { @@ -3461,8 +3461,8 @@ class SPIRVTensorFloat32ConversionINTELInstBase : public SPIRVUnaryInst { // because it may call a method of class Module that may modify LiteralMap // of Module field. That modification is not impacting validate method for // these instructions, so const_cast is safe here. - using SPVTF32ConvTy = SPIRVTensorFloat32ConversionINTELInstBase; - SPIRVValue *Input = const_cast(this)->getOperand(0); + using SPVTF32RoundTy = SPIRVTensorFloat32RoundingINTELInstBase; + SPIRVValue *Input = const_cast(this)->getOperand(0); SPIRVType *InCompTy = Input->getType(); SPIRVWord InCompCount = 1; @@ -3490,8 +3490,8 @@ class SPIRVTensorFloat32ConversionINTELInstBase : public SPIRVUnaryInst { }; #define _SPIRV_OP(x) \ - typedef SPIRVTensorFloat32ConversionINTELInstBase SPIRV##x; -_SPIRV_OP(ConvertFToTF32INTEL) + typedef SPIRVTensorFloat32RoundingINTELInstBase SPIRV##x; +_SPIRV_OP(RoundFToTF32INTEL) #undef _SPIRV_OP } // namespace SPIRV diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index 0b9ebeeb0e..963be0b0e4 100644 --- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -584,8 +584,8 @@ template <> inline void SPIRVMap::init() { add(internal::CapabilityFPArithmeticFenceINTEL, "FPArithmeticFenceINTEL"); add(internal::CapabilityBfloat16ConversionINTEL, "Bfloat16ConversionINTEL"); add(internal::CapabilityMaskedGatherScatterINTEL, "MaskedGatherScatterINTEL"); - add(internal::CapabilityTensorFloat32ConversionINTEL, - "TensorFloat32ConversionINTEL"); + add(internal::CapabilityTensorFloat32RoundingINTEL, + "TensorFloat32RoundingINTEL"); add(internal::CapabilityHWThreadQueryINTEL, "HWThreadQueryINTEL"); } SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap) diff --git a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnumInternal.h b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnumInternal.h index 7bdd9f85a1..6382f18324 100644 --- a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnumInternal.h +++ b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnumInternal.h @@ -10,4 +10,4 @@ _SPIRV_OP_INTERNAL(ConvertFToBF16INTEL, internal::OpConvertFToBF16INTEL) _SPIRV_OP_INTERNAL(ConvertBF16ToFINTEL, internal::OpConvertBF16ToFINTEL) _SPIRV_OP_INTERNAL(MaskedGatherINTEL, internal::OpMaskedGatherINTEL) _SPIRV_OP_INTERNAL(MaskedScatterINTEL, internal::OpMaskedScatterINTEL) -_SPIRV_OP_INTERNAL(ConvertFToTF32INTEL, internal::ConvertFToTF32INTEL) +_SPIRV_OP_INTERNAL(RoundFToTF32INTEL, internal::RoundFToTF32INTEL) diff --git a/lib/SPIRV/libSPIRV/spirv_internal.hpp b/lib/SPIRV/libSPIRV/spirv_internal.hpp index 69f3232b4a..5f6ad69768 100644 --- a/lib/SPIRV/libSPIRV/spirv_internal.hpp +++ b/lib/SPIRV/libSPIRV/spirv_internal.hpp @@ -42,7 +42,7 @@ enum InternalOp { IOpConvertFToBF16INTEL = 6116, IOpConvertBF16ToFINTEL = 6117, IOpArithmeticFenceINTEL = 6145, - IOpConvertFToTF32INTEL = 6426, + IOpRoundFToTF32INTEL = 6426, IOpMaskedGatherINTEL = 6428, IOpMaskedScatterINTEL = 6429, IOpPrev = OpMax - 2, @@ -70,7 +70,7 @@ enum InternalCapability { ICapTokenTypeINTEL = 6112, ICapBfloat16ConversionINTEL = 6115, ICapFPArithmeticFenceINTEL = 6144, - ICapabilityTensorFloat32ConversionINTEL = 6425, + ICapabilityTensorFloat32RoundingINTEL = 6425, ICapabilityMaskedGatherScatterINTEL = 6427, ICapabilityHWThreadQueryINTEL = 6134, }; @@ -94,8 +94,8 @@ _SPIRV_OP(Capability, MaskedGatherScatterINTEL) _SPIRV_OP(Op, MaskedGatherINTEL) _SPIRV_OP(Op, MaskedScatterINTEL) -_SPIRV_OP(Capability, TensorFloat32ConversionINTEL) -_SPIRV_OP(Op, ConvertFToTF32INTEL) +_SPIRV_OP(Capability, TensorFloat32RoundingINTEL) +_SPIRV_OP(Op, RoundFToTF32INTEL) enum InternalBuiltIn { IBuiltInSubDeviceIDINTEL = 6135, diff --git a/test/transcoding/SPV_INTEL_tensor_float32_conversion/convert_tensor_float32.ll b/test/transcoding/SPV_INTEL_tensor_float32_conversion/convert_tensor_float32.ll index 9f8f54f345..dad3d503b4 100644 --- a/test/transcoding/SPV_INTEL_tensor_float32_conversion/convert_tensor_float32.ll +++ b/test/transcoding/SPV_INTEL_tensor_float32_conversion/convert_tensor_float32.ll @@ -13,7 +13,7 @@ target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" target triple = "spir64-unknown-unknown" -; CHECK-SPIRV: Capability TensorFloat32ConversionINTEL +; CHECK-SPIRV: Capability TensorFloat32RoundingINTEL ; CHECK-SPIRV: Extension "SPV_INTEL_tensor_float32_conversion" ; CHECK-SPIRV: TypeFloat [[#FP32Ty:]] 32 ; CHECK-SPIRV: TypeVector [[#FP32v8Ty:]] [[#FP32Ty]] 8 @@ -22,24 +22,24 @@ target triple = "spir64-unknown-unknown" ; CHECK-SPIRV: FunctionParameter [[#FP32Ty]] [[FP32ValId:.*]] ; CHECK-SPIRV: FunctionParameter [[#FP32v8Ty]] [[FP32v8ValId:.*]] -; CHECK-SPIRV: ConvertFToTF32INTEL [[#FP32Ty]] [[#]] [[FP32ValId]] -; CHECK-SPIRV: ConvertFToTF32INTEL [[#FP32v8Ty]] [[#]] [[FP32v8ValId]] -; CHECK-SPIRV: ConvertFToTF32INTEL [[#FP32Ty]] [[#]] [[#CONST]] +; CHECK-SPIRV: RoundFToTF32INTEL [[#FP32Ty]] [[#]] [[FP32ValId]] +; CHECK-SPIRV: RoundFToTF32INTEL [[#FP32v8Ty]] [[#]] [[FP32v8ValId]] +; CHECK-SPIRV: RoundFToTF32INTEL [[#FP32Ty]] [[#]] [[#CONST]] -; CHECK-LLVM: call spir_func float @_Z27__spirv_ConvertFToTF32INTELf(float -; CHECK-LLVM: call spir_func <8 x float> @_Z27__spirv_ConvertFToTF32INTELDv8_f(<8 x float> -; CHECK-LLVM: call spir_func float @_Z27__spirv_ConvertFToTF32INTELf(float 1.000000e+00) +; CHECK-LLVM: call spir_func float @_Z25__spirv_RoundFToTF32INTELf(float +; CHECK-LLVM: call spir_func <8 x float> @_Z25__spirv_RoundFToTF32INTELDv8_f(<8 x float> +; CHECK-LLVM: call spir_func float @_Z25__spirv_RoundFToTF32INTELf(float 1.000000e+00) define spir_func void @_Z2opffv8(float %a, <8 x float> %in) { - %1 = tail call spir_func float @_Z27__spirv_ConvertFToTF32INTELf(float %a) - %2 = tail call spir_func <8 x float> @_Z27__spirv_ConvertFToTF32INTELDv8_f(<8 x float> %in) - %3 = tail call spir_func float @_Z27__spirv_ConvertFToTF32INTELf(float 1.000000e+00) + %1 = tail call spir_func float @_Z25__spirv_RoundFToTF32INTELf(float %a) + %2 = tail call spir_func <8 x float> @_Z25__spirv_RoundFToTF32INTELDv8_f(<8 x float> %in) + %3 = tail call spir_func float @_Z25__spirv_RoundFToTF32INTELf(float 1.000000e+00) ret void } -declare spir_func float @_Z27__spirv_ConvertFToTF32INTELf(float) +declare spir_func float @_Z25__spirv_RoundFToTF32INTELf(float) -declare spir_func <8 x float> @_Z27__spirv_ConvertFToTF32INTELDv8_f(<8 x float>) +declare spir_func <8 x float> @_Z25__spirv_RoundFToTF32INTELDv8_f(<8 x float>) !opencl.spir.version = !{!0} !spirv.Source = !{!1}