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PowerPC64 fixes #16404
PowerPC64 fixes #16404
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I'm not seeing any TOC issues on recent LLVM versions, so remove the workaround.
Disassembling little endian PowerPC instructions is now fixed upstream with LLVM commit r242288, so we can remove this workaround.
Fast isel is causing a number of test case failures on PowerPC64. Disable it until we solve the LLVM issues.
This fixes an issue when reusing a JIT context on PowerPC64.
This fixes some little endian fast isel issues as well as setting a sane default for the generic target on little endian.
@@ -5797,7 +5797,7 @@ extern "C" void jl_init_codegen(void) | |||
targetFeatures); | |||
assert(jl_TargetMachine && "Failed to select target machine -" | |||
" Is the LLVM backend for this CPU enabled?"); | |||
#if defined(USE_MCJIT) && !defined(_CPU_ARM_) | |||
#if defined(USE_MCJIT) && (!defined(_CPU_ARM_) && !defined(_CPU_PPC64_)) |
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I'm wonder what's wrong about fastisel... it works on AArch64 but not AArch32 for example......
What's the issue you see with FastISel?
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Most likely a bug in the PowerPC64 fast-isel code, it doesn't get a whole lot of testing. We are working to find the bugs in llvm and fix them. One failure:
y = Float32(1)
i = trunc(Int32, y)
We get junk, instead of 1.
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So it's a different kind of failure with ARM backend, where the codegen messes up addressing mode and causes segfault...
LGTM |
A number of fixes for PowerPC64