Visualization problem of undefined signal in VHDL

[FranciscoNaveros]

In VHDL, when a signal is defined as undefined at the begining of the simulation (for instance, when that one is the output signal of a circuit with a delay), the visualization of that signal in the chronogram (showing the differences between the professor's and student's solutions) is wrong. After the first modification of the signal, assigning for instance the value '0', the chronogram will still represent that value as undefined. It will not be until the second modification of the signal that the chronogram will properly represente the value.

For instance, in the next example, the signal "salida" should be undefined for 2ns, '0' for another 2ns and '1' for the rest of the time:
salida<='U', '0' AFTER 2 NS, '1' AFTER 4 NS;

Nevertheless, we can see in the plot how the signal "salida" is undefined for the first 4 ns of the simulation.

Francisco Naveros.