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vendingmachine.fsm
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vendingmachine.fsm
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity statmachine is
port( vdd: in bit;
vss: in bit;
clk: in bit;
input: in bit_vector(2 downto 0);
rst: in bit;
output: out bit_vector(1 downto 0);
change: out bit_vector(1 downto 0)
);
end statmachine;
architecture beh of statmachine is
type STATE_TYPE is (s0, s1, s2, s3, s4, s5, s6, s7, s8);
signal current_s, next_s: state_type;
--Synthesis directives :
-- pragma current_state current_s
-- pragma next_state next_s
-- pragma clock clk
begin
process(current_s,input,rst)begin
if(rst ='1') then next_s <= s0;
else
case current_s is
when s0 => if(input = "000") then
next_s <= s1;
elsif(input = "001") then
next_s <= s2;
elsif(input = "010") then
next_s <= s4;
else next_s <= s0;
end if;
output <= "00";
change <= "00";
when s1 => if(input = "000") then
next_s <= s2;
elsif(input = "001") then
next_s <= s3;
elsif(input = "010") then
next_s <= s5;
else next_s <= s1;
end if;
output <= "00";
change <= "00";
when s2 => if (input = "000") then
next_s <= s3;
change <= "00";
elsif(input = "001") then
next_s <= s4;
change <= "00";
elsif(input = "010") then
next_s <= s6;
change <= "01";
else next_s <= s2;
end if;
output <= "00";
when s3 => if(input = "000") then
next_s <= s4;
change <= "00";
elsif(input = "001") then
next_s <= s5;
change <= "00";
elsif(input = "010") then
next_s <= s7;
change <= "10";
else next_s <= s3;
end if;
output <= "00";
when s4 => if(input = "000") then
next_s <= s5;
change <= "00";
elsif(input = "001") then
next_s <= s6;
change <= "01";
elsif(input = "010") then
next_s <= s8;
change <= "11";
else next_s <= s4;
end if;
output <= "00";
when s5 => if(input = "011") then
next_s <= s0;
output <= "01";
elsif(input = "100") then
next_s <= s0;
output <= "10";
else next_s <= s5;
end if;
change <= "00";
when s6 => if(input = "011") then
next_s <= s0;
output <= "01";
elsif(input = "100") then
next_s <= s0;
output <= "10";
else next_s <= s6;
end if;
change <= "00";
when s7 => if(input = "011") then
next_s <= s0;
output <= "01";
elsif(input = "100") then
next_s <= s0;
output <= "10";
else next_s <= s7;
end if;
change <= "00";
when s8 => if(input = "011") then
next_s <= s0;
output <= "01";
elsif(input = "100") then
next_s <= s0;
output <= "10";
else next_s <= s8;
end if;
change <= "00";
end case;
end if;
end process;
process(clk)
begin
if clk = '1' and not clk'stable then
current_s <= next_s;
end if;
end process;
end beh;