diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index c4d94e8..fa12b24 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -31,14 +31,14 @@ jobs: run: | mkdir -p "$HOME/.local/bin" cd "$HOME/.local/bin" - curl -L https://github.com/typst/typst/releases/download/v0.11.1/typst-x86_64-unknown-linux-musl.tar.xz | tar -xJ --strip-components=1 typst-x86_64-unknown-linux-musl/typst - curl -L https://github.com/casey/just/releases/download/1.28.0/just-1.28.0-x86_64-unknown-linux-musl.tar.gz | tar -xz just + curl -L https://github.com/typst/typst/releases/download/v0.12.0/typst-x86_64-unknown-linux-musl.tar.xz | tar -xJ --strip-components=1 typst-x86_64-unknown-linux-musl/typst + curl -L https://github.com/casey/just/releases/download/1.36.0/just-1.36.0-x86_64-unknown-linux-musl.tar.gz | tar -xz just echo "$HOME/.local/bin" >> $GITHUB_PATH - name: Install Font Awesome run: | mkdir -p "$HOME/.fonts" - curl -L https://github.com/FortAwesome/Font-Awesome/releases/download/6.5.2/fontawesome-free-6.5.2-desktop.zip -o fontawesome.zip - unzip -j fontawesome.zip 'fontawesome-free-6.5.2-desktop/otfs/*' -d "$HOME/.fonts" + curl -L https://github.com/FortAwesome/Font-Awesome/releases/download/6.6.0/fontawesome-free-6.6.0-desktop.zip -o fontawesome.zip + unzip -j fontawesome.zip 'fontawesome-free-6.6.0-desktop/otfs/*' -d "$HOME/.fonts" fc-cache - run: just build - name: Upload built PDF diff --git a/appendix/memory-map.typ b/appendix/memory-map.typ index 5b67055..ad61822 100644 --- a/appendix/memory-map.typ +++ b/appendix/memory-map.typ @@ -2,12 +2,12 @@ #let detail(..args) = text(7pt, ..args) -#let gbc-bit(content) = cellx(fill: rgb("#FFFFED"), content) -#let gbc-bits(length, content) = colspanx(length, fill: rgb("#FFFFED"), content) +#let gbc-bit(content) = table.cell(fill: rgb("#FFFFED"), content) +#let gbc-bits(length, content) = table.cell(colspan: length, fill: rgb("#FFFFED"), content) -#let unmapped-bit = cellx(fill: rgb("#D3D3D3"))[] +#let unmapped-bit = table.cell(fill: rgb("#D3D3D3"))[] #let unmapped-bits(length) = range(length).map((_) => unmapped-bit) -#let unmapped-byte = colspanx(8, fill: rgb("D3D3D3"))[] +#let unmapped-byte = table.cell(colspan: 8, fill: rgb("D3D3D3"))[] #let todo(length) = range(length).map((_) => []) #set text(9pt) @@ -16,19 +16,19 @@ #set page(flipped: true) #figure( - tablex( + table( columns: (auto, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr), inset: (x: 5pt, y: 3.5pt), align: (left, center, center, center, center, center, center, center, center), [], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0], [#hex("FF00") P1], ..unmapped-bits(2), [P15 #detail[buttons]], [P14 #detail[d-pad]], [P13 #detail[#awesome("\u{f358}") start]], [P12 #detail[#awesome("\u{f35b}") select]], [P11 #detail[#awesome("\u{f359}") B]], [P10 #detail[#awesome("\u{f35a}") A]], - [#hex("FF01") SB], colspanx(8)[SB\<7:0\>], + [#hex("FF01") SB], table.cell(colspan: 8)[SB\<7:0\>], [#hex("FF02") SC], [SIO_EN], ..unmapped-bits(5), gbc-bit[SIO_FAST], [SIO_CLK], hex("FF03"), unmapped-byte, - [#hex("FF04") DIV], colspanx(8)[DIVH\<7:0\>], - [#hex("FF05") TIMA], colspanx(8)[TIMA\<7:0\>], - [#hex("FF06") TMA], colspanx(8)[TMA\<7:0\>], - [#hex("FF07") TAC], ..unmapped-bits(5), [TAC_EN], colspanx(2)[TAC_CLK\<1:0\>], + [#hex("FF04") DIV], table.cell(colspan: 8)[DIVH\<7:0\>], + [#hex("FF05") TIMA], table.cell(colspan: 8)[TIMA\<7:0\>], + [#hex("FF06") TMA], table.cell(colspan: 8)[TMA\<7:0\>], + [#hex("FF07") TAC], ..unmapped-bits(5), [TAC_EN], table.cell(colspan: 2)[TAC_CLK\<1:0\>], hex("FF08"), unmapped-byte, hex("FF09"), unmapped-byte, hex("FF0A"), unmapped-byte, @@ -62,7 +62,7 @@ #pagebreak() #figure( - tablex( + table( columns: (auto, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr), inset: (x: 5pt, y: 3.5pt), align: (left, center, center, center, center, center, center, center, center), @@ -108,18 +108,18 @@ #pagebreak() #figure( - tablex( + table( columns: (auto, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr), inset: (x: 5pt, y: 3.5pt), align: (left, center, center, center, center, center, center, center, center), [], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0], [#hex("FF40") LCDC], [LCD_EN], [WIN_MAP], [WIN_EN], [TILE_SEL], [BG_MAP], [OBJ_SIZE], [OBJ_EN], [BG_EN], - [#hex("FF41") STAT], unmapped-bit, [INTR_LYC], [INTR_M2], [INTR_M1], [INTR_M0], [LYC_STAT], colspanx(2)[LCD_MODE\<1:0\>], + [#hex("FF41") STAT], unmapped-bit, [INTR_LYC], [INTR_M2], [INTR_M1], [INTR_M0], [LYC_STAT], table.cell(colspan: 2)[LCD_MODE\<1:0\>], [#hex("FF42") SCY], ..todo(8), [#hex("FF43") SCX], ..todo(8), [#hex("FF44") LY], ..todo(8), [#hex("FF45") LYC], ..todo(8), - [#hex("FF46") DMA], colspanx(8)[DMA\<7:0\>], + [#hex("FF46") DMA], table.cell(colspan: 8)[DMA\<7:0\>], [#hex("FF47") BGP], ..todo(8), [#hex("FF48") OBP0], ..todo(8), [#hex("FF49") OBP1], ..todo(8), @@ -154,7 +154,7 @@ #pagebreak() #figure( - tablex( + table( columns: (auto, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr), inset: (x: 5pt, y: 3.5pt), align: (left, center, center, center, center, center, center, center, center), @@ -191,7 +191,7 @@ hex("FF7D"), unmapped-byte, hex("FF7E"), unmapped-byte, hex("FF7F"), unmapped-byte, - [#hex("FFFF") IE], colspanx(3)[IE_UNUSED\<2:0\>], [IE_JOYPAD], [IE_SERIAL], [IE_TIMER], [IE_STAT], [IE_VBLANK], + [#hex("FFFF") IE], table.cell(colspan: 3)[IE_UNUSED\<2:0\>], [IE_JOYPAD], [IE_SERIAL], [IE_TIMER], [IE_STAT], [IE_VBLANK], [], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0], ), kind: table, diff --git a/chapter/cartridges/mbc1.typ b/chapter/cartridges/mbc1.typ index e764c41..ae3f383 100644 --- a/chapter/cartridges/mbc1.typ +++ b/chapter/cartridges/mbc1.typ @@ -17,7 +17,7 @@ The MBC1 chip includes four registers that affect the behaviour of the chip. Of )[ #reg-table( [U], [U], [U], [U], [W-0], [W-0], [W-0], [W-0], - unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), colspanx(4)[RAMG\<3:0\>], + unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), table.cell(colspan: 4)[RAMG\<3:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -46,7 +46,7 @@ When RAM access is disabled, all writes to the external RAM area #hex-range("A00 )[ #reg-table( [U], [U], [U], [W-0], [W-0], [W-0], [W-0], [W-1], - unimpl-bit(), unimpl-bit(), unimpl-bit(), colspanx(5)[BANK1\<4:0\>], + unimpl-bit(), unimpl-bit(), unimpl-bit(), table.cell(colspan: 5)[BANK1\<4:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -71,7 +71,7 @@ MBC1 doesn't allow the BANK1 register to contain zero (bit pattern #bin("00000") )[ #reg-table( [U], [U], [U], [U], [U], [U], [W-0], [W-0], - unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), colspanx(2)[BANK2\<1:0\>], + unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), table.cell(colspan: 2)[BANK2\<1:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -125,22 +125,22 @@ When the #hex-range("4000", "7FFF") addess range is accessed, the effective bank If the cartridge ROM is smaller than 16 Mbit, there are less ROM address pins to connect to and therefore some bank number bits are ignored. For example, 4 Mbit ROMs only need a 5-bit bank number, so the BANK2 register value is always ignored because those bits are simply not connected to the ROM. #figure( - tablex( + table( columns: 4, - auto-hlines: false, + stroke: (y: none), align: center, - hlinex(), - [], colspanx(3)[ROM address bits], - [Accessed address], colspanx(2)[Bank number], [Address within bank], - hlinex(), + table.hline(), + [], table.cell(colspan: 3)[ROM address bits], + [Accessed address], table.cell(colspan: 2)[Bank number], [Address within bank], + table.hline(), [], [20-19], [18-14], [13-0], - hlinex(), + table.hline(), [#hex-range("0000", "3FFF"), MODE = #bin("0")], bin("00"), bin("00000"), [A\<13:0\>], - hlinex(), + table.hline(), [#hex-range("0000", "3FFF"), MODE = #bin("1")], [BANK2], bin("00000"), [A\<13:0\>], - hlinex(), + table.hline(), hex-range("4000", "7FFF"), [BANK2], [BANK1], [A\<13:0\>], - hlinex(), + table.hline(), ), kind: table, caption: "Mapping of physical ROM address bits in MBC1 carts" @@ -155,11 +155,10 @@ Let's assume we have previously written #hex("12") to the BANK1 register and #bi let bank2 = box(inset: (y: 2pt), fill: rgb("#ff00004c"))[01] let prefix = box(inset: (y: 2pt))[0b] let pass(text) = box(inset: (y: 2pt), fill: rgb("#00000019"), text) - tablex( + table( columns: 3, align: (left + horizon, right + horizon, left + horizon), - auto-vlines: false, - auto-hlines: false, + stroke: none, [*Value of the BANK 1 register*], monotext[#prefix#bank1], [], [*Value of the BANK 2 register*], @@ -183,11 +182,10 @@ Let's assume we have previously requested ROM bank number 68, MBC1 mode is #bin( let addr(content) = box(inset: (y: 2pt), fill: rgb("#00ff004c"), content) let prefix = box(inset: (y: 2pt))[0b] let pass(content) = box(inset: (y: 2pt), fill: rgb("#00000019"), content) - tablex( + table( columns: 3, align: (left + horizon, right + horizon, left + horizon), - auto-vlines: false, - auto-hlines: false, + stroke: none, [*Value of the BANK 1 register*], monotext[#prefix#bank1("00100")], [], [*Value of the BANK 2 register*], @@ -210,20 +208,20 @@ On boards that have RAM, the A0-A12 cartridge bus signals are connected directly In MODE #bin("0") the BANK2 register value is not used, so the first RAM bank is always mapped to the #hex-range("A000", "BFFF") area. In MODE #bin("1") the BANK2 register value is used as the bank number. #figure( - tablex( + table( columns: 3, - auto-hlines: false, + stroke: (y: none), align: center + bottom, - hlinex(), - [], colspanx(2)[RAM address bits], + table.hline(), + [], table.cell(colspan: 2)[RAM address bits], [Accessed address], [Bank number], [Address within bank], - hlinex(), + table.hline(), [], [14-13], [12-0], - hlinex(), + table.hline(), [#hex-range("A000", "BFFF"), MODE = #bin("0")], bin("00"), [A\<12:0\>], - hlinex(), + table.hline(), [#hex-range("A000", "BFFF"), MODE = #bin("1")], [BANK2], [A\<12:0\>], - hlinex(), + table.hline(), ), kind: table, caption: "Mapping of physical RAM address bits in MBC1 carts" @@ -238,11 +236,10 @@ Let's assume we have previously written #bin("10") to the BANK2 register, MODE i let addr(content) = box(inset: (y: 2pt), fill: rgb("#00ff004c"), content) let prefix = box(inset: (y: 2pt))[0b] let pass(content) = box(inset: (y: 2pt), fill: rgb("#00000019"), content) - tablex( + table( columns: 3, align: (left + horizon, right + horizon, left + horizon), - auto-vlines: false, - auto-hlines: false, + stroke: none, [*Value of the BANK 2 register*], monotext[#prefix#bank2("10")], [], [*Address being read*], @@ -261,22 +258,22 @@ In MBC1 multicarts bit 4 of the BANK1 register is not physically connected to an From a ROM banking point of view, multicarts simply skip bit 4 of the BANK1 register, but otherwise the behaviour is the same. MODE #bin("1") guarantees that all ROM accesses, including accesses to #hex-range("0000", "3FFF"), use the BANK2 register value. #figure( - tablex( + table( columns: 4, - auto-hlines: false, + stroke: (y: none), align: center, - hlinex(), - [], colspanx(3)[ROM address bits], - [Accessed address], colspanx(2)[Bank number], [Address within bank], - hlinex(), + table.hline(), + [], table.cell(colspan: 3)[ROM address bits], + [Accessed address], table.cell(colspan: 2)[Bank number], [Address within bank], + table.hline(), [], [19-18], [17-14], [13-0], - hlinex(), + table.hline(), [#hex-range("0000", "3FFF"), MODE = #bin("0")], bin("00"), bin("0000"), [A\<13:0\>], - hlinex(), + table.hline(), [#hex-range("0000", "3FFF"), MODE = #bin("1")], [BANK2], bin("0000"), [A\<13:0\>], - hlinex(), + table.hline(), hex-range("4000", "7FFF"), [BANK2], [BANK1\<3:0\>], [A\<13:0\>], - hlinex(), + table.hline(), ), kind: table, caption: "Mapping of physical ROM address bits in MBC1 multicarts" @@ -292,11 +289,10 @@ Let's assume we have previously requested "game number" 3 (= #bin("11")) and ROM let addr(content) = box(inset: (y: 2pt), fill: rgb("#00ff004c"), content) let prefix = box(inset: (y: 2pt))[0b] let pass(content) = box(inset: (y: 2pt), fill: rgb("#00000019"), content) - tablex( + table( columns: 3, align: (left + horizon, right + horizon, left + horizon), - auto-vlines: false, - auto-hlines: false, + stroke: none, [*Value of the BANK 1 register*], monotext[#prefix#pass("1")#bank1("1101")], [], [*Value of the BANK 2 register*], diff --git a/chapter/cartridges/mbc2.typ b/chapter/cartridges/mbc2.typ index d88ac7c..341c8a0 100644 --- a/chapter/cartridges/mbc2.typ +++ b/chapter/cartridges/mbc2.typ @@ -21,7 +21,7 @@ The MBC2 chip includes two registers that affect the behaviour of the chip. The )[ #reg-table( [U], [U], [U], [U], [W-0], [W-0], [W-0], [W-0], - unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), colspanx(4)[RAMG\<3:0\>], + unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), table.cell(colspan: 4)[RAMG\<3:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -50,7 +50,7 @@ When RAM access is disabled, all writes to the external RAM area #hex-range("A00 )[ #reg-table( [U], [U], [U], [U], [W-0], [W-0], [W-0], [W-1], - unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), colspanx(4)[ROMB\<3:0\>], + unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), table.cell(colspan: 4)[ROMB\<3:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -78,20 +78,20 @@ When the #hex-range("0000", "3FFF") address range is accessed, the effective ban When the #hex-range("4000", "7FFF") address range is accessed, the effective bank number is the current ROMB register value. #figure( - tablex( + table( columns: 3, - auto-hlines: false, + stroke: (y: none), align: center, - hlinex(), - [], colspanx(2)[ROM address bits], + table.hline(), + [], table.cell(colspan: 2)[ROM address bits], [Accessed address], [Bank number], [Address within bank], - hlinex(), + table.hline(), [], [17-14], [13-0], - hlinex(), + table.hline(), hex-range("0000", "3FFF"), bin("0000"), [A\<13:0\>], - hlinex(), + table.hline(), hex-range("4000", "7FFF"), [ROMB], [A\<13:0\>], - hlinex(), + table.hline(), ), kind: table, caption: "Mapping of physical ROM address bits in MBC2 carts" @@ -106,18 +106,18 @@ MBC2 RAM is only 4-bit RAM, so the upper 4 bits of data do not physically exist MBC2 RAM consists of 512 addresses, so only A0-A8 matter when accessing the RAM region. There is no banking, and the #hex-range("A000", "BFFF") area is larger than the RAM, so the addresses wrap around. For example, accessing #hex("A000") is the same as accessing #hex("A200"), so it is possible to write to the former address and later read the written data using the latter address. #figure( - tablex( + table( columns: 2, - auto-hlines: false, + stroke: (y: none), align: center + bottom, - hlinex(), + table.hline(), [], [RAM address bits], [Accessed address], [], - hlinex(), + table.hline(), [], [8-0], - hlinex(), + table.hline(), hex-range("A000", "BFFF"), [A\<8:0\>], - hlinex(), + table.hline(), ), kind: table, caption: "Mapping of physical RAM address bits in MBC2 carts" diff --git a/chapter/cartridges/mbc5.typ b/chapter/cartridges/mbc5.typ index e6b6761..23ec952 100644 --- a/chapter/cartridges/mbc5.typ +++ b/chapter/cartridges/mbc5.typ @@ -11,7 +11,7 @@ The majority of games for Game Boy Color use the MBC5 chip. MBC5 supports ROM si )[ #reg-table( [W-0], [W-0], [W-0], [W-0], [W-0], [W-0], [W-0], [W-0], - colspanx(8)[RAMG\<7:0\>], + table.cell(colspan: 8)[RAMG\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -39,7 +39,7 @@ When RAM access is disabled, all writes to the external RAM area #hex-range("A00 )[ #reg-table( [W-0], [W-0], [W-0], [W-0], [W-0], [W-0], [W-0], [W-1], - colspanx(8)[ROMB0\<7:0\>], + table.cell(colspan: 8)[ROMB0\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -78,7 +78,7 @@ The 1-bit ROMB1 register is used as the most significant bit (bit 9) of the ROM )[ #reg-table( [U], [U], [U], [U], [W-0], [W-0], [W-0], [W-0], - unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), colspanx(4)[RAMB\<3:0\>], + unimpl-bit(), unimpl-bit(), unimpl-bit(), unimpl-bit(), table.cell(colspan: 4)[RAMB\<3:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) diff --git a/chapter/cpu/timing.typ b/chapter/cpu/timing.typ index bacc55e..e80e475 100644 --- a/chapter/cpu/timing.typ +++ b/chapter/cpu/timing.typ @@ -29,14 +29,14 @@ Let's assume the CPU is executing a program that starts from the address #hex("1 ) #monotext[ - #tablex( + #table( columns: 2, align: left + horizon, stroke: none, - hex("1000"), cellx(fill: colors.inc)[INC A], - hex("1001"), cellx(fill: colors.ldh)[LDH (n), A], - hex("1003"), cellx(fill: colors.rst)[RST #hex("08")], - hex("0008"), cellx(fill: colors.nop)[NOP] + hex("1000"), table.cell(fill: colors.inc)[INC A], + hex("1001"), table.cell(fill: colors.ldh)[LDH (n), A], + hex("1003"), table.cell(fill: colors.rst)[RST #hex("08")], + hex("0008"), table.cell(fill: colors.nop)[NOP] ) ] diff --git a/chapter/peripherals/dma.typ b/chapter/peripherals/dma.typ index dc1d967..252839d 100644 --- a/chapter/peripherals/dma.typ +++ b/chapter/peripherals/dma.typ @@ -17,7 +17,7 @@ Writing to the DMA register updates the upper bits of the DMA source address and )[ #reg-table( [R/W-x], [R/W-x], [R/W-x], [R/W-x], [R/W-x], [R/W-x], [R/W-x], [R/W-x], - colspanx(8)[DMA\<7:0\>], + table.cell(colspan: 8)[DMA\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) diff --git a/chapter/peripherals/ppu.typ b/chapter/peripherals/ppu.typ index 1b1510e..5773d12 100644 --- a/chapter/peripherals/ppu.typ +++ b/chapter/peripherals/ppu.typ @@ -17,7 +17,7 @@ )[ #reg-table( [U], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R-0], [R-0], [R-0], - unimpl-bit(), [INTR_LYC], [INTR_M2], [INTR_M1], [INTR_M0], [LYC_STAT], colspanx(2)[LCD_MODE\<1:0\>], + unimpl-bit(), [INTR_LYC], [INTR_M2], [INTR_M1], [INTR_M0], [LYC_STAT], table.cell(colspan: 2)[LCD_MODE\<1:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) ] @@ -27,7 +27,7 @@ )[ #reg-table( [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], - colspanx(8)[SCY\<7:0\>], + table.cell(colspan: 8)[SCY\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) ] @@ -37,7 +37,7 @@ )[ #reg-table( [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], - colspanx(8)[SCX\<7:0\>], + table.cell(colspan: 8)[SCX\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) ] @@ -47,7 +47,7 @@ )[ #reg-table( [R-0], [R-0], [R-0], [R-0], [R-0], [R-0], [R-0], [R-0], - colspanx(8)[LY\<7:0\>], + table.cell(colspan: 8)[LY\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) ] @@ -57,7 +57,7 @@ )[ #reg-table( [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], - colspanx(8)[LYC\<7:0\>], + table.cell(colspan: 8)[LYC\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) ] diff --git a/chapter/peripherals/serial.typ b/chapter/peripherals/serial.typ index 5d32f28..a8fc056 100644 --- a/chapter/peripherals/serial.typ +++ b/chapter/peripherals/serial.typ @@ -7,7 +7,7 @@ )[ #reg-table( [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], [R/W-0], - colspanx(8)[SB\<7:0\>], + table.cell(colspan: 8)[SB\<7:0\>], [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) diff --git a/common.typ b/common.typ index 1d8529f..2ba548c 100644 --- a/common.typ +++ b/common.typ @@ -1,5 +1,4 @@ -#import "@preview/cetz:0.2.2" -#import "@preview/tablex:0.0.8": tablex, cellx, colspanx, hlinex +#import "@preview/cetz:0.3.0" #let monotext(..args) = text(font: "Anonymous Pro", fallback: false, ..args) @@ -33,10 +32,10 @@ #let hex(content) = monotext("0x" + content) #let hex-range(start, end) = monotext({"0x" + start + "-0x" + end}) -#let unimpl-bit() = cellx(fill: rgb("#D3D3D3ff"))[] +#let unimpl-bit() = table.cell(fill: rgb("#D3D3D3ff"))[] #let reg-table(..args) = monotext(9pt)[ - #tablex( + #table( columns: (1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr, 1fr), inset: 5pt, align: center + horizon, diff --git a/gbctr.typ b/gbctr.typ index ca807d9..a0663c8 100644 --- a/gbctr.typ +++ b/gbctr.typ @@ -45,7 +45,9 @@ #if config.draft [ #place(left, text(style: "italic", [DRAFT! #config.revision])) ] - #box(counter(page).display()) + #context { + box(counter(page).display()) + } ] ] ) diff --git a/preface.typ b/preface.typ index 1cfb6d6..9f961a1 100644 --- a/preface.typ +++ b/preface.typ @@ -60,7 +60,7 @@ Examples: )[ #reg-table( [R/W-0], [R/W-1], [U-1], [R-0], [R-1], [R-x], [W-1], [U-0], - colspanx(2)[VALUE\<1:0\>], unimpl-bit(), colspanx(3)[BIGVAL\<7:5\>], [FLAG], unimpl-bit(), + table.cell(colspan: 2)[VALUE\<1:0\>], unimpl-bit(), table.cell(colspan: 3)[BIGVAL\<7:5\>], [FLAG], unimpl-bit(), [bit 7], [6], [5], [4], [3], [2], [1], [bit 0] ) #set align(left) @@ -82,7 +82,7 @@ Examples: #v(1em) *Middle row legend:* - #tablex( + #table( columns: 2, align: center + horizon, `VALUE<1:0>`, [Bits 1 and 0 of VALUE],